Surge protection unit and circuit not supporting power over ethernet functionality

Abstract

The present disclosure relates to a surge protection unit and a circuit (non-POE circuit) that does not support power over Ethernet function, the non-POE circuit comprising a connector, the connector being electrically connected with the surge protection unit. The surge protection unit can comprise a capacitance element, two resistance elements (denoted as a first resistance element and a second resistance element), and two surge protection elements (denoted as a first surge protection element and a second surge protection element), the taps of at least one differential pair of the connector being electrically connected with a first end of the first resistance element, and the taps of the remaining differential pairs of the connector being electrically connected with a first end of the second resistance element. After the surge protection unit of the present disclosure is applied to the non-POE circuit, the requirements of common-mode output voltage test and surge test can be met simultaneously, and the space occupation and cost can be reduced to a certain extent.

Description

Technical Field

[0001] This disclosure relates to the field of surge protection technology, and in particular to a surge protection unit and a circuit that does not support Power over Ethernet (PoE) functionality. Background Technology

[0002] Ethernet circuits are generally divided into circuits that support Power over Ethernet (PoE) and circuits that do not support PoE (non-PoE). PoE circuits transmit both data signals and power over an Ethernet cable. Non-PoE circuits transmit data signals over Ethernet but do not support power transmission.

[0003] In non-PoE circuits, surge protection units are generally required. However, some related technologies use a single resistor as the surge protection unit, which has a high failure rate in common-mode output voltage testing. Other related technologies use four resistors connected in parallel, which can meet the requirements of common-mode output voltage testing but not surge testing.

[0004] In summary, current surge protection units used in non-POE circuits cannot simultaneously meet the requirements for common-mode output voltage testing and surge testing. Utility Model Content

[0005] This disclosure provides a surge protection unit and a circuit that does not support Power over Ethernet (PoE) functionality, which can simultaneously meet the requirements for common-mode output voltage testing and surge testing.

[0006] This disclosure provides a surge protection unit, which includes a first resistive element, a second resistive element, a first surge protection element, a second surge protection element, and a capacitor element. A first end of the first surge protection element is electrically connected to a first end of the first resistive element, and a first end of the second surge protection element is electrically connected to a first end of the second resistive element. The second ends of the first and second resistive elements are both electrically connected to the first end of the capacitor element. The second ends of the first, second, and capacitor elements are all grounded.

[0007] The surge protection unit is applied to a circuit that does not support Power over Ethernet (PoE) functionality. The circuit that does not support PoE functionality includes a connector, at least one differential pair of the connector is electrically connected to the first end of the first resistor element, and the remaining differential pairs of the connector are electrically connected to the first end of the second resistor element.

[0008] In one possible implementation,

[0009] The connector includes four differential pairs, wherein one differential pair has a tap electrically connected to the first end of the first resistive element, and the taps of the other three differential pairs are electrically connected to the first end of the second resistive element, respectively.

[0010] In one possible implementation,

[0011] The connector includes four differential pairs, wherein the taps of two differential pairs are electrically connected to the first end of the first resistive element, and the taps of the other two differential pairs are electrically connected to the first end of the second resistive element.

[0012] In one possible implementation,

[0013] The first resistive element and the second resistive element are the same; and / or,

[0014] The first surge protection element is the same as the second surge protection element.

[0015] In one possible implementation,

[0016] The first surge protection element includes at least one of the following: a solid-state discharge tube, a gas discharge tube, a varistor, an air discharge tube; and / or,

[0017] The second surge protection element includes at least one of the following: a solid discharge tube, a gas discharge tube, a varistor, and an air discharge tube.

[0018] In one possible implementation,

[0019] The resistance of the first resistive element is greater than or equal to 25Ω and less than or equal to 100Ω; and / or,

[0020] The resistance of the second resistive element is greater than or equal to 25Ω and less than or equal to 100Ω.

[0021] In one possible implementation,

[0022] The capacitance value of the capacitor element is greater than or equal to 10pF and less than or equal to 2.2nF.

[0023] This disclosure also provides a circuit that does not support Power over Ethernet (PoE) functionality, the circuit including a connector and a surge protection unit as described in any of the first aspects.

[0024] In one possible implementation,

[0025] The common-mode choke of the connector has a magnetic ring made of two or three wires wound together.

[0026] In one possible implementation,

[0027] The circuit that does not support Power over Ethernet includes a motherboard chip side and a cable side, wherein the cable side is electrically connected to the motherboard chip side via the connector.

[0028] According to the surge protection unit and the circuit that does not support Power over Ethernet (PoE circuit) provided in the embodiments of this disclosure, the surge protection unit is applied to the aforementioned non-PoE circuit. The non-PoE circuit includes a connector, and the connector is electrically connected to the surge protection unit. The surge protection unit may include a capacitor element, two resistor elements (denoted as a first resistor element and a second resistor element), and two surge protection elements (denoted as a first surge protection element and a second surge protection element). At least one differential pair of the connector has a tap electrically connected to a first end of the first resistor element, and the remaining differential pairs of the connector have taps electrically connected to a first end of the second resistor element. The first end of the first surge protection element is electrically connected to the first end of the first resistor element, and the first end of the second surge protection element is electrically connected to the first end of the second resistor element. The second ends of both the first and second resistor elements are electrically connected to the first end of the capacitor element. The second ends of the first, second, and capacitor elements are all grounded. In this disclosure, two resistors in the surge protection unit are connected in parallel and then electrically connected to a capacitor. These two resistors optimize common-mode impedance matching, reducing the common-mode output voltage in the circuit (equivalent to superimposing the common-mode output voltages of only the two output terminals (TX)). This arrangement not only controls the cost of the surge protection unit and reduces space occupation, but also meets the requirements for common-mode output voltage testing. The two surge protection components in this surge protection unit prevent the resistors from burning out and causing abnormalities during surge testing due to the surge protection components breaking down and conducting. Therefore, it effectively meets the requirements for surge testing. In other words, when the surge protection unit of this disclosure is applied to non-POE circuits, it can simultaneously meet the requirements for common-mode output voltage testing and surge testing, while also reducing space occupation and cost to a certain extent. Attached Figure Description

[0029] The accompanying drawings, incorporated in and forming part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort. One or more embodiments are illustrated by way of example through the corresponding images in the accompanying drawings. These exemplary descriptions do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale.

[0030] Figure 1 A schematic diagram of a non-POE circuit provided in an embodiment of this disclosure;

[0031] Figure 2 This is a schematic diagram of another non-POE circuit provided in an embodiment of this disclosure. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0033] The following disclosure provides numerous different embodiments or examples for implementing various structures of this disclosure. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this disclosure. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this disclosure; however, those skilled in the art will recognize the applicability of other processes and / or the use of other materials.

[0034] For ease of description, spatial relative terms may be used in the text to describe the relative position or movement of one element or feature relative to another element or feature, as shown in the figure. These relative terms include, for example, "inside," "outside," "middle," "outer," "below," "below," "above," "front," "back," etc. Such spatial relative terms are intended to include different orientations of the device in use or operation, other than those depicted in the figure. For example, if the device in the figure undergoes a positional flip, orientation change, or change of motion, these directional indications will change accordingly. For instance, an element described as "below other elements or features" or "below other elements or features" will subsequently be oriented "above other elements or features" or "above other elements or features." Therefore, the example term "below" can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or in other directions), and the spatial relative descriptors used in the text will be interpreted accordingly.

[0035] In some exemplary embodiments, reference is made to Figure 1 or Figure 2 As shown, a surge protection unit 100 and a circuit that does not support Power over Ethernet (referred to as a non-POE circuit) is provided with the surge protection unit 100.

[0036] The surge protection unit 100 may include a first resistor element R1, a second resistor element R2, a first surge protection element P1, a second surge protection element P2, and a capacitor element Cap. The first end of the first surge protection element P1 is electrically connected to the first end of the first resistor element R1, and the first end of the second surge protection element P2 is electrically connected to the first end of the second resistor element R2. The second ends of the first resistor element R1 and the second resistor element R2 are both electrically connected to the first end of the capacitor element Cap. The second ends of the first surge protection element P1, the second surge protection element P2, and the second end of the capacitor element Cap are all grounded.

[0037] It should be noted that the first resistive element R1 and the second resistive element R2 can be the same or different, and this is not limited. When they are the same, it is easier to replace and configure them, which can significantly reduce material costs and subsequent maintenance costs. The resistance values ​​of the first resistive element R1 and the second resistive element R2 can be set according to actual conditions, and their specific values ​​are not limited. For example, the resistance values ​​of the first resistive element R1 and the second resistive element R2 can both be greater than or equal to 25Ω and less than or equal to 100Ω, thereby better ensuring their impedance matching performance. In addition, in this embodiment, the capacitance value of the capacitor element Cap can also be set according to actual needs, and its specific value is not limited. For example, the capacitance value of the capacitor element Cap can be greater than or equal to 10pF and less than or equal to 2.2nF.

[0038] The first surge protection element P1 and the second surge protection element P2 can be the same or different, and there is no limitation on this. When they are the same, it is easier to replace and configure them, which can significantly reduce material costs and subsequent maintenance costs. Both the first surge protection element P1 and the second surge protection element P2 can be solid-state discharge tubes (TSS), gas discharge tubes (GDT), varistors (MOV), or air discharge tubes, etc., and there is no limitation on this. For example, both the first surge protection element P1 and the second surge protection element P2 can be solid-state discharge tubes.

[0039] The non-PoE circuit includes a connector (e.g., an RJ45 connector), with at least one differential pair tap electrically connected to the first end of a first resistor R1, and the remaining differential pairs tap electrically connected to the first end of a second resistor R2. Additionally, the non-PoE circuit may also include a motherboard chip-side PHY IC and a cable side, with the cable side electrically connected to the motherboard chip-side PHY IC via the connector to enable signal transmission between them.

[0040] It should be noted that in some related technologies, surge protection units use a single resistive element. There are two parallel lines between the output end and the ground end of the surge protection unit. One line is a common-mode output line, i.e., output end - resistive element - capacitor element - ground end, which is for electromagnetic shielding to ground noise. The other line is a surge protection line. When encountering a surge (such as a lightning strike), the surge protection element will usually break down and conduct under extremely high voltage (such as hundreds of volts to thousands of volts).

[0041] Under normal circumstances, the current from the transmitting end flows through the common-mode output line. The grounding line, composed of resistors and capacitors, absorbs common-mode energy, while unwanted energy noise flows to ground through the line. Resistors are used for impedance matching; without them, a short circuit may occur. Capacitors prevent noise from the ground terminal from flowing back into the transmitting end. In the event of a surge (such as a lightning strike), the surge protection element breaks down and conducts, allowing the current from the transmitting end to flow through the surge protection line. This protects the chips on the motherboard chip side of non-PoE circuits from being burned out.

[0042] The above technology uses a single resistor element, that is, the taps of the four differential pairs of the non-POE circuit connector are connected in series and then connected to the common-mode output line. When the common-mode output voltage is tested, the common-mode output voltage is the sum of the common-mode output voltages of the four differential pairs. Therefore, the final test result is likely to exceed the rated voltage threshold (e.g., 50mV), causing the circuit to fail to meet the common-mode output voltage test requirements (e.g., the actual requirement is less than 50mV to meet the requirements).

[0043] In other related technologies, in order to improve the problem of common-mode output voltage test failure, the surge protection component is changed to a design of 4 resistors. However, in the case of surge testing, the surge current is prone to burning out the resistors. After the resistors are damaged, the network card chip and other components on the motherboard chip side are easily damaged.

[0044] When designed with four resistive elements, each differential pair's tap is connected to a common-mode output line equipped with a resistive element, forming a total of four common-mode output lines. During common-mode output voltage testing, the actual measured voltage is the output voltage corresponding to each individual differential pair. Since the common-mode output voltage corresponding to each differential pair is extremely small under normal conditions, the measured common-mode output voltage easily meets the requirements.

[0045] However, in this related technology, the four common-mode output lines are independent of each other, and each line normally requires a surge protection line. This arrangement leads to excessive space requirements, potentially causing space shortages, and is also very costly. Therefore, this related technology configures one surge protection line for each of the four common-mode output lines. However, in surge testing, because the large current must first pass through the resistor, the resistor is very prone to burning out. Once the resistor burns out, the surge protection line fails to provide protection, and the components of the PHY IC on the motherboard chip side (non-POE circuit) are easily damaged. Therefore, although this related technology can meet the requirements for common-mode output voltage testing, it cannot meet the requirements for surge testing.

[0046] In this embodiment, in the surge protection unit 100 and the non-POE circuit, the non-POE circuit output terminal (TX) - first resistor element R1 - capacitor element Cap - ground terminal (reference) Figure 1 Alternatively, the ground terminal (or the ground terminal in step 2) forms one common-mode output line. The non-POE circuit's output terminal – first resistor R1 – capacitor Cap – ground terminal form another common-mode output line. That is, this embodiment has two common-mode output lines at the output terminal. During common-mode output voltage testing, the actual measured voltage is the output voltage of each common-mode output line. Since at least one differential pair tap of the connector is electrically connected to the first terminal of the first resistor R1, and the remaining differential pairs tap of the connector are electrically connected to the first terminal of the second resistor R2, the common-mode output voltage of each path is relatively small under normal conditions, and the tested common-mode output voltage easily meets the requirements. In other words, this embodiment, through the above-mentioned setting of two common-mode output lines, can effectively enable the non-POE circuit to meet the requirements for common-mode output voltage testing.

[0047] Furthermore, in this embodiment, since only two independent common-mode output lines are set up, even if a surge protection line is laid for each line, the surge protection level can be improved without occupying too much space, and the cost will not be high. Therefore, this embodiment sets up two surge protection lines. That is, the line where the first surge protection element P1 is located and the line where the second surge protection element P2 is located. With this setting, when a surge (such as a lightning strike) occurs, the corresponding surge protection element is broken down and conducts, and the current at the output end can be transmitted through the surge protection line, thereby protecting the components of the motherboard chip-side PHYIC in the non-POE circuit from being burned out.

[0048] In other words, this embodiment, through the surge protection unit 100, enables non-POE circuits to simultaneously meet the requirements of common-mode output voltage testing and surge testing, while also reducing space occupation and cost to a certain extent. Common-mode output voltage testing can be performed using, for example, IEEE 802.3 (IEEE 802.3 is the core international standard for Ethernet, developed by the Institute of Electrical and Electronics Engineers (IEEE), covering the technical specifications of Ethernet from the physical layer to the data link layer. Its testing content mainly revolves around physical layer (PHY) performance, signal integrity, electromagnetic compatibility (EMC), and compliance, ensuring the compatibility and reliability of equipment under different speeds and topologies). Surge testing can be performed using IEC 61000-4-5 (IEC 61000-4-5 is a standard for electrical fast transient / burst and surge immunity developed by the International Electrotechnical Commission (IEC), specifically targeting the ability of equipment to withstand surges (such as lightning strikes, overvoltages / overcurrents generated by power grid switching operations)). Of course, other testing methods can also be used, and there are no limitations on this.

[0049] It should be noted that the surge protection of this embodiment can be applied to 1G / 2.5G / 5G / 10G Ethernet. For example, it can be integrated inside a high-speed RJ45 connector and used in devices that use Ethernet connections, such as network servers, switches, routers, hubs, game consoles, printers, and personal computers (PCs), to ensure that the Ethernet simultaneously meets the requirements of common-mode output voltage testing and surge testing. Furthermore, it can reduce costs and space requirements for the Ethernet network to a certain extent, facilitating the arrangement of other components within the Ethernet network.

[0050] In some exemplary embodiments, reference is made to Figure 1 and Figure 2 As shown, a surge protection unit 100 and a non-PoE circuit incorporating the surge protection unit 100 are provided. In this embodiment, the connector includes four differential pairs. It should be noted that since the surge protection unit 100 in this embodiment is applied to a non-PoE circuit, there is no need to consider power transmission or the difference between the positive and negative terminals of the four differential pairs connected to the power supply. Therefore, the connection relationship between the taps of the four differential pairs and the surge protection unit 100 can be arbitrarily matched without affecting the surge protection effect.

[0051] For example, refer to Figure 1 As shown, of the four differential pairs of the connector, one differential pair (e.g.) Figure 1 The tap of the differential pair consisting of TX4+ and TX4- is electrically connected to the first terminal of the first resistor element R1, and the taps of the other three differential pairs (e.g., Figure 1The taps of the differential pairs (TX1+ and TX1-, TX2+ and TX2-, and TX3+ and TX3-) are electrically connected to the first terminal of the second resistor R2. In other words, in the two common-mode output lines, one common-mode output line's output terminal is a single differential pair tap, while the other common-mode output line's output terminal is the taps of the remaining three differential pairs out of four.

[0052] For example, refer to Figure 2 As shown, of the four differential pairs in the connector, two differential pairs (e.g.) Figure 2 The taps of the differential pair consisting of TX3+ and TX3-, and the differential pair consisting of TX4+ and TX4-, are electrically connected to the first terminal of the first resistor element R1. The taps of the other two differential pairs (e.g., Figure 2 The taps of the differential pairs (TX1+ and TX1-, and TX2+ and TX2-) are electrically connected to the first terminal of the second resistor R2. That is, in the two common-mode output lines, the output terminal of one common-mode output line is the tap of the two differential pairs, while the output terminal of the other common-mode output line is the tap of the other two differential pairs out of the four differential pairs.

[0053] In this embodiment, by using four differential pairs in any grouping manner such as "1+3" or "2+2" (i.e., some differential pairs are connected to the first resistor element R1, and the rest are connected to the second resistor element R2), there is no need to distinguish between the positive and negative terminals of the power supply (because non-POE circuits have no power transmission requirements). This flexibility allows the circuit to be adapted to connectors of different specifications, improving the compatibility of the surge protection unit 100 and non-POE circuits.

[0054] Additionally, in this embodiment, the common-mode choke of the connector (refer to...) Figure 1 or Figure 2 The magnetic ring of T2 in the connector is wound with two or three wires. That is, the common mode choke of the connector can be in the form of two wires or three wires, and there is no limitation on this.

[0055] This embodiment, through flexible grouping of four differential pairs and multi-wire design of common-mode choke, further enhances the circuit's environmental adaptability, anti-interference capability, and cost advantage while ensuring common-mode voltage compliance and reliable surge protection. It is especially suitable for non-POE circuits of highly Ethernet devices with stringent requirements for compatibility and stability.

[0056] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a specific order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0057] Although terms such as first, second, third, etc., may be used in this document to describe multiple elements, components, regions, layers, and / or segments, these elements, components, regions, layers, and / or segments should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or segment from another. Unless the context clearly indicates otherwise, terms such as "first," "second," and other numerical terms used herein do not imply order or sequence. Therefore, the first element, component, region, layer, or segment discussed below may be referred to as the second element, component, region, layer, or segment without departing from the teachings of the exemplary embodiments.

[0058] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A surge protection unit, characterized by The surge protection unit includes a first resistor element, a second resistor element, a first surge protection element, a second surge protection element, and a capacitor element. The first end of the first surge protection element is electrically connected to the first end of the first resistor element, the first end of the second surge protection element is electrically connected to the first end of the second resistor element, the second ends of the first resistor element and the second ends of the second resistor element are both electrically connected to the first end of the capacitor element, and the second ends of the first surge protection element, the second end of the second surge protection element, and the second end of the capacitor element are all grounded. The surge protection unit is applied to a circuit that does not support Power over Ethernet (PoE) functionality. The circuit that does not support PoE functionality includes a connector, at least one differential pair of the connector is electrically connected to the first end of the first resistor element, and the remaining differential pairs of the connector are electrically connected to the first end of the second resistor element.

2. The surge protection unit of claim 1, wherein, The connector includes four differential pairs, wherein one differential pair has a tap electrically connected to the first end of the first resistive element, and the taps of the other three differential pairs are electrically connected to the first end of the second resistive element, respectively.

3. The surge protection unit of claim 1, wherein, The connector includes four differential pairs, wherein the taps of two differential pairs are electrically connected to the first end of the first resistive element, and the taps of the other two differential pairs are electrically connected to the first end of the second resistive element.

4. The surge protection unit according to claim 1, characterized in that, The first resistive element and the second resistive element are the same; and / or, The first surge protection element is the same as the second surge protection element.

5. The surge protection unit according to claim 1, characterized in that, The first surge protection element includes at least one of the following: a solid-state discharge tube, a gas discharge tube, a varistor, an air discharge tube; and / or, The second surge protection element includes at least one of the following: a solid discharge tube, a gas discharge tube, a varistor, and an air discharge tube.

6. The surge protection unit according to any one of claims 1-5, characterized in that, The resistance of the first resistive element is greater than or equal to 25Ω and less than or equal to 100Ω; and / or, The resistance of the second resistive element is greater than or equal to 25Ω and less than or equal to 100Ω.

7. The surge protection unit according to any of claims 1-5, characterized in that, The capacitance value of the capacitor element is greater than or equal to 10pF and less than or equal to 2.2nF.

8. A circuit that does not support Power over Ethernet (PoE) functionality, characterized in that, The circuit that does not support Power over Ethernet includes a connector and a surge protection unit as described in any one of claims 1-7.

9. The circuit according to claim 8, wherein the circuit does not support a power over Ethernet function, and The common-mode choke of the connector has a magnetic ring made of two or three wires wound together.

10. The circuit according to claim 8 or 9, not supporting the Power over Ethernet function, characterized in that, The circuit that does not support Power over Ethernet includes a motherboard chip side and a cable side, wherein the cable side is electrically connected to the motherboard chip side via the connector.

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