A three-phase inverter suitable for a dSpace simulation bench

Abstract

The utility model relates to steering system technical field, concretely is a kind of three-phase inverter suitable for dSpace simulation bench.The three-phase inverter suitable for dSpace simulation bench, including shell, PCB board, its characterized in that: the top of shell is equipped with acrylic panel, the inside of shell is equipped with PCB board, is equipped with radiator below PCB board, the above of PCB board is connected LCD display screen, the side of PCB board is connected power cord, ground wire, sampling test interface, one end of power cord, ground wire, sampling test interface is connected with PCB board, the other end of power cord, ground wire, sampling test interface is through shell and located the outside of shell.Compared with prior art, provide a kind of three-phase inverter suitable for dSpace simulation bench, can diagnose the input and output of itself;Monitor its operating state, implement protection when necessary;Support fault injection function;Can support in inverter local motor control algorithm.

Description

Technical Field

[0001] This utility model relates to the field of steering system technology, specifically a three-phase inverter suitable for the dSpace simulation test bench. Background Technology

[0002] In the automotive parts industry, brushless DC (BLDC) motors have wide applications. Three-phase DC-AC inverter bridge circuits are the preferred choice for driving three-phase brushless DC motors. Meanwhile, the design of control algorithms for brushless DC motors requires simulation on a test bench before deployment to the product for verification. However, the dSpace test bench itself does not have the capability to directly drive a three-phase motor during bench simulation. Therefore, a device integrating a three-phase DC-AC inverter bridge circuit is needed to assist the simulation bench in driving the motor.

[0003] The three-phase DC-AC inverters currently in use have low intelligence levels. They lack diagnostic capabilities for the PWM waveform output from the dSpace test bench and have no protection functions for their own output terminals. They are often damaged due to illegal operating conditions calculated incorrectly by the dSpace test bench or overheating under high load conditions. Furthermore, they are manufactured using outdated technology, employing single-sided circuit boards, through-hole components, and modular three-phase half-bridges. Damage to a single MOSFET requires replacement of the entire half-bridge module, making maintenance difficult and costly.

[0004] Therefore, it is particularly important to design a three-phase inverter suitable for the dSpace simulation test bench to address the above shortcomings. Summary of the Invention

[0005] To overcome the shortcomings of the prior art, this utility model provides a three-phase inverter suitable for the dSpace simulation bench, which can diagnose its own input and output; monitor its own operating status and implement protection when necessary; support fault injection function; and support running motor control algorithms locally on the inverter.

[0006] To achieve the above objectives, a three-phase inverter suitable for the dSpace simulation bench is designed, comprising a housing and a PCB board. The key features are: an acrylic panel on the top of the housing, a PCB board inside the housing, a heat sink below the PCB board, an LCD display connected above the PCB board, and power lines, ground lines, and sampling test interfaces connected to the sides of the PCB board. One end of each power line, ground line, and sampling test interface is connected to the PCB board, while the other end passes through the housing and is located outside the housing. The PCB board includes a power management chip module, a microprocessor module, a pre-drive chip module, a phase separation controller module, a filter anti-reverse circuit, a dSpace bench interface module, a PWM level conversion circuit module, and an XOR logic... One end of the gate circuit module, LCD screen interface module, power management chip module, and filter anti-reverse circuit is connected to a DC power supply. The other end of the power management chip module is connected to the microprocessor module, pre-driver chip module, phase separator controller module, PWM level conversion circuit module, XOR logic gate circuit module, and LCD screen interface module, respectively, and provides power. The dSpace bench interface module is connected to the pre-driver chip module via the PWM level conversion circuit module. One end of the XOR logic gate circuit module is connected to the PWM level conversion circuit module, and the other end of the XOR logic gate circuit module is connected to the input terminal of the microprocessor module. The output terminal of the microprocessor module is connected to the LCD screen interface module, pre-driver chip module, and phase separator controller module, respectively. The phase separator controller module is connected to the motor drive terminal.

[0007] The power management chip module uses a TLE7368-2E power chip, the microprocessor module uses an STM32F103ZGT6 microprocessor chip, the pre-driver chip module uses a TLE9183OK pre-driver chip, the phase separation controller module uses an A6862KLPTR-T phase separation control chip, the PWM level conversion circuit module uses a TXS0108EQPWRQ1 level conversion chip, the XOR logic gate circuit module uses a first XOR gate circuit chip and a second XOR gate circuit chip of SN74HCS86DR, and the dSpace bench interface module uses a connector of L77SDB25S1ACO4F.

[0008] The CLK_SPI port of the pre-driver chip module is connected to the PA5 port of the microprocessor chip; the CSN port of the pre-driver chip is connected to the PA4 port of the microprocessor chip; the MOSI port of the pre-driver chip is connected to the PA7 port of the microprocessor chip; the MISO port of the pre-driver chip is connected to the PA6 port of the microprocessor chip; the IL1 port of the pre-driver chip is connected to port 8 of the second XOR gate circuit chip; the IH1 port of the pre-driver chip is connected to port 11 of the second XOR gate circuit chip; the IL2 port of the pre-driver chip is connected to port 3 of the second XOR gate circuit chip; the IH2 port of the pre-driver chip is connected to port 6 of the second XOR gate circuit chip; and the IL3 port of the pre-driver chip is connected to port 6 of the first XOR gate circuit chip. The pre-driver chip's IH3 port is connected to port 3 of the first XOR gate circuit chip; the pre-driver chip's SOFF port is connected to the microprocessor chip's PE3 port; the pre-driver chip's INH port is connected to the microprocessor chip's PE4 port; the pre-driver chip's ENA port is connected to the microprocessor chip's PE5 port; the pre-driver chip's ERR port is connected to the microprocessor chip's PE6 port; the pre-driver chip's PFB1 port and the microprocessor chip's PE14 port are combined and connected to port 7 of the dSpace benchtop interface module's connector; the pre-driver chip's PFB2 port and the microprocessor chip's PE10 port are combined and connected to port 8 of the dSpace benchtop interface module's connector; the pre-driver chip's PFB3 port and the microprocessor chip's PE14 port are combined and connected to port 8 of the dSpace benchtop interface module's connector; and the pre-driver chip's PFB3 port and the microprocessor chip's PE14 port are combined and connected to port 7 of the microprocessor chip's connector. The 11-port connector is combined with port 9 of the dSpace rack interface module's connector. The VO1 port of the pre-driver chip is connected to one end of the first resistor. The other end of the first resistor and the PC4 port of the microprocessor chip are combined and connected to port 14 of the dSpace rack interface module's connector. The VO2 port of the pre-driver chip is connected to one end of the second resistor. The other end of the second resistor and the PB0 port of the microprocessor chip are combined and connected to port 15 of the dSpace rack interface module's connector. The VO3 port of the pre-driver chip is connected to one end of the third resistor. The other end of the third resistor and the PB1 port of the microprocessor chip are combined and connected to port 16 of the dSpace rack interface module's connector. The VRO port of the pre-driver chip is connected to... One end of the fourth resistor, the other end of the fourth resistor, and the PC5 port of the microprocessor chip are connected together to port 17 of the wiring plug of the dSpace bench interface module. The GND port, CP_GND port, and AGND port of the pre-driver chip are grounded together. The CH1 port of the pre-driver chip is connected to one end of the first capacitor. The other end of the first capacitor and the CL1 port of the pre-driver chip are connected together to one end of the fifth resistor. The other end of the fifth resistor is grounded. The CH2 port of the pre-driver chip is connected to one end of the second capacitor. The other end of the second capacitor and the CL2 port of the pre-driver chip are connected together to the cathode of the first Zener diode. The anode of the first Zener diode is grounded. The CB port of the pre-driver chip is connected to one end of the third capacitor. The other end of the third capacitor is grounded.The VDH1, VDH2, and VDH3 ports of the pre-driver chip are interconnected; the GH1 port of the pre-driver chip is connected to one end of the sixth resistor, and the other end of the sixth resistor is connected to the gate of the first power transistor; the BH1 port of the pre-driver chip is connected to one end of the seventh resistor, and the other end of the seventh resistor is connected to one end of the fourth capacitor; the SH1 port of the pre-driver chip is connected to one end of the eighth resistor, and the other end of the eighth resistor and the other end of the fourth capacitor are combined and connected to the source of the first power transistor; the GL1 port of the pre-driver chip is connected to one end of the ninth resistor, and the other end of the ninth resistor is connected to the gate of the second power transistor; the SL1 port of the pre-driver chip is connected to one end of the tenth resistor, and the other end of the tenth resistor is connected to the second power transistor. The source of the pre-driver chip; the ISP1 port of the pre-driver chip is connected to one end of the fifth capacitor and one end of the eleventh resistor, the other end of the eleventh resistor is connected to one end of the sixth capacitor, the ISN1 port of the pre-driver chip is connected to the other end of the fifth capacitor and one end of the twelfth resistor, the other end of the twelfth resistor is connected to one end of the seventh capacitor, and the other ends of the sixth and seventh capacitors are grounded together; the GH2 port of the pre-driver chip is connected to one end of the thirteenth resistor, the other end of the thirteenth resistor is connected to the gate of the third power transistor; the BH2 port of the pre-driver chip is connected to one end of the fourteenth resistor, the other end of the fourteenth resistor is connected to one end of the eighth capacitor, the SH2 port of the pre-driver chip is connected to one end of the fifteenth resistor, the tenth... The other end of resistor 5 is combined with the other end of capacitor 8 and connected to the source of power transistor 3; the GL2 port of pre-driver chip is connected to one end of resistor 16, and the other end of resistor 16 is connected to the gate of power transistor 4; the SL2 port of pre-driver chip is connected to one end of resistor 17, and the other end of resistor 17 is connected to the source of power transistor 4; the ISP2 port of pre-driver chip is connected to one end of capacitor 9 and one end of resistor 18, and the other end of resistor 18 is connected to one end of capacitor 10; the ISN2 port of pre-driver chip is connected to the other end of capacitor 9 and one end of resistor 19, and the other end of resistor 19 is connected to one end of capacitor 11; the other ends of capacitors 10 and 11 are connected to each other. The circuit is grounded; the GH3 port of the pre-driver chip is connected to one end of the twentieth resistor, and the other end of the twentieth resistor is connected to the gate of the fifth power transistor; the BH3 port of the pre-driver chip is connected to one end of the twenty-first resistor, and the other end of the twenty-first resistor is connected to one end of the twelfth capacitor; the SH3 port of the pre-driver chip is connected to one end of the twenty-second resistor, and the other end of the twenty-second resistor and the other end of the twelfth capacitor are connected together to the source of the fifth power transistor; the GL3 port of the pre-driver chip is connected to one end of the twenty-third resistor, and the other end of the twenty-third resistor is connected to the gate of the sixth power transistor; the SL3 port of the pre-driver chip is connected to one end of the twenty-fourth resistor, and the other end of the twenty-fourth resistor is connected to the source of the sixth power transistor.The ISP3 port of the pre-driver chip is connected to one end of the thirteenth capacitor and one end of the twenty-fifth resistor, respectively. The other end of the twenty-fifth resistor is connected to one end of the fourteenth capacitor. The ISN3 port of the pre-driver chip is connected to the other end of the thirteenth capacitor and one end of the twenty-sixth resistor, respectively. The other end of the twenty-sixth resistor is connected to one end of the fifteenth capacitor. The other ends of the fourteenth and fifteenth capacitors are grounded together. The two cathodes of the first dual diode are connected to the SH1 and SL1 ports of the pre-driver chip, respectively. The two anodes of the first dual diode are grounded together. The two cathodes of the second dual diode D3 are connected to the SH2 and SL2 ports of the pre-driver chip U3, respectively. The two anodes of the second dual diode D3 are grounded together. The two cathodes of the third dual diode are connected to the SH3 and SL3 ports of the pre-driver chip, respectively. The two anodes of the third dual diode are grounded together. The drain electrodes of the first, third, and fifth power transistors are connected together to the VBAT port. The source of the first power transistor and the drain electrode of the second power transistor are connected together to the phase separation controller module. The source of the third power transistor and the drain electrode of the fourth power transistor are connected together to the phase separation controller module. The source of the fifth power transistor and the drain electrode of the sixth power transistor are connected together to the phase separation controller module. In the controller module, the source of the second power transistor is also connected to the other end of the eleventh resistor and one end of the first fuse resistor. The source of the sixth power transistor is also connected to the other end of the eighteenth resistor and one end of the second fuse resistor. The other end of the first fuse resistor, the other end of the twelfth resistor, the source of the fourth power transistor, the other end of the nineteenth resistor, and the other end of the second fuse resistor are combined and connected to one end of the third fuse resistor and the other end of the twenty-fifth resistor. The other end of the third fuse resistor and the other end of the twenty-sixth resistor are combined and grounded. The VDHP port of the pre-driver chip is connected to one end of the sixteenth capacitor and one end of the twenty-seventh resistor. The other end of the twenty-seventh resistor is connected to the VBAT port. The other end of the sixteenth capacitor is connected to one end of the seventeenth capacitor. The other end of the seventeenth capacitor is grounded. The VS port of the pre-driver chip is connected to one end of the eighteenth capacitor, one end of the nineteenth capacitor, and the VBATF port. The other end of the eighteenth capacitor is connected to one end of the twentieth capacitor. The other end of the nineteenth capacitor is connected to one end of the twenty-first capacitor. The other ends of the twentieth and twenty-first capacitors are combined and grounded. The VCC port of the pre-driver chip is connected to one end of the twenty-second capacitor and the 3.3V voltage. The other end of the twenty-second capacitor is grounded.

[0009] The phase separation controller module's phase separation control chip's VBB port is connected to the VBATF port and one end of the 23rd capacitor. The other end of the 22nd capacitor is connected to the phase separation control chip's VCP port. The phase separation control chip's CP4 port is connected to one end of the 24th capacitor, and the other end of the 24th capacitor is connected to the phase separation control chip's CP3 port. The phase separation control chip's CP2 port is connected to one end of the 25th capacitor, and the other end of the 25th capacitor is connected to the phase separation control chip's CP1 port. The phase separation control chip's IG port is connected to one end of the 28th resistor, and the other end of the 28th resistor is connected to the VBAT port. The phase separation control chip's POK port is connected to the microprocessor chip's PG0 port. The phase separation control chip's ENA port is connected to the microprocessor chip's PG1 port. The phase separation control chip's TAB port and GND port are grounded. The phase separation control chip's SU port is connected to the source of the first power transistor. The drain of the second power transistor and the source of the seventh power transistor are connected to the source of the third power transistor, the drain of the fourth power transistor, and the source of the eighth power transistor, respectively. The SW port of the phase separation control chip is connected to the source of the fifth power transistor, the drain of the sixth power transistor, and the source of the ninth power transistor, respectively. The GU port of the phase separation control chip is connected to one end of the twenty-ninth resistor, and the other end of the twenty-ninth resistor is connected to the gate of the seventh power transistor. The drain of the seventh power transistor is connected to the U terminal of the motor. The GV port of the phase separation control chip is connected to one end of the thirtieth resistor, and the other end of the thirtieth resistor is connected to the gate of the eighth power transistor. The drain of the eighth power transistor is connected to the V terminal of the motor. The GW port of the phase separation control chip is connected to one end of the thirty-first resistor, and the other end of the thirty-first resistor is connected to the gate of the ninth power transistor. The drain of the ninth power transistor is connected to the W terminal of the motor. The VBAT port of the phase separation controller module is interconnected with the VBAT port of the pre-driver chip module.

[0010] The power management chip module's RT port is connected to one end of the 26th capacitor, and the other end of the 26th capacitor and the power chip's GND_A port are grounded together; the RT port of the power chip is connected to the EN_UC port, which is connected to the PC6 port of the microprocessor chip; the EN_IGN port of the power chip is connected to one end of the 32nd resistor, and the other end of the 32nd resistor is connected to the VBATF port; the SEL_STBY port of the power chip is grounded; the C1- port of the power chip is connected to one end of the 27th capacitor, and the other end of the 27th capacitor is connected to the C1+ port of the power chip; the C2- port of the power chip is connected to one end of the 28th capacitor, and the other end of the 28th capacitor... One end is connected to the C2+ port of the power supply chip. The GND_P and GND_A ports of the power supply chip are grounded together. The IN port of the power supply chip is connected to the VBATF port and one end of the 29th capacitor, with the other end of the 29th capacitor grounded. The WDI port of the power supply chip is connected to the PC7 port of the microprocessor chip. The BST port of the power supply chip is connected to one end of the 30th capacitor, with the other end of the 30th capacitor connected to the SW port of the power supply chip. The FB_EXT port of the power supply chip is connected to one end of the 31st capacitor and the DRV_EXT port, with the other end of the 31st capacitor grounded. The IN_STBY port of the power supply chip is connected to the VBATF port. The GND_A port of the chip is grounded. The MON_STBY port of the power supply chip is connected to the PC8 port of the microprocessor chip. The Q_STBY port of the power supply chip is connected to one end of the 32nd capacitor, and the other end of the 32nd capacitor is grounded. The Q_LDO1 port of the power supply chip is connected to one end of the 33rd capacitor, and the other end of the 33rd capacitor is grounded. The SW port of the power supply chip is connected to the cathode of the first diode and one end of the first inductor, respectively. The anode of the first diode is grounded. The other end of the first inductor is connected to one end of the 34th capacitor, one end of the 35th capacitor, one end of the 36th capacitor, one end of the 37th capacitor, one end of the 38th capacitor, and the IN_LDO2 port of the power supply chip. The other ends of capacitors 34, 35, 36, 37, and 38 are connected to ground. The WDO port of the power chip is connected to the PC9 port of the microprocessor chip. The SEL_Q2 port and Q_LDO2 port of the power chip are connected to one end of capacitor 39, and the other end of capacitor 39 is grounded. The CPP port, Q_T2 port, and Q_T1 port of the power chip are connected to one end of capacitor 40, one end of capacitor 41, and one end of capacitor 42, respectively. The other ends of capacitors 40, 41, and 42 and the GND_A port of the power chip are connected to ground.The RO_2 port of the source chip is connected to one end of the 33rd resistor and the PA8 port of the microprocessor chip, respectively. The RO_1 port of the source chip is connected to one end of the 34th resistor and the PA9 port of the microprocessor chip, respectively. The other ends of the 33rd and 34th resistors are connected together to a 3.3V voltage. The VBATF port of the power management chip module is interconnected with the VBATF ports of the pre-driver chip module and the phase separation controller module.

[0011] The A1 port of the level conversion chip in the PWM level conversion circuit module is connected to the PE8 port of the microprocessor chip and the 4th port of the first XOR gate chip, respectively. The first VCCA port of the level conversion chip is connected to the 3.3V voltage, the OE port of the level conversion chip, and one end of the 43rd capacitor, with the other end of the 43rd capacitor grounded. The A2 port of the level conversion chip is connected to the PE9 port of the microprocessor chip and the 1st port of the first XOR gate chip, the A3 port of the level conversion chip is connected to the PE10 port of the microprocessor chip and the 1st port of the second XOR gate chip, and the A4 port of the level conversion chip is connected to the PE11 port of the microprocessor chip and the 4th port of the second XOR gate chip, respectively. Port A5 is connected to port PE12 of the microprocessor chip and port 9 of the second XOR gate chip. Port A6 of the level conversion chip is connected to port PE13 of the microprocessor chip and port 12 of the second XOR gate chip. Ports A7 and A8 of the level conversion chip are grounded together. Ports B1, B2, B3, B4, B5, and B6 of the level conversion chip are connected to ports 1 to 6 of the wiring plug of the dSpace bench interface module. Ports B7 and B8 of the level conversion chip are grounded together. The GND port of the level conversion chip is grounded. The second VCCA port of the level conversion chip is connected to a 5.0V voltage and one end of the forty-fourth capacitor. The other end of the forty-fourth capacitor is grounded.

[0012] The XOR logic gate module has the following connections: port 2 of the first XOR gate chip is connected to port PG7 of the microprocessor chip; port 5 of the first XOR gate chip is connected to port PG6 of the microprocessor chip; port 8 of the first XOR gate chip is connected to one end of the 35th resistor, the other end of the 35th resistor is grounded; port 11 of the first XOR gate chip is connected to one end of the 36th resistor, the other end of the 36th resistor is grounded; and port 14 of the first XOR gate chip is connected to a 3.3V voltage source and one end of the 45th capacitor, the other end of the 45th capacitor is grounded. The 7th port of the first XOR gate chip is grounded; the 2nd port of the second XOR gate chip is connected to the PG4 port of the microprocessor chip; the 5th port of the second XOR gate chip is connected to the PG5 port of the microprocessor chip; the 10th port of the second XOR gate chip is connected to the PG2 port of the microprocessor chip; the 13th port of the second XOR gate chip is connected to the PG3 port of the microprocessor chip; the 14th port of the second XOR gate chip is connected to a 3.3V voltage and one end of the 46th capacitor, the other end of the 46th capacitor is grounded; and the 7th port of the second XOR gate chip is grounded.

[0013] The LCD screen interface module includes wiring pins and a switch. Pin 1 of the LCD screen interface module is connected to 3.3V, pin 2 is grounded, pin 3 is connected to the PB12 port of the microprocessor chip, and pin 4 is connected to the PD12 port of the microprocessor chip, pins 1 and 2 of the first switch, one end of the 37th resistor, and one end of the 47th capacitor. The other end of the 37th resistor is connected to 3.3V. The other end of the seventeen capacitors is grounded by connecting to ports 3 and 4 of the first switch; port 5 of the LCD screen interface module is connected to port PD13 of the microprocessor chip, port 6 of the LCD screen interface module is connected to port PB15 of the microprocessor chip, port 7 of the LCD screen interface module is connected to port PB13 of the microprocessor chip, port 8 of the LCD screen interface module is connected to port PD14 of the microprocessor chip, and port 9 of the LCD screen interface module is connected to port PB14 of the microprocessor chip.

[0014] The microprocessor module's microprocessor chip's PA11 port is connected to port 11 of the dSpace bench interface module's connector; its PA12 port is connected to port 12 of the dSpace bench interface module's connector; its PC1 port is connected to one end of the 38th resistor, and the other end of the 38th resistor is connected to the power chip's Q_STBY port; its PD8, PD9, PD10, and PD11 ports are each connected to four LEDs; its PF6 port is connected to port 19 of the dSpace bench interface module's connector; a crystal oscillator is connected between the microprocessor chip's OSC_IN and OSC_OUT ports; and its NRST port is connected to ports 1 and 2 of the second switch, one end of the 39th resistor, one end of the 48th capacitor, and the other end of the 39th resistor. Connect to a 3.3V voltage. The other end of the 48th capacitor is grounded together with ports 3 and 4 of the second switch. The VSS_1 to VSS_11 ports, VSSA port, and VREF- port of the microprocessor chip are grounded together. The VDD_1 to VDD_11 ports, VDDA port, and VBAT port of the microprocessor chip are connected together to one end of the 49th, 50th, 51st, 52nd, 53rd, 54th, 55th, 56th, 57th, 58th, 59th, 60th, and 61st capacitors. The other ends of the 49th, 50th, 51st, 52nd, 53rd, 54th, 55th, 56th, 57th, 58th, 59th, 60th, and 61st capacitors are grounded together.

[0015] The aforementioned filtering and anti-reverse circuit includes a second inductor. One end of the second inductor is connected to the motor, and the other end is connected to one end of capacitors 62, 63, 64, 65, 66, 67, 68, and 69, the VBAT port of the phase separation controller module and the pre-drive chip module, and the anode of a second diode. The cathode of the second diode is connected to the VBATF port of the power management chip module, the pre-drive chip module, and the phase separation controller module, respectively. The other end of capacitor 62 is connected to one end of resistors 40 and 41, and the other ends of resistors 40 and 41 are grounded together. The other end of capacitor 63 is connected to one end of capacitor 70, and the other end of capacitor 70 is grounded. The other ends of capacitors 64 and 65 are grounded together. The other ends of capacitors 66, 67, 68, and 69 are grounded together.

[0016] Compared with the prior art, this utility model provides a three-phase inverter suitable for the dSpace simulation bench, which can diagnose its own input and output; monitor its own operating status and implement protection when necessary; support fault injection function; and support running motor control algorithms locally on the inverter. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of the three-phase inverter of this utility model.

[0018] Figure 2 This is a circuit block diagram of the three-phase inverter of this utility model.

[0019] Figure 3 This is a schematic diagram of the circuit connection of the pre-drive chip module in the three-phase inverter of this utility model.

[0020] Figure 4 This is a schematic diagram of the circuit connection of the phase separation controller module in the three-phase inverter of this utility model.

[0021] Figure 5 This is a schematic diagram of the power management chip module circuit connection in the three-phase inverter of this utility model.

[0022] Figure 6 This is a schematic diagram of the PWM level conversion circuit module in the three-phase inverter of this utility model.

[0023] Figure 7 This is a schematic diagram of the XOR logic gate circuit module in the three-phase inverter of this utility model.

[0024] Figure 8 This is a schematic diagram of the circuit connection of the LCD screen interface module in the three-phase inverter of this utility model.

[0025] Figure 9 This is a schematic diagram of the microprocessor module circuit connection in the three-phase inverter of this utility model.

[0026] Figure 10 This is a schematic diagram of the circuit connection of the filter anti-reverse circuit module in the three-phase inverter of this utility model.

[0027] Figure 11 This is a schematic diagram of the circuit connection of the dSpace benchtop interface module in the three-phase inverter of this utility model. Detailed Implementation

[0028] The present invention will be further described below with reference to the accompanying drawings.

[0029] like Figures 1 to 11As shown, the top of the housing 4 is provided with an acrylic panel 2, and the interior of the housing 4 is provided with a PCB board 3. A heat sink is located below the PCB board 3. An LCD display screen 1 is connected to the top of the PCB board 3. A power cord 5, a ground wire 6, and a sampling test interface 7 are connected to the side of the PCB board 3. One end of the power cord 5, ground wire 6, and sampling test interface 7 is connected to the PCB board 3, and the other end of the power cord 5, ground wire 6, and sampling test interface 7 passes through the housing 4 and is located outside the housing 4. The PCB board 3 includes a power management chip module, a microprocessor module, a pre-drive chip module, a phase separation controller module, a filter anti-reverse circuit, a dSpace bench interface module, a PWM level conversion circuit module, an XOR logic gate circuit module, and an LCD screen. One end of the interface module, power management chip module, and filter anti-reverse circuit is connected to a DC power supply. The other end of the power management chip module is connected to the microprocessor module, pre-driver chip module, phase separation controller module, PWM level conversion circuit module, XOR logic gate circuit module, and LCD screen interface module, respectively, and provides power. The dSpace bench interface module is connected to the pre-driver chip module via the PWM level conversion circuit module. One end of the XOR logic gate circuit module is connected to the PWM level conversion circuit module, and the other end of the XOR logic gate circuit module is connected to the input terminal of the microprocessor module. The output terminal of the microprocessor module is connected to the LCD screen interface module, pre-driver chip module, and phase separation controller module, respectively. The phase separation controller module is connected to the motor drive terminal.

[0030] The power management chip module uses power chip U5 of model TLE7368-2E, the microprocessor module uses microprocessor chip U1 of model STM32F103ZGT6, the pre-driver chip module uses pre-driver chip U3 of model TLE9183OK, the phase separation controller module uses phase separation control chip U2 of model A6862KLPTR-T, the PWM level conversion circuit module uses level conversion chip U4 of model TXS0108EQPWRQ1, the XOR logic gate circuit module uses first XOR gate circuit chip U6 and second XOR gate circuit chip U7 of model SN74HCS86DR, and the dSpace bench interface module uses connector P1 of model L77SDB25S1ACO4F.

[0031] The CLK_SPI port of the pre-driver chip U3 is connected to the PA5 port of the microprocessor chip U1; the CSN port of the pre-driver chip U3 is connected to the PA4 port of the microprocessor chip U1; the MOSI port of the pre-driver chip U3 is connected to the PA7 port of the microprocessor chip U1; the MISO port of the pre-driver chip U3 is connected to the PA6 port of the microprocessor chip U1; the IL1 port of the pre-driver chip U3 is connected to the 8th port of the second XOR gate circuit chip U7; the IH1 port of the pre-driver chip U3 is connected to the 11th port of the second XOR gate circuit chip U7; the IL2 port of the pre-driver chip U3 is connected to the 3rd port of the second XOR gate circuit chip U7; and the IH2 port of the pre-driver chip U3 is connected to the second XOR gate circuit chip U7. Port 6 of gate chip U7 and port IL3 of pre-driver chip U3 are connected to port 6 of the first XOR gate chip U6. Port IH3 of pre-driver chip U3 is connected to port 3 of the first XOR gate chip U6. Port SOFF of pre-driver chip U3 is connected to port PE3 of microprocessor chip U1. Port INH of pre-driver chip U3 is connected to port PE4 of microprocessor chip U1. Port ENA of pre-driver chip U3 is connected to port PE5 of microprocessor chip U1. Port ERR of pre-driver chip U3 is connected to port PE6 of microprocessor chip U1. Port PFB1 of pre-driver chip U3 and port PE14 of microprocessor chip U1 are connected together to the wiring plug of the dSpace bench interface module. Port 7 of P1, PFB2 port of pre-driver chip U3, and PE10 port of microprocessor chip U1 are combined and connected to the wiring connector of the dSpace bench interface module. Port 8 of P1, PFB3 port of pre-driver chip U3, and PE11 port of microprocessor chip U1 are combined and connected to the wiring connector of the dSpace bench interface module. Port 9 of P1, VO1 port of pre-driver chip U3 is connected to one end of the first resistor R43, and the other end of the first resistor R43 and PC4 port of microprocessor chip U1 are combined and connected to the wiring connector of the dSpace bench interface module. Port 14 of P1, VO2 port of pre-driver chip U3 is connected to one end of the second resistor R44, and the other end of the second resistor R44 is connected to the wiring connector of the dSpace bench interface module. The PB0 port of the pre-drive chip U1 and the microprocessor chip U1 are connected together to port 15 of the wiring plug P1 of the dSpace bench interface module. The VO3 port of the pre-drive chip U3 is connected to one end of the third resistor R45. The other end of the third resistor R45 and the PB1 port of the microprocessor chip U1 are connected together to port 16 of the wiring plug P1 of the dSpace bench interface module. The VRO port of the pre-drive chip U3 is connected to one end of the fourth resistor R46. The other end of the fourth resistor R46 and the PC5 port of the microprocessor chip U1 are connected together to port 17 of the wiring plug P1 of the dSpace bench interface module. The GND port, CP_GND port, and AGND port of the pre-drive chip U3 are grounded together.The pre-driver chip U3's CH1 port is connected to one end of the first capacitor C24. The other end of the first capacitor C24, together with the pre-driver chip U3's CL1 port, is connected to one end of the fifth resistor R26, and the other end of the fifth resistor R26 is grounded. The pre-driver chip U3's CH2 port is connected to one end of the second capacitor C23. The other end of the second capacitor C23, together with the pre-driver chip U3's CL2 port, is connected to the cathode of the first Zener diode D5, and the anode of the first Zener diode D5 is grounded. The pre-driver chip U3's CB port is connected to one end of the third capacitor C25, and the other end of the third capacitor C25 is grounded. The pre-driver chip U3's VDH1, VDH2, and VDH3 ports... Interconnection: The GH1 port of pre-driver chip U3 is connected to one end of the sixth resistor R5, and the other end of the sixth resistor R5 is connected to the gate of the first power transistor Q1; the BH1 port of pre-driver chip U3 is connected to one end of the seventh resistor R6, and the other end of the seventh resistor R6 is connected to one end of the fourth capacitor C11; the SH1 port of pre-driver chip U3 is connected to one end of the eighth resistor R7, and the other end of the eighth resistor R7 and the other end of the fourth capacitor C11 are combined and connected to the source of the first power transistor Q1; the GL1 port of pre-driver chip U3 is connected to one end of the ninth resistor R8, and the other end of the ninth resistor R8 is connected to the gate of the second power transistor Q5; the SL1 port of pre-driver chip U3 is connected to the tenth resistor R9. One end of the tenth resistor R9 is connected to the source of the second power transistor Q5; the ISP1 port of the pre-driver chip U3 is connected to one end of the fifth capacitor C12 and one end of the eleventh resistor R10, and the other end of the eleventh resistor R10 is connected to one end of the sixth capacitor C15; the ISN1 port of the pre-driver chip U3 is connected to the other end of the fifth capacitor C12 and one end of the twelfth resistor R11, and the other end of the twelfth resistor R11 is connected to one end of the seventh capacitor C14; the other ends of the sixth capacitor C15 and the seventh capacitor C14 are grounded together; the GH2 port of the pre-driver chip U3 is connected to one end of the thirteenth resistor R12, and the other end of the thirteenth resistor R12 is connected to the third power transistor Q5. The gate of power transistor Q2; the BH2 port of pre-driver chip U3 is connected to one end of the fourteenth resistor R13, the other end of the fourteenth resistor R13 is connected to one end of the eighth capacitor C13, the SH2 port of pre-driver chip U3 is connected to one end of the fifteenth resistor R14, the other end of the fifteenth resistor R14 and the other end of the eighth capacitor C13 are combined and connected to the source of the third power transistor Q2; the GL2 port of pre-driver chip U3 is connected to one end of the sixteenth resistor R15, the other end of the sixteenth resistor R15 is connected to the gate of the fourth power transistor Q6; the SL2 port of pre-driver chip U3 is connected to one end of the seventeenth resistor R16, the other end of the seventeenth resistor R16 is connected to the source of the fourth power transistor Q6;The ISP2 port of the pre-driver chip U3 is connected to one end of the ninth capacitor C16 and one end of the eighteenth resistor R17. The other end of the eighteenth resistor R17 is connected to one end of the tenth capacitor C18. The ISN2 port of the pre-driver chip U3 is connected to the other end of the ninth capacitor C16 and one end of the nineteenth resistor R18. The other end of the nineteenth resistor R18 is connected to one end of the eleventh capacitor C19. The other ends of the tenth capacitor C18 and the eleventh capacitor C19 are grounded together. The GH3 port of the pre-driver chip U3 is connected to one end of the twentieth resistor R19. The twentieth resistor R1... The other end of 9 is connected to the gate of the fifth power transistor Q3; the BH3 port of the pre-driver chip U3 is connected to one end of the twenty-first resistor R20, the other end of the twenty-first resistor R20 is connected to one end of the twelfth capacitor C17, the SH3 port of the pre-driver chip U3 is connected to one end of the twenty-second resistor R21, the other end of the twenty-second resistor R21 and the other end of the twelfth capacitor C17 are combined and connected to the source of the fifth power transistor Q3; the GL3 port of the pre-driver chip U3 is connected to one end of the twenty-third resistor R22, the other end of the twenty-third resistor R22 is connected to the gate of the sixth power transistor Q7. The SL3 port of the pre-driver chip U3 is connected to one end of the 24th resistor R23, and the other end of the 24th resistor R23 is connected to the source of the 6th power transistor Q7; the ISP3 port of the pre-driver chip U3 is connected to one end of the 13th capacitor C20 and one end of the 25th resistor R24, and the other end of the 25th resistor R24 ​​is connected to one end of the 14th capacitor C21; the ISN3 port of the pre-driver chip U3 is connected to the other end of the 13th capacitor C20 and one end of the 26th resistor R25, and the other end of the 26th resistor R25 is connected to the 15th capacitor C22. At one end, the other ends of the fourteenth capacitor C21 and the fifteenth capacitor C22 are grounded together; the two cathodes of the first dual diode D2 are connected to the SH1 port and SL1 port of the pre-driver chip U3 respectively, and the two anodes of the first dual diode D2 are grounded together; the two cathodes of the second dual diode D3 are connected to the SH2 port and SL2 port of the pre-driver chip U3 respectively, and the two anodes of the second dual diode D3 are grounded together; the two cathodes of the third dual diode D4 are connected to the SH3 port and SL3 port of the pre-driver chip U3 respectively, and the two anodes of the third dual diode D4 are grounded together.The drain electrodes of the first power transistor Q1, the third power transistor Q2, and the fifth power transistor Q3 are connected together to the VBAT port. The source electrode of the first power transistor Q1 and the drain electrode of the second power transistor Q5 are connected together to the phase separation controller module. The source electrode of the third power transistor Q2 and the drain electrode of the fourth power transistor Q6 are connected together to the phase separation controller module. The source electrode of the fifth power transistor Q3 and the drain electrode of the sixth power transistor Q7 are connected together to the phase separation controller module. The source electrode of the second power transistor Q5 is also connected to the other end of the eleventh resistor R10 and one end of the first fuse resistor F1. The source electrode of the sixth power transistor Q7 is also connected to the other end of the eighteenth resistor R17 and one end of the second fuse resistor F3. The other end of the first fuse resistor F1, the other end of the twelfth resistor R11, the source electrode of the fourth power transistor Q6, the other end of the nineteenth resistor R18, and the other end of the second fuse resistor F3 are connected together to one end of the third fuse resistor F2 and the twenty-fifth resistor R24. At the other end, the other end of the third fuse resistor F2 and the other end of the twenty-sixth resistor R25 are grounded together; the VDHP port of the pre-driver chip U3 is connected to one end of the sixteenth capacitor C8 and one end of the twenty-seventh resistor R2, the other end of the twenty-seventh resistor R2 is connected to the VBAT port, the other end of the sixteenth capacitor C8 is connected to one end of the seventeenth capacitor C10, and the other end of the seventeenth capacitor C10 is grounded; the VS port of the pre-driver chip U3 is connected to one end of the eighteenth capacitor C2, one end of the nineteenth capacitor C3, and the VBATF port, the other end of the eighteenth capacitor C2 is connected to one end of the twentieth capacitor C4, the other end of the nineteenth capacitor C3 is connected to one end of the twenty-first capacitor C5, and the other ends of the twentieth capacitor C4 and the twenty-first capacitor C5 are grounded together; the VCC port of the pre-driver chip U3 is connected to one end of the twenty-second capacitor C7 and the 3.3V voltage, the other end of the twenty-second capacitor C7 is grounded.

[0032] GateDriverUnit (GDU): This module uses the recommended circuitry for the GateDriver Unit U3 and adds corresponding current-limiting resistors to the connection lines between the GateDriver Unit U3 and the three-phase bridge MOS to prevent damage to the GateDriver Unit U3 caused by MOSFET turn-on current surges. A TVS diode is added to the input lines to the MOS source stage to prevent damage to the GateDriver Unit U3 from static electricity introduced by the external power supply. The three current sampling interfaces are connected to the sampling resistors on the U-phase, W-phase, and the sampling resistor for the total three-phase current, respectively.

[0033] The VBB port of the phase separation control chip U2 in the phase separation controller module is connected to the VBATF port and one end of the 23rd capacitor C1. The other end of the 22nd capacitor C1 is connected to the VCP port of the phase separation control chip U2. The CP4 port of the phase separation control chip U2 is connected to one end of the 24th capacitor C6. The other end of the 24th capacitor C6 is connected to the CP3 port of the phase separation control chip U2. The CP2 port of the phase separation control chip U2 is connected to one end of the 25th capacitor C9. The other end of the 25th capacitor C9 is connected to the CP1 port of the phase separation control chip U2. The IG port of the phase separation control chip U2 is connected to one end of the 28th resistor R42. The other end of the 28th resistor R42 is connected to the VBAT port. The POK port of the phase separation control chip U2 is connected to the PG0 port of the microprocessor chip U1. The ENA port of the phase separation control chip U2 is connected to the PG1 port of the microprocessor chip U1. The TAB port and GND port of the phase separation control chip U2 are grounded. The SU port of the phase separation control chip U2 is connected to the source of the first power transistor Q1 and the second power transistor Q2. The drain electrode of transistor Q5 and the source of the seventh power transistor Q4 are connected to the source of the third power transistor Q2, the drain electrode of the fourth power transistor Q6, and the source of the eighth power transistor Q8, respectively. The SW port of the phase separation control chip U2 is connected to the source of the fifth power transistor Q3, the drain electrode of the sixth power transistor Q7, and the source of the ninth power transistor Q9, respectively. The GU port of the phase separation control chip U2 is connected to one end of the twenty-ninth resistor R1, and the other end of the twenty-ninth resistor R1 is connected to the gate of the seventh power transistor Q4. The drain electrode of the seventh power transistor Q4 is connected to the source of the seventh power transistor Q4. The phase separation control chip U2 is connected to the U terminal of the motor. The GV port of the phase separation control chip U2 is connected to one end of the thirtieth resistor R3. The other end of the thirtieth resistor R3 is connected to the gate of the eighth power transistor Q8. The drain of the eighth power transistor Q8 is connected to the V terminal of the motor. The GW port of the phase separation control chip U2 is connected to one end of the thirty-first resistor R4. The other end of the thirty-first resistor R4 is connected to the gate of the ninth power transistor Q9. The drain of the ninth power transistor Q9 is connected to the W terminal of the motor. The VBAT port of the phase separation controller module is interconnected with the VBAT port of the pre-drive chip module.

[0034] Phase Separation Control (PSC) module: This module is required to enable emergency avoidance in the event of a motor failure, disconnecting the three-phase windings to prevent electrical lock-up, and simulating the function of the steering ECU. This module is controlled by a phase separation control chip U2, which is enabled by the microprocessor module. Similar to the pre-drive chip module, resistors are connected in series on the lines connecting the phase separation control chip U2 and the MOS to protect the phase separation control chip U2 from damage caused by current surges.

[0035] The RT port of power chip U5 in the power management chip module is connected to one end of the 26th capacitor C37. The other end of the 26th capacitor C37 and the GND_A port of power chip U5 are grounded together. The RT port of power chip U5 is connected to the EN_UC port, which is connected to the PC6 port of microprocessor chip U1. The EN_IGN port of power chip U5 is connected to one end of the 32nd resistor R61. The other end of the 32nd resistor R61 is connected to the VBATF port. The SEL_STBY port of power chip U5 is grounded. The C1- port of power chip U5 is connected to one end of the 27th capacitor C38. The other end of the 27th capacitor C38 is connected to the C1+ port of power chip U5. The C2- port of power chip U5 is connected to... One end of the 28th capacitor C41 is connected to the C2+ port of power chip U5. The GND_P and GND_A ports of power chip U5 are grounded together. The IN port of power chip U5 is connected to the VBATF port and one end of the 29th capacitor C50. The other end of the 29th capacitor C50 is grounded. The WDI port of power chip U5 is connected to the PC7 port of microprocessor chip U1. The BST port of power chip U5 is connected to one end of the 30th capacitor C52. The other end of the 30th capacitor C52 is connected to the SW port of power chip U5. The FB_EXT port of power chip U5 is connected to one end of the 31st capacitor C54 and the DRV_EXT port of power chip U5. The other end of the 31st capacitor C54 is grounded; the IN_STBY port of power chip U5 is connected to the VBATF port, the GND_A port of power chip U5 is grounded, the MON_STBY port of power chip U5 is connected to the PC8 port of microprocessor chip U1, the Q_STBY port of power chip U5 is connected to one end of the 32nd capacitor C40, and the other end of the 32nd capacitor C40 is grounded; the Q_LDO1 port of power chip U5 is connected to one end of the 33rd capacitor C39, and the other end of the 33rd capacitor C39 is grounded; the SW port of power chip U5 is connected to the cathode of the first diode D6 and one end of the first inductor L2, respectively, the anode of the first diode D6 is grounded, and the other end of the first inductor L2 is... Connect one end of capacitor C42 (34th), one end of capacitor C43 (35th), one end of capacitor C44 (36th), one end of capacitor C45 (37th), one end of capacitor C46 (38th), to the IN_LDO2 port and the FB / L_IN port of power chip U5 respectively. Connect the other ends of capacitors C42, C43, C44, C45, and C46 together to ground. Connect the WDO port of power chip U5 to the PC9 port of microprocessor chip U1. Connect the SEL_Q2 port and Q_LDO2 port of power chip U5 together to one end of capacitor C51 (39th). Connect the other end of capacitor C51 to ground.The CPP, Q_T2, and Q_T1 ports of power chip U5 are connected to one end of the 40th capacitor C47, one end of the 41st capacitor C48, and one end of the 42nd capacitor C49, respectively. The other ends of the 40th capacitor C47, 41st capacitor C48, and 42nd capacitor C49 are connected to the GND_A port of power chip U5 and grounded. The RO_2 port of source chip U5 is connected to one end of the 33rd resistor R39 and the PA8 port of microprocessor chip U1, respectively. The RO_1 port of source chip U5 is connected to one end of the 34th resistor R40 and the PA9 port of microprocessor chip U1, respectively. The other ends of the 33rd resistor R39 and the 34th resistor R40 are connected to a 3.3V voltage. The VBATF port of the power management chip module is interconnected with the VBATF ports of the pre-driver chip module and the phase separation controller module.

[0036] The power management chip module (System Basic Chip, SBC) accepts DC power input with an input voltage range of 4.5~45V and a standard input voltage of 12V. The SBC outputs a 3.3V supply voltage to power the microprocessor module, pre-driver chip module, PWM level conversion circuit module, and LCD screen interface module; and a 5V supply voltage to power the PWM level conversion circuit module. A watchdog output is connected to the microprocessor module via WDI, and a watchdog input is connected to WDO, forming a watchdog feeding circuit. The microprocessor module periodically feeds the watchdog to monitor its operating status and provide feedback. RO1 and RO2 are connected to the microprocessor module's input I / O, outputting reset signals for LDO1 and LDO2. Since this invention does not involve wake-up management, the IGN (ignition) enable signal is directly connected to the main power supply, synchronously waking up the power chip U5 of the power management chip module each time power is applied. The remaining power supply circuits are built according to the chip's recommended circuit design.

[0037] The A1 port of the level conversion chip U4 in the PWM level conversion circuit module is connected to the PE8 port of the microprocessor chip U1 and the 4th port of the first XOR gate chip U6, respectively. The first VCCA port of the level conversion chip U4 is connected to the 3.3V voltage, the OE port of the level conversion chip U4, and one end of the 43rd capacitor C35, with the other end of the 43rd capacitor C35 grounded. The A2 port of the level conversion chip U4 is connected to the PE9 port of the microprocessor chip U1 and the 1st port of the first XOR gate chip U6, respectively. The A3 port of the level conversion chip U4 is connected to the PE10 port of the microprocessor chip U1 and the 1st port of the second XOR gate chip U7, respectively. The A4 port of the level conversion chip U4 is connected to the PE11 port of the microprocessor chip U1 and the 4th port of the second XOR gate chip U7, respectively. Port A5 of chip 4 is connected to port PE12 of microprocessor chip U1 and port 9 of the second XOR gate chip U7. Port A6 of level conversion chip U4 is connected to port PE13 of microprocessor chip U1 and port 12 of the second XOR gate chip U7. Ports A7 and A8 of level conversion chip U4 are grounded together. Ports B1, B2, B3, B4, B5, and B6 of level conversion chip U4 are connected to ports 1 to 6 of the wiring plug P1 of the dSpace bench interface module. Ports B7 and B8 of level conversion chip U4 are grounded together. Port GND of level conversion chip U4 is grounded. Port VCCA of level conversion chip U4 is connected to a 5.0V voltage and one end of capacitor C36. The other end of capacitor C36 is grounded.

[0038] PWM Level Conversion Circuit Module: An 8-channel level conversion chip U4 is selected to convert the six 5V PWM signals output from the dSpace test bench into six 3.3V PWM signals so that the pre-driver chip module powered by 3.3V logic can correctly identify the PWM signals output from the dSpace test bench.

[0039] The XOR logic gate module has the following connections: Port 2 of the first XOR gate chip U6 is connected to port PG7 of the microprocessor chip U1; Port 5 of the first XOR gate chip U6 is connected to port PG6 of the microprocessor chip U1; Port 8 of the first XOR gate chip U6 is connected to one end of the 35th resistor R65, with the other end of the 35th resistor R65 grounded; Port 11 of the first XOR gate chip U6 is connected to one end of the 36th resistor R66, with the other end of the 36th resistor R66 grounded; and Port 14 of the first XOR gate chip U6 is connected to a 3.3V voltage source and one end of the 45th capacitor C102, with the other end of the 45th capacitor C102 grounded. The first XOR gate chip U6 has its 7th port grounded; the second XOR gate chip U7 has its 2nd port connected to the PG4 port of the microprocessor chip U1, its 5th port connected to the PG5 port of the microprocessor chip U1, its 10th port connected to the PG2 port of the microprocessor chip U1, its 13th port connected to the PG3 port of the microprocessor chip U1, its 14th port connected to a 3.3V voltage and one end of the 46th capacitor C101, the other end of the 46th capacitor C101 grounded, and its 7th port grounded.

[0040] XOR logic gate module: Two four-channel XOR gate chips, U6 and U7, are used to perform logic toggling operations on the PWM signal. Since the PWM input required by the pre-driver chip module is a negative logic for the control signal of the low-side MOS, while the logic output of the dSpace test bench is a normal logic, it is necessary to toggle the control signal of the low-side MOS provided by the dSpace test bench. One end of the XOR logic gate module is connected to the PWM signal, and the other end is connected to the microprocessor module. To ensure the synchronization of the PWM signal, all six PWM signals will pass through the XOR logic gate module. On the gates of the PWM signal that need to be toggled, the microprocessor module inputs a "1" logic, and the PWM signal is toggled. On the gates of the PWM signal that need to remain unchanged, the microprocessor module inputs a "0" logic, and the PWM signal remains unchanged.

[0041] The LCD screen interface module includes wiring pins and switches. Pin 1 of the LCD screen interface module is connected to 3.3V, pin 2 of the LCD screen interface module is grounded, pin 3 of the LCD screen interface module is connected to port PB12 of the microprocessor chip U1, pin 4 of the LCD screen interface module is connected to port PD12 of the microprocessor chip U1, ports 1 and 2 of the first switch SW2, one end of the thirty-seventh resistor R50, and one end of the forty-seventh capacitor C70. The other end of the thirty-seventh resistor R50 is connected to 3.3V, and the forty-seventh capacitor... The other end of capacitor C70 is grounded together with ports 3 and 4 of the first switch SW2; port 5 of the LCD screen interface module's connector P12 is connected to port PD13 of the microprocessor chip U1, port 6 of the LCD screen interface module's connector P12 is connected to port PB15 of the microprocessor chip U1, port 7 of the LCD screen interface module's connector P12 is connected to port PB13 of the microprocessor chip U1, port 8 of the LCD screen interface module's connector P12 is connected to port PD14 of the microprocessor chip U1, and port 9 of the LCD screen interface module's connector P12 is connected to port PB14 of the microprocessor chip U1.

[0042] LCD screen interface module: Uses a 9-pin connector as the interface for the LCD display, including 3.3V power supply to the LCD, SPI bus data transmission, and other functional I / O. A reset button is also provided for manual reset in case of malfunction.

[0043] The PA11 port of the microprocessor chip U1 of the microprocessor module is connected to port 11 of the wiring connector P1 of the dSpace bench interface module; the PA12 port of the microprocessor chip U1 is connected to port 12 of the wiring connector P1 of the dSpace bench interface module; the PC1 port of the microprocessor chip U1 is connected to one end of the 38th resistor R35; the other end of the 38th resistor R35 is connected to the Q_STBY port of the power chip U5; the PD8, PD9, PD10, and PD11 ports of the microprocessor chip U1 are respectively... Connect four LEDs; connect the PF6 port of microprocessor chip U1 to port 19 of the wiring plug P1 of the dSpace bench interface module; connect crystal oscillator X1 between the OSC_IN and OSC_OUT ports of microprocessor chip U1; connect the NRST port of microprocessor chip U1 to ports 1 and 2 of the second switch SW1, one end of the thirty-ninth resistor R41, and one end of the forty-eighth capacitor C100; connect the other end of the thirty-ninth resistor R41 to a 3.3V voltage; connect the other end of the forty-eighth capacitor C100 to... The third and fourth ports of the second switch SW1 are grounded together; the VSS_1 to VSS_11 ports, the VSSA port, and the VREF- port of the microprocessor chip U1 are grounded together; the VDD_1 to VDD_11 ports, the VDDA port, and the VBAT port of the microprocessor chip U1 are connected together to the forty-ninth capacitor C55, the fiftieth capacitor C56, the fifty-first capacitor C57, the fifty-second capacitor C58, the fifty-third capacitor C59, the fifty-fourth capacitor C60, the fifty-fifth capacitor C61, the fifty-sixth capacitor C62, and the fifth... One end of capacitors C63 (17th), C64 (58th), C65 (59th), C66 (60th), and C67 (61st), and the other end of capacitors C55 (49th), C56 (50th), C57 (51st), C58 (52nd), C59 (53rd), C60 (54th), C61 (55th), C62 (56th), C63 (57th), C64 (58th), C65 (59th), C66 (60th), and C67 (61st) are connected to ground.

[0044] Microprocessor Module (MCU): The microprocessor module connects to the pre-driver chip module and LCD screen interface module via the SPI protocol. It configures the registers of the pre-driver chip module through SPI to ensure its normal operation and diagnostics; it writes display data to the LCD via SPI to enable functions such as LCD screen illumination, interface display, and status display; it connects to the LCD controller via I / O pins such as LCD_RST, LCD_RS, and LCD_LED to control the LCD's operating status and backlight LEDs; and it connects to the WDI, WDO, EN, RO1, RO2, and MON_STB pins. The I / O pins are connected to the power management chip module to enable the power management chip module, act as a watchdog timer, and monitor the power management chip module's status, ensuring the stable operation of the microprocessor module and the stability of the system power supply. The clock output I / O pins IHx and ILx (Input High / Lowside, x = 1, 2, 3) are connected to the pre-driver chip module to control the motor from the PWM waveform output by the pre-driver chip module, as controlled by the microprocessor module. The IHx_S and ILx_S (x = 1, 2, 3) are connected to the logic unit to selectively toggle the low-side PWM input signal. The PFBx (Phase Feedback) pins are also connected to the logic unit. The clock input I / O (k, x = 1, 2, 3) is connected to the pre-driver chip module to receive motor control feedback signals from the pre-driver chip module, enabling the control algorithm to complete the closed loop. The SOFF, INH, ENA, and ERR input / output I / Os are connected to the pre-driver chip module to set and monitor its operating and fault states. LEDx (x = 1, 2, 3, 4) is connected to LEDs of different colors: green LED indicates normal operation, yellow LED indicates startup, red LED indicates a fault, and blue LED indicates the microprocessor module is controlling the motor, and the dSpace test bench is no longer actively controlling the motor. The TMS... The four-wire JTAG (TCK, TDI, TDO) is connected to the microprocessor module debugging tool for flashing and debugging. The microprocessor module is connected to an external 2-pin crystal oscillator with a frequency of 20MHz. The ADC pin is connected to the current sampling outputs VO1, VO2, and VO3 of the pre-driver chip module, the current sampling reference voltage output VRO of the pre-driver chip U3, and the output of the thermistor sampling circuit to achieve current and temperature sampling. The microprocessor module reset pin is connected to the push-button switch and is externally pulled high to ensure the reset effect of the microprocessor module.

[0045] The anti-reverse filtering circuit includes a second inductor L1. One end of the second inductor L1 is connected to the motor, and the other end of the second inductor L1 is connected to one end of capacitors C29 (62nd), C26 (63rd), C27 (64th), C28 (65th), C30 (66th), C31 (67th), C32 (68th), and C33 (69th), the VBAT port of the phase separation controller module and the pre-drive chip module, and the anode of the second diode D1. The cathode of the second diode D1 is connected to the power management chip module, the pre-drive chip module, and the phase separation controller module. On the VBATF port of the device module, the other end of capacitor C29 (the 62nd capacitor) is connected to one end of resistors R27 (the 40th resistor) and R28 (the 41st resistor), and the other ends of resistors R27 and R28 are grounded together; the other end of capacitor C26 (the 63rd capacitor) is connected to one end of capacitor C34 (the 70th capacitor), and the other end of capacitor C34 is grounded; the other ends of capacitors C27 (the 64th capacitor) and C28 (the 65th capacitor) are grounded together; the other ends of capacitors C30 (the 66th capacitor), C31 (the 67th capacitor), C32 (the 68th capacitor), and C33 (the 69th capacitor) are grounded together.

[0046] Filtering anti-reverse circuit: The filtering anti-reverse circuit adopts a design scheme with a common mode inductor, a set of X resistors and capacitors, and other filter capacitors; a diode is selected at the power supply point of the logic chip to provide reverse connection protection for the logic chip power supply; four 3300uF capacitors are connected in parallel to provide DC rectification function for motor drive.

[0047] dSpace bench interface module: The dSpace bench interface module uses a DB25 connector as the wiring connector P1, and includes the following signals: six motor control PWM signals output by the dSpace bench interface module, three current sampling signals output by the pre-drive chip module, three phase voltage feedback signals output by the pre-drive chip module, and CAN signals for communication between the dSpace bench interface module and the microprocessor module.

[0048] The dSpace bench interface module continuously sends current motor angle and torque request signals to the microprocessor module via CAN communication. The microprocessor module calculates the PWM output value through the motor control algorithm, thereby realizing the motor control function.

[0049] The inverter of this utility model has three main working modes, which need to be switched by flashing the program in the microprocessor module chip.

[0050] Operating Mode 1, Basic Inverter Operating Mode:

[0051] In operating mode 1, after the device starts up, the power management chip module supplies power to the microprocessor module, pre-driver chip module, phase separator controller module, level conversion chip, and logic gate chips. After starting up, the microprocessor module feeds the watchdog timer to the power management chip module's U5 power chip and begins monitoring its operating status. The microprocessor module sends an SPI command to the pre-driver chip module, configuring it to enter normal mode and setting its current sampling gain, and begins monitoring its ERR status. The microprocessor module uses I / O to configure logic gates, setting the logic connected to the high-side PWM input to "0" and the logic connected to the low-side PWM input to "1". At this point, the high-side PWM will maintain its original logic, while the low-side PWM will toggle. After these configurations, the microprocessor module sends a "Standby" status signal to the dSpace benchtop interface module via the CAN channel and illuminates a yellow light, monitoring the PWM input status of the dSpace benchtop interface module. The microprocessor module sends an enable signal to the phase separator controller module chip, enabling the three-phase phase separator to conduct.

[0052] When the dSpace bench interface module outputs, the PWM signal output by the bench first passes through a level conversion chip, converting the 5V PWM signal into a 3.3V PWM signal. The converted 3.3V PWM signal then passes through a logic gate circuit, toggling the low-side PWM logic. Finally, a 3.3V PWM signal conforming to the pre-driver chip module's operating logic reaches the pre-driver chip module and the microprocessor module. The pre-driver chip module outputs according to the PWM signal from the dSpace bench interface module. Upon receiving the PWM signal, the microprocessor module changes its state to Running, sends it to the bench via CAN, and illuminates a green indicator light. The current sampling signal and PWM feedback signal output by the pre-driver chip module are transmitted via the DB25 interface to the bench's ADC and I / O for use as input to the motor control algorithm.

[0053] Operating Mode 2, Smart Inverter Operating Mode:

[0054] Based on operating mode 1, the microprocessor module will additionally initialize the LCD screen, ADC, and clocked I / O. After the LCD screen initialization is complete, the screen will display "Waiting for input" before the dSpace test bench provides the PWM signal. The microprocessor module's ADC samples the phase current and thermistor, processes the sampled raw data, and displays the three-phase current, total current, and inverter board temperature on the LCD screen.

[0055] Once the inverter enters the Running state, the LCD screen displays the three-phase current, total current, inverter board temperature, and inverter operating status. If no errors are reported in the power management chip module or the pre-driver chip module, the operating status is displayed as normal. If the pre-driver chip module fails, the screen will display the information in its fault register; if the power management chip module fails, the screen will display "SBC Fault". The microprocessor module's clocked I / O will monitor the PWM signal output from dSpace and verify its logic. If an incorrect dSpace algorithm setting causes the output PWM signal to fail, the microprocessor module will pull the pre-driver chip module enable signal low. The inverter will refuse to execute the bench's output requirements before resetting, and the LCD screen will display "Input Abnormal".

[0056] When any fault or abnormality occurs, the microprocessor module will immediately cut off the enable signal of the phase separator. The phase separator will then cut off the inverter's output to the motor, thereby preventing the motor from entering an abnormal operating condition and causing further losses.

[0057] Operating mode 3, analog steering electronic controller operating mode:

[0058] In this operating mode, the motor control algorithm to be verified will be flashed into the microprocessor module, and the inverter will autonomously control the motor according to the requirements of the test bench. The device will perform initialization as in operating mode 2, but the clocked I / O will switch from input mode to output mode. At the same time, the CAN communication with the test bench will be initialized.

[0059] Since the low-side PWM logic of the motor control clock output of the microprocessor module is originally inverted logic, there is no need to invert the input signal of the pre-driver chip module. At this time, the input of the logic gate connected to the low side is changed to "0" so that the low-side input also maintains the original logic.

[0060] The inverter designed in this invention effectively improves the reliability, intelligence, and maintainability of the dSpace test bench inverter, while also enhancing its motor control performance. Because the old inverter lacked internal diagnostic protection for high duty cycle PWM, overcurrent damage to the MOSFET modules was common during high duty cycle operation. The new design optimizes high duty cycle control using a pre-driver chip, reducing the risk of MOSFET module damage. Furthermore, it replaces the MOSFETs with easily replaceable modules, lowering maintenance costs. When using the new inverter, there is no need to limit the results calculated by the dSpace test bench, allowing for more accurate verification of the motor control algorithm.

Claims

1. A three-phase inverter suitable for dSpace simulation test bench, comprising a housing and a PCB board, characterized in that: An acrylic panel (2) is provided on the top of the housing (4). A PCB board (3) is provided inside the housing (4). A heat sink is provided below the PCB board (3). An LCD display screen (1) is connected to the top of the PCB board (3). A power cord (5), a ground wire (6), and a sampling test interface (7) are connected to the side of the PCB board (3). One end of the power cord (5), the ground wire (6), and the sampling test interface (7) are connected to the PCB board (3). The other end of the power cord (5), the ground wire (6), and the sampling test interface (7) passes through the housing (4) and is located outside the housing (4). The PCB board (3) includes a power management chip module, a microprocessor module, a pre-drive chip module, a phase separation controller module, a filter anti-reverse circuit, a dSpace bench interface module, and a PWM level conversion circuit. One end of the circuit module, XOR logic gate module, LCD screen interface module, power management chip module, and filter anti-reverse circuit is connected to a DC power supply. The other end of the power management chip module is connected to the microprocessor module, pre-driver chip module, phase separator controller module, PWM level conversion circuit module, XOR logic gate module, and LCD screen interface module, respectively, and provides power. The dSpace bench interface module is connected to the pre-driver chip module. One end of the XOR logic gate module is connected to the PWM level conversion circuit module, and the other end of the XOR logic gate module is connected to the input of the microprocessor module. The output of the microprocessor module is connected to the LCD screen interface module, pre-driver chip module, and phase separator controller module, respectively. The phase separator controller module is connected to the motor drive.

2. A three-phase inverter suitable for dSpace simulation test bench according to claim 1, characterized in that: The power management chip module uses a power chip of model TLE7368-2E (U5), the microprocessor module uses a microprocessor chip of model STM32F103ZGT6 (U1), the pre-driver chip module uses a pre-driver chip of model TLE9183OK (U3), the phase separation controller module uses a phase separation control chip of model A6862KLPTR-T (U2), the PWM level conversion circuit module uses a level conversion chip of model TXS0108EQPWRQ1 (U4), the XOR logic gate circuit module uses a first XOR gate circuit chip of model SN74HCS86DR (U6) and a second XOR gate circuit chip (U7), and the dSpace bench interface module uses a wiring plug of model L77SDB25S1ACO4F (P1).

3. A three-phase inverter suitable for dSpace simulation test bench according to claim 1 or 2, characterized in that: The CLK_SPI port of the pre-driver chip (U3) of the pre-driver chip module is connected to the PA5 port of the microprocessor chip (U1); the CSN port of the pre-driver chip (U3) is connected to the PA4 port of the microprocessor chip (U1); the MOSI port of the pre-driver chip (U3) is connected to the PA7 port of the microprocessor chip (U1); the MISO port of the pre-driver chip (U3) is connected to the PA6 port of the microprocessor chip (U1); the IL1 port of the pre-driver chip (U3) is connected to the 8th port of the second XOR gate circuit chip (U7); the IH1 port of the pre-driver chip (U3) is connected to the 11th port of the second XOR gate circuit chip (U7); and the IL2 port of the pre-driver chip (U3) is connected to the second XOR gate circuit chip (U7). The pre-driver chip (U3) connects to port 3 of the microprocessor chip (U1), the IH2 port of the pre-driver chip (U3) connects to port 6 of the second XOR gate chip (U7), the IL3 port of the pre-driver chip (U3) connects to port 6 of the first XOR gate chip (U6), the IH3 port of the pre-driver chip (U3) connects to port 3 of the first XOR gate chip (U6), the SOFF port of the pre-driver chip (U3) connects to port PE3 of the microprocessor chip (U1), the INH port of the pre-driver chip (U3) connects to port PE4 of the microprocessor chip (U1), the ENA port of the pre-driver chip (U3) connects to port PE5 of the microprocessor chip (U1), and the ERR port of the pre-driver chip (U3) connects to port PE6 of the microprocessor chip (U1). The PFB1 port of chip (U3) and the PE14 port of microprocessor chip (U1) are connected together to port 7 of the wiring plug (P1) of the dSpace bench interface module. The PFB2 port of pre-driver chip (U3) and the PE10 port of microprocessor chip (U1) are connected together to port 8 of the wiring plug (P1) of the dSpace bench interface module. The PFB3 port of pre-driver chip (U3) and the PE11 port of microprocessor chip (U1) are connected together to port 9 of the wiring plug (P1) of the dSpace bench interface module. The VO1 port of pre-driver chip (U3) is connected to one end of the first resistor (R43), and the other end of the first resistor (R43) is connected to the PC4 port of microprocessor chip (U1). The ports are connected to port 14 of the dSpace benchtop interface module's connector (P1). The VO2 port of the pre-driver chip (U3) is connected to one end of the second resistor (R44). The other end of the second resistor (R44) and the PB0 port of the microprocessor chip (U1) are connected to port 15 of the dSpace benchtop interface module's connector (P1). The VO3 port of the pre-driver chip (U3) is connected to one end of the third resistor (R45). The other end of the third resistor (R45) and the PB1 port of the microprocessor chip (U1) are connected to port 16 of the dSpace benchtop interface module's connector (P1). The VRO port of the pre-driver chip (U3) is connected to one end of the fourth resistor (R46).The other end of the fourth resistor (R46) and the PC5 port of the microprocessor chip (U1) are connected together to port 17 of the wiring plug (P1) of the dSpace bench interface module. The GND port, CP_GND port, and AGND port of the pre-driver chip (U3) are grounded together. The CH1 port of the pre-driver chip (U3) is connected to one end of the first capacitor (C24). The other end of the first capacitor (C24) and the CL1 port of the pre-driver chip (U3) are connected together to one end of the fifth resistor (R26). The other end of the fifth resistor (R26) is grounded. The CH2 port of the pre-driver chip (U3) is connected to one end of the second capacitor (C23). The other end of the second capacitor (C23) and the CL2 port of the pre-driver chip (U3) are connected together. The cathode of the first Zener diode (D5) is connected in a combined manner, and the anode of the first Zener diode (D5) is grounded; the CB port of the pre-driver chip (U3) is connected to one end of the third capacitor (C25), and the other end of the third capacitor (C25) is grounded; the VDH1, VDH2, and VDH3 ports of the pre-driver chip (U3) are interconnected; the GH1 port of the pre-driver chip (U3) is connected to one end of the sixth resistor (R5), and the other end of the sixth resistor (R5) is connected to the gate of the first power transistor (Q1); the BH1 port of the pre-driver chip (U3) is connected to one end of the seventh resistor (R6), and the other end of the seventh resistor (R6) is connected to one end of the fourth capacitor (C11); the SH1 port of the pre-driver chip (U3) is connected to the eighth resistor (C11). One end of resistor R7 is connected to the source of the first power transistor (Q1), and the other end of resistor R7 is connected to the other end of capacitor C11. The GL1 port of the pre-driver chip (U3) is connected to one end of resistor R8, and the other end of resistor R8 is connected to the gate of the second power transistor (Q5). The SL1 port of the pre-driver chip (U3) is connected to one end of resistor R9, and the other end of resistor R9 is connected to the source of the second power transistor (Q5). The ISP1 port of the pre-driver chip (U3) is connected to one end of capacitor C12 and one end of resistor R10, and the other end of resistor R10 is connected to one end of capacitor C15. The ISN1 port of the pre-driver chip (U3) is connected to the other end of the fifth capacitor (C12) and one end of the twelfth resistor (R11). The other end of the twelfth resistor (R11) is connected to one end of the seventh capacitor (C14). The other ends of the sixth capacitor (C15) and the seventh capacitor (C14) are grounded together. The GH2 port of the pre-driver chip (U3) is connected to one end of the thirteenth resistor (R12), and the other end of the thirteenth resistor (R12) is connected to the gate of the third power transistor (Q2). The BH2 port of the pre-driver chip (U3) is connected to one end of the fourteenth resistor (R13), and the other end of the fourteenth resistor (R13) is connected to one end of the eighth capacitor (C13). The SH2 port of the pre-driver chip (U3) is connected to one end of the fifteenth resistor (R14).The other end of the fifteenth resistor (R14) is combined with the other end of the eighth capacitor (C13) and connected to the source of the third power transistor (Q2); the GL2 port of the pre-driver chip (U3) is connected to one end of the sixteenth resistor (R15), and the other end of the sixteenth resistor (R15) is connected to the gate of the fourth power transistor (Q6); the SL2 port of the pre-driver chip (U3) is connected to one end of the seventeenth resistor (R16), and the other end of the seventeenth resistor (R16) is connected to the source of the fourth power transistor (Q6); the ISP2 port of the pre-driver chip (U3) is connected to one end of the ninth capacitor (C16) and one end of the eighteenth resistor (R17), and the other end of the eighteenth resistor (R17) is connected to one end of the tenth capacitor (C18). The ISN2 port of the pre-driver chip (U3) is connected to the other end of the ninth capacitor (C16) and one end of the nineteenth resistor (R18). The other end of the nineteenth resistor (R18) is connected to one end of the eleventh capacitor (C19). The other ends of the tenth capacitor (C18) and the eleventh capacitor (C19) are grounded together. The GH3 port of the pre-driver chip (U3) is connected to one end of the twentieth resistor (R19). The other end of the twentieth resistor (R19) is connected to the gate of the fifth power transistor (Q3). The BH3 port of the pre-driver chip (U3) is connected to one end of the twenty-first resistor (R20). The other end of the twenty-first resistor (R20) is connected to one end of the twelfth capacitor (C17). The SH3 port of the pre-driver chip (U3) is connected to the twenty-second resistor. One end of resistor R21, the other end of resistor R21 and the other end of capacitor C17 are connected together to the source of the fifth power transistor (Q3); the GL3 port of the pre-driver chip (U3) is connected to one end of resistor R22, and the other end of resistor R22 is connected to the gate of the sixth power transistor (Q7); the SL3 port of the pre-driver chip (U3) is connected to one end of resistor R23, and the other end of resistor R23 is connected to the source of the sixth power transistor (Q7); the ISP3 port of the pre-driver chip (U3) is connected to one end of capacitor C20 and one end of resistor R24, and the other end of resistor R24 ​​is connected to... One end of the fourteenth capacitor (C21) is connected to the other end of the thirteenth capacitor (C20) and one end of the twenty-sixth resistor (R25) via the ISN3 port of the pre-driver chip (U3). The other end of the twenty-sixth resistor (R25) is connected to one end of the fifteenth capacitor (C22). The other ends of the fourteenth capacitor (C21) and the fifteenth capacitor (C22) are grounded together. The two cathodes of the first dual diode (D2) are connected to the SH1 port and SL1 port of the pre-driver chip (U3) respectively. The two anodes of the first dual diode (D2) are grounded together. The two cathodes of the second dual diode (D3) are connected to the SH2 port and SL2 port of the pre-driver chip (U3) respectively. The two anodes of the second dual diode (D3) are grounded together.The two cathodes of the third dual diode (D4) are connected to the SH3 and SL3 ports of the pre-driver chip (U3), respectively, and the two anodes of the third dual diode (D4) are grounded. The drain electrodes of the first power transistor (Q1), the third power transistor (Q2), and the fifth power transistor (Q3) are connected to the VBAT port. The source of the first power transistor (Q1) and the drain electrode of the second power transistor (Q5) are connected to the phase separation controller module. The source of the third power transistor (Q2) and the drain electrode of the fourth power transistor (Q6) are connected to the phase separation controller module. The fifth power transistor (Q... 3) The source and drain of the sixth power transistor (Q7) are connected together to the phase separation controller module. The source of the second power transistor (Q5) is also connected to the other end of the eleventh resistor (R10) and one end of the first fuse resistor (F1). The source of the sixth power transistor (Q7) is also connected to the other end of the eighteenth resistor (R17) and one end of the second fuse resistor (F3). The other end of the first fuse resistor (F1), the other end of the twelfth resistor (R11), the source of the fourth power transistor (Q6), the other end of the nineteenth resistor (R18), and the other end of the second fuse resistor (F3) are also connected. One end of the pre-driver chip (U3) is connected to one end of the third fuse resistor (F2) and the other end of the twenty-fifth resistor (R24). The other end of the third fuse resistor (F2) and the other end of the twenty-sixth resistor (R25) are connected to ground. The VDHP port of the pre-driver chip (U3) is connected to one end of the sixteenth capacitor (C8) and one end of the twenty-seventh resistor (R2). The other end of the twenty-seventh resistor (R2) is connected to the VBAT port. The other end of the sixteenth capacitor (C8) is connected to one end of the seventeenth capacitor (C10). The other end of the seventeenth capacitor (C10) is grounded. The VS port of chip (U3) is connected to one end of capacitor 18 (C2), one end of capacitor 19 (C3), and the VBATF port, respectively. The other end of capacitor 18 (C2) is connected to one end of capacitor 20 (C4), and the other end of capacitor 19 (C3) is connected to one end of capacitor 21 (C5). The other ends of capacitors 20 (C4) and 21 (C5) are grounded together. The VCC port of pre-driver chip (U3) is connected to one end of capacitor 22 (C7) and the 3.3V voltage, respectively. The other end of capacitor 22 (C7) is grounded.

4. A three-phase inverter suitable for dSpace simulation test bench according to claim 1 or 2, characterized in that: The phase separation controller module's phase separation control chip (U2) has its VBB port connected to the VBATF port and one end of the 23rd capacitor (C1). The other end of the 22nd capacitor (C1) is connected to the VCP port of the phase separation control chip (U2). The CP4 port of the phase separation control chip (U2) is connected to one end of the 24th capacitor (C6). The other end of the 24th capacitor (C6) is connected to the CP3 port of the phase separation control chip (U2). The CP2 port of the phase separation control chip (U2) is connected to one end of the 25th capacitor (C9). The other end of the 25th capacitor (C9) is connected to the phase separation control chip (U2). The CP1 port of the phase separation control chip (U2) and the IG port of the phase separation control chip (U2) are connected to one end of the 28th resistor (R42), and the other end of the 28th resistor (R42) is connected to the VBAT port. The POK port of the phase separation control chip (U2) is connected to the PG0 port of the microprocessor chip (U1), and the ENA port of the phase separation control chip (U2) is connected to the PG1 port of the microprocessor chip (U1). The TAB port and GND port of the phase separation control chip (U2) are grounded respectively. The SU port of the phase separation control chip (U2) is connected to the source of the first power transistor (Q1) and the second power transistor respectively. The drain electrode of transistor (Q5) and the source of the seventh power transistor (Q4) are connected. The SV port of the phase separation control chip (U2) is connected to the source of the third power transistor (Q2), the drain electrode of the fourth power transistor (Q6), and the source of the eighth power transistor (Q8). The SW port of the phase separation control chip (U2) is connected to the source of the fifth power transistor (Q3), the drain electrode of the sixth power transistor (Q7), and the source of the ninth power transistor (Q9). The GU port of the phase separation control chip (U2) is connected to one end of the twenty-ninth resistor (R1), and the other end of the twenty-ninth resistor (R1) is connected to the gate of the seventh power transistor (Q4). The seventh power transistor (Q5) is connected to the source of the seventh power transistor (Q4). 4) The drain electrode of the phase separation control chip (U2) is connected to the U terminal of the motor. The GV port of the phase separation control chip (U2) is connected to one end of the thirtieth resistor (R3). The other end of the thirtieth resistor (R3) is connected to the gate of the eighth power transistor (Q8). The drain electrode of the eighth power transistor (Q8) is connected to the V terminal of the motor. The GW port of the phase separation control chip (U2) is connected to one end of the thirty-first resistor (R4). The other end of the thirty-first resistor (R4) is connected to the gate of the ninth power transistor (Q9). The drain electrode of the ninth power transistor (Q9) is connected to the W terminal of the motor. The VBAT port of the phase separation controller module is interconnected with the VBAT port of the pre-drive chip module.

5. A three-phase inverter suitable for dSpace simulation test bench according to claim 1 or 2, characterized in that: The power management chip module's power chip (U5) has its RT port connected to one end of the 26th capacitor (C37), and the other end of the 26th capacitor (C37) and the power chip (U5)'s GND_A port are grounded together. The power chip (U5)'s RT port is connected to the EN_UC port, which is connected to the microprocessor chip (U1)'s PC6 port. The power chip (U5)'s EN_IGN port is connected to one end of the 32nd resistor (R61), and the other end of the 32nd resistor (R61) is connected to the VBATF port. The power chip (U5)'s SEL_... The STBY port is grounded. The C1- port of the power chip (U5) is connected to one end of the 27th capacitor (C38), and the other end of the 27th capacitor (C38) is connected to the C1+ port of the power chip (U5). The C2- port of the power chip (U5) is connected to one end of the 28th capacitor (C41), and the other end of the 28th capacitor (C41) is connected to the C2+ port of the power chip (U5). The GND_P and GND_A ports of the power chip (U5) are grounded together. The IN port of the power chip (U5) is connected to the VBATF port and the 20th capacitor. One end of capacitor 9 (C50) and the other end of capacitor 29 (C50) are grounded. The WDI port of power chip (U5) is connected to the PC7 port of microprocessor chip (U1). The BST port of power chip (U5) is connected to one end of capacitor 30 (C52). The other end of capacitor 30 (C52) is connected to the SW port of power chip (U5). The FB_EXT port of power chip (U5) is connected to one end of capacitor 31 (C54) and the DRV_EXT port of power chip (U5). The other end of capacitor 31 (C54) is connected to the other end of capacitor 32. The power supply chip (U5) is grounded; the IN_STBY port of the power supply chip (U5) is connected to the VBATF port, the GND_A port of the power supply chip (U5) is grounded, the MON_STBY port of the power supply chip (U5) is connected to the PC8 port of the microprocessor chip (U1), the Q_STBY port of the power supply chip (U5) is connected to one end of the thirty-second capacitor (C40), and the other end of the thirty-second capacitor (C40) is grounded; the Q_LDO1 port of the power supply chip (U5) is connected to one end of the thirty-third capacitor (C39), and the other end of the thirty-third capacitor (C39) is grounded;The SW port of the power chip (U5) is connected to the cathode of the first diode (D6) and one end of the first inductor (L2), respectively. The anode of the first diode (D6) is grounded. The other end of the first inductor (L2) is connected to one end of the thirty-fourth capacitor (C42), one end of the thirty-fifth capacitor (C43), one end of the thirty-sixth capacitor (C44), one end of the thirty-seventh capacitor (C45), one end of the thirty-eighth capacitor (C46), the IN_LDO2 port of the power chip (U5), and the FB / L_IN port of the power chip (U5). The other ends of the thirty-fourth capacitor (C42), the thirty-fifth capacitor (C43), the thirty-sixth capacitor (C44), the thirty-seventh capacitor (C45), and the thirty-eighth capacitor (C46) are grounded together. The WDO port of the power chip (U5) is connected to the PC9 port of the microprocessor chip (U1). The SEL_Q2 port and the Q_LDO2 port of the power chip (U5) are connected together to one end of the thirty-ninth capacitor (C51). The other end of capacitor 39 (C51) is grounded; the CPP port, Q_T2 port, and Q_T1 port of power chip (U5) are respectively connected to one end of capacitor 40 (C47), one end of capacitor 41 (C48), and one end of capacitor 42 (C49). The other ends of capacitors 40 (C47), 41 (C48), and 42 (C49) and the GND_A port of power chip (U5) are grounded together; the RO_2 port of source chip (U5) is respectively connected to one end of resistor 33 (R39) and the PA8 port of microprocessor chip (U1). The RO_1 port of source chip (U5) is respectively connected to one end of resistor 34 (R40) and the PA9 port of microprocessor chip (U1). The other ends of resistors 33 (R39) and 34 (R40) are connected together to a 3.3V voltage; the VBATF port of power management chip module is interconnected with the VBATF port of pre-driver chip module and phase separation controller module.

6. A three-phase inverter suitable for dSpace simulation test bench according to claim 1 or 2, characterized in that: The A1 port of the level conversion chip (U4) in the PWM level conversion circuit module is connected to the PE8 port of the microprocessor chip (U1) and the 4th port of the first XOR gate chip (U6), respectively. The first VCCA port of the level conversion chip (U4) is connected to a 3.3V voltage, the OE port of the level conversion chip (U4), and one end of the 43rd capacitor (C35), with the other end of the 43rd capacitor (C35) grounded. The A2 port of the level conversion chip (U4) is connected to the PE9 port of the microprocessor chip (U1) and the 1st port of the first XOR gate chip (U6), respectively. The A3 port of the level conversion chip (U4) is connected to the PE10 port of the microprocessor chip (U1) and the 1st port of the second XOR gate chip (U7), respectively. The A4 port of the level conversion chip (U4) is connected to the PE11 port of the microprocessor chip (U1) and the 4th port of the second XOR gate chip (U7), respectively. The A5 port of the level converter chip (U4) is connected to the PE12 port of the microprocessor chip (U1) and the 9th port of the second XOR gate chip (U7). The A6 port of the level converter chip (U4) is connected to the PE13 port of the microprocessor chip (U1) and the 12th port of the second XOR gate chip (U7). The A7 and A8 ports of the level converter chip (U4) are grounded together. The B1, B2, B3, B4, B5, and B6 ports of the level converter chip (U4) are connected to the 1st to 6th ports of the wiring plug (P1) of the dSpace bench interface module. The B7 and B8 ports of the level converter chip (U4) are grounded together. The GND port of the level converter chip (U4) is grounded. The second VCCA port of the level converter chip (U4) is connected to a 5.0V voltage and one end of the 44th capacitor (C36). The other end of the 44th capacitor (C36) is grounded.

7. A three-phase inverter suitable for dSpace simulation test bench according to claim 1 or 2, characterized in that: The XOR logic gate module has the following connections: Port 2 of the first XOR gate chip (U6) is connected to port PG7 of the microprocessor chip (U1); Port 5 of the first XOR gate chip (U6) is connected to port PG6 of the microprocessor chip (U1); Port 8 of the first XOR gate chip (U6) is connected to one end of the 35th resistor (R65), with the other end of the 35th resistor (R65) grounded; Port 11 of the first XOR gate chip (U6) is connected to one end of the 36th resistor (R66), with the other end of the 36th resistor (R66) grounded; Port 14 of the first XOR gate chip (U6) is connected to a 3.3V voltage source and one end of the 45th capacitor (C102), with the other end of the 45th capacitor (C102) connected to... The first XOR gate chip (U6) has its 7th port grounded; the second XOR gate chip (U7) has its 2nd port connected to the PG4 port of the microprocessor chip (U1), its 5th port connected to the PG5 port of the microprocessor chip (U1), its 10th port connected to the PG2 port of the microprocessor chip (U1), its 13th port connected to the PG3 port of the microprocessor chip (U1), its 14th port connected to a 3.3V voltage and one end of the 46th capacitor (C101), the other end of the 46th capacitor (C101) grounded, and its 7th port grounded.

8. A three-phase inverter suitable for dSpace simulation test bench according to claim 1, characterized in that: The LCD screen interface module includes a connector and a switch. Connector pin 1 (P12) is connected to 3.3V. Connector pin 2 (P12) is grounded. Connector pin 3 (P12) is connected to port PB12 of the microprocessor chip (U1). Connector pin 4 (P12) is connected to port PD12 of the microprocessor chip (U1), ports 1 and 2 of the first switch (SW2), one end of the 37th resistor (R50), and one end of the 47th capacitor (C70). The other end of the 37th resistor (R50) is connected to 3.3V. The other end of the capacitor (C70) is grounded together with ports 3 and 4 of the first switch (SW2); port 5 of the LCD screen interface module's connector pin (P12) is connected to port PD13 of the microprocessor chip (U1); port 6 of the LCD screen interface module's connector pin (P12) is connected to port PB15 of the microprocessor chip (U1); port 7 of the LCD screen interface module's connector pin (P12) is connected to port PB13 of the microprocessor chip (U1); port 8 of the LCD screen interface module's connector pin (P12) is connected to port PD14 of the microprocessor chip (U1); and port 9 of the LCD screen interface module's connector pin (P12) is connected to port PB14 of the microprocessor chip (U1).

9. A three-phase inverter suitable for dSpace simulation test bench according to claim 1 or 2, characterized in that: The microprocessor chip (U1) of the microprocessor module has its PA11 port connected to port 11 of the wiring plug (P1) of the dSpace bench interface module, its PA12 port connected to port 12 of the wiring plug (P1) of the dSpace bench interface module, its PC1 port connected to one end of the 38th resistor (R35), and the other end of the 38th resistor (R35) connected to the Q_STBY port of the power chip (U5); the PD8, PD9, PD10, and PD11 ports of the microprocessor chip (U1) are respectively connected to four... LED light; the PF6 port of the microprocessor chip (U1) is connected to port 19 of the wiring plug (P1) of the dSpace bench interface module; the OSC_IN and OSC_OUT ports of the microprocessor chip (U1) are connected to the crystal oscillator (X1); the NRST port of the microprocessor chip (U1) is connected to ports 1 and 2 of the second switch (SW1), one end of the thirty-ninth resistor (R41), and one end of the forty-eighth capacitor (C100); the other end of the thirty-ninth resistor (R41) is connected to a 3.3V voltage; and the other end of the forty-eighth capacitor (C100) is connected to the second switch (SW1). Ports 3 and 4 of the microprocessor chip (U1) are grounded together; ports VSS_1 to VSS_11, VSSA, and VREF- of the microprocessor chip (U1) are grounded together; ports VDD_1 to VDD_11, VDDA, and VBAT of the microprocessor chip (U1) are connected together to capacitors 49 (C55), 50 (C56), 51 (C57), 52 (C58), 53 (C59), 54 (C60), 55 (C61), 56 (C62), and 57 (C63). One end of capacitors 18 (C64), 59 (C65), 60 (C66), and 61 (C67), and the other end of capacitors 49 (C55), 50 (C56), 51 (C57), 52 (C58), 53 (C59), 54 (C60), 55 (C61), 56 (C62), 57 (C63), 58 (C64), 59 (C65), 60 (C66), and 61 (C67) are connected to ground.

10. A three-phase inverter suitable for dSpace simulation test bench according to claim 1, characterized in that: The aforementioned filtering and anti-reverse circuit includes a second inductor (L1). One end of the second inductor (L1) is connected to the motor, and the other end of the second inductor (L1) is connected to one end of the sixty-second capacitor (C29), sixty-third capacitor (C26), sixty-fourth capacitor (C27), sixty-fifth capacitor (C28), sixty-sixth capacitor (C30), sixty-seventh capacitor (C31), sixty-eighth capacitor (C32), and sixty-ninth capacitor (C33), the VBAT port of the phase separation controller module and the pre-drive chip module, and the anode of the second diode (D1). The cathode of the second diode (D1) is connected to the power management chip module, the pre-drive chip module, and the phase separation controller module. On the VBATF port of the controller module, the other end of the 62nd capacitor (C29) is connected to one end of the 40th resistor (R27) and the 41st resistor (R28), respectively, and the other ends of the 40th resistor (R27) and the 41st resistor (R28) are grounded together; the other end of the 63rd capacitor (C26) is connected to one end of the 70th capacitor (C34), and the other end of the 70th capacitor (C34) is grounded; the other ends of the 64th capacitor (C27) and the 65th capacitor (C28) are grounded together; the other ends of the 66th capacitor (C30), the 67th capacitor (C31), the 68th capacitor (C32), and the 69th capacitor (C33) are grounded together.

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