A multi-stage frequency divider, control system and drive system
By dividing the clock signal multiple times using a multi-stage frequency divider, various frequency-divided signals of different frequencies are generated. This solves the problem that existing frequency dividers cannot meet the requirements of multi-frequency signal input and improves the adaptability of the frequency divider.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- JIANGXI LUXSHARE INTELLIGENT MFG CO LTD
- Filing Date
- 2025-08-13
- Publication Date
- 2026-07-07
AI Technical Summary
Existing frequency dividers can only perform fixed single-level frequency division on the input clock signal, which cannot meet the multi-frequency signal input requirements of the equipment.
A multi-stage frequency divider is used. The clock signal is divided once by the first frequency divider module, and then divided twice by the second frequency divider module. The clock signal is then divided three times by multiplexing the first frequency divider module, generating a variety of frequency-divided signals of different frequencies.
It enables the generation of multiple frequency division signals to meet the multi-frequency signal input requirements of equipment, and improves the flexibility and adaptability of the frequency division device.
Smart Images
Figure CN224473303U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of multi-frequency clock technology, and in particular to a multi-level frequency division device and control system and drive system. Background Technology
[0002] With the advent of the intelligent era, the application of electronic devices has become increasingly widespread. The operation of electronic devices relies on clock signals, which are used for various aspects such as signal synchronization and signal transmission. Electronic devices typically require multiple clock domains, each with a different clock frequency and responsible for different functions, to ensure the stability and performance of the electronic device.
[0003] However, in the existing technology, the frequency divider can only divide the input clock signal by a fixed single level. The frequency of the clock signal output by the frequency divider is single, and the frequency divider cannot meet the multi-frequency signal input requirements of the device. Utility Model Content
[0004] This utility model provides a multi-level frequency division device and control system, and a drive system. At least one embodiment solves the problem that the frequency division device cannot meet the multi-frequency signal input requirements of the equipment.
[0005] According to one aspect of the present invention, a multi-stage frequency divider is provided, the multi-stage frequency divider comprising: a first frequency divider module, a level converter, and a second frequency divider module;
[0006] The first input terminal of the first frequency divider module is used to receive a clock signal. The first frequency divider module is configured to output multiple first frequency divider signals of the same or different frequencies according to the clock signal. The first output terminal of the first frequency divider module is coupled to the first input terminal of the second frequency divider module through the level converter.
[0007] The second frequency divider module is configured to output multiple second frequency divider signals of the same or different frequencies based on the first frequency divider signal output from the first output terminal of the first frequency divider module, wherein the first output terminal of the second frequency divider module is coupled to the second input terminal of the first frequency divider module through the level converter;
[0008] The first frequency divider module is further configured to output multiple third frequency divider signals of the same or different frequencies based on the second frequency divider signal output from the first output terminal of the second frequency divider module.
[0009] Optionally, the multi-stage frequency divider also includes an oscillator;
[0010] The oscillator is coupled to the first input terminal of the first frequency divider module;
[0011] The oscillator is used to generate the clock signal.
[0012] Optionally, the second output terminal of the first frequency divider module is coupled to the second input terminal of the second frequency divider module through the level converter. The second frequency divider module is further configured to output multiple fourth frequency divider signals of the same or different frequencies based on the third frequency divider signal output from the second output terminal of the first frequency divider module.
[0013] Optionally, both the first frequency divider module and the second frequency divider module are divide-by-two triggers.
[0014] Optionally, the multi-level frequency divider further includes a first buffer and a second buffer; the first buffer is used to couple multiple load devices and drive the corresponding load devices based on the received first frequency divider signal and the third frequency divider signal respectively;
[0015] The second buffer is used to couple the load device and drive the corresponding load device based on the received second frequency division signal.
[0016] Optionally, the multi-stage frequency divider further includes a first buffer and a second buffer;
[0017] The first buffer is used to couple multiple load devices and drive the corresponding load devices based on the received first frequency division signal and the third frequency division signal;
[0018] The second buffer is used to couple multiple load devices and drive the corresponding load devices based on the received second and fourth frequency division signals.
[0019] Optionally, the second output terminal of the second frequency divider module is coupled to a signal converter via the level converter, the signal converter being used to convert the fourth frequency divider signal representing the square wave into a sine wave of the same frequency.
[0020] Optionally, the first input terminal of the first buffer is coupled to the third output terminal of the first frequency divider module to receive the first frequency divider signal, and the second input terminal of the first buffer is coupled to the fourth output terminal of the first frequency divider signal to receive the third frequency divider signal.
[0021] The first input terminal of the second buffer is coupled to the third output terminal of the second frequency divider module to receive the second frequency divider signal, and the second input terminal of the second buffer is coupled to the fourth output terminal of the second frequency divider module to receive the fourth frequency divider signal.
[0022] According to another aspect of the present invention, a control system is also provided, which includes the multi-level frequency division device described in any of the above embodiments, and a control module;
[0023] The multi-level frequency divider is used to provide control signals to the control module.
[0024] According to another aspect of the present invention, a drive system is also provided, which includes the multi-level frequency division device described in any of the above embodiments, and a load terminal;
[0025] The multi-level frequency divider is used to provide drive signals to the load terminal.
[0026] This utility model embodiment divides the clock signal once using a first frequency divider module, divides the clock signal twice using a second frequency divider module, and divides the clock signal a third time using the multiplexing of the first frequency divider module, thereby generating multiple frequency-divided signals of different frequencies, which is beneficial to meeting the multi-frequency signal input requirements of the device.
[0027] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description
[0028] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0029] Figure 1 This is a schematic diagram of a multi-stage frequency division device provided in one embodiment of the present invention.
[0030] Figure 2 This is a schematic diagram of another multi-stage frequency division device provided in one embodiment of the present invention;
[0031] Figure 3 This is a schematic diagram of an oscillator provided in one embodiment of the present invention;
[0032] Figure 4 This is a schematic diagram of another multi-level frequency division device provided in an embodiment of the present invention;
[0033] Figure 5 This is a schematic diagram of a first frequency divider module provided in an embodiment of the present invention;
[0034] Figure 6 This is a schematic diagram of a second frequency divider module provided in an embodiment of the present invention;
[0035] Figure 7This is a schematic diagram of another multi-level frequency division device provided in an embodiment of the present invention;
[0036] Figure 8 This is a schematic diagram of a first buffer provided in an embodiment of the present invention;
[0037] Figure 9 This is a schematic diagram of a second buffer provided in one embodiment of the present invention;
[0038] Figure 10 This is a schematic diagram of a level converter provided in one embodiment of the present invention;
[0039] Figure 11 This is a schematic diagram of a control system provided in one embodiment of the present invention;
[0040] Figure 12 This is a schematic diagram of a drive system provided in one embodiment of the present invention. Detailed Implementation
[0041] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.
[0042] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0043] One embodiment of this utility model provides a multi-stage frequency divider. This multi-stage frequency divider divides the input clock signal to generate multiple clock signals of different frequencies. Figure 1 This is a schematic diagram of a multi-stage frequency division device provided in an embodiment of this utility model. (Refer to...) Figure 1The multi-stage frequency divider includes: a first frequency divider module 110, a second frequency divider module 120, and a level converter 150.
[0044] The first input terminal of the first frequency divider module 110 is used to receive the clock signal SIG. The first frequency divider module 110 is configured to output multiple first frequency divider signals FP1 with the same or different frequencies according to the clock signal SIG. The first output terminal of the first frequency divider module 110 is coupled to the first input terminal of the second frequency divider module 120 through a level converter 150. The second frequency divider module 120 is configured to output multiple second frequency divider signals FP2 with the same or different frequencies according to the first frequency divider signals FP1 output from the first output terminal of the first frequency divider module 110. The first output terminal of the second frequency divider module 120 is coupled to the second input terminal of the first frequency divider module 110 through a level converter 150. The first frequency divider module 110 is also configured to output multiple third frequency divider signals FP3 with the same or different frequencies according to the second frequency divider signals FP2 output from the first output terminal of the second frequency divider module 120.
[0045] Specifically, the first input terminal of the first frequency divider module 110 acquires the clock signal SIG. For example, the clock signal SIG can be generated by an oscillator; in practical applications, different oscillators can be selected according to actual needs to determine the frequency of the clock signal SIG. The first frequency divider module 110 divides the clock signal SIG input to its first input terminal to generate a first frequency divider signal FP1. The frequency of the first frequency divider signal FP1 is different from the frequency of the clock signal SIG, and the frequency of the first frequency divider signal FP1 is less than the frequency of the clock signal SIG. In practical applications, the first frequency divider module 110 can divide the clock signal SIG into multiple first frequency divider signals FP1 with the same frequency, i.e., equally divide the clock signal SIG, in which case the frequencies of each first frequency divider signal FP1 output by the first frequency divider module 110 are the same; alternatively, it can divide the clock signal SIG into multiple first frequency divider signals FP1 with different frequencies, in which case the frequencies of each first frequency divider signal FP1 output by the first frequency divider module 110 are different.
[0046] The first frequency division signal FP1 output from the first output terminal of the first frequency division module 110 is transmitted to the second frequency division module 120 through the level converter 150. The level converter 150 provides gain to the first frequency division signal FP1 output from the first frequency division module 110 to enhance the first frequency division signal FP1. For example, the level converter 150 can be a TXB0304 type bidirectional four-channel level converter.
[0047] The second frequency divider module 120 further divides the first frequency divider signal FP1 input to its first input terminal to generate a second frequency divider signal FP2. The frequency of the second frequency divider signal FP2 is different from the frequency of the first frequency divider signal FP1, and the frequency of the second frequency divider signal FP2 is less than the frequency of the first frequency divider signal FP1. Similarly, in practical applications, the second frequency divider module 120 can divide the first frequency divider signal FP1 into multiple second frequency divider signals FP2 with the same frequency, or it can divide the first frequency divider signal FP1 into multiple second frequency divider signals FP2 with different frequencies.
[0048] The second frequency division signal FP2 output from the first output terminal of the second frequency division module 120 is transmitted to the first frequency division module 110 through the level converter 150. The level converter 150 provides gain to the second frequency division signal FP2 output by the second frequency division module 120 to enhance the second frequency division signal FP2.
[0049] The first frequency divider module 110 further divides the second frequency divider signal FP2 input to its second input terminal to generate a third frequency divider signal FP3. Similarly, the frequency of the third frequency divider signal FP3 is different from the frequency of the second frequency divider signal FP2, and the frequency of the third frequency divider signal FP3 is less than the frequency of the second frequency divider signal FP2.
[0050] It should be noted that the first frequency division signal FP1 and the third frequency division signal FP3 output by the first frequency division module 110, as well as the second frequency division signal FP2 output by the second frequency division module, can all be used as output signals of the multi-stage frequency division device. In practical applications, the output signal of the multi-stage frequency division device can be selected according to actual needs.
[0051] This embodiment of the invention divides the clock signal SIG once using the first frequency divider module 110, divides the clock signal SIG twice using the second frequency divider module 120, and divides the clock signal SIG a third time using the multiplexing of the first frequency divider module 110, thereby generating multiple frequency-divided signals of different frequencies, which is beneficial to meeting the multi-frequency signal input requirements of the device.
[0052] Figure 2 This is a schematic diagram of another multi-stage frequency division device provided in one embodiment of the present invention. Optionally, based on the above embodiments, refer to... Figure 2 The multi-stage frequency divider also includes an oscillator 160.
[0053] Oscillator 160 is coupled to the first input terminal of the first frequency divider module 110; oscillator 160 is used to generate clock signal SIG.
[0054] Specifically, oscillator 160 generates a clock signal SIG and outputs the clock signal SIG to the first frequency divider module 110. The frequency of the clock signal SIG generated by oscillator 160 can be set according to actual needs. In one embodiment, oscillator 160 is an LMK6D type BAW oscillator.
[0055] Based on the above embodiments, optionally, in practical applications, the oscillator 160 can be in the form of a chip. Figure 3 This is a schematic diagram of an oscillator 160 provided in one embodiment of the present invention. (Refer to...) Figure 3 The oscillator 160 includes: oscillator chip U1.
[0056] The power supply terminal VDD and enable terminal OE of oscillator chip U1 are connected to the power supply voltage VCC, the ground terminal GND of oscillator chip U1 is grounded, and the output terminal OUT of oscillator chip U1 is coupled to the first frequency divider module 110. In practical applications, oscillator 160 may also include a first capacitor C1 and a second capacitor C2. The first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 are both connected to the power supply terminal VDD of oscillator chip U1, and the second terminals of the first capacitor C1 and the second terminals of the second capacitor C2 are both grounded. The first capacitor C1 and the second capacitor C2 are used to absorb low-frequency fluctuations and suppress high-frequency interference.
[0057] Figure 4 This is a schematic diagram of another multi-stage frequency division device provided in one embodiment of the present invention. Optionally, based on the above embodiments, refer to... Figure 4 The second output terminal of the first frequency divider module 110 is coupled to the second input terminal of the second frequency divider module 120 through a level converter 150. The second frequency divider module 120 is also configured to output multiple fourth frequency divider signals FP4 of the same or different frequencies based on the third frequency divider signal FP3 output from the second output terminal of the first frequency divider module 110.
[0058] Specifically, the second frequency divider module 120 further divides the third frequency divider signal FP3 input to its second input terminal to generate a fourth frequency divider signal FP4. The frequency of the fourth frequency divider signal FP4 is different from the frequency of the third frequency divider signal FP3, and the frequency of the fourth frequency divider signal FP4 is lower than the frequency of the third frequency divider signal FP3. Similarly, in practical applications, the second frequency divider module 120 can divide the third frequency divider signal FP3 into multiple fourth frequency divider signals FP4 with the same frequency, or it can divide the third frequency divider signal FP3 into multiple fourth frequency divider signals FP4 with different frequencies.
[0059] Based on the above embodiments, optionally, both the first frequency divider module 110 and the second frequency divider module 120 can be frequency divider-by-two flip-flops. For example, the frequency divider-by-two flip-flops constituting the first frequency divider module 110 and the second frequency divider module can be SN74LVC74A type D flip-flops. In practical applications, the specific form of the first frequency divider module 110 and the second frequency divider module 120 can be a frequency divider-by-two flip-flop chip.
[0060] Figure 5 This is a schematic diagram of a first frequency divider module 110 provided in one embodiment of the present invention. Optionally, based on the above embodiments, refer to... Figure 5 The first frequency divider module 110 is composed of the first frequency divider trigger chip U2.
[0061] The first input terminal 1CLK of the first frequency divider chip U2 serves as the first input terminal of the first frequency divider module 110 and is connected to the clock signal SIG. The first output terminal 1Q of the first frequency divider chip U2 serves as the first output terminal of the first frequency divider module 110 and is coupled to the first input terminal of the second frequency divider module 120 through a level converter 150. The second input terminal 2CLK of the first frequency divider chip U2 serves as the second input terminal of the first frequency divider module 110 and is coupled to the first output terminal of the second frequency divider module 120 through a level converter 150. The second output terminal 2Q of the first frequency divider chip U2 serves as the second output terminal of the first frequency divider module 110 and is coupled to the second input terminal of the second frequency divider module 120 through a level converter 150.
[0062] The power supply terminal VCCA, the first reset input terminal 1CLR*, the first preset input terminal 1PRE*, the second reset input terminal 2CLR*, and the second preset input terminal 2PRE* of the first divide-by-two trigger chip U2 are all connected to the power supply voltage VCC. The first inverting output terminal 1Q* of the first divide-by-two trigger chip U2 is coupled to the first data input terminal 1D of the first divide-by-two trigger chip U2, and the second inverting output terminal 2Q* of the first divide-by-two trigger chip U2 is coupled to the second data input terminal 2D of the first divide-by-two trigger chip U2. The ground terminal GND of the first divide-by-two trigger chip U2 is grounded. It should be noted that the power supply terminal VCCA of the first divide-by-two trigger chip U2 can also be coupled to the first terminal of the third capacitor C3 and the first terminal of the fourth capacitor C4, and the second terminals of the third capacitor C3 and the fourth capacitor C4 are grounded. The third capacitor C3 and the fourth capacitor C4 are used to absorb low-frequency fluctuations and suppress high-frequency interference.
[0063] Figure 6 This is a schematic diagram of a second frequency divider module 120 provided in one embodiment of the present invention. Optionally, based on the above embodiments, refer to... Figure 6 The second frequency divider module 120 is composed of the second frequency divider trigger chip U3.
[0064] The first input terminal 1CLK of the second frequency divider chip U3 serves as the first input terminal of the second frequency divider module 120 and is coupled to the first output terminal of the first frequency divider module 110 through a level converter 150. The first output terminal 1Q of the second frequency divider chip U3 serves as the first output terminal of the second frequency divider module 120 and is coupled to the second input terminal of the first frequency divider module 110 through a level converter 150. The second input terminal 2CLK of the second frequency divider chip U3 serves as the second input terminal of the second frequency divider module 120 and is coupled to the second output terminal of the first frequency divider module 110 through a level converter 150. The second output terminal 2Q of the second frequency divider chip U3 serves as the second output terminal of the second frequency divider module 120 and is coupled to the load device 10.
[0065] The power supply terminal VCCA, the first reset input 1CLR*, the first preset input 1PRE*, the second reset input 2CLR*, and the second preset input 2PRE* of the second divide-by-two trigger chip U3 are all connected to the power supply voltage VCC. The first inverting output terminal 1Q* of the second divide-by-two trigger chip U3 is coupled to the first data input terminal 1D of the second divide-by-two trigger chip U3, and the second inverting output terminal 2Q* of the second divide-by-two trigger chip U3 is coupled to the second data input terminal 2D of the second divide-by-two trigger chip U3. The ground terminal GND of the second divide-by-two trigger chip U3 is grounded. It should be noted that the power supply terminal VCCA of the second divide-by-two trigger chip U3 can also be coupled to the first terminal of the fifth capacitor C5 and the first terminal of the sixth capacitor C6, and the second terminals of the fifth capacitor C5 and the sixth capacitor C6 are grounded. The fifth capacitor C5 and the sixth capacitor C6 are used to absorb low-frequency fluctuations and suppress high-frequency interference.
[0066] Figure 7 This is a schematic diagram of another multi-stage frequency division device provided in one embodiment of the present invention. Optionally, based on the above embodiments, refer to... Figure 7 The multi-stage frequency divider also includes a first buffer 130 and a second buffer 140.
[0067] The first buffer 130 is used to couple multiple load devices 10 and drive the corresponding load devices 10 based on the received first frequency division signal FP1 and third frequency division signal FP3 respectively; the second buffer 140 is used to couple the load devices 10 and drive the corresponding load devices 10 based on the received second frequency division signal FP2. It should be noted that the load devices 10 is a general term for all devices connected to the multi-level frequency divider, and the load devices 10 do not specifically refer to one type or class of devices; the load devices 10 can be different devices.
[0068] Specifically, when the second frequency divider module 120 is coupled to the first frequency divider module 110 via the level converter 150, i.e., when the multi-stage frequency divider outputs the fourth frequency divider signal FP4, the second buffer 140 acquires the fourth frequency divider signal FP4 output by the second frequency divider module 120 and drives the connected load device 10 based on the acquired fourth frequency divider signal FP4. For example, the first buffer 130 and the second buffer 140 can be SN74AUC2G241 type dual-channel buffer drivers.
[0069] It should be noted that in some embodiments of practical applications, the first frequency divider module 110 may also have a third output terminal and a fourth output terminal. Both the third and first output terminals of the first frequency divider module 110 are used to output the first frequency-divided signal FP1. The difference is that the first output terminal of the first frequency divider module 110 is coupled to the second frequency divider module 120, while the third output terminal of the first frequency divider module 110 is coupled to the first buffer 130. Similarly, both the fourth and second output terminals of the first frequency divider module 110 are used to output the third frequency-divided signal FP3. The difference is that the second output terminal of the first frequency divider module 110 is coupled to the second frequency divider module 120, while the fourth output terminal of the first frequency divider module 110 is coupled to the first buffer 130.
[0070] Similarly, in some practical applications, the second frequency divider module 120 may also have a third output terminal and a fourth output terminal. The third output terminal and the first output terminal of the second frequency divider module 120 are both used to output the second frequency divided signal FP2. The difference is that the first output terminal of the second frequency divider module 120 is coupled to the first frequency divider module 110, while the third output terminal of the second frequency divider module 120 is coupled to the second buffer 140. The fourth output terminal and the second output terminal of the second frequency divider module 120 are both used to output the fourth frequency divided signal FP4. The difference is that the second output terminal of the second frequency divider module 120 is coupled to the first frequency divider module 110, while the fourth output terminal of the second frequency divider module 120 is coupled to the second buffer 140.
[0071] Specifically, the first frequency divider module 110 can simultaneously output multiple first frequency divider signals FP1. At least one first frequency divider signal FP1 output by the first frequency divider module 110 is output to the second frequency divider module 120 through a level converter 150. The at least one first frequency divider signal FP1 output by the first frequency divider module 110 is also output to the load device 10 through a first buffer 130. The first buffer 130 amplifies the first frequency divider signal FP1 output by the first frequency divider module 110 to prevent signal distortion. After being amplified by the first buffer 130, the signal strength of the first frequency divider signal FP1 is improved. In practical applications, the first buffer 130 can simultaneously amplify and output multiple first frequency divider signals FP1 to respond to multiple load devices 10 simultaneously.
[0072] The second frequency divider module 120 can simultaneously output multiple second frequency divider signals FP2 and multiple fourth frequency divider signals FP4, and the first frequency divider module 110 can simultaneously output multiple third frequency divider signals FP3. At least one second frequency divider signal FP2 output by the second frequency divider module 120 is output to the first frequency divider module 110 via a level converter 150, and at least one second frequency divider signal FP2 output by the second frequency divider module 120 is output to the load device 10 via a second buffer 140. At least one third frequency divider signal FP3 output by the first frequency divider module 110 is output to the second frequency divider module 120 via a level converter 150, and at least one third frequency divider signal FP3 output by the first frequency divider module 110 is output to the load device 10 via a first buffer 130. The fourth frequency divider signal FP4 output by the second frequency divider module 120 is output to the load device 10 via a second buffer 140. Among them, the third frequency division signal FP3 after being enhanced by the first buffer 130, the second frequency division signal FP2 after being enhanced by the second buffer 140, and the fourth frequency division signal FP4 after being enhanced by the second buffer 140 can all respond to multiple load devices 10.
[0073] In this embodiment, the first frequency division signal FP1 and the third frequency division signal FP3 are enhanced by the first buffer 130, and the third frequency division signal FP3 and the fourth frequency division signal FP4 are enhanced by the second buffer 140, which is beneficial to improving the load capacity of the multi-level frequency division device.
[0074] Based on the above embodiments, optionally, the first buffer 130 can be a first buffer chip U4 in actual application, and the second buffer 140 can be a second buffer chip U5 in actual application.
[0075] Figure 8 This is a schematic diagram of a first buffer 130 provided in one embodiment of the present invention. Optionally, based on the above embodiments, refer to... Figure 8 The first buffer 130 is composed of the first buffer chip U4.
[0076] The first input terminal 1A of the first buffer chip U4 is coupled to the first output terminal of the first frequency divider module 110, the first output terminal 1Y of the first buffer chip U4 is coupled to the load device 10, the second input terminal 2A of the first buffer chip U4 is coupled to the second output terminal of the first frequency divider module 110, and the second output terminal 2Y of the first buffer chip U4 is coupled to the load device 10.
[0077] The power supply terminal VCCA of the first buffer chip U4 is connected to the power supply voltage VCC, the ground terminal GND of the first buffer chip U4 is grounded, the first output enable terminal 1OE of the first buffer chip U4 is grounded, and the second output enable terminal 2OE of the first buffer chip U4 is connected to the power supply voltage VCC through the first resistor R1. The first resistor R1 is used to pull the level of the second output enable terminal 2OE of the first buffer chip U4 high, so that the second output enable terminal 2OE of the first buffer chip U4 is clamped at a high level. The power supply terminal VCCA of the first buffer chip U4 can also be coupled to the first terminal of the seventh capacitor C7 and the first terminal of the eighth capacitor C8, and the second terminals of the seventh capacitor C7 and the eighth capacitor C8 are grounded. The seventh capacitor C7 and the eighth capacitor C8 are used to absorb low-frequency fluctuations and suppress high-frequency interference.
[0078] Figure 9 This is a schematic diagram of a second buffer 140 provided in one embodiment of the present invention. Optionally, based on the above embodiments, refer to... Figure 9 The second buffer 140 is composed of the second buffer chip U5.
[0079] The first input terminal 1A of the second buffer chip U5 is coupled to the first output terminal of the second frequency divider module 120, the first output terminal 1Y of the second buffer chip U5 is coupled to the load device 10, the second input terminal 2A of the second buffer chip U5 is coupled to the second output terminal of the second frequency divider module 120, and the second output terminal of the second buffer chip U5 is coupled to the load device 10.
[0080] The power supply terminal VCCA of the second buffer chip U5 is connected to the power supply voltage VCC, the ground terminal GND of the second buffer chip U5 is grounded, the first output enable terminal 1OE of the second buffer chip U5 is grounded, and the second output enable terminal 2OE of the second buffer chip U5 is connected to the power supply voltage VCC through the second resistor R2. The second resistor R2 is used to pull the level of the second output enable terminal 2OE of the second buffer chip U5 high, so that the second output enable terminal 2OE of the second buffer chip U5 is clamped at a high level. The power supply terminal VCCA of the second buffer chip U5 can also be coupled to the first terminal of the ninth capacitor C9 and the first terminal of the tenth capacitor C10, and the second terminals of the ninth capacitor C9 and the tenth capacitor C10 are grounded. The ninth capacitor C9 and the tenth capacitor C10 are used to absorb low-frequency fluctuations and suppress high-frequency interference.
[0081] Based on the above embodiments, optionally, in practical applications, the second output terminal of the second frequency divider module 120 can also be coupled to the signal converter 20 via a level converter 150. The signal converter 20 is used to convert the fourth frequency divider signal FP4, which represents a square wave, into a sine wave of the same frequency.
[0082] Optionally, based on the above embodiments, the level converter 150 may also be in the form of a chip. Figure 10 This is a schematic diagram of a level converter 150 provided in one embodiment of the present invention. (Refer to...) Figure 10 The level converter 150 is composed of the level converter chip U6.
[0083] The first input terminal A1 of the level converter chip U6 is coupled to the first output terminal of the first frequency divider module 110. The first output terminal B1 of the level converter chip U6 is coupled to the first input terminal of the second frequency divider module 120. The second input terminal B2 of the level converter chip U6 is coupled to the first output terminal of the second frequency divider module 120. The second output terminal A2 of the level converter chip U6 is coupled to the second input terminal of the first frequency divider module 110. The third input terminal A3 of the level converter chip U6 is coupled to the second output terminal of the first frequency divider module 110. The third output terminal B3 of the level converter chip U6 is coupled to the second input terminal of the second frequency divider module 120. The fourth input terminal B4 of the level converter chip U6 is coupled to the second output terminal of the second frequency divider module 120. The fourth output terminal A4 of the level converter chip U6 is coupled to the signal converter 20. The first power supply terminal VCCA and the second power supply terminal VCCB of the level converter chip U6 are connected to the power supply voltage VCC. The output enable terminal OE of the level converter chip U6 is connected to the power supply voltage VCC through the third resistor R3. The ground terminal GND of the level converter chip U6 is grounded. The first power supply terminal VCCA of the level converter chip U6 can also be coupled to the first terminal of the eleventh capacitor C11 and the first terminal of the twelfth capacitor C12. The second terminals of the eleventh capacitor C11 and the twelfth capacitor C12 are grounded. The second power supply terminal VCCB of the level converter chip U6 can also be coupled to the first terminal of the thirteenth capacitor C13 and the first terminal of the fourteenth capacitor C14. The second terminals of the thirteenth capacitor C13 and the fourteenth capacitor C14 are grounded. The eleventh capacitor C11, the twelfth capacitor C12, the thirteenth capacitor C13, and the fourteenth capacitor C14 are used to absorb low-frequency fluctuations and suppress high-frequency interference.
[0084] In practical applications, it is optional to connect the signal converter 20 based on actual needs. When the signal converter 20 is not required, the fourth input terminal B4 and the fourth output terminal A4 of the level converter chip U6 are left floating.
[0085] This utility model embodiment also provides a control system 1000. Figure 11 This is a schematic diagram of a control system 1000 provided in one embodiment of the present invention. (Refer to...) Figure 11The control system 1000 includes the multi-level frequency divider 100 and the control module 200 provided in any of the above embodiments. The multi-level frequency divider 100 provides control signals to the control module 200. For example, the control module 200 can be a field-programmable gate array (FPGA).
[0086] The control system 1000 provided in this embodiment has the beneficial effects of the multi-level frequency division device 100 provided in any of the above embodiments, which will not be described in detail here.
[0087] This utility model embodiment also provides a drive system 2000. Figure 12 This is a schematic diagram of a drive system 2000 provided in an embodiment of the present invention. (Refer to...) Figure 12 The control system 2000 includes the multi-level frequency divider 100 and the load terminal 300 provided in any of the above embodiments. The multi-level frequency divider 100 provides drive signals to the load terminal 300. For example, the load terminal 300 can be an image acquisition device such as a camera or monitor.
[0088] The control system 2000 provided in this embodiment has the beneficial effects of the multi-level frequency division device 100 provided in any of the above embodiments, which will not be described in detail here.
[0089] It should be understood that the various forms of the process shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this utility model can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this utility model can be achieved, and this is not limited herein.
[0090] The specific embodiments described above do not constitute a limitation on the scope of protection of this utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.
Claims
1. A multi-stage frequency division device, characterized in that, include: First frequency divider module, level converter, and second frequency divider module; The first input terminal of the first frequency divider module is used to receive a clock signal. The first frequency divider module is configured to output multiple first frequency divider signals of the same or different frequencies according to the clock signal. The first output terminal of the first frequency divider module is coupled to the first input terminal of the second frequency divider module through the level converter. The second frequency divider module is configured to output multiple second frequency divider signals of the same or different frequencies based on the first frequency divider signal output from the first output terminal of the first frequency divider module, wherein the first output terminal of the second frequency divider module is coupled to the second input terminal of the first frequency divider module through the level converter; The first frequency divider module is further configured to output multiple third frequency divider signals of the same or different frequencies based on the second frequency divider signal output from the first output terminal of the second frequency divider module.
2. The multi-stage frequency division device according to claim 1, characterized in that, It also includes oscillators; The oscillator is coupled to the first input terminal of the first frequency divider module; The oscillator is used to generate the clock signal.
3. The multi-stage frequency division device according to claim 1, characterized in that, The second output terminal of the first frequency divider module is coupled to the second input terminal of the second frequency divider module through the level converter. The second frequency divider module is further configured to output multiple fourth frequency divider signals of the same or different frequencies based on the third frequency divider signal output from the second output terminal of the first frequency divider module.
4. The multi-stage frequency division device according to any one of claims 1-3, characterized in that, Both the first frequency divider module and the second frequency divider module are divide-by-two triggers.
5. The multi-stage frequency division device according to claim 1, characterized in that, It also includes a first buffer and a second buffer; the first buffer is used to couple multiple load devices and drive the corresponding load devices based on the received first frequency division signal and the third frequency division signal; The second buffer is used to couple the load device and drive the corresponding load device based on the received second frequency division signal.
6. The multi-stage frequency division device according to claim 3, characterized in that, It also includes a first buffer and a second buffer; The first buffer is used to couple multiple load devices and drive the corresponding load devices based on the received first frequency division signal and the third frequency division signal; The second buffer is used to couple multiple load devices and drive the corresponding load devices based on the received second and fourth frequency division signals.
7. The multi-stage frequency division device according to claim 3, characterized in that, The second output terminal of the second frequency divider module is coupled to a signal converter through the level converter. The signal converter is used to convert the fourth frequency divider signal, which represents a square wave, into a sine wave of the same frequency.
8. The multi-stage frequency division device according to claim 6, characterized in that, The first input terminal of the first buffer is coupled to the third output terminal of the first frequency divider module to receive the first frequency divider signal, and the second input terminal of the first buffer is coupled to the fourth output terminal of the first frequency divider signal to receive the third frequency divider signal. The first input terminal of the second buffer is coupled to the third output terminal of the second frequency divider module to receive the second frequency divider signal, and the second input terminal of the second buffer is coupled to the fourth output terminal of the second frequency divider module to receive the fourth frequency divider signal.
9. A control system, characterized in that, Includes the multi-stage frequency division device as described in any one of claims 1-8, and a control module; The multi-level frequency divider is used to provide control signals to the control module.
10. A drive system, characterized in that, Includes the multi-level frequency division device as described in any one of claims 1-8, and a load terminal; The multi-level frequency divider is used to provide drive signals to the load terminal.