A filter circuit

Abstract

This utility model relates to the field of filtering circuit technology and discloses a filtering circuit, including a buffer BUF, an upper switch S1, a lower switch S2, a capacitor C1, a Schmitt trigger SIMT, an inverter INV1, and at least one capacitor branch. In use, this utility model shapes the signal to be filtered in the buffer BUF and enhances it in the Schmitt trigger SIMT and the inverter INV1. By setting at least one capacitor branch at the input of the Schmitt trigger SIMT, and controlling whether the switch SW in the capacitor branch is turned on, the filtering time of the filtering circuit changes when the number of capacitors in parallel changes, thus realizing the adjustment of the filtering time.

Description

Technical Field

[0001] This utility model relates to the field of filter circuit technology, and specifically to a filter circuit. Background Technology

[0002] Filtering circuits are crucial electronic circuits used to screen or process the frequency components of signals. Their core function is to allow signals within a specific frequency range to pass through while suppressing signals in other frequency ranges. In electronic devices, filtering circuits are widely used in power supply regulation, signal processing, and communication systems, for example, to remove AC ripple from power supplies and extract specific frequency bands from audio signals.

[0003] Existing filter circuits typically have a fixed filtering time that cannot be adjusted, resulting in poor applicability and making them unsuitable for a wide range of filtering applications. Utility Model Content

[0004] In view of the shortcomings of the prior art, the present invention provides a filtering circuit. The technical problem to be solved is that the filtering time of the existing filtering circuit is fixed and cannot be adjusted.

[0005] To solve the above technical problems, this utility model provides the following technical solution: a filter circuit, including a buffer BUF, an upper switch S1, a lower switch S2, a capacitor C1, a Schmitt trigger SIMT, an inverter INV1, and at least one capacitor branch;

[0006] The input terminal of the buffer BUF is a filter interface used to input the signal to be filtered. The output terminal of the buffer BUF is electrically connected to the control terminal of the upper switch S1 and the control terminal of the lower switch S2. The output terminal of the upper switch S1 is electrically connected to the input terminal of the lower switch S2, one end of the capacitor C1, and the input terminal of the Schmitt trigger SIMT. The output terminal of the lower switch S2 and the other end of the capacitor C1 are both grounded. The output terminal of the Schmitt trigger SIMT is electrically connected to the input terminal of the inverter INV1.

[0007] The capacitor branch includes a switch SW and a capacitor C2. One end of the switch SW is electrically connected to the input of the Schmitt trigger (SIMT), and the other end of the switch SW is grounded through the capacitor C2.

[0008] In one embodiment, the upper switch S1 is turned on when the output terminal of the buffer BUF outputs a low-level signal, and turned off when the output terminal of the buffer BUF outputs a high-level signal.

[0009] In one embodiment, the upper switching transistor S1 is a PMOS transistor.

[0010] In one embodiment, the channel width of the upper switching transistor S1 is less than the channel length.

[0011] In one embodiment, the lower switch S2 is turned off when the output of the buffer BUF is low, and turned on when the output of the buffer BUF is high.

[0012] In one embodiment, the lower switching transistor S2 is an NMOS transistor.

[0013] In one embodiment, the channel width of the lower switching transistor S2 is less than the channel length.

[0014] In one embodiment, the input terminal of the upper switch S1 is used to connect to the power supply voltage.

[0015] In one embodiment, the input terminal of the upper switching transistor S1 is electrically connected to a bias current generating unit, which is used to input a bias current to the input terminal of the upper switching transistor S1.

[0016] In one embodiment, the bias current generating unit includes MOSFET P10, MOSFET P11, operational amplifier EA, MOSFET N10, and resistor R10;

[0017] The source of MOSFET P10 and the source of MOSFET P11 are electrically connected for power supply. The gate of MOSFET P10 is electrically connected to the gate of MOSFET P11, the drain of MOSFET P10, and the drain of MOSFET N10. The gate of MOSFET N10 is electrically connected to the output terminal of operational amplifier EA. The positive input terminal of operational amplifier EA is used to input bias voltage. The negative input terminal of operational amplifier EA is electrically connected to the source of MOSFET N10 and one end of resistor R10. The other end of resistor R10 is grounded. The drain of MOSFET P11 is electrically connected to the input terminal of the upper switching transistor S1.

[0018] The advantages of this invention compared to the prior art are as follows: Based on the shaping of the signal to be filtered by the buffer BUF and the shaping and enhancement by the Schmitt trigger SIMT and the inverter INV1, this invention sets at least one capacitor branch at the input of the Schmitt trigger SIMT. By controlling whether the switch SW in the capacitor branch is turned on, the filtering time of the filtering circuit changes when the number of capacitors connected in parallel changes, thus realizing the adjustment of the filtering time. Attached Figure Description

[0019] Figure 1 This is a circuit diagram of the present invention in the embodiments;

[0020] Figure 2 This is a circuit diagram of the bias current generating unit in the embodiment. Detailed Implementation

[0021] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the present invention, and therefore only show the components relevant to the present invention.

[0022] like Figure 1 As shown, a filter circuit includes a buffer BUF, an upper switch S1, a lower switch S2, a capacitor C1, a Schmitt trigger SIMT, an inverter INV1, and a capacitor branch 1.

[0023] The input terminal of the buffer BUF is a filter interface used to input the signal to be filtered. The output terminal of the buffer BUF is electrically connected to the control terminal of the upper switch S1 and the control terminal of the lower switch S2. The output terminal of the upper switch S1 is electrically connected to the input terminal of the lower switch S2, one end of the capacitor C1, and the input terminal of the Schmitt trigger SIMT. The output terminal of the lower switch S2 and the other end of the capacitor C1 are both grounded. The output terminal of the Schmitt trigger SIMT is electrically connected to the input terminal of the inverter INV1.

[0024] The capacitor branch 1 includes a switch SW and a capacitor C2. One end of the switch SW is electrically connected to the input of a Schmitt trigger (SIMT), and the other end of the switch SW is grounded through the capacitor C2.

[0025] for Figure 1 The circuit shown uses a buffer BUF to shape the signal to be filtered, and a Schmitt trigger SIMT and an inverter INV1 to shape and enhance the signal.

[0026] In practical use, this invention shapes the signal to be filtered in the buffer BUF and enhances it in the Schmitt trigger SIMT and inverter INV1. It then sets at least one capacitor branch 1 at the input of the Schmitt trigger SIMT and controls whether the capacitor C2 is connected to the filter by controlling whether the switch SW in the capacitor branch 1 is on. In this way, when the number of capacitors connected in parallel for filtering changes, the filtering time of the filtering circuit changes, thus realizing the adjustment of the filtering time.

[0027] In one implementation, two capacitor branches 1, three capacitor branches 1, or other numbers of capacitor branches 1 can be set according to actual needs, thereby enabling more adjustments to the filtering time.

[0028] In one embodiment, the capacitance value of capacitor C2 in all capacitor branches 1 can be the same. In another embodiment, the capacitance value of capacitor C2 in all capacitor branches 1 can be different from each other. In yet another embodiment, the capacitance value of capacitor C2 in some capacitor branches 1 can be the same.

[0029] In this embodiment, switch SW is a transmission gate.

[0030] Specifically, in this embodiment, the upper switch S1 is turned on when the output terminal of the buffer BUF outputs a low-level signal, and turned off when the output terminal of the buffer BUF outputs a high-level signal.

[0031] In addition, the upper switch S1 is a PMOS transistor, and the channel width of the upper switch S1 is less than the channel length. At this time, the upper switch S1 is an inverting transistor. The signal can be changed slowly through the inverting transistor, capacitor C1 and capacitor C2 to achieve filtering.

[0032] Specifically, in this embodiment, the lower switch S2 is turned off when the output of the buffer BUF is low, and turned on when the output of the buffer BUF is high.

[0033] In addition, the lower switch S2 is an NMOS transistor, and the channel width of the lower switch S2 is less than the channel length. At this time, the lower switch S2 is an inverting transistor. The signal can be changed slowly through the inverting transistor, capacitor C1 and capacitor C2, so as to achieve filtering.

[0034] In this embodiment, Figure 1 In the middle, the input terminal of the upper switch S1 is used to connect the power supply voltage VDD.

[0035] In one embodiment, the bias current generating unit can be electrically connected to the input terminal of the switching transistor S1. The bias current generating unit is used to input bias current to the input terminal of the switching transistor S1, and to achieve filtering by charging capacitors C1 and C2 through the bias current.

[0036] The circuit of the bias current generating unit is as follows: Figure 2 As shown, it includes MOSFET P10, MOSFET P11, operational amplifier EA, MOSFET N10, and resistor R10;

[0037] The source of MOSFET P10 and the source of MOSFET P11 are electrically connected to the power supply. The gate of MOSFET P10 is electrically connected to the gate of MOSFET P11, the drain of MOSFET P10, and the drain of MOSFET N10. The gate of MOSFET N10 is electrically connected to the output terminal of operational amplifier EA. The positive input terminal of operational amplifier EA is used to input the bias voltage VREF. The negative input terminal of operational amplifier EA is electrically connected to the source of MOSFET N10 and one end of resistor R10. The other end of resistor R10 is grounded. The drain of MOSFET P11 is electrically connected to the input terminal of the upper switching transistor S1.

[0038] for Figure 2In the circuit shown, MOSFETs P10 and P11 form a current mirror. The bias voltage VREF is applied to resistor R10 through operational amplifier EA, forming the primary current. The value of the primary current is VREF / R10. Assuming... Figure 2 If the current replication ratio of the MOSFET P11 in the current mirror is K, then the expression for the bias current output from the drain of the MOSFET P11 is K*VREF / R10. Therefore, by adjusting the values ​​of VREF, R10, and K, the bias current can be adjusted, thereby adjusting the charging current of capacitors C1 and C2, and further adjusting the charging time of capacitors C1 and C2, thus realizing the adjustment of the filtering time.

[0039] Based on the above description and inspired by this utility model, those skilled in the art can make various changes and modifications without departing from the technical concept of this utility model. The technical scope of this utility model is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A filter circuit, characterized in that, It includes a buffer BUF, an upper switch S1, a lower switch S2, a capacitor C1, a Schmitt trigger SIMT, an inverter INV1, and at least one capacitor branch; The input terminal of the buffer BUF is a filter interface used to input the signal to be filtered. The output terminal of the buffer BUF is electrically connected to the control terminal of the upper switch S1 and the control terminal of the lower switch S2. The output terminal of the upper switch S1 is electrically connected to the input terminal of the lower switch S2, one end of the capacitor C1, and the input terminal of the Schmitt trigger SIMT. The output terminal of the lower switch S2 and the other end of the capacitor C1 are both grounded. The output terminal of the Schmitt trigger SIMT is electrically connected to the input terminal of the inverter INV1. The capacitor branch includes a switch SW and a capacitor C2. One end of the switch SW is electrically connected to the input of the Schmitt trigger (SIMT), and the other end of the switch SW is grounded through the capacitor C2.

2. The filter circuit according to claim 1, characterized in that, The upper switch S1 is turned on when the output terminal of the buffer BUF outputs a low-level signal, and turned off when the output terminal of the buffer BUF outputs a high-level signal.

3. A filter circuit according to claim 2, characterized in that, The upper switch S1 is a PMOS transistor.

4. A filter circuit according to claim 3, characterized in that, The channel width of the upper switch S1 is less than the channel length.

5. A filter circuit according to any one of claims 1-4, characterized in that, The lower switch S2 is turned off when the output of the buffer BUF is low, and turned on when the output of the buffer BUF is high.

6. A filter circuit according to claim 5, characterized in that, The lower switch S2 is an NMOS transistor.

7. A filter circuit according to claim 6, characterized in that, The channel width of the lower switching transistor S2 is less than the channel length.

8. A filter circuit according to claim 1, characterized in that, The input terminal of the upper switch S1 is used to connect to the power supply voltage.

9. A filter circuit according to claim 1, characterized in that, The input terminal of the upper switch S1 is electrically connected to the bias current generating unit, which is used to input bias current to the input terminal of the upper switch S1.

10. A filter circuit according to claim 9, characterized in that, The bias current generating unit includes MOSFET P10, MOSFET P11, operational amplifier EA, MOSFET N10, and resistor R10; The source of MOSFET P10 and the source of MOSFET P11 are electrically connected for power supply. The gate of MOSFET P10 is electrically connected to the gate of MOSFET P11, the drain of MOSFET P10, and the drain of MOSFET N10. The gate of MOSFET N10 is electrically connected to the output terminal of operational amplifier EA. The positive input terminal of operational amplifier EA is used to input bias voltage. The negative input terminal of operational amplifier EA is electrically connected to the source of MOSFET N10 and one end of resistor R10. The other end of resistor R10 is grounded. The drain of MOSFET P11 is electrically connected to the input terminal of the upper switching transistor S1.

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