Semiconductor device

Abstract

A semiconductor device includes a transistor structure comprising a plurality of source and drain regions adjacent to a gate; a first interlayer dielectric layer above the gate and source and drain regions; a plurality of source / drain contacts extending through the first interlayer dielectric layer and electrically coupled to the source and drain regions; a plurality of contact spacers on a plurality of sidewalls of the source / drain contacts; a low-k contact etch stop layer above the first interlayer dielectric layer, the source / drain contacts, and the contact spacers; a second interlayer dielectric layer above the low-k contact etch stop layer; a first conductive feature in the second interlayer dielectric layer and the low-k contact etch stop layer; and a plurality of insulating plugs plugged in the low-k contact etch stop layer and the contact spacers. The first conductive feature is electrically coupled to the source / drain contacts. The insulating plugs are adjacent to the first conductive feature in the low-k contact etch stop layer and to the source / drain contacts in the contact spacers.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously increases the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Utility Model Content

[0004] In some embodiments, a semiconductor device includes a transistor structure, a first interlayer dielectric layer, a plurality of source / drain contacts, a plurality of contact spacers, a low-k contact etch stop layer, a second interlayer dielectric layer, a first conductive feature, and a plurality of insulating plugs. The transistor structure includes a plurality of source and drain regions adjacent to a gate. The first interlayer dielectric layer is above the gate and the source and drain regions. The plurality of source / drain contacts extend through the first interlayer dielectric layer and electrically couple the source and drain regions. The plurality of contact spacers are on a plurality of sidewalls of the source / drain contacts. The low-k contact etch stop layer is above the first interlayer dielectric layer, the source / drain contacts, and the contact spacers. The second interlayer dielectric layer is above the low-k contact etch stop layer. The first conductive feature is in the second interlayer dielectric layer and the low-k contact etch stop layer, and the first conductive feature is electrically coupled to the source / drain contacts. Multiple insulating plugs are located in the low-k contact etch stop layer and in these contact spacers. These insulating plugs are adjacent to the first conductive feature in the low-k contact etch stop layer and to the source / drain contacts in these contact spacers.

[0005] In some embodiments, a semiconductor device includes a transistor structure, a first interlayer dielectric layer, a plurality of source / drain contacts, a plurality of contact spacers, a low-k contact etch stop layer, a second interlayer dielectric layer, a first conductive feature, a plurality of insulating plugs, and a gate contact. The transistor structure includes a plurality of source and drain regions adjacent to a gate. The first interlayer dielectric layer is above the gate and source / drain regions. The plurality of source / drain contacts extend through the first interlayer dielectric layer and electrically couple these source and drain regions. The plurality of contact spacers are on a plurality of sidewalls of the source / drain contacts. The low-k contact etch stop layer is above the first interlayer dielectric layer, the source / drain contacts, and the contact spacers. The second interlayer dielectric layer is above the low-k contact etch stop layer. The first conductive feature is in the second interlayer dielectric layer and the low-k contact etch stop layer. The plurality of insulating plugs are in the low-k contact etch stop layer and the contact spacers, and these insulating plugs are adjacent to the first conductive feature in the low-k contact etch stop layer and to the source / drain contacts in the contact spacers. The gate contact extends through the second interlayer dielectric layer, the low-k contact etch stop layer, and the first interlayer dielectric layer.

[0006] In some embodiments, a semiconductor device includes a transistor structure, a first interlayer dielectric layer, a plurality of source / drain contacts, a plurality of contact spacers, a low-k contact etch stop layer, a second interlayer dielectric layer, a first conductive feature, and a plurality of insulating plugs. The transistor structure includes a plurality of source and drain regions adjacent to a gate. The first interlayer dielectric layer is above the gate and the source and drain regions. The plurality of source / drain contacts extend through the first interlayer dielectric layer and electrically couple the source and drain regions. The plurality of contact spacers are on a plurality of sidewalls of the source / drain contacts. The low-k contact etch stop layer is above the first interlayer dielectric layer, the source / drain contacts, and the contact spacers. The second interlayer dielectric layer is above the low-k contact etch stop layer. The first conductive feature is located in the second interlayer dielectric layer and the low-k contact etch stop layer, and the first conductive feature is electrically coupled to the source / drain contacts, wherein the distance between the plurality of outer sidewalls of the first conductive feature is in the range of 20 nm to 1000 nm. Multiple insulating plugs are located in the low-k contact etch stop layer and contact spacers, with the insulating plugs adjacent to a first conductive feature in the low-k contact etch stop layer. Attached Figure Description

[0007] The form of this disclosure is similar to that of the accompanying document. Figure 1 The best way to understand this text is by referring to the detailed description below. Please note that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1An example of a three-dimensional view of a nanostructure field-effect transistor (nano-FET) according to some embodiments is shown;

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B and Figure 20C This is a cross-sectional view of an intermediate stage in the fabrication of a nano-FET according to some implementation methods;

[0010] Figure 21A , Figure 21B and Figure 21C This is a cross-sectional view of a nano-FET according to some implementation methods;

[0011] Figure 22 , Figure 23 , Figure 24 , Figure 25 , Figure 26 , Figure 27 , Figure 28A , Figure 28B and Figure 28C A cross-sectional view of a further process of a nano-FET according to some embodiments is shown;

[0012] Figure 29A and Figure 29B A cross-sectional view of a further process of a nano-FET according to some embodiments is shown.

[0013] [Symbol Explanation]

[0014] 20: Spacer

[0015] 50:Substrate

[0016] 50N: n-type region

[0017] 50P:p-type area

[0018] 51, 51A, 51B, 51C: First semiconductor layer

[0019] 52, 52A, 52B, 52C: First Nanostructure

[0020] 53, 53A, 53B, 53C: Second semiconductor layer

[0021] 54, 54A, 54B, 54C: Second nanostructure

[0022] 55: Nanostructures

[0023] 64: Multi-layer stacking

[0024] 66: Fin

[0025] 68: Shallow Trench Isolation (STI) Zone

[0026] 70: Virtual Dielectric Layer

[0027] 71: Virtual gate dielectric

[0028] 72: Virtual Gate Layer

[0029] 74: Masking layer

[0030] 76: Virtual Gate

[0031] 78: Mask

[0032] 80: First spacer layer

[0033] 81: First spacer

[0034] 82: Second spacer layer

[0035] 83: Second spacer

[0036] 86: First Groove

[0037] 88: Sidewall Groove

[0038] 90: First internal spacer

[0039] 92: Source / Drain Region

[0040] 92A: First semiconductor material layer

[0041] 92B: Second semiconductor material layer

[0042] 92C: Third semiconductor material layer

[0043] 94:CESL

[0044] 96, 106, 122: ILD

[0045] 98: Second groove

[0046] 100: Gate dielectric layer

[0047] 102, 102N, 102P: Gate

[0048] 104: Gate Mask

[0049] 108: Third Groove

[0050] 110: Silicide region

[0051] 112: Contact spacer

[0052] 114: Contact element

[0053] 120: Intermediate CESL (MCESL)

[0054] 126: Gate contact

[0055] 128: Three-layer photoresist

[0056] 130: Bottom

[0057] 132: Intermediate Layer

[0058] 134: Photoresist layer

[0059] 136: Groove

[0060] 138: Processing Technology

[0061] 140: Processing Layer

[0062] 140': Oxide plug

[0063] 148: Through-hole drain rail

[0064] A-A', B-B', C-C': Cross-sections

[0065] D1, D2: Distance

[0066] W1, W2, W3, W4: Width

[0067] H1, H2, H3, H4: Height

[0068] A, B, C: Areas Detailed Implementation

[0069] The following disclosure provides many different implementations or examples for carrying out various features of the novel invention. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include implementations where the first and second features are formed in direct contact, and may also include implementations where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various implementations and / or configurations discussed.

[0070] Additionally, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and the like are used herein for ease of description to describe the relationship between one element or feature and another illustrated in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein will be interpreted accordingly.

[0071] This disclosure relates to various methods and structures for semiconductor devices, with a particular focus on the challenges associated with the formation of conductive features in semiconductor devices as feature sizes continue to shrink. As the semiconductor industry strives to increase the integration density of electronic components, the reduction in minimum feature sizes introduces new challenges, including the potential increase in leakage current between closely spaced features. This leakage can degrade device performance and reliability, thus requiring innovative solutions to mitigate such issues.

[0072] In some aspects, the disclosed method involves forming a first interlayer dielectric (ILD) over a transistor structure, followed by forming a plurality of conductive contacts through the ILD to the transistor structure. Next, a contact etch stop layer (CESL) is formed over the conductive contacts and the ILD. Subsequent layers and features are built on this structure, including a second ILD and additional conductive contacts. In some embodiments, the disclosed method includes etching trenches in the second ILD and CESL, followed by an oxygen-based treatment within the trenches. This treatment alters the CESL and any existing contact spacers, forming a treated layer as a protective barrier against leakage.

[0073] Oxygen-based processing is an innovative aspect of the revealed method because it involves exposing the groove to an oxygen-containing gas at a specific pressure, possibly in combination with an inert gas such as nitrogen, argon, or a rare gas. The resulting processed layer formed in the CESL and contact spacers has a controlled range of dimensions, thickness, and width, and is tailored to provide effective leakage protection while maintaining the structural integrity of the semiconductor device.

[0074] The revealed methods and structures offer several advantages, including improved electrical isolation between conductive features, enhanced device performance, and increased reliability. By addressing the leakage current challenges associated with advanced semiconductor devices, the revealed methods and structures contribute to the continued development of the semiconductor industry, enabling the production of more complex and capable electronic components for a wide range of applications.

[0075] The following description of embodiments is in a specific context, and one device includes a nano-FET. However, various embodiments can be applied to dies including other types of transistors (e.g., fin field-effect transistors, planar transistors, etc.) that replace or are combined with nano-FETs.

[0076] Figure 1An example of a three-dimensional view of a nano-FET (e.g., nanowire FET, nanosheet FET, Nano-FET, etc.) according to some embodiments is shown. The nano-FET includes a plurality of nanostructures 55 (e.g., nanosheets, nanowires, etc.) above a plurality of fins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructures 55 act as channel regions of the nano-FET. The nanostructures 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Shallow trench isolation (STI) regions 68 are disposed between adjacent fins 66, which may protrude over and between adjacent shallow trench isolation (STI) regions 68. Although the shallow trench isolation (STI) regions 68 are described / shown as separate from the substrate 50, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom of fin 66 is shown as being a single, continuous material with substrate 50, the bottom of fin 66 and / or substrate 50 may comprise a single material or multiple materials. In this document, fin 66 refers to the portion extending between adjacent shallow trench isolation (STI) regions 68.

[0077] The gate dielectric layer 100 is above the top surface of the fin 66 and extends along the top, sidewalls, and bottom surface of the nanostructure 55. The gate 102 is above the gate dielectric layer 100. Epitaxial source / drain regions 92 are formed on the fin 66 on opposite sides of the gate dielectric layer 100 and the gate 102. The source / drain regions 92 may refer individually or collectively to either the source or the drain, depending on the context.

[0078] Figure 1 The reference cross-sections used in the following figures are further illustrated. Cross-section A-A' is along the longitudinal axis of gate 102 and in the direction of current flow, for example, perpendicular to the source / drain region 92 of the nano-FET epitaxial layer. Cross-section B-B' is perpendicular to cross-section A-A' and parallel to the longitudinal axis of the nano-FET fin 66 and in the direction of current flow, for example, between the source / drain region 92 of the nano-FET epitaxial layer. Cross-section C-C' is parallel to cross-section A-A' and extends through the source / drain region of the nano-FET epitaxial layer. For clarity, the following figures refer to these reference cross-sections.

[0079] Some of the embodiments discussed herein are discussed in the context of nano-FETs formed using a post-gate fabrication process. In other embodiments, a gate-first process may be used. Moreover, some embodiments consider layers used in planar devices, such as planar FETs or FinFETs.

[0080] Figures 2 to 20C This is a cross-sectional view of an intermediate stage in the fabrication of a nano-FET according to some implementation methods. Figures 2 to 5 , Figure 6A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A and Figure 21A It shows Figure 1 The reference section A-A' is shown in the figure. Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 10C , Figure 11B , Figure 11C , Figure 12B , Figure 12D , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B and Figure 21B It shows Figure 1 The reference section B-B' is shown in the figure. Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 12C , Figure 13C , Figure 18C , Figure 19C , Figure 20C and Figure 21C It shows Figure 1 The reference cross section C-C' shown is illustrated.

[0081] exist Figure 2In this embodiment, a substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc. The substrate 50 can be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate has a semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is supplied on the substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of substrate 50 may include silicon, germanium, compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, alloy semiconductors including silicon germanium, gallium arsenide phosphide, indium aluminum arsenide, indium gallium arsenide, indium gallium phosphide and / or gallium indium arsenide phosphide, or combinations thereof.

[0082] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an n-type metal-oxide-semiconductor (NMOS) transistor like an n-type nano-FET, and the p-type region 50P can be used to form a p-type device, such as a p-type metal-oxide-semiconductor (PMOS) transistor like a p-type nano-FET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by spacer 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be disposed.

[0083] Further in Figure 2In this process, a multilayer stack 64 is formed above the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A, 51B, and 51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A, 53B, and 53C (collectively referred to as second semiconductor layers 53). For illustrative purposes and in more detail below, the second semiconductor layer 53 will be removed and the first semiconductor layer 51 will be patterned to form a channel region for a nano-FET in the p-type region 50P. The first semiconductor layer 51 will also be removed and the second semiconductor layer 53 will also be patterned to form a channel region for a nano-FET in the n-type region 50N. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region for a nano-FET in the n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region for a nano-FET in the p-type region 50P.

[0084] In another embodiment, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form channel regions for a nano-FET in both the n-type region 50N and the p-type region 50P. In another embodiment, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form non-FET channel regions in both the n-type region 50N and the p-type region 50P. In such an embodiment, the channel regions in both the n-type region 50N and the p-type region 50P may have the same material composition (e.g., silicon or another semiconductor material) and be formed simultaneously. Figure 21A , Figure 21B and Figure 21C The structure resulting from such an implementation is shown, wherein the channel regions in both the p-type region 50P and the n-type region 50N comprise, for example, silicon.

[0085] For illustrative purposes, the multilayer stack 64 is described as comprising three layers, each of a first semiconductor layer 51 and a second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), or molecular beam epitaxy (MBE). In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for a p-type nano-FET, such as silicon germanium, and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for an n-type nano-FET, such as silicon or silicon carbon. For illustrative purposes, the multilayer stack 64 is described as having a bottom semiconductor layer suitable for a p-type nano-FET. In some embodiments, the multilayer stack 64 may be formed such that the bottom layer is a semiconductor layer suitable for an n-type nano-FET.

[0086] The multiple first semiconductor materials and the multiple second semiconductor materials can be materials with high etch selectivity to each other. Therefore, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material in the n-type region 50N, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the n-type nano-FET. Similarly, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material in the p-type region 50P, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the p-type nano-FET.

[0087] Now for reference Figure 3According to some embodiments, fins 66 are formed in substrate 50 and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches in multilayer stack 64 and substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic. The nanostructures 55 formed by etching multilayer stack 64 can further define first nanostructures 52A, 52B, and 52C (collectively referred to as first nanostructures 52) from first semiconductor layer 51 and second nanostructures 54A, 54B, and 54C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. First nanostructures 52 and second nanostructures 54 are further collectively referred to as nanostructures 55.

[0088] The fins 66 and nanostructures 55 can be patterned by any suitable method. For example, one or more lithography processes, including dual or multiple patterning processes, can be used to pattern the fins 66 and nanostructures 55. Generally, dual or multiple patterning processes combine lithography with self-alignment processes, allowing the creation of patterns with smaller spacing, for example, than that achievable using other methods employing a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the fins 66.

[0089] For the purpose of explanation, Figure 3 The fins 66 in the n-type region 50N and the p-type region 50P are shown to have substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N may be larger or thinner than the width of the fins 66 in the p-type region 50P. Further, while each of the fins 66 and nanostructures 55 is shown to have a uniform width everywhere, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls, such that the width of each of the fins 66 and / or nanostructures 55 increases continuously in the direction toward the substrate 50. In some embodiments, each nanostructure 55 may have a different width and be trapezoidal in shape.

[0090] exist Figure 4In this embodiment, shallow trench isolation (STI) regions 68 are formed on adjacent fins 66. The shallow trench isolation (STI) regions 68 can be formed by depositing an insulating material over the substrate 50, fins 66, and nanostructure 55, and between adjacent fins 66. The insulating material can be an oxide, nitride, or combination thereof of silicon oxide, and can be formed using high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or combinations thereof. Other insulating materials can be formed using any acceptable process. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed such that an excess of insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments may use multiple layers. For example, in some embodiments, a liner (not shown separately) may be formed first along the surfaces of the substrate 50, fins 66, and nanostructure 55. Afterward, a filling material, such as those discussed above, can be formed on top of the padding.

[0091] Next, a removal process is applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof can be used. The planarization process exposes the nanostructure 55 such that the nanostructure 55 and the multiple top surfaces of the insulating material are at the same height after the planarization process is completed.

[0092] Next, the insulating material is recessed to form shallow trench isolation (STI) regions 68. The insulating material is recessed such that the upper portion of the fin 66 in the n-type region 50N and the p-type region 50P protrudes between adjacent shallow trench isolation (STI) regions 68. Further, the top surface of the shallow trench isolation (STI) region 68 can have a flat surface, a convex surface, a concave surface (e.g., dishing), or a combination thereof, as shown. The top surface of the shallow trench isolation (STI) region 68 can be formed as flat, convex, and / or concave by appropriate etching. The shallow trench isolation (STI) region 68 can be recessed using an acceptable etching process, such as a material-selective etching process for the insulating material (e.g., etching the insulating material at a faster rate than the material of the fin 66 and the nanostructure 55). For example, dilute hydrofluoric acid (dHF) can be used to remove oxides.

[0093] The above about Figures 2 to 4 The described process is merely one example of how the fins 66 and nanostructures 55 can be formed. In some embodiments, masking and epitaxial growth processes can be used to form the fins 66 and / or nanostructures 55. For example, a dielectric layer can be formed above the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structures can include alternating semiconductor materials, such as a first semiconductor material and a second semiconductor material, as discussed below. In some embodiments where the epitaxial structure is epitaxially grown, the material for epitaxial growth can be doped in situ during growth, which can avoid prior and / or subsequent implantation, although in-situ and implantation doping can be used together.

[0094] Furthermore, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) are shown and discussed herein as comprising the same material in the p-type region 50P and the n-type region 50N, for illustrative purposes only. Therefore, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials or formed in different orders in the p-type region 50P and the n-type region 50N.

[0095] Further in Figure 4In this process, suitable traps (not shown separately) can be formed in the fin 66, nanostructure 55, and / or shallow trench isolation (STI) region 68. In embodiments with different trap types, different implantation steps for the n-type region 50N and p-type region 50P can be implemented using photoresist or other masks (not shown separately). For example, photoresist can be formed over the fin 66 and shallow trench isolation (STI) region 68 in the n-type region 50N and p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed using spin coating techniques and can be patterned using acceptable lithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, etc., and the n-type impurity is implanted in the region at a concentration of about 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 Within the range. After implantation, the photoresist is removed, for example, through an acceptable ashing process.

[0096] After or before the implantation of the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 66, nanostructures 55, and shallow trench isolation (STI) regions 68 in both the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating and can be patterned using acceptable lithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, etc., and the concentration of the p-type impurities implanted in the region is approximately 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 Within a certain range. After implantation, the photoresist can be removed, for example, through an acceptable ashing process.

[0097] After the implantation of the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be doped in situ during growth, which can avoid implantation, although in-situ and implantation doping can be used together.

[0098] exist Figure 5 In this configuration, a dummy dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. The dummy dielectric layer 70 can be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed over the dummy dielectric layer 70, and a masking layer 74 is formed over the dummy gate layer 72. The dummy gate layer 72 can be deposited over the dummy dielectric layer 70 and subsequently planarized, for example, by CMP. The masking layer 74 can be deposited over the dummy gate layer 72. The dummy gate layer 72 can be a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polycrystalline silicon, polycrystalline silicon-germanium, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 72 can be made of other materials with high etch selectivity for etching the shallow trench isolation (STI) region 68. The mask layer 74 can include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. It should be noted that, for illustrative purposes only, the dummy dielectric layer 70 is shown as covering only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 can be deposited such that the dummy dielectric layer 70 covers the shallow trench isolation (STI) region 68, such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the shallow trench isolation (STI) region 68.

[0099] Figures 6A to 18C Various additional steps in the manufacture of the apparatus in multiple embodiments are shown. Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 12C , Figure 13A , Figure 13C , Figure 14A , Figure 15A and Figure 18C The characteristics of either the n-type region 50N or the p-type region 50P are shown. Figure 6A and Figure 6B In the middle, mask layer 74 (see Figure 5 The mask 78 can be patterned using acceptable lithography and etching techniques. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form the dummy gate 76 and dummy gate dielectric 71, respectively. The dummy gate 76 covers the channel region of the respective fin 66. The pattern of the mask 78 can be used to separate each dummy gate 76 from adjacent dummy gate 76 entities. The dummy gate 76 may also have a length direction, which is substantially perpendicular to the length direction of the respective fin 66.

[0100] exist Figure 7A and Figure 7B In, respectively in Figure 6A and Figure 6B A first spacer layer 80 and a second spacer layer 82 are formed above the structure shown. The first spacer layer 80 and the second spacer layer 82 are then patterned as spacers for forming self-aligned source / drain regions. Figure 7A and Figure 7B In this configuration, a first spacer layer 80 is formed on the top surface of the shallow trench isolation (STI) region 68, multiple top surfaces and sidewalls of the fin 66, nanostructure 55, and mask 78, as well as multiple sidewalls of the dummy gate 76 and dummy gate dielectric 71. A second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 may be formed of silicon oxide, silicon nitride, or the like, and may be formed using techniques such as thermal oxidation or deposition via CVD, ALD, etc. The second spacer layer 82 may be formed of a material having a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and may be deposited via CVD, ALD, etc.

[0101] After the first spacer layer 80 is formed and before the second spacer layer 82 is formed, the placement of lightly doped source / drain (LDD) regions (not shown separately) can be performed. In embodiments with different device types, this is similar to the above. Figure 4The implantation discussed herein can involve forming a mask, such as a photoresist, over the n-type region 50N, while simultaneously exposing the p-type region 50P, and implanting an appropriate type of impurity (e.g., p-type) into the exposed fins 66 and nanostructures 55 within the p-type region 50P. The mask can then be removed. Subsequently, a mask, such as a photoresist, can be formed over the p-type region 50P, while simultaneously exposing the n-type region 50N, and implanting an appropriate type of impurity (e.g., n-type) into the exposed fins 66 and nanostructures 55 within the n-type region 50N. The mask can then be removed. The n-type impurity can be any of the n-type impurities discussed previously, and the p-type impurity can be any of the p-type impurities discussed previously. The mask can then be removed. The lightly doped source / drain regions can have a density of approximately 1 × 10⁻⁶. 15 atoms / cm 3 To approximately 1×10 19 atoms / cm 3 The concentration of impurities within the specified range. Annealing can be used to repair damaged fabric and revitalize the fabric.

[0102] exist Figure 8A and Figure 8B In the process, a first spacer layer 80 and a second spacer layer 82 are etched to form a first spacer 81 and a second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 serve to self-align the subsequently formed source and drain regions and to protect the multiple sidewalls of the fin 66 and / or nanostructure 55 during subsequent processes. The first spacer layer 80 and the second spacer layer 82 can be etched using appropriate etching processes, such as isotropic etching processes (e.g., wet etching processes), anisotropic etching processes (e.g., dry etching processes), etc. In some embodiments, the material of the second spacer layer 82 has a different etch rate than the material of the first spacer layer 80, such that when the second spacer layer 82 is patterned, the first spacer layer 80 can act as an etch stop layer, and when the first spacer layer 80 is patterned, the second spacer layer 82 can act as a mask. For example, as Figure 8A As shown, the second spacer layer 82 can be processed using an anisotropic etching process, wherein the first spacer layer 80 acts as an etch stop layer, and the remaining portion of the second spacer layer 82 forms the second spacer 83. Subsequently, as... Figure 8A As shown, the second spacer 83 acts as a mask, while the exposed portion of the first spacer layer 80 is etched to form the first spacer 81.

[0103] like Figure 8A As shown, a first spacer 81 and a second spacer 83 are disposed on multiple sidewalls of the fin 66 and / or the nanostructure 55. Figure 8BAs shown, the second spacer layer 82 can be removed from above the first spacer layer 80 adjacent to the mask 78, dummy gate 76, and dummy gate dielectric 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, dummy gate 76, and dummy gate dielectric 71. In some embodiments, a portion of the second spacer layer 82 may remain above the first spacer layer 80 adjacent to the mask 78, dummy gate 76, and dummy gate dielectric 71.

[0104] It should be noted that the above disclosure generally describes the process for forming the spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, different sequences of steps may be used (e.g., the first spacer 81 may be patterned before the second spacer layer 82 is deposited), additional spacers may be formed and removed, and / or the like. Furthermore, n-type and p-type devices may be formed using different structures and steps.

[0105] exist Figure 9A and Figure 9B In some embodiments, a first groove 86 is formed in the fin 66, nanostructure 55, and substrate 50. Epitaxial source / drain regions are then formed in the first groove 86. The first groove 86 may extend through the first nanostructure 52 and the second nanostructure 54 and into the substrate 50. Figure 9A As shown, the top surface of the shallow trench isolation (STI) region 68 can be flush with the bottom surface of the first groove 86. In various embodiments, the fin 66 can be etched such that the bottom surface of the first groove 86 is positioned below the top surface of the shallow trench isolation (STI) region 68. The first groove 86 can be formed by etching the fin 66, nanostructure 55, and substrate 50 using anisotropic etching processes such as RIE, NBE, etc. The first spacer 81, the second spacer 83, and the mask 78, the fin 66, the nanostructure 55, and the mask portion of the substrate 50 are used to form the first groove 86 during the etching process. A single etching process or multiple etching processes can be used to etch each layer of the nanostructure 55 and / or the fin 66. A timed etch process can be used to stop the etching of the first groove 86 after it reaches a desired depth.

[0106] exist Figure 10A and Figure 10BIn the process, portions of the sidewalls of the layer of nanostructure 55 formed of a first semiconductor material (e.g., first nanostructure 52) exposed by the first groove 86 are etched to form sidewall grooves 88 in the n-type region 50N, and portions of the sidewalls of the layer of nanostructure 55 formed of a second semiconductor material (e.g., second nanostructure 54) exposed by the first groove 86 are etched to form sidewall grooves 88 in the p-type region 50P. Although the multiple sidewalls of the first nanostructure 52 and the second nanostructure 54 in the sidewall grooves 88 are... Figure 10B The p-type region 50P is shown as straight, but the sidewalls can be concave or convex. The sidewalls can be etched using an isotropic etching process such as wet etching. The p-type region 50P can be protected using a photomask (not shown) while the first nanostructure 52 is etched using an etchant selective for the first semiconductor material, such that the second nanostructure 54 and the substrate 50 remain relatively unetched compared to the first nanostructure 52 in the n-type region 50N. Similarly, the n-type region 50N can be protected using a mask (not shown) while the second nanostructure 54 is etched using an etchant selective for the second semiconductor material, such that the first nanostructure 52 and the substrate 50 remain relatively unetched compared to the second nanostructure 54 in the p-type region 50P. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si or SiC, a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., can be used to etch the sidewalls of the first nanostructure 52 in the n-type region 50N, and a wet or dry etching process using hydrogen fluoride, another fluorine-based etchant, etc., can be used to etch the sidewalls of the second nanostructure 54 in the p-type region 50P.

[0107] Figure 10C Other embodiments are shown, wherein portions of the sidewalls of the layer of nanostructure 55 formed of a first semiconductor material (e.g., first nanostructure 52), exposed by the first recess 86, are etched to form sidewall recesses 88 in both the n-type region 50N and the p-type region 50P. In these embodiments, the channel regions in the n-type region 50N and the p-type region 50P can be formed simultaneously in a subsequent process, for example, by removing the first nanostructure 52 from both the n-type region 50N and the p-type region 50P. In such embodiments, the multiple channel regions of the n-type nano-FET and the p-type nano-FET can have the same material composition, such as silicon, silicon germanium, or the like. Figure 21A , Figure 21B and Figure 21CA structure resulting from such an embodiment is shown, wherein the channel regions in both the p-type region 50P and the n-type region 50N are provided by a second nanostructure 54 and the channel regions in both the p-type region 50P and the n-type region 50N comprise, for example, silicon.

[0108] exist Figures 11A to 11C In the middle, a first internal spacer 90 is formed in the sidewall groove 88. The first internal spacer 90 can be formed by, for example, Figure 10A and Figure 10B The structure shown is formed by depositing an internal spacer layer (not shown separately) over it. The first internal spacer 90 serves as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the first recess 86, while the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P will be replaced with the corresponding gate structures.

[0109] The internal spacer layer can be deposited using conformal deposition processes such as CVD, ALD, etc. The internal spacer layer can comprise materials such as silicon nitride or silicon oxynitride, although any suitable material can be used, such as low-k materials with a k value less than about 3.5. The internal spacer layer can then be anisotropically etched to form a first internal spacer 90. Although the outer walls of the first internal spacer 90 are shown flush with the sidewalls of the second nanostructure 54 in the n-type region 50N and the first nanostructure 52 in the p-type region 50P, the outer walls of the first internal spacer 90 can extend beyond or recess from the sidewalls of the second nanostructure 54 and / or the first nanostructure 52, respectively.

[0110] Furthermore, although the outer wall of the first internal spacer 90 is in Figure 11B The middle section is shown as straight, but the outer wall of the first inner spacer 90 may be concave or convex. As an example, Figure 11C One embodiment is shown in which the sidewalls of the first nanostructure 52 are concave, the outer sidewalls of the first internal spacer 90 are concave, and the first internal spacer 90 is recessed from the sidewalls of the second nanostructure 54 in the n-type region 50N. Another embodiment is also shown in which the sidewalls of the second nanostructure 54 are concave, the outer sidewalls of the first internal spacer 90 are concave, and the first internal spacer 90 is recessed from the sidewalls of the first nanostructure 52 in the p-type region 50P. The internal spacer layer can be etched using anisotropic etching processes, such as RIE, NBE, etc. The first internal spacer 90 can be used to prevent damage to the subsequently formed source / drain regions by subsequent etching processes, such as etching processes used to form gate structures.

[0111] exist Figures 12A to 12C In the first groove 86, an epitaxial source / drain region 92 is formed. In some embodiments, the source / drain region 92 can apply stress to the second nanostructure 54 in the n-type region 50N and the first nanostructure 52 in the p-type region 50P, thereby improving performance. Figure 12B As shown, epitaxial source / drain regions 92 are formed in the first recess 86 such that each dummy gate 76 is disposed between adjacent pairs of its respective epitaxial source / drain regions 92. In some embodiments, a first spacer 81 is used to separate the epitaxial source / drain regions 92 from the dummy gates 76 and a first inner spacer 90 is used to separate the epitaxial source / drain regions 92 from the nanostructure 55, with appropriate lateral spacing so that the epitaxial source / drain regions 92 subsequently form the gate of the resulting nano-FET without short-circuiting.

[0112] Epitaxial source / drain regions 92 in an n-type region 50N, such as an NMOS region, can be formed by shielding a p-type region 50P, such as a PMOS region. The source / drain regions 92 are then epitaxially grown in a first recess 86 in the n-type region 50N. The epitaxial source / drain regions 92 can comprise any acceptable material suitable for an n-type nano-FET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain regions 92 can comprise a material to which tensile strain is applied to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain regions 92 can have surfaces protruding from various upper surfaces of the nanostructure 55 and can have multiple small planes.

[0113] An epitaxial source / drain region 92 in a p-type region 50P, such as a PMOS region, can be formed by shielding an n-type region 50N, such as an NMOS region. The epitaxial source / drain region 92 is then epitaxially grown in a first recess 86 in the p-type region 50P. The epitaxial source / drain region 92 can comprise any acceptable material suitable for a p-type nano-FET. For example, if the first nanostructure 52 is silicon-germanium, the epitaxial source / drain region 92 can comprise a material that applies compressive strain to the first nanostructure 52, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or the like. The epitaxial source / drain region 92 can also have surfaces protruding from the various surfaces of the multilayer stack and can have multiple small planes.

[0114] The epitaxial source / drain regions 92, the first nanostructure 52, the second nanostructure 54, and / or the substrate 50 can be doped to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The source / drain regions can have a dopant density of approximately 1 × 10⁻⁶. 19 atoms / cm 3 1×1021 atoms / cm 3 The impurity concentrations between these values. The n-type and / or p-type impurities used in the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0115] Because the epitaxial process is used to form epitaxial source / drain regions 92 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions 92 has small facets that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these small facets result in the epitaxial source / drain regions 92 of the same nano-FET being arranged as follows: Figure 12A The shown is a merge. In other embodiments, such as... Figure 12C As shown, after the epitaxial process is completed, the source / drain regions 92 of adjacent epitaxial layers remain separated. Figure 12A and Figure 12C In the illustrated embodiment, the first spacer 81 may be formed to the top surface of the shallow trench isolation (STI) region 68, thereby blocking epitaxial growth. In some other embodiments, the first spacer 81 may cover a portion of the sidewalls of the nanostructure 55, further blocking epitaxial growth. In some other embodiments, the spacer etching used to form the first spacer 81 may be adjusted to remove spacer material, allowing the epitaxial growth region to extend to the surface of the shallow trench isolation (STI) region 68.

[0116] The epitaxial source / drain region 92 may include one or more layers of semiconductor material. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers can be used for the epitaxial source / drain region 92. Each first semiconductor material layer 92A, second semiconductor material layer 92B, and third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration less than that of the second semiconductor material layer 92B and greater than that of the third semiconductor material layer 92C. In embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0117] Figure 12DOne embodiment is shown in which the sidewalls of the first nanostructure 52 in the n-type region 50N and the sidewalls of the second nanostructure 54 in the p-type region 50P are concave, the outer sidewall of the first internal spacer 90 is concave, and the first internal spacer 90 is recessed from the sidewalls of the second nanostructure 54 and the first nanostructure 52, respectively. Figure 12D As shown, the epitaxial source / drain region 92 can be formed to contact the first internal spacer 90 and can extend beyond the sidewall of the second nanostructure 54 in the n-type region 50N and beyond the sidewall of the first nanostructure 52 in the p-type region 50P.

[0118] exist Figures 13A to 13C In the middle, ILD 96 respectively in Figure 6A , Figure 12B and Figure 12A Deposition above the structure shown ( Figures 7A to 12D The process has not changed. Figure 6A (See the cross-section shown). ILD 96 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, CESL 94 is disposed between ILD 96 and the epitaxial source / drain region 92, mask 78, and first spacer 81. CESL 94 may include a dielectric material having a different etch rate than the material covering ILD 96, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0119] exist Figures 14A to 14B In this process, a planarization process such as CMP can be performed to make the top surface of the ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process can also remove the mask 78 on the dummy gate 76 and a portion of the first spacer 81 along the sidewalls of the mask 78. After the planarization process, the dummy gate 76, the first spacer 81, and the top surface of the ILD 96 are flush during the change. Therefore, the top surface of the dummy gate 76 is exposed through the ILD 96. In some embodiments, the mask 78 can be retained, in which case the planarization process makes the top surface of the ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0120] exist Figure 15A and Figure 15B In one or more etching steps, the dummy gate 76 and mask 78 (if present) are removed such that a second recess 98 is formed. A portion of the dummy dielectric layer in the second recess 98 is also removed. In some embodiments, the dummy gate 76 and dummy dielectric layer are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 76 at a faster rate than the ILD 96 or the first spacer 81. Each second recess 98 exposes and / or covers a portion of a nanostructure 55, which serves as a channel region in the subsequently completed nano-FET. The portions of the nanostructure 55 serving as channel regions are positioned between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy dielectric layer can be used as an etch stop layer as the dummy gate 76 is etched. After the dummy gate 76 is removed, the dummy dielectric layer can then be removed.

[0121] exist Figure 16A and Figure 16B In this embodiment, the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P are removed, extending the second groove 98. The first nanostructure 52 can be removed by forming a mask (not shown) over the p-type region 50P and performing an isotropic etching process, such as wet etching, using an etchant selective for the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the shallow trench isolation (STI) region 68 remain relatively unetched compared to the first nanostructure 52. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., can be used to remove the first nanostructure 52 in the n-type region 50N.

[0122] The second nanostructure 54 in the p-type region 50P can be removed by forming a mask (not shown) over the n-type region 50N and using an isotropic etching process, such as wet etching, with an etchant selective for the material of the second nanostructure 54. Meanwhile, the first nanostructure 52, the substrate 50, and the shallow trench isolation (STI) region 68 remain relatively unetched compared to the second nanostructure 54. In embodiments where the second nanostructure 54 comprises, for example, SiGe and the first nanostructure 52 comprises Si or SiC, hydrogen fluoride, another fluorine-based etchant, etc., can be used to remove the second nanostructure 54 in the p-type region 50P.

[0123] In other embodiments, the channel regions in the n-type region 50N and the p-type region 50P can be formed simultaneously, for example, by removing the first nanostructure 52 from both the n-type region 50N and the p-type region 50P, or by removing the second nanostructure 54 from both the n-type region 50N and the p-type region 50P. In such embodiments, the multiple channel regions of the n-type nano-FET and the p-type nano-FET can have the same material composition, such as silicon, silicon germanium, etc. Figure 21A , Figure 21B and Figure 21C A structure resulting from such an embodiment is shown, wherein the channel regions in both the p-type region 50P and the n-type region 50N are provided by a second nanostructure 54 and include, for example, silicon.

[0124] exist Figure 17A and Figure 17B In this configuration, gate dielectric layer 100 and gate 102 are formed to replace the gate. Gate dielectric layer 100 is conformally deposited in the second trench 98. In the n-type region 50N, gate dielectric layer 100 can be formed on the top surface and sidewalls of substrate 50 and the top surface, sidewalls, and bottom surface of the second nanostructure 54, and in the p-type region 50P, gate dielectric layer 100 can be formed on the top surface and sidewalls of substrate 50 and the top surface, sidewalls, and bottom surface of the first nanostructure 52. Gate dielectric layer 100 can also be deposited on multiple upper surfaces of ILD 96, CESL 94, the first spacer 81, and the shallow trench isolation (STI) region 68.

[0125] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a k value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structures of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P may be the same or different. Methods for forming the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0126] Gate 102 is deposited over gate dielectric layer 100 and fills the remaining portion of second trench 98. Gate 102 may include metallic materials such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although Figure 17A and Figure 17B A single-layer gate 102 is shown, but the gate 102 may include any number of pad layers, any number of work function adjustment layers, and filler material. Any combination of layers constituting the gate 102 may be deposited between adjacent second nanostructures 54 in the n-type region 50N and between the second nanostructure 54A and the substrate 50, and may be deposited between adjacent first nanostructures 52 in the p-type region 50P.

[0127] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 100 in each region can be formed of the same material, and the formation of the gate 102 can occur simultaneously, such that the gate 102 in each region can be formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed by different processes, such that the gate dielectric layer 100 can be of different materials and / or have different numbers of layers, and / or the gate 102 in each region can be formed by different processes, such that the gate 102 can be of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate areas.

[0128] After filling the second recess 98, a planarization process, such as CMP, can be performed to remove excess material from the gate dielectric layer 100 and gate 102 above the top surface of the ILD 96. The remaining material of gate 102 and gate dielectric layer 100 thus form the alternative gate structure of the resulting nano-FET. Gate 102 and gate dielectric layer 100 can be collectively referred to as the “gate structure”.

[0129] exist Figures 18A to 18C In this configuration, the gate structure (including the gate dielectric layer 100 and the corresponding covered gate 102) is recessed, such that the groove is formed directly above the gate structure and between opposing portions of the first spacer 81. The gate mask 104 comprises one or more layers of dielectric material, such as silicon nitride or silicon oxynitride, which are filled in the groove. A planarization process is then performed to remove excess dielectric material extending over the ILD 96. The subsequently formed gate contacts (such as those referenced below) Figure 22 The gate contact 126 discussed penetrates the gate shield 104 to contact the top surface of the recessed gate 102.

[0130] Depend on Figures 18A to 18CAs further shown, ILD 106 is deposited over ILD 96 and gate mask 104. In some embodiments, ILD 106 is a flowable film formed by FCVD. In some embodiments, ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc.

[0131] exist Figures 19A to 19C In this process, ILD 106, ILD 96, CESL 94, and gate mask 104 are etched to form a third recess 108 on the surface exposing the epitaxial source / drain regions 92. The third recess 108 can be formed using isotropic etching processes such as RIE, NBE, etc. In some embodiments, the third recess 108 can be etched through ILD 106 and ILD 96 using a first etching process, through gate mask 104 using a second etching process, and then through CESL 94 using a third etching process. A mask, such as photoresist, can be formed and patterned over ILD 106 to shield portions of ILD 106 from the effects of the first and second etching processes. In some embodiments, the etching process may over-etch, so the third groove 108 extends into the epitaxial source / drain region 92 and / or gate structure, and the bottom of the third groove 108 may be flush with the epitaxial source / drain region 92 and / or gate structure (e.g., at the same height, or at the same distance from the substrate), or lower than the epitaxial source / drain region 92 and / or gate structure (e.g., closer to the substrate). Although Figure 19B The third groove 108 is shown as exposing the epitaxial source / drain region 92 and gate structure in the same cross section, but in various embodiments, the epitaxial source / drain region 92 and gate structure can be exposed in different cross sections, thereby reducing the risk of short circuits in the subsequently formed contacts.

[0132] After the third groove 108 is formed, a silicide region 110 is formed over the epitaxial source / drain region 92. In some embodiments, the silicide region 110 is formed by first depositing a semiconductor material (e.g., silicon, silicon-germanium, germanium) capable of reacting with the underlying epitaxial source / drain region 92 to form a silicide or germanide region over the exposed area of ​​the epitaxial source / drain region 92, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof, followed by a thermal annealing process to form the silicide region 110. Unreacted areas of the deposited metal are then removed, for example, by an etching process. Although the silicide region 110 is referred to as a silicide region, it can also be a germanide region or a silicon-germanide region (e.g., a region comprising both silicides and germanides). In one embodiment, the silicide region 110 comprises TiSi and has a thickness ranging from about 2 nm to about 10 nm.

[0133] In some embodiments, contact spacers 112 are formed in the third recess 108. The contact spacers 112 may be formed before or after the formation of the silicide region 110, but will be described as being formed after the silicide region 110. Forming the contact spacers 112 within the third recess 108 includes depositing spacer material over the structure (third recess 108 and silicide region 110) after the formation of the third recess 108 and the silicide region 110. In some embodiments, the spacer material is selected based on the etch selectivity of the spacer material relative to the surrounding material, such as ILD 106 and the silicide region 110, to ensure that the spacer material can be selectively etched to form the contact spacers 112 without damaging adjacent structures. The spacer material may include silicon nitride, silicon oxide, silicon oxynitride, or other suitable dielectric materials. After deposition, an anisotropic etching process is used to remove the spacer material from the horizontal surface while retaining the spacer material on the sidewalls of the third recess 108, thereby forming the contact spacers 112. These contact spacers 112 can be used to electrically isolate the contact 114 from the gate 102 and other device features, and to protect the sidewalls of the third recess 108 during subsequent metallization processes.

[0134] Next, in Figures 20A to 20CIn this embodiment, contacts 114 (also referred to as contact plugs) are formed in a third groove 108 between contact spacers 112. Each contact 114 may comprise one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, each contact 114 comprises a barrier layer and a conductive material, and is electrically coupled to an underlying conductive feature (e.g., the silicide region 110 in the illustrated embodiment). The contact 114 is electrically coupled to the silicide region 110 and may be referred to as a source / drain contact 114. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the ILD 106.

[0135] Figures 21A to 21C A cross-sectional view of an apparatus according to some alternative embodiments is shown. Figure 21A It shows Figure 1 The reference section A-A' is shown. Figure 21B It shows Figure 1 The reference section B-B' is shown. Figure 21C It shows Figure 1 The reference section C-C' is shown. Figures 21A to 21C In this context, similar symbols represent combinations of... Figures 20A to 20C Similar components are formed using processes with similar structures. However, in Figures 21A to 21C In this configuration, the channel regions in the n-type region 50N and the p-type region 50P comprise the same material. For example, a second nanostructure 54 comprising silicon provides a p-type nano-FET for the p-type region 50P and an n-type nano-FET for the n-type region 50N. For example, this can be formed by simultaneously removing the first nanostructure 52 from both the p-type region 50P and the n-type region 50N. Figures 21A to 21C The structure includes: depositing a gate dielectric layer 100 and a gate 102P (e.g., a gate suitable for a p-type nano-FET) around a second nanostructure 54 in the p-type region 50P; and depositing a gate dielectric layer 100 and a gate 102N (e.g., a gate suitable for an n-type nano-FET) around a second nanostructure 54 in the n-type region 50N. In such an embodiment, as described above, the material of the epitaxial source / drain region 92 in the n-type region 50N can be different from that in the p-type region 50P.

[0136] Figures 22 to 28C The diagram illustrates a method according to some embodiments. Figures 20A to 20CThe embodiments are shown in cross-section for further processing. Further processing forms an interconnect structure (sometimes referred to as a front-side interconnect structure) over the transistor structure. In some embodiments, the formed interconnect structure includes a gate contact 126 and a via drain rail 148 (sometimes referred to as a power rail). These figures use... Figures 20A to 20C The embodiments shown are illustrated, but are also applicable to other embodiments. Figures 21A to 21C The implementation method. Figures 22 to 28C It shows Figure 1 The reference cross-section is shown as B-B'. These figures show multiple source / drain regions 92 adjacent to multiple gates 102, with source / drain contacts 114 coupled to each source / drain region 92.

[0137] Figure 22 The diagram shows a CESL (sometimes referred to as intermediate CESL (MCESL) 120) and ILD 122 formed over a previously formed structure including ILD 106 and gate mask 104.

[0138] Intermediate CESL (MCESL) 120 is formed above ILD 106. In some embodiments, intermediate CESL (MCESL) 120 is formed of a carbon-containing low-k dielectric material, which is designed to have a lower dielectric constant than silicon nitride, thereby improving device performance by reducing parasitic capacitance. In these embodiments, intermediate CESL (MCESL) 120 is characterized by its density (ranging from 1.9 g / cm³). 3 Up to 2.0 g / cm 3 The intermediate CESL (MCESL) 120 and its components (which include silicon, carbon, nitrogen, and oxygen in approximately 38 / 26 / 30 / 6 to 41 / 26 / 30 / 3%). In some embodiments, the k-value of the intermediate CESL (MCESL) 120 is approximately 4. In some embodiments, the intermediate CESL (MCESL) 120 is formed using precursors such as ammonia (NH3) and tetramethylsilane, resulting in the film providing etch selectivity during patterning and providing electrical isolation for the device.

[0139] After the intermediate CESL (MCESL) 120 is formed, the ILD 122 is formed from a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method, such as CVD, PECVD, etc. The ILD 122 serves as an additional insulating layer, providing further electrical isolation between the various components of the semiconductor device.

[0140] After depositing ILD 122, gate contact 126 is formed, extending through ILD 122, intermediate CESL (MCESL) 120, ILD 106, and CESL 94. Gate contact 126 is electrically coupled to gate 102, providing a conductive path for electrical signals entering and exiting gate 102. The formation of gate contact 126 includes controlled patterning and etching processes to ensure precise alignment and connection with gate 102.

[0141] Gate contact 126 may include a barrier layer (not shown). The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material of gate contact 126 may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc., or combinations thereof. A planarization process such as CMP may be performed to remove excess material from the surface of ILD 122.

[0142] Figure 23 A three-layer photoresist 128 is shown formed over ILD 122, which was previously deposited over ILD 106 and gate mask 104. The three-layer photoresist 128 includes a bottom layer 130, an intermediate layer 132, and a photoresist layer 134. This three-layer photoresist structure is designed to facilitate the subsequent lithography and etching processes for defining the via drain rail 148.

[0143] In some implementations, the bottom layer 130 of the three-layer photoresist 128 serves a dual purpose. It can act as an adhesion promoter and an anti-reflective coating. This ensures the adhesion of the overlay and improves the accuracy of the lithography process.

[0144] The intermediate layer 132 and photoresist layer 134 of the three-layer photoresist 128 are patterned to produce desired features in a semiconductor device. The patterning process involves selectively removing portions of these layers using lithography, i.e., transferring the desired pattern from the photomask to the photoresist layer. This patterned structure defines the region of the via drain rail 148 that will subsequently be formed.

[0145] Figure 24 The patterning of three photoresist layers 128 is shown to form a recess 136. The patterning process involves selectively removing portions of the photoresist layer 134, the intermediate layer 132, and the bottom layer 130 using lithography, i.e., transferring the desired pattern from the photomask to the photoresist layers. This patterned structure defines the region of the via drain rail 148 that will subsequently be formed. The recess 136 corresponds to the location and size of the subsequently formed via drain rail 148.

[0146] Figure 25Patterning of the ILD 122 extending the recess 136 using a three-layer photoresist 128 as a mask is illustrated. In some embodiments, patterning is an etching process in which exposed areas of the ILD 122 are selectively removed. During this etching process, a C4F6 / O2 / Ar gas mixture is used under controlled conditions at pressures ranging from 20 to 60 mTorr. In some embodiments, etching is performed using a frequency of 2 MHz and a power setting of 100 to 900 watts, combined with additional power of 27 MHz, 50 to 200 watts, and 60 MHz, 50 to 200 watts. These specific etching parameters are controlled to achieve the desired etching rate and selectivity. In some embodiments, as etching proceeds, the photoresist layer 134 and the intermediate layer 132 can be removed, leaving the complete underlayer 130. Depending on the etching conditions, the patterning step may extend partially into the intermediate CESL (MCESL) 120, or it may stop at the intermediate CESL (MCESL) 120. After the patterning step, the remaining bottom layer 130 serves as an etch mask for subsequent etching processes, which can further extend the groove 136 through the intermediate CESL (MCESL) 120.

[0147] Figure 26 Process 138 is shown to be performed on this structure, resulting in the formation of a processing layer 140 within the groove 136. Process 138 modifies portions of the contact spacer 112 and the intermediate CESL (MCESL) 120 to form the processing layer 140. The processing layer 140 is designed to enhance the protective properties of the contact spacer 112 and the intermediate CESL (MCESL) 120, improving the device's resistance to leakage and other forms of electrical interference.

[0148] In some embodiments, process 138 includes an oxygen-based treatment that transforms the exposed portions of the low-k intermediate CESL (MCESL) 120 and the silicon nitride contact spacer 112 into an oxide or similar oxide material. This transformation results in oxide plug 140' (see, for example...). Figure 27The oxide plug 140' is formed adjacent to the via drain rail 148 in the low-k intermediate CESL (MCESL) 120 and adjacent to the source / drain contact 114 in the contact spacer 112. The oxide plug 140' serves to electrically isolate the subsequently formed via drain rail 148 from the surrounding structure and prevent potential short circuits or leakage paths that could impair the performance of the semiconductor device. Furthermore, compared to the unchanged intermediate CESL (MCESL) 120 and the unchanged contact spacer 112, the processed layer 140 has a lower etch rate for subsequent etch processes extending through the intermediate CESL (MCESL) 120 to the contact 114. Therefore, the processed layer 140 prevents the intermediate CESL (MCESL) 120 and the contact spacer 112 from being over-etched during the process and forming depressions or protrusions for subsequent filling of conductive features.

[0149] In some embodiments, oxygen-based treatment may involve exposing the groove 136 to an oxygen-containing gas at a pressure ranging from 10 to 100 millitors, a power ranging from 50 to 600 watts, and a frequency of 60 MHz. The oxygen-containing gas may consist of pure oxygen or further include an inert gas selected from the group consisting of nitrogen, argon, and inert gases.

[0150] Figure 27 A further etching process is shown, which extends the groove 136 through the intermediate CESL (MCESL) 120 to expose the top surface of the contact 114. During this etching process, a CH3F / H2 gas mixture is used at pressures of 10 mTorr to 50 mTorr, and dual-frequency power applications are applied at 2 MHz, 20 W to 100 W and 60 MHz, 200 W to 900 W. These specific etching parameters are controlled to selectively remove portions of the previously formed processed layer 140, leaving the remaining portions forming oxide plugs 140'. The material composition of these oxide plugs 140' has been altered by the processing process 138 to exhibit different properties compared to the original materials of the intermediate CESL (MCESL) 120 and the contact spacer 112. For example, the oxide plugs 140' may have a higher oxygen content, which enhances their electrical isolation performance. An oxide plug 140' is located within the first conductive feature adjacent to the low-k intermediate CESL (MCESL) 120 and the source / drain contact 114 adjacent to the contact spacer 112 for electrically isolating the via drain rail 148, which will be formed in a recess 136 by the surrounding device features. This isolation enhances the reliability and performance of the semiconductor device by preventing electrical short circuits and leakage paths.

[0151] Figure 28AA via drain rail 148 is shown formed within a recess 136. The via drain rail 148 is formed to provide a conductive path across a specific distance D1 in the semiconductor device structure, connecting multiple source / drain contacts 114. In this cross-section of the distance D1 between the outer walls of the via drain rail 148, the distance D1 can range from about 20 nm to about 1000 nm, depending on the design requirements of the semiconductor device. The via drain rail 148 is a power distribution element within the device, particularly in structures such as ring oscillators or other integrated circuits requiring uniform power distribution across multiple transistors.

[0152] Figure 28A A via drain rail 148 is shown formed within a recess 136. The via drain rail 148 may be made of a metal such as copper or tungsten. The via drain rail 148 is formed to provide a conductive path connecting multiple source / drain contacts 114 across a specific distance D1 in the semiconductor device structure. In some embodiments, in this cross-section of the distance D1 between the outer walls of the via drain rail 148, the distance D1 can range from about 20 nm to about 1000 nm, depending on the design requirements of the semiconductor device.

[0153] Metal is deposited into groove 136, filling groove 136 to form via drain rail 148. After deposition, a planarization process such as chemical mechanical polishing (CMP) can be performed to flush the top surface of via drain rail 148 with the surrounding ILD 122. This ensures a uniform surface structure for subsequent manufacturing steps. Via drain rail 148 serves as a power distribution element within a device, such as in the structure of a ring oscillator or other integrated circuits requiring uniform power distribution across multiple transistors.

[0154] As described above, the processing layer 140 for Figure 27 The etching process shown has a low etching rate, which prevents the intermediate CESL (MCESL) 120 and contact spacer 112 from being over-etched during the etching process. If these layers were allowed to be over-etched, grooves or protrusions would be formed and would be filled with the conductive material of the via drain rail 148. These protrusions of the conductive material of the via drain rail 148 could lead to leakage problems in the device.

[0155] Figure 28B and Figure 28C They provided Figure 28AEnlarged views of regions A and B highlight the protective features formed around the via drain rail 148. The remaining processing layer (also referred to as oxide plug 140'), produced by an oxygen-based processing process 138, is shown as surrounding the lower portion of the via drain rail 148, forming a protective barrier. The width W1 and height H1 of the oxide plug 140' are depicted, showing the dimensions of the oxide plug 140' in the intermediate CESL (MCESL) 120, which prevents leakage between the via drain rail 148 and adjacent structures. In some embodiments, the width W1 of the oxide plug 140' is in the range of 1 nm to 5 nm, and the height H1 is in the range of 2 nm to 9 nm. The width W2 and height H2 of the oxide plug 140' are depicted, showing the dimensions of the oxide plug 140' in the contact spacer 112, which also prevents leakage between the via drain rail 148 and adjacent structures. In some embodiments, the width W2 of the oxide plug 140' is in the range of 1 nm to 3 nm, and the height H1 is in the range of 1 nm to 5 nm. These dimensions are controlled to ensure that the oxide plug 140' provides sufficient protection without adversely affecting the structural integrity or electrical performance of the semiconductor device.

[0156] The heights H1 and H2 of the oxide plug 140' are related to the power used in the oxygen-based processing 138, such that higher power processing can result in a larger height of the oxide plug 140'. Conversely, lower power processing can result in a smaller height of the oxide plug 140'. Furthermore, the widths W1 and W2 of the oxide plug 140' are related to the pressure used in the oxygen-based processing 138, such that higher pressure processing can result in a larger width of the oxide plug 140'. Conversely, lower pressure processing can result in a smaller width of the oxide plug 140'.

[0157] Figure 29A and Figure 29B A cross-sectional view of further processing of a nano-FET according to some embodiments is shown. Figure 29A A semiconductor device structure is shown in which a via drain rail 148 is formed to connect to a single contact 114, as opposed to previous embodiments where the via drain rail 148 is connected to multiple contacts 114. The via drain rail 148 spans a distance D2 across the semiconductor device structure, which can range from about 20 nm to about 1000 nm, depending on the design requirements of the semiconductor device. In some embodiments, the distance D2 is smaller than the distance D1. This embodiment demonstrates the sizing adaptability of the via drain rail 148 and its impact on the overall device structure and performance. Figures 28A to 28C and Figures 29A to 29B The implementation can be formed on the same integrated circuit device.

[0158] In some embodiments, when the through-hole drain rail 148 is large, the oxide plug 140' has a larger width and height to further ensure the isolation of the through-hole drain rail 148. Furthermore, the ratio of distance D1 to distance D2 is approximately 10, the ratio of width W1 to width W3 is in the range of 1 to 4, the ratio of height H1 to height H3 is in the range of 1 to 9, the ratio of width W2 to width W4 is in the range of 1 to 3, and the ratio of height H2 to height H4 is in the range of 1 to 5.

[0159] Figure 29B Provides semiconductor device structure ( Figure 29A An enlarged view of the protective component (region C) formed around the via drain rail 148 within the CESL (MCESL) 120. Width W3 and height H3 represent the dimensions of the oxide plug 140' in the intermediate CESL (MCESL) 120, while width W4 and height H4 represent the dimensions of the oxide plug 140' in the contact spacer 112. These dimensions represent the protective barrier formed by the oxygen-based processing 138, designed to prevent leakage between the via drain rail 148 and adjacent structures, thereby enhancing the reliability and performance of the semiconductor device. The specific dimensions of width W3, height H3, width W4, and height H4 are controlled to provide sufficient protection without compromising the structural integrity or electrical performance of the device.

[0160] The implementation method offers several advantages. The disclosed implementation includes a semiconductor device structure incorporating a carbon-containing low-k dielectric material as a middle contact etch stop layer (MCESL). Compared to conventional methods, this approach provides several advantages and benefits. The use of a carbon-containing low-k material in the MCESL results in a reduction in the dielectric constant, thereby effectively reducing parasitic capacitance within the device. This reduction in capacitance can lead to an improvement in the resistive-capacitor (RC) delay effect, thereby enhancing the overall speed and performance of the semiconductor device.

[0161] The disclosed implementation further includes the application of an oxygen-based treatment during the via drain rail (VDR) etching process. This treatment alters the sidewalls of the low-k MCESL and contact spacers, forming an oxide-like protective layer. The formation of this protective layer acts as a barrier to leakage current, particularly between the VDR and the metal gate region. This protection helps maintain the integrity and reliability of the device, especially as feature sizes continue to shrink in advanced semiconductor manufacturing.

[0162] Oxygen treatment also improves the coverage window between the via and the gate by preventing VDR protrusion. This results in a more uniform and precise VDR pattern, which facilitates the alignment and connection of various device components. Furthermore, processing conditions such as power and pressure can be adjusted to customize the width and thickness of the protective layer, providing flexibility in the design and manufacturing process.

[0163] In one embodiment, a method of forming a semiconductor device may include forming a first interlayer dielectric (ILD) over a transistor structure. This method may also include forming a first conductive contact through the first ILD to the transistor structure. Furthermore, this method may include forming a first contact etch stop layer (CESL) over the first conductive contact and the first ILD. Furthermore, this method may include forming a second ILD over the first CESL. Furthermore, this method may include forming a second conductive contact through the second ILD, the first CESL, and the first ILD to the transistor structure. This method may also include etching trenches in the second ILD and the first CESL. Furthermore, this method may include performing a process in the trench to form a processing layer in the first CESL. Furthermore, this method may include forming a first conductive feature in the trench, the first conductive feature being electrically coupled to the first conductive contact.

[0164] The described implementation may also include one or more of the following features: The method may include a first CESL comprising a carbon-containing material. The method may include a first CESL having a k-value lower than that of silicon nitride. Furthermore, the method may include forming contact spacers on the sidewalls of the first conductive contact prior to forming the first CESL. The method may also include performing a process in the trench to form a processing layer in the contact spacer. Furthermore, the contact spacer may comprise silicon nitride. At least one of the contact spacers may extend from the transistor structure through the first ILD to the first CESL. This process may include exposing the trench to pure oxygen. This process may also include exposing the trench to one or more gases selected from the group consisting of nitrogen, argon, and inert gases.

[0165] In one embodiment, a method of forming a semiconductor device may include forming a transistor structure having source and drain regions adjacent to a gate. This method may also include depositing a first interlayer dielectric (ILD) layer over the gate and the source and drain regions. Furthermore, this method may include patterning the first ILD layer to expose portions of the source and drain regions. Furthermore, this method may include forming source / drain contacts that extend through the first ILD layer and are electrically coupled to the source and drain regions. Furthermore, this method may include forming contact spacers on the sidewalls of the source / drain contacts. This method may also include forming a low-k contact etch stop layer (CESL) over the first ILD layer, the source / drain contacts, and the contact spacers. Furthermore, this method may include depositing a second ILD layer over the low-k CESL and patterning the second ILD layer and the low-k CESL to form a first trench. Furthermore, this method may include applying a process in the first trench to modify the low-k CESL and the contact spacers. Furthermore, this method may include forming a first conductive feature in the first trench, the first conductive feature being electrically coupled to the source / drain contacts.

[0166] The described implementation may also include one or more of the following features. This method may include forming a gate contact through a second ILD, a low-k CESL, and a first ILD, the gate contact being electrically coupled to the gate of a transistor structure. The contact spacer may include a material selected from the group consisting of silicon nitride, silicon oxynitride, and combinations thereof, and the low-k CESL may include a material having a lower k-value than the material of the contact spacer. The low-k CESL may include silicon, carbon, nitrogen, and oxygen. This process may include performing an in-situ oxygen-based treatment on the patterned second ILD layer and the low-k CESL to form a first trench. This process may also include performing a non-in-situ oxygen-based treatment on the patterned second ILD layer and the low-k CESL to form the first trench. The contact spacer is formed prior to forming source / drain contacts. This process may include exposing the first trench to an oxygen-containing gas, wherein the oxygen-containing gas may further include one or more gases selected from the group consisting of nitrogen, argon, and inert gases.

[0167] In one embodiment, the semiconductor device may include a transistor structure having source and drain regions adjacent to the gate. The semiconductor device may also include a first interlayer dielectric (ILD) layer over the gate and the source and drain regions. Furthermore, the device may include source / drain contacts extending through the first ILD layer and electrically coupled to the source and drain regions. Additionally, the device may include contact spacers on the sidewalls of the source / drain contacts. Furthermore, the device may include a low-k contact etch stop layer (CESL) over the first ILD layer, the source / drain contacts, and the contact spacers. The device may also include a second ILD layer over the low-k CESL. Furthermore, the device may include a first conductive feature in the second ILD and the low-k CESL, the first conductive feature being electrically coupled to the source / drain contacts. Furthermore, the device may include an insulating plug in the low-k CESL and the contact spacers, the insulating plug being adjacent to the first conductive feature in the low-k CESL and adjacent to the source / drain contacts in the contact spacers.

[0168] In some embodiments, the distance between the plurality of outer sidewalls of the first conductive feature is in the range of 20 nm to 1000 nm.

[0169] In some implementations, the width of the insulating plug is in the range of 1 nm to 5 nm.

[0170] The described embodiments may also include one or more of the following features. The contact spacer may include a material selected from the group consisting of silicon nitride, silicon oxynitride, and combinations thereof, and the low-k CESL may include a material having a lower k value than the material of the contact spacer. The first conductive feature may include a material selected from the group consisting of copper, tungsten, aluminum, and combinations thereof.

[0171] In some embodiments, a semiconductor device includes a transistor structure, a first interlayer dielectric layer, a plurality of source / drain contacts, a plurality of contact spacers, a low-k contact etch stop layer, a second interlayer dielectric layer, a first conductive feature, a plurality of insulating plugs, and a gate contact. The transistor structure includes a plurality of source and drain regions adjacent to a gate. The first interlayer dielectric layer is above the gate and source / drain regions. The plurality of source / drain contacts extend through the first interlayer dielectric layer and electrically couple these source and drain regions. The plurality of contact spacers are on a plurality of sidewalls of the source / drain contacts. The low-k contact etch stop layer is above the first interlayer dielectric layer, the source / drain contacts, and the contact spacers. The second interlayer dielectric layer is above the low-k contact etch stop layer. The first conductive feature is in the second interlayer dielectric layer and the low-k contact etch stop layer. The plurality of insulating plugs are in the low-k contact etch stop layer and the contact spacers, and these insulating plugs are adjacent to the first conductive feature in the low-k contact etch stop layer and to the source / drain contacts in the contact spacers. The gate contact extends through the second interlayer dielectric layer, the low-k contact etch stop layer, and the first interlayer dielectric layer.

[0172] In some implementations, the first conductive feature is electrically coupled to the source / drain contact.

[0173] In some implementations, the gate contact is electrically coupled to the gate.

[0174] In some implementations, the height of the insulating plug is in the range of 2 nm to 9 nm.

[0175] In some embodiments, a semiconductor device includes a transistor structure, a first interlayer dielectric layer, a plurality of source / drain contacts, a plurality of contact spacers, a low-k contact etch stop layer, a second interlayer dielectric layer, a first conductive feature, and a plurality of insulating plugs. The transistor structure includes a plurality of source and drain regions adjacent to a gate. The first interlayer dielectric layer is above the gate and the source and drain regions. The plurality of source / drain contacts extend through the first interlayer dielectric layer and electrically couple the source and drain regions. The plurality of contact spacers are on a plurality of sidewalls of the source / drain contacts. The low-k contact etch stop layer is above the first interlayer dielectric layer, the source / drain contacts, and the contact spacers. The second interlayer dielectric layer is above the low-k contact etch stop layer. The first conductive feature is located in the second interlayer dielectric layer and the low-k contact etch stop layer, and the first conductive feature is electrically coupled to the source / drain contacts, wherein the distance between the plurality of outer sidewalls of the first conductive feature is in the range of 20 nm to 1000 nm. Multiple insulating plugs are located in the low-k contact etch stop layer and contact spacers, with the insulating plugs adjacent to a first conductive feature in the low-k contact etch stop layer.

[0176] In some implementations, the width of the insulating plug is in the range of 1 nm to 5 nm, and the height of the insulating plug is in the range of 2 nm to 9 nm.

[0177] In some implementations, the width of the insulating plug is in the range of 1 nm to 3 nm, and the height of the insulating plug is in the range of 1 nm to 5 nm.

[0178] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be easily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced in various ways without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A transistor structure comprising multiple source and drain regions adjacent to a gate; A first interlayer dielectric layer is disposed above the gate and the plurality of source and drain regions; Multiple source / drain contacts extend through the first interlayer dielectric layer and electrically couple the multiple source and drain regions; Multiple contact spacers are located on multiple sidewalls of the multiple source / drain contacts; A low-k contact etch stop layer is placed above the first interlayer dielectric layer, the plurality of source / drain contacts and the plurality of contact spacers; A second interlayer dielectric layer is placed above the low-k contact etch stop layer; A first conductive feature is present in the second interlayer dielectric layer and the low-k contact etch stop layer, and the first conductive feature is electrically coupled to the plurality of source / drain contacts; as well as Multiple insulating plugs are provided in the low-k contact etch stop layer and the multiple contact spacers, wherein the multiple insulating plugs are adjacent to the first conductive feature in the low-k contact etch stop layer and to the multiple source / drain contacts in the multiple contact spacers.

2. The semiconductor device as claimed in claim 1, characterized in that, The distance between the multiple outer walls of the first conductive feature is in the range of 20 nm to 1000 nm.

3. The semiconductor device as claimed in claim 1 or 2, characterized in that, The width of the plurality of insulating plugs is in the range of 1 nm to 5 nm.

4. A semiconductor device, characterized in that, include: A transistor structure comprising multiple source and drain regions adjacent to a gate; A first interlayer dielectric layer is disposed above the gate and the plurality of source and drain regions; Multiple source / drain contacts extend through the first interlayer dielectric layer and electrically couple the multiple source and drain regions; Multiple contact spacers are located on multiple sidewalls of the multiple source / drain contacts; A low-k contact etch stop layer is placed above the first interlayer dielectric layer, the plurality of source / drain contacts and the plurality of contact spacers; A second interlayer dielectric layer is placed above the low-k contact etch stop layer; A first conductive feature is present in the second interlayer dielectric layer and the low-k contact etch stop layer; Multiple insulating plugs are provided in the low-k contact etch stop layer and the multiple contact spacers, wherein the multiple insulating plugs are adjacent to the first conductive feature in the low-k contact etch stop layer and to the multiple source / drain contacts in the multiple contact spacers; as well as A gate contact extends through the second interlayer dielectric layer, the low-k contact etch stop layer, and the first interlayer dielectric layer.

5. The semiconductor device as claimed in claim 4, characterized in that, The first conductive feature is electrically coupled to the plurality of source / drain contacts.

6. The semiconductor device as claimed in claim 4 or 5, characterized in that, The gate contact is electrically coupled to the gate.

7. The semiconductor device as claimed in claim 4 or 5, characterized in that, The height of the plurality of insulating plugs is in the range of 2 nm to 9 nm.

8. A semiconductor device, characterized in that, include: A transistor structure comprising multiple source and drain regions adjacent to a gate; A first interlayer dielectric layer is disposed above the gate and the plurality of source and drain regions; Multiple source / drain contacts extend through the first interlayer dielectric layer and electrically couple the multiple source and drain regions; Multiple contact spacers are located on multiple sidewalls of the multiple source / drain contacts; A low-k contact etch stop layer is placed above the first interlayer dielectric layer, the plurality of source / drain contacts and the plurality of contact spacers; A second interlayer dielectric layer is placed above the low-k contact etch stop layer; A first conductive feature is present in the second interlayer dielectric layer and the low-k contact etch stop layer, and the first conductive feature is electrically coupled to the plurality of source / drain contacts, wherein a distance between the plurality of outer sidewalls of the first conductive feature is in the range of 20 nm to 1000 nm; and Multiple insulating plugs are located in the low-k contact etch stop layer and the multiple contact spacers, and the multiple insulating plugs are adjacent to the first conductive feature in the low-k contact etch stop layer.

9. The semiconductor device as claimed in claim 8, characterized in that, The width of the plurality of insulating plugs is in the range of 1 nm to 5 nm, and the height of the plurality of insulating plugs is in the range of 2 nm to 9 nm.

10. The semiconductor device as claimed in claim 8, characterized in that, The width of the plurality of insulating plugs is in the range of 1 nm to 3 nm, and the height of the plurality of insulating plugs is in the range of 1 nm to 5 nm.

Images