Semiconductor device package

Abstract

A semiconductor device package, a thermal management component is included on top of the semiconductor components on both sides of the package substrate of the semiconductor component package to provide a dual-sided thermal management system for the semiconductor component package to dissipate heat from the semiconductor components on both sides of the package substrate of the semiconductor component package. This enables the semiconductor components on both sides of the package substrate of the semiconductor component package to operate at a lower temperature, which can improve the performance of the semiconductor components, can allow the performance of the semiconductor components to be maintained for a longer period of time, and / or can increase the reliability and lifetime of the semiconductor components, among others.

Description

Technical Field

[0001] This utility model relates to a semiconductor device package. Background Technology

[0002] In the electronics industry, effective heat dissipation is crucial for maintaining optimal performance and reliability of semiconductor components within electronic devices (such as semiconductor device packages). Thermal management of semiconductor device packages typically involves various structures and techniques to remove heat from the semiconductor components within the package (cooling) to reduce and / or minimize thermal stress on the semiconductor components. Utility Model Content

[0003] The purpose of this utility model embodiment is to provide a conductor device package to solve at least one of the above-mentioned problems.

[0004] This utility model provides a semiconductor device package, including a substrate, a plurality of semiconductor dies, a plurality of integrated circuit devices, a first vapor chamber cover structure, and a second vapor chamber cover structure. The plurality of semiconductor dies are located on a first side of the substrate. The plurality of integrated circuit devices are located on a second side of the substrate, opposite to the first side. The first vapor chamber cover structure is located above the semiconductor dies and thermally coupled to them. The second vapor chamber cover structure is located above the integrated circuit devices and thermally coupled to them.

[0005] According to one embodiment of the present invention, the plurality of integrated circuit devices include a plurality of voltage regulation module integrated circuit devices; and wherein the plurality of voltage regulation module integrated circuit devices are thermally coupled to the second heat spreader cover structure through a thermal interface material.

[0006] According to one embodiment of the present invention, the second heat spreader cover structure includes: a base having a continuous closed-loop structure defining a space in which a plurality of said integrated circuit devices are located; a cover coupled to the base and spanning the space defined by the base, wherein the cover is thermally coupled to the plurality of said integrated circuit devices; and a heat spreader located in the cover.

[0007] According to one embodiment of the present invention, the first heat spreader cover structure includes: another base having a continuous closed-loop structure defining a space in which a plurality of said semiconductor grains are located, wherein an outer periphery of the base of the second heat spreader cover structure is located within an outer periphery of the other base of the first heat spreader cover structure.

[0008] According to one embodiment of the present invention, the inner periphery of the base of the second heat-equalizing plate cover structure is located within the inner periphery of the other base of the first heat-equalizing plate cover structure.

[0009] According to one embodiment of the present invention, a base of the first heat spreader cover structure is coupled to the first side of the substrate; and a base of the second heat spreader cover structure is coupled to the second side of the substrate.

[0010] This utility model provides a semiconductor device package, including a substrate, a plurality of semiconductor dies, a plurality of voltage-regulating integrated circuit devices, a first vapor chamber cover structure, a second vapor chamber cover structure, and one or more package connection elements. The plurality of semiconductor dies are located on a front side of the substrate. The plurality of voltage-regulating integrated circuit devices are located on a back side of the substrate, opposite to the front side. The first vapor chamber cover structure is located above the semiconductor dies and thermally coupled to them. The second vapor chamber cover structure is located above the voltage-regulating integrated circuit devices and thermally coupled to them. One or more package connection elements are located on the back side of the substrate, wherein one or more package connection elements are located around the second vapor chamber cover structure.

[0011] According to one embodiment of the present invention, the periphery of the second heat-equalizing plate cover structure is at least partially located within a periphery of the first heat-equalizing plate cover structure.

[0012] According to one embodiment of the present invention, the first heat spreader cover structure includes a cover wall surrounding a portion of the substrate and coupled to a front portion of the substrate; and wherein one or more packaged connection elements are located below the portion of the front portion of the substrate coupled to the cover wall, such that the cover wall and the one or more packaged connection elements are arranged vertically in the semiconductor device package.

[0013] According to one embodiment of the present invention, at least a subset of the plurality of semiconductor chips includes a multi-chip semiconductor chip package, wherein at least two of the plurality of semiconductor chips are directly connected to each other and arranged vertically. Attached Figure Description

[0014] The embodiments of this utility model will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, many features are not shown to scale and are only used for illustrative purposes. In fact, the dimensions of the components may be arbitrarily enlarged or reduced to clearly demonstrate the features of this utility model.

[0015] Figures 1A to 1E This is a diagram illustrating an example of a semiconductor device package according to the present invention.

[0016] Figure 2 This is a diagram illustrating an example of the thermal lid structure described in this utility model.

[0017] Figure 3This is a diagram illustrating an example of the heat-cap structure described in this utility model.

[0018] Figures 4A to 4K This is a diagram illustrating an example of a semiconductor device package as described in this utility model.

[0019] Figure 5A and Figure 5B This is a diagram illustrating an example of mounting the semiconductor device package described in this invention onto a mounting structure.

[0020] Figure 6A and Figure 6B This is a diagram of an example of another semiconductor device package according to the present invention.

[0021] Figure 7A and Figure 7B This is a diagram of an example of another semiconductor device package according to the present invention.

[0022] Figure 8 This is a diagram of an example of another semiconductor device package according to the present invention.

[0023] Figure 9 This is a diagram of an example of another semiconductor device package according to the present invention.

[0024] Figure 10 This is a flowchart of an exemplary process related to forming the semiconductor device package described in this utility model.

[0025] The attached figures are labeled as follows:

[0026] 102, 602, 702, 802, 902: Semiconductor device packages

[0027] 104, 604, 704, 804, 904: Packaging substrate

[0028] 106, 606, 706, 806, 906, 906a, 906b: Semiconductor grains

[0029] 108, 114: Connection Structure

[0030] 110, 116, 616, 716, 816, 916: Bottom fill layer

[0031] 112, 612, 712, 812, 912: Integrated circuit devices

[0032] 118: Encapsulated Connecting Components

[0033] 120,132,620,632,720,732,820,832,920,932: Heat-sealed structure

[0034] 122,134,634,734,834,934: Base

[0035] 124,136,636,736,836: Cover

[0036] 126, 138: Heat exchange plate

[0037] 128,140: Fins

[0038] 130, 142, 642, 742, 842, 848, 942: Thermal interface material layer

[0039] 100, 144, 148, 150, 152, 200, 300, 400, 500, 600, 646, 700, 748, 800, 900: Examples

[0040] 146,644,744,844,944: Installation structure

[0041] 202,302: Inner cavity

[0042] 204, 304: wicking layer

[0043] 206, 210, 306, 310: Calories

[0044] 208, 308: Steam

[0045] 212, 312: Liquid

[0046] 402, 404: Supporting structure

[0047] 406: Solder template

[0048] 408: Metal Pad

[0049] 746, 846: Passive circuit devices

[0050] 946: Multi-chip Semiconductor Die Packaging

[0051] 1000: Process

[0052] 1010, 1020, 1030, 1040, 1050: Squares Detailed Implementation

[0053] The following discloses many different embodiments or examples to implement the various features provided. Specific examples of elements and their arrangements are described below to illustrate the present invention. These embodiments are illustrative only and do not limit the scope of the present invention. For example, the specification mentions that a first feature is formed on a second feature, which includes embodiments where the first and second feature are in direct contact, and also embodiments where there are other features between the first and second feature, meaning the first and second feature are not in direct contact. Furthermore, repeated reference numerals or designations may be used in different embodiments. These repetitions are only for the purpose of clearly and simply describing the present invention and do not represent a specific relationship between the different embodiments and / or structures discussed.

[0054] Furthermore, spatially related terms may be used, such as "below," "below," "lower," "above," "higher," and similar terms. These spatially related terms are used to facilitate the description of the relationship between one or more elements or features in the illustrations and to one or more other elements or features. These spatially related terms include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially related adjectives used will also be interpreted according to the orientation after the turn.

[0055] Semiconductor device packages are typically manufactured to allow the semiconductor device package to be mounted or attached to a mounting structure (such as a socket or printed circuit board, PCB) on one side of the semiconductor. The other side of the semiconductor device package, opposite the mounting structure, provides opportunities for thermal management within the package. Specifically, various types of heat sinks, heat spreaders, fins, fans, and / or other thermal management components are often included on this side of the semiconductor device package to dissipate heat generated by the semiconductor components within the package.

[0056] Some advanced packaging technologies used in semiconductor device packages involve mounting or attaching semiconductor components to both sides of the package substrate (e.g., an interposer, redistribution layer, RDL) of the semiconductor device package to increase the density of semiconductor components contained within the package. In other words, semiconductor elements are mounted or attached to both the top and bottom sides of the package substrate. This results in at least a subset of the semiconductor components of the semiconductor device package being positioned between the package substrate and the mounting structure when the package is mounted or connected to a mounting structure. Consequently, the heat generated by these semiconductor elements may be trapped between the package substrate and the mounting structure, causing the semiconductor elements to be exposed to high temperatures for extended periods. This can lead to reduced performance and / or reliability of the semiconductor elements between the package substrate and the mounting structure, and may cause premature failure of the semiconductor elements.

[0057] In some embodiments described in this invention, thermal management components are included on semiconductor components on both sides of the packaging substrate of the semiconductor device package to provide a double-sided thermal management system for the semiconductor device package. Semiconductor components (e.g., semiconductor dies) may be mounted or attached to the top side of the packaging substrate, and semiconductor components such as integrated circuit devices (e.g., voltage regulator module (VRM) devices and / or other active integrated circuit devices) and / or integrated passive devices (IPDs) may be mounted or attached to the bottom side of the packaging substrate. Thermal management components such as heat sinks, fins, vapor chamber lid structures, and / or other types of thermal management components may be included above the semiconductor components on the top and bottom sides of the packaging substrate. For example, a first vapor chamber lid structure (and thermally coupled to the semiconductor component) may be included above the semiconductor component on the top side of the packaging substrate, and a second vapor chamber lid structure (and thermally coupled to the semiconductor component) may be included above the semiconductor component on the bottom side of the packaging substrate. The dimensions of the second vapor chamber cover structure can be designed such that the semiconductor components on the bottom side of the package structure and the associated second vapor chamber cover structure mate with the package connection element of the semiconductor device package, and this package connection element is used to mount or attach the semiconductor device package to a mounting structure.

[0058] Therefore, the thermal management system on both sides of the semiconductor device package allows heat dissipation from the semiconductor components on both sides of the package substrate. This enables the semiconductor components on both sides of the package substrate to operate at lower temperatures, thereby improving the performance of the semiconductor components, maintaining their performance for a longer period of time, and / or increasing the reliability and lifespan of the semiconductor components.

[0059] Figures 1A to 1E This is a diagram illustrating an example of a semiconductor device package according to the present invention. Figure 1A A cross-sectional view of an example 100 of a semiconductor device package 102 is shown. In some embodiments, the semiconductor device package 102 includes a package substrate 104 and one or more semiconductor dies 106 mounted or attached to a first side (e.g., the top side) of the package substrate 104. In some embodiments, the semiconductor device package 102 includes a plurality of semiconductor dies 106 and is a multi-die semiconductor device package. The plurality of semiconductor dies 106 may be arranged horizontally (e.g., along the x-direction, y-direction) in the semiconductor device package 102 and / or vertically along the z-direction in the semiconductor device package 102.

[0060] The package substrate 104 includes multiple conductive traces or conductive layers interconnected to enable signal and / or power routing between semiconductor dies 106 and / or between semiconductor dies 106 and devices outside the semiconductor device package 102. In some embodiments, the package substrate 104 is an interposer and includes a silicon (Si) interposer, an organic interposer (e.g., an organic polymer interposer), and a dielectric interposer (e.g., silicon oxide (SiO2)). x The package substrate 104 may contain a glass interposer and / or other types of interposers. Conductive traces in the package substrate 104 may be arranged in interconnect layers called RDLs. Each RDL may include trenches, wires, and / or other types of conductive structures extending primarily laterally or horizontally (e.g., in the x-direction, y-direction) within the package substrate 104. The RDLs in the package substrate 104 may be interconnected via interconnect layers, which may include vias, conductive pillars, conductive columns, and / or other types of interconnect structures extending primarily vertically (e.g., in the z-direction) within the package substrate 104. Conductive traces in the package substrate 104 may include one or more conductive materials, such as gold (Au), copper (Cu), silver (Ag), nickel (Ni), aluminum (Al), ruthenium (Ru), cobalt (Co), titanium (Ti), tungsten (W), tin (Sn), lead (Pb), and / or palladium (Pd).

[0061] The semiconductor device package 102 may include one or more types of semiconductor dies 106. Each of the one or more types of semiconductor dies 106 may include a system-on-chip (SoC) die, such as a logic die, a central processing unit (CPU) die, a graphics processing unit (GPU) die, a digital signal processing (DSP) die, an application-specific integrated circuit (ASIC) die, and / or other types of SoC dies. Each of the one or more semiconductor dies 106 may include a memory die, an input / output (I / O) die, a pixel sensor die, a high-voltage (HV) die, and / or other types of semiconductor dies. One or more semiconductor dies 106 may each include a memory die, such as a static random access memory (SRAM) die, a dynamic random access memory (DRAM) die, a NAND die, a high bandwidth memory (HBM) die, and / or other types of memory wafers. In some embodiments, one or more semiconductor dies 106 are included in a semiconductor die package, wherein the semiconductor die 106 is packaged together with other components such as input / output dies and / or memory dies.

[0062] Semiconductor die 106 can be mounted or attached to a first side of package substrate 104 via connection structure 108. Connection structure 108 may include bonding pads, solder balls arranged in a ball grid array (BGA), microbumps, controlled collapse chip connection (C4) bumps, metal pads arranged in a land grid array (LGA), pin grid array (PGA) arranged in conductive pins, and / or other types of connection structures. In some embodiments, connection structure 108 includes two or more types of connection structures.

[0063] An underfill layer 110 may be provided between the semiconductor die 106 and a first side of the package substrate 104. The underfill layer 110 may be present between and around the connection structures 108, and may electrically isolate the connection structures 108 and protect the semiconductor die 106 from vibration and moisture ingress. The underfill layer 110 may include an underfill material, such as a polymer, one or more fillers dispersed in a resin, an epoxy-based resin, and / or other types of electrically insulating materials. In some embodiments, a sealing material is provided around the semiconductor die 106 above the underfill layer 110. The sealing material may include a plastic molding compound and / or other types of sealant.

[0064] like Figure 1A As further shown, the integrated circuit device 112 is mounted or attached to a second side (e.g., the bottom side) of the package substrate 104 perpendicular to the first side. Therefore, components are mounted or attached to both sides of the package substrate 104, and conductive traces in the package substrate 104 are configured to pass through the package substrate 104 to route signals and / or power between the semiconductor die 106 and the integrated circuit device 112. In some embodiments, one or more integrated circuit devices 112 include active circuitry, such as a VRM integrated circuit device configured to actively regulate the voltage supplied to the semiconductor die 106. In some embodiments, one or more integrated circuit devices 112 include active electrostatic discharge (ESD) protection integrated circuitry (e.g., ESD-triggered circuitry) configured to redirect electrical energy from the semiconductor die 106 to the ESD protection circuitry in the event of excessive voltage or current. In some embodiments, one or more integrated circuit devices 112 include power inverter circuitry, analog-to-digital converter circuitry, and / or other types of integrated circuit devices.

[0065] The integrated circuit device 112 is mounted or attached to the second side of the package substrate 104 via a connection structure 114. The connection structure 114 may include bonding pads, solder balls, microbumps, C4 bumps, metal pads, conductive pins, leads, and / or other types of connection structures. In some embodiments, the connection structure 114 includes two or more types of connection structures.

[0066] An underfill layer 116 may be provided between the integrated circuit device 112 and the second side of the package substrate 104. The underfill layer 116 may be present between and around the connection structures 114, and may electrically isolate the connection structures 114 and protect the integrated circuit device 112 from vibration and moisture ingress. The underfill layer 116 may include an underfill material, such as a polymer, one or more fillers dispersed in a resin, an epoxy resin, and / or other types of electrically insulating materials. In some embodiments, a sealing material is provided around the integrated circuit device 112 above the underfill layer 116. The sealing material may include plastic molding compounds and / or other types of sealants.

[0067] The package connection element 118 of the semiconductor device package 102 may be included on the second side of the package substrate 104. The package connection element 118 may include sockets, pins, contact pads and / or other types of package connection elements on the substrate (e.g., PCB) that enable the semiconductor device package 102 to be mounted or attached to a mounting structure.

[0068] Referring to a first side of the package substrate 104, a heat cover structure 120 is included above and mounted or attached to the first side of the package substrate 104. The heat cover structure 120 is included above and thermally coupled to the semiconductor die 106. This enables the heat cover structure 120 to provide thermal management for the semiconductor die 106. Specifically, the heat cover structure 120 can dissipate heat from the semiconductor die 106 and / or from the area surrounding the semiconductor die 106, thereby cooling the semiconductor die 106.

[0069] The thermal cap structure 120 includes a footing 122 mounted or attached to a first side (e.g., the front side) of the package substrate 104. Package connection elements 118 may be located below a portion of the first side of the package substrate 104 coupled to the footing 122, such that the footing 122 and each package connection element 118 are arranged perpendicularly in the z-direction within the semiconductor device package 102. The footing 122 serves as a lid wall and supports the cover 124 of the thermal cap structure 120. The footing 122 may also serve as a stiffener and may provide additional structural stiffness and support to the semiconductor device package 102. The cover 124 spans the footing 122 and is positioned over the semiconductor die 106, such that the cover 124 is thermally coupled to the semiconductor die 106 (e.g., thermally coupled to the side opposite to the first side of the package substrate 104 where the semiconductor die 106 is mounted or attached).

[0070] In some embodiments, the vapor chamber 126 is integrated into the cover 124. Therefore, the thermal cover structure 120 may be referred to as a vapor chamber cover structure. Conversely, including a separate vapor chamber heatsink on the thermal cover structure 120 reduces the vertical dimension (e.g., height) of the semiconductor device package 102 by including the vapor chamber 126 within the cover 124, and allows the vapor chamber 126 to be closer to the semiconductor die 106. Placing the vapor chamber 126 closer to the semiconductor die 106 improves heat transfer between the semiconductor die 106 and the vapor chamber 126 compared to a case where the vapor chamber 126 is located in a separate heatsink and further away from the semiconductor die 106.

[0071] Because the vapor chamber 126 extracts heat from the semiconductor die 106 and distributes it on the side surface of the cover 124, giving the cover 124 a larger surface area for heat exchange from the cover 124 to the fins 128 above it, the vapor chamber 126 acts as a heat sink and heat exchanger. Heat is then transferred from the fins 128 to the environment surrounding the semiconductor device package 102 and / or to an external heat sink assembly. The fins 128 are physically coupled to one side of the cover 124, opposite to the side of the cover 124 thermally coupled to the semiconductor die 106. Including the fins 128 above the cover 124 increases the surface area, allowing heat to be transferred to the environment surrounding the semiconductor device package 102. In some embodiments, a fan can blow cool air across the fins 128 to accelerate heat dissipation from the fins. Additional details regarding the operation of the vapor chamber 126 can be found in [reference needed]. Figure 2 Show and describe.

[0072] The base 122, cover 124, and fins 128 can be formed from the same (or similar) or different materials. The base 122, cover 124, and fins 128 can be formed from thermally conductive metals, such as aluminum (Al), copper (Cu), gold (Au), and / or silver (Ag). Alternatively and alternatively, the base 122, cover 124, and / or fins 128 can be one or more other materials with high thermal conductivity (e.g., thermal conductivity greater than aluminum), such as diamond, silicon carbide (SiC), and / or aluminum nitride (AlN).

[0073] The top surface of the semiconductor die 106 can be thermally coupled to the cover 124 of the thermal cap structure 120 via a thermal interface material layer 130. Each thermal interface material layer 130 includes a layer of thermal interface material. The thermal interface material may include thermal interface paste, thermal interface sheet, and / or other types of thermal interface materials. In some embodiments, the thermal interface material of the thermal interface material layer 130 includes a paste comprising metal particles (e.g., gold particles, silver particles) suspended in a liquid compound. In some embodiments, the thermal interface material of the thermal interface material layer 130 includes graphene sheets and / or other types of carbon-based thermal interface materials. In some embodiments, the thermal interface material of the thermal interface material layer 130 includes a phase change material, such as a polymer-based phase change material. In some embodiments, the thermal interface material of the thermal interface material layer 130 includes a liquid metal thermal interface material, which may include one or more types of metals (e.g., gallium (Ga), indium (In), tin (Sn)).

[0074] Referring to the second side of the package substrate 104, a heat cover structure 132 is also included below the second side of the package substrate 104 and is mounted or attached to the second side of the package substrate 104. The heat cover structure 132 is included on and thermally coupled to the integrated circuit device 112. This enables the heat cover structure 132 to provide thermal management for the integrated circuit device 112. Specifically, the heat cover structure 132 can dissipate heat from the integrated circuit device 112 and / or from the surrounding area of ​​the integrated circuit device 112, thereby cooling the integrated circuit device 112.

[0075] The thermal cap structure 132 includes a base 134 that is mounted or attached to a second side (e.g., the back side) of the package substrate 104. Package connection elements 118 may be adjacent to one or more sides of the base 134. The base 134 serves as a cover wall and supports the cover 136 of the thermal cap structure 132. The base 134 may also serve as a reinforcement and may provide increased structural rigidity and support for the semiconductor device package 102. The cover 136 extends across the base 134 and across the integrated circuit device 112, such that the cover 136 is thermally coupled to the integrated circuit device 112 (e.g., one side of the integrated circuit device 112 is opposite to the other side of the integrated circuit device 112 mounted or attached to the second side of the package substrate 104).

[0076] In some embodiments, the vapor chamber 138 is integrated into the cover 136. Therefore, the heat cover structure 132 can be referred to as a vapor chamber cover structure. Contrary to including a separate vapor chamber heatsink on the heat cover structure 132, including the vapor chamber 138 within the cover 136 reduces the vertical dimension (e.g., height) of the semiconductor device package 102 and allows the vapor chamber 138 to be closer to the integrated circuit device 112. Compared to a case where the vapor chamber 138 is located in a separate heatsink and away from the integrated circuit device 112, bringing the vapor chamber 138 closer to the integrated circuit device 112 increases heat transfer between the integrated circuit device 112 and the vapor chamber 138. Furthermore, the reduced vertical dimension of the semiconductor device package 102 allows for shorter package connection elements 118, which can reduce signal propagation distances within the semiconductor device package 102 and / or reduce resistance within the semiconductor device package 102.

[0077] The vapor chamber 138 serves as both a heat sink and a heat exchanger because it extracts heat from the integrated circuit device 112 and distributes it across the side surface of the cover 136. This allows the larger surface area of ​​the cover 136 to be used for heat exchange from the cover 136 to the fins 140 above it. The heat is then transferred from the fins 140 to the environment surrounding the semiconductor device package 102. The fins 140 are physically coupled to the side of the cover 136 opposite to the side thermally coupled to the integrated circuit device 112. Including the fins 140 above the cover 136 increases the surface area, thereby allowing heat to be transferred to the environment surrounding the semiconductor device package 102. Figure 3 Additional details regarding the operation of the vapor chamber 138 are shown and described.

[0078] The base 134, cover 136, and fins 140 can all be formed from the same material (or multiple materials) or different materials. The base 134, cover 136, and fins 140 can all be formed from thermally conductive metals, such as aluminum (Al), copper (Cu), gold (Au), and / or silver (Ag). Additionally and / or alternatively, the base 134, cover 136, and / or fins 140 can be one or more other materials with high thermal conductivity (e.g., thermal conductivity greater than aluminum), such as diamond, silicon carbide (SiC), and / or aluminum nitride (AlN).

[0079] The top surface of the integrated circuit device 112 can be thermally coupled to the cover 136 of the thermal cap structure 132 via a thermal interface material layer 142. The thermal interface material may include thermal paste, thermal pads, and / or other types of thermal interface materials. In some embodiments, the thermal interface material of the thermal interface material layer 142 includes a paste comprising metal particles (e.g., gold particles, silver particles) suspended in a liquid compound. In some embodiments, the thermal interface material of the thermal interface material layer 142 includes graphene sheets and / or other types of carbon-based thermal interface materials. In some embodiments, the thermal interface material of the thermal interface material layer 142 includes a phase change material, such as a polymer-based phase change material. In some embodiments, the thermal interface material of the thermal interface material layer 142 includes a liquid metal thermal interface material, which may include one or more types of metals (e.g., gallium (Ga), indium (In), tin (Sn)).

[0080] Figure 1B An example 144 is shown showing a semiconductor device package 102 mounted or attached to a mounting structure 146 via a package connection element 118. In some embodiments, the mounting structure 146 includes a PCB (e.g., a system board, motherboard, riser board, adapter board). In some embodiments, the mounting structure 146 includes a socket into which the package connection element 118 is inserted. In some embodiments, the mounting structure 146 includes a connector inserted into the package connection element 118.

[0081] Figure 1C Example 148 shows a top view of a semiconductor device package 102. The cover 124 of the heat cover structure 120 is omitted in the top view, so that the semiconductor die 106 and the base 122 on the first side (e.g., the front side) of the package substrate 104 are visible. Figure 1C It also showed Figure 1A and Figure 1B The location of section AA. For example... Figure 1C As shown, the base 122 has a continuous closed-loop structure (e.g., an approximately annular structure) above the perimeter of the package substrate 104. The closed-loop structure of the base 122 defines the space in which the semiconductor die 106 is located. A cover 124 (not shown) can be coupled to the base 122 such that the cover 124 spans the space defined by the base 122.

[0082] In some embodiments, the top view shape of the packaging substrate 104 may be approximately rectangular, approximately square, or other shapes. In some embodiments, the x-direction dimension and the y-direction dimension of the packaging substrate 104 are approximately the same. In some embodiments, the x-direction dimension and the y-direction dimension of the packaging substrate 104 are different.

[0083] In some embodiments, the top view shape of the semiconductor die 106 may be approximately rectangular, approximately square, or other shapes. In some embodiments, the x-direction dimension and the y-direction dimension of the semiconductor die 106 are approximately the same. In some embodiments, the x-direction dimension and the y-direction dimension of the semiconductor die 106 are different.

[0084] In some embodiments, the width of the base 122 may range from about 1 mm to about 5 mm. However, other values ​​are also within the scope of this invention. In some embodiments, the base 122 may have a uniform width around the heat cover structure 120. In some embodiments, the width of one or more segments of the base 122 differs from the width of the other one or more segments of the base 122.

[0085] Figure 1D Example 150 shows a bottom view of a semiconductor device package 102. The cover 136 of the heat cover structure 132 is omitted in the bottom view, so that the integrated circuit device 112 and the base 134 on the second side (e.g., the back side) of the package substrate 104 are visible. Figure 1D It also showed Figure 1A and Figure 1B The location of section AA. For example... Figure 1D As shown, the base 134 has a continuous closed-loop structure (e.g., an approximately annular structure) above the second side of the package substrate 104. The closed-loop structure of the base 134 defines the space where the integrated circuit device 112 is located. Therefore, the integrated circuit device 112 is located around the base 134. In some embodiments, one or more integrated circuit devices 112 are adjacent to one or more inner walls of the base 134. A cover 136 (not shown) may be coupled to the base 134 such that the cover 136 spans the space defined by the base 134.

[0086] like Figure 1D As further shown, the encapsulation connection element 118 is located outside the base 134 of the heat-cap structure 132. In some embodiments, the encapsulation connection element 118 may abut one or more outer walls of the base 134. For example, a first encapsulation connection element 118 may abut a first outer wall of the base 134, and a second encapsulation connection element 118 may abut a second outer wall of the base 134 opposite to the first outer wall. Other arrangements of the encapsulation connection element 118 are also within the scope of this invention.

[0087] In some embodiments, integrated circuit devices 112 are arranged in a grid around the base 134 of the heat cover structure 132. One or more segments of the base 134 of the heat cover structure 132 may be located between one or more integrated circuit devices 112 and package connection elements 118.

[0088] In some embodiments, the top view shape of the integrated circuit device 112 may be approximately rectangular, approximately square, or other shapes. In some embodiments, the x-axis dimension and the y-axis dimension of the integrated circuit device 112 are approximately the same. In some embodiments, the x-axis dimension and the y-axis dimension of the integrated circuit device 112 are different.

[0089] In some embodiments, the top view shape of the packaged connecting element 118 may be approximately rectangular, approximately square, or other shapes. In some embodiments, the x-direction dimension and the y-direction dimension of the packaged connecting element 118 are approximately the same. In some embodiments, the x-direction dimension and the y-direction dimension of the packaged connecting element 118 are different.

[0090] In some embodiments, the width of the base 134 may range from about 1 mm to about 5 mm. However, other ranges are also within the scope of this invention. In some embodiments, the base 134 may have a uniform width around the heat cover structure 132. In some embodiments, the width of one or more segments of the base 134 differs from the width of other one or more segments of the base 134.

[0091] Figure 1E Another example 152 shows a top view of a semiconductor device package 102, in which the base 134 of the heat cap structure 132 below the package substrate 104 is shown in dashed lines to show the relative position of the base 134 and the base 122 of the heat cap structure 120. Figure 1E As shown, the outer periphery of the base 134 of the heat cover structure 132 is located within the outer periphery of the base 122 of the heat cover structure 120 (e.g., inside). In other words, the outer wall of the base 134 of the heat cover structure 132 is located around the outer wall of the base 122 of the heat cover structure 120.

[0092] The inner periphery of the base 134 of the heat-cap structure 132 is located within the outer periphery of the base 122 (e.g., inside), and also within the inner periphery of the base 122 (e.g., inside). In other words, the inner wall of the base 134 is located around the outer wall of the base 122, and also around the inner wall of the base 122. The outer periphery of the base 134 may be at least partially located within the inner periphery of the base 122. For example, one or more segments of the outer wall of the base 134 may be located around the inner wall of the base 122. In some embodiments, one or more other segments of the outer wall of the base 134 may be located outside the periphery of the inner wall of the base 122.

[0093] As mentioned above, providing Figures 1A to 1E As an example. Other examples can be found related to... Figures 1A to 1E The descriptions are different.

[0094] Figure 2 This is a diagram of an example 200 of the heat-cap structure described in this utility model. In some embodiments, example 200 includes an example of the heat-cap structure 120 described in this utility model. In some embodiments, example 200 includes examples of other heat-cap structures described in this utility model, such as heat-cap structure 620, heat-cap structure 720, heat-cap structure 820 and / or heat-cap structure 920, etc.

[0095] Figure 2 A cross-sectional view of the heat cover structure 120 is shown. (See attached image.) Figure 2 As shown, the heat spreader 126 of the heat cover structure 120 includes an inner cavity 202 located within the cover body 124 of the heat cover structure 120. A wicking layer 204 may be included on the wall of the inner cavity 202 to control and facilitate the flow of vapor and liquid within the inner cavity 202.

[0096] During operation of the semiconductor device package 102, the semiconductor die 106 generates heat 206, which is transferred to the cover 124 of the heat cap structure 120. The heat 206 increases the temperature of the bottom side of the cover 124, causing liquid within the cavity 202 of the vaporizer 126 to vaporize into vapor 208. The vapor 208 rises within the cavity 202 towards the top side of the cover 124. The top side of the cover 124 cools the vapor 208 and dissipates heat 210 from the vapor 208 to the fins 128. This converts the vapor 208 back into liquid 212, which flows back along the wicking layer 204 to the bottom of the cavity 202. This cycle continues during operation of the semiconductor device package 102 to continuously cool the semiconductor die 106.

[0097] As mentioned above, providing Figure 2 As an example. Other examples can be compared with... Figure 2 The differences described in [the text].

[0098] Figure 3 This is a diagram of an example 300 of the heat-cap structure described in this utility model. In some embodiments, example 300 includes an example of the heat-cap structure 132 described in this utility model. In some embodiments, example 300 includes examples of other heat-cap structures described in this utility model, such as heat-cap structure 632, heat-cap structure 732, heat-cap structure 832 and / or heat-cap structure 932, etc.

[0099] Figure 3 A cross-sectional view of the heat-cap structure 132 is shown. Figure 3As shown, the heat spreader 138 of the heat cover structure 132 includes an inner cavity 302 located within the cover 136 of the heat cover structure 132. A wicking layer 304 may be included on the wall of the inner cavity 302 to control and facilitate the flow of vapor and liquid within the inner cavity 302.

[0100] During operation of the semiconductor device package 102, the integrated circuit device 112 generates heat 306, which is transferred to the cover 136 of the heat cover structure 132. The heat 306 increases the temperature of the top side of the cover 136, causing liquid within the cavity 302 of the vaporizer 138 to vaporize into vapor 308. Vapor 308 flows towards the bottom of the cavity within the cavity 302 and towards the bottom side of the cover 136. The bottom side of the cover 136 cools the vapor 308, and heat 310 is expelled from the vapor 308 to the fins 140 via the bottom side of the cover 136. This converts the vapor 308 back into liquid 312, which then returns to the top of the cavity 302 along the wicking layer 304. The wicking layer 304 retains the liquid 312 at the top side of the cavity 302 until the liquid 312 is again converted into vapor 308 by the heat 306. This cycle continues during the operation of the semiconductor device package 102 to continuously cool the integrated circuit device 112.

[0101] As mentioned above, providing Figure 3 As an example. Other examples can be compared with... Figure 3 The differences described in [the text].

[0102] Figures 4A to 4K This is a diagram illustrating an example 400 of the semiconductor device package described in this invention. In some embodiments, one or more operations related to example 400 may be performed to form the semiconductor device package 102 described in this invention. In some embodiments, one or more operations related to example 400 may be performed to form other semiconductor device packages described in this invention, such as semiconductor device package 602, semiconductor device package 702, semiconductor device package 802, and / or semiconductor device package 902, etc. In some embodiments, one or more packaging tools (e.g., in a semiconductor packaging apparatus) are used to perform the operations related to example 400, such as RDL tools, connection tools, pick and place tools, dispensing tools, solder mask tools, and / or solder reflow tools, etc.

[0103] like Figure 4A As shown, the packaging substrate 104 can be placed on the support structure 402. The support structure 402 may include a frame, tape, die boat, conveyor belt and / or other types of support structures.

[0104] like Figure 4B As shown, the semiconductor die 106 can be placed (e.g., using a pick-and-place tool) on a first side (e.g., the front side) of the package substrate 104 to allow the connection structure 108 to be connected to the package substrate 104. In some embodiments, the semiconductor die 106 is located on a solder pad on the package substrate 104. The package substrate 104 can be bonded to the connection structure 108 and the package substrate 104 by reflowing the solder pads using a soldering tool (e.g., a wave soldering tool and / or other types of soldering tools).

[0105] like Figure 4C As shown, after the semiconductor die 106 is mounted or attached to the package substrate 104, an underfill layer 110 may be applied (e.g., using an application tool) around the semiconductor die 106. The underfill layer 110 may be applied such that it fills the gaps around the connection structure 108. In some embodiments, the underfill layer 110 may be applied such that it merges with each other between adjacent semiconductor dies 106.

[0106] like Figure 4D As shown, a thermal interface material layer 130 can be provided on the top surface of the semiconductor die 106 (e.g., the surface opposite to the surface to which the semiconductor die 106 is mounted or attached to the package substrate 104). In some embodiments, the thermal interface material layer 130 is a paste, liquid, or other flowable material dispensed (e.g., using a dispensing tool) onto the semiconductor die 106. In some embodiments, the thermal interface material layer 130 is placed on the semiconductor die 106 (e.g., in the form of a sheet or pad). In some embodiments, the thermal interface material layer 130 is formed or grown on the semiconductor die 106.

[0107] like Figure 4E As shown, the thermal cap structure 120 is mounted or attached to a first side (e.g., the front side) of the package substrate 104, such that the cover 124 of the thermal cap structure 120 is positioned over the semiconductor die 106. A pick-and-place tool or other suitable tool may be used to place the thermal cap structure 120 onto the package substrate 104 such that the cover 124 of the thermal cap structure 120 contacts the thermal interface material layer 130 to form a thermal connection between the semiconductor die 106 and the thermal interface material layer 130. Among other examples, the base 122 can be secured to the first side of the package substrate 104 by adhesives, epoxy resins, solder pads, and / or metal pads bonded to the base 122 on the package substrate 104.

[0108] like Figure 4FAs shown, the semiconductor device package 102 can be flipped and placed on another support structure 404 such that the second side (e.g., the bottom side) of the package substrate 104 faces upward. The solder stencil 406 can be used to deposit solder paste (e.g., using a dispensing tool) onto the metal pad 408 on the second side of the package substrate 104.

[0109] like Figure 4G As shown, the integrated circuit device 112 can be placed (e.g., using a pick-and-place tool) onto a second side (e.g., the bottom side) of the package substrate 104. Specifically, the connection structure 114 of the integrated circuit device 112 can be located on a solder pad above a metal pad 408 on the second side of the package substrate 104.

[0110] like Figure 4H As shown, the integrated circuit device 112 can be mounted or attached to the second side of the package substrate 104 by forming a bond between the connection structure 114 and the metal pad 408 of the package substrate 104. The semiconductor device package 102 can be bonded to the connection structure 114 and the metal pad 408 by reflowing the solder pads using a soldering tool (e.g., a wave soldering tool and / or other types of soldering tools).

[0111] like Figure 4I As shown, after the integrated circuit device 112 is mounted or attached to the second side of the package substrate 104, an underfill layer 116 can be distributed (e.g., using a dispensing tool) around the integrated circuit device 112. The underfill layer 116 can be dispensed such that it fills the gaps around the connection structure 114 and the gaps around the spaces between the integrated circuit devices 112.

[0112] like Figure 4J As shown, a thermal interface material layer 142 can be provided on the top surface of the integrated circuit device 112 (e.g., the surface opposite to the surface to which the integrated circuit device 112 is mounted or attached to the package substrate 104). In some embodiments, the thermal interface material layer 142 is a paste, liquid, or other flowable material dispensed (e.g., using a dispensing tool) onto the integrated circuit device 112. In some embodiments, the thermal interface material layer 142 is placed on the integrated circuit device 112 (e.g., in sheet or pad form). In some embodiments, the thermal interface material layer 142 is formed or grown on the integrated circuit device 112.

[0113] like Figure 4KAs shown, the thermal cap structure 132 is mounted or attached to a second side (e.g., the bottom side) of the package substrate 104, such that the cover 136 of the thermal cap structure 120 is positioned above the integrated circuit device 112. A pick-and-place tool or other suitable tool can be used to place the thermal cap structure 132 onto the package substrate 104 such that the cover 136 of the thermal cap structure 132 contacts the thermal interface material layer 142 to form a thermal connection between the integrated circuit device 112 and the cover 136 of the thermal cap structure 132 through the thermal interface material layer 142. The base 134 can be secured to the second side of the package substrate 104 by adhesives, epoxy resins, solder pads, and / or by bonding the base 134 to metal pads on the package substrate 104.

[0114] As mentioned above, providing Figures 4A to 4K As an example. Other examples can be compared with... Figures 4A to 4K The descriptions differ. For example, although... Figures 4A to 4K The example 400 shown and described includes installing or attaching the heat cover structure 132 after installing or attaching the heat cover structure 120; however, these operations can be reversed, such that the heat cover structure 120 is installed or attached after the heat cover structure 132 is installed or attached. Figures 4A to 4K Other modifications to the sequence of operations shown and described also fall within the scope of this invention.

[0115] Figure 5A and Figure 5B This is a diagram illustrating an example 600 of mounting a semiconductor device package according to the present invention to a mounting structure. In some embodiments, one or more operations related to the description of Example 500 may be performed to mount a semiconductor device package 102 to a mounting structure 146. In some embodiments, one or more operations related to the description of Example 500 may be performed to mount another semiconductor device package to the mounting structure, such as semiconductor device package 602, semiconductor device package 702, semiconductor device package 802, and / or semiconductor device package 902, etc. In some embodiments, one or more packaging tools (e.g., in a semiconductor packaging facility) are used to perform the operations related to the description of Example 500, such as RDL tools, connection tools, pick-and-place tools, dispensing tools, solder mask tools, and / or reflow tools, etc.

[0116] like Figure 5AAs shown, the package connection element 118 can be mounted or attached to a second side (e.g., the bottom side) of the package substrate 104. The package connection element 118 can be positioned such that one or more package connection elements 118 are located below the base 122 in the z-direction. Furthermore, the package connection element 118 can be positioned such that it is positioned outside and adjacent to the periphery of the base 134. The package connection element 118 can be secured to the second side of the package substrate 104 using adhesives, epoxy resins, solder pads, sockets, and / or metal pads bonded to the package substrate 104.

[0117] like Figure 5A and Figure 5B As shown, a semiconductor device package 102 can be mounted or attached to a mounting structure 146 by mounting or attaching a package connection element 118 to the mounting structure 146. In some embodiments, the package connection element 118 is placed in a socket on the mounting structure 146. In some embodiments, the package connection element 118 is soldered to a pad on the mounting structure 146. In some embodiments, a connector is inserted into the package connection element 118.

[0118] As mentioned above, providing Figure 5A and Figure 5B As an example. Other examples can be found related to... Figure 5A and Figure 5B The descriptions are different.

[0119] Figure 6A and Figure 6B This is a diagram of another example of a semiconductor device package according to the present invention. Figure 6A A cross-sectional view of an example 600 of a semiconductor device package 602 is shown. Figure 6A As shown, the semiconductor device package 602 includes combinations and arrangements of elements (e.g., devices, structures, and / or layers) 604 to 642 similar to the elements 104 to 142 of the semiconductor device package 102. Furthermore, the semiconductor device package 602 can be mounted or attached to the mounting structure 644 in a manner similar to mounting or attaching the semiconductor device package 102 to the mounting structure 146.

[0120] The difference between semiconductor device package 602 and semiconductor device package 102 is that the spacing between integrated circuit devices 612 in semiconductor device package 602 is greater than the spacing between integrated circuit devices 112 in semiconductor device package 102. Therefore, a larger heat dissipation area can be provided around the integrated circuit devices 612, while the spacing between the integrated circuit devices 112 in semiconductor device package 102 allows for a higher density of integrated circuit devices 112 within semiconductor device package 102.

[0121] Figure 6B Example 646 shows a bottom view of a semiconductor device package 602. The cover 636 of the heat cover structure 632 is omitted in the bottom view, making the integrated circuit device 612 and the base 634 on the second side (e.g., the back side) of the package substrate 604 visible. Figure 6B It also showed Figure 6A The location of section BB. For example... Figure 6B As shown, the integrated circuit device 612 is located around the continuous closed-loop structure of the base 634 and arranged in a grid, wherein the spacing between adjacent rows and columns of the integrated circuit device 612 is larger than the spacing in the semiconductor device package 102.

[0122] As mentioned above, providing Figure 6A and Figure 6B As an example. Other examples can be found related to... Figure 6A and Figure 6B The descriptions are different.

[0123] Figure 7A and Figure 7B This is a diagram of an example of another semiconductor device package according to the present invention. Figure 7A A cross-sectional view of an example 700 of a semiconductor device package 702 is shown. Figure 7A As shown, the semiconductor device package 702 includes combinations and arrangements of elements (e.g., devices, structures, and / or layers) 704 to 742 similar to the elements 104 to 142 of the semiconductor device package 102. Furthermore, the semiconductor device package 702 can be mounted or connected to the mounting structure 744 in a manner similar to mounting or attaching the semiconductor device package 102 to the mounting structure 146.

[0124] like Figure 7A As further shown, one or more passive circuit devices 746 may be mounted or attached to a second side (e.g., the bottom side) of the package substrate 704. The passive circuit device 746 may be adjacent to one or more integrated circuit devices 712. In Example 700, the z-axis dimension of the passive circuit device 746 is smaller than that of the integrated circuit device 712. Therefore, the passive circuit device 746 may be separated from the cover 736 of the heat-shrink structure 732 by an air gap (e.g., not in physical contact).

[0125] Passive circuitry 746 may include resistors, capacitors, inductors, diodes, and / or other types of passive circuitry. In some embodiments, one or more passive circuitry 746 include decoupling capacitors for shunting noise (e.g., voltage spikes, voltage swings) in the power delivered to the semiconductor die 106. In some embodiments, one or more passive circuitry 746 include diodes arranged in a passive ESD protection circuit. In some embodiments, one or more passive circuitry 746 include diodes arranged in a rectifier circuit for converting between alternating current (AC) and direct current (DC). In some embodiments, passive circuitry 746 includes IPDs, each IPD containing multiple packaged passive circuitry devices.

[0126] Figure 7B Example 748 shows a bottom view of a semiconductor device package 702. The cover 736 of the heat cover structure 732 is omitted in the bottom view, so that the integrated circuit device 712 and the base 734 on the second side (e.g., the back side) of the package substrate 704 are visible. Figure 7B It also showed Figure 7A The location of section CC. For example... Figure 7B As shown, integrated circuit device 712 and passive circuit device 746 are located around the continuous closed-loop structure of base 134. In some embodiments, passive circuit device 746 is arranged in one or more rows adjacent to one or more sides of the grid in which integrated circuit device 712 is located. In some embodiments, one or more rows of passive circuit device 746 are located between integrated circuit device 712 and one or more segments of base 134 (e.g., the inner walls of one or more segments).

[0127] As mentioned above, providing Figure 7A and Figure 7B As an example. Other examples can be compared with... Figure 7A and Figure 7B The descriptions are different.

[0128] Figure 8 This is a diagram of an example of another semiconductor device package according to the present invention. Figure 8 A cross-sectional view of an example 800 of a semiconductor device package 802 is shown. Figure 8As shown, the semiconductor device package 802 includes combinations and arrangements of elements (e.g., devices, structures, and / or layers) 804 to 842 similar to the elements 104 to 142 of the semiconductor device package 102. Furthermore, the semiconductor device package 802 includes one or more passive circuit devices 846 (similar to the passive circuit devices 746 in the semiconductor device package 702), and can be mounted or attached to the mounting structure 844 in a manner similar to mounting or attaching the semiconductor device package 102 to the mounting structure 146.

[0129] like Figure 8 As further shown, the passive circuit device 846 differs from the passive circuit device 746 in that the passive circuit device 846 is thermally coupled to the cover 836 of the heat cover structure 832 via a thermal interface material layer 848. This allows the passive circuit device 846 to be cooled by the heat cover structure 832 in a manner similar to that of the integrated circuit device 812.

[0130] As mentioned above, providing Figure 8 As an example. Other examples can be compared with... Figure 8 The differences described in [the text].

[0131] Figure 9 This is a diagram of an example of another semiconductor device package according to the present invention. Figure 9 A cross-sectional view of an example 900 of a semiconductor device package 902 is shown. Figure 9 As shown, the semiconductor device package 902 includes combinations and arrangements of elements (e.g., devices, structures, and / or layers) 904 to 942 similar to the elements 104 to 142 of the semiconductor device package 102. Furthermore, the semiconductor device package 902 can be mounted or connected to the mounting structure 944 in a manner similar to mounting or attaching the semiconductor device package 102 to the mounting structure 146.

[0132] like Figure 9Further shown, one or more semiconductor dies 906 may be arranged laterally (e.g., along the x-direction, along the y-direction) on a first side (e.g., the front side) of the semiconductor die. The package substrate 904 has one or more multi-die semiconductor die packages 946. In the multi-die semiconductor die package 946, semiconductor dies 906a and 906b may be stacked and arranged vertically in the z-direction. In some embodiments, semiconductor dies 906a and 906b are directly bonded together by metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, semiconductor dies 906a and 906b are stacked and electrically connected through a wafer package substrate. In some embodiments, semiconductor dies 906a and 906b are stacked and electrically connected through vias (e.g., through silicon vias (TSVs) or through insulator vias (TIVs)). In some embodiments, one or more semiconductor dies 906a and 906b are also arranged horizontally with another semiconductor die in the multi-die semiconductor die package 946.

[0133] As mentioned above, providing Figure 9 As an example. Other examples can be compared with... Figure 9 The differences described in [the text].

[0134] Figure 10 This is a flowchart of an exemplary process 1000 related to forming the semiconductor device package described in this utility model. In some embodiments, one or more packaging tools are used to perform the process. Figure 10 One or more process blocks, such as RDL tools, connection tools, pick-and-place tools, dispensing tools, solder mask tools and / or reflow tools, etc.

[0135] like Figure 10 As shown, process 1000 may include attaching a plurality of semiconductor dies to a first side (block 1010) of a substrate of a semiconductor device package. As described in the embodiments of the present invention, for example, one or more packaging tools may be used to attach a plurality of semiconductor dies (e.g., semiconductor dies 106, 606, 706, 806, 906 and / or 946) to a first side of a substrate (e.g., packaging substrate 104, 604, 704, 804 and / or 904) of a semiconductor device package (e.g., semiconductor device packages 102, 602, 702, 802 and / or 902).

[0136] like Figure 10As further shown, process 1000 may include attaching a heat-cap structure to a first side of a substrate, such that the heat-cap structure is located above and thermally coupled to the plurality of semiconductor dies (block 1020). As described in the embodiments of the present invention, one or more packaging tools may be used, for example, to attach a heat-cap structure (e.g., heat-cap structures 120, 620, 720, 820 and / or 920) to a first side of a substrate, such that the heat-cap structure is located above and thermally coupled to the plurality of semiconductor dies.

[0137] like Figure 10 As further shown, process 1000 may include attaching a plurality of integrated circuit devices to a second side of a substrate, the second side being perpendicular to and opposite to the first side (block 1030). As described in the embodiments of the present invention, one or more packaging tools may be used to attach a plurality of integrated circuit devices (e.g., integrated circuit devices 112, 612, 712, 812 and / or 912) to a second side of the substrate that is perpendicular to and opposite to the first side (e.g., along the z-direction).

[0138] like Figure 10 As further shown, process 1000 may include distributing thermal interface material onto a plurality of integrated circuit devices (block 1040). As described in this invention, one or more packaging tools may be used, for example, to distribute thermal interface material (e.g., thermal interface material layers 142, 642, 742, 842 and / or 942) onto a plurality of integrated circuit devices.

[0139] like Figure 10 As further shown, process 1000 may include attaching a vapor chamber cover structure to a second side of a substrate, such that the vapor chamber cover structure is positioned above a plurality of integrated circuit devices and is thermally coupled to the plurality of integrated circuit devices via a thermal interface material (block 1050). As described in the embodiments of the present invention, for example, one or more packaging tools may be used to connect the vapor chamber cover structure (e.g., heat cover structures 132, 632, 732, 832 and / or 932) to the second side of the substrate, such that the vapor chamber cover structure is positioned above a plurality of integrated circuit devices and is thermally coupled to the plurality of integrated circuit devices via a thermal interface material.

[0140] Process 1000 may include other embodiments, such as any single embodiment or any combination of embodiments described below and / or combined with one or more other processes described elsewhere in this utility model.

[0141] In a first embodiment, process 1000 includes distributing an underfill material (e.g., underfill layers 116, 616, 716, 816 and / or 916) between a plurality of integrated circuit devices and a second side of a substrate, wherein distributing a thermal interface material onto the plurality of integrated circuit devices includes distributing the thermal interface material onto the plurality of integrated circuit devices after distributing the underfill material between the plurality of integrated circuit devices and the second side of the substrate.

[0142] In a second embodiment, process 1000 includes attaching a plurality of passive circuit devices (e.g., passive circuit devices 746 and / or 846) to a second side of a substrate, wherein attaching a heat spreader cover structure to the second side of the substrate includes attaching the heat spreader cover structure to the second side of the substrate such that the heat spreader cover structure is positioned above the plurality of passive circuit devices.

[0143] In the third embodiment, a plurality of passive circuit devices are located between a plurality of integrated circuit devices and the cover walls of the vapor chamber cover (e.g., bases 134, 634, 734, 834 and / or 934).

[0144] In the fourth embodiment, attaching a plurality of integrated circuit devices to a second side of a substrate and attaching a heat spreader cover structure to a second side of a substrate includes: after attaching a plurality of semiconductor dies and a heat spreader cover structure to a first side of a substrate, attaching a plurality of integrated circuit devices to a second side of a substrate and attaching a heat spreader cover structure to a second side of a substrate.

[0145] In a fifth embodiment, process 1000 includes attaching a semiconductor device package to a mounting structure (e.g., mounting structures 146, 644, 744, 844, and / or 944), wherein a vapor chamber cover structure is located between a substrate and the mounting structure.

[0146] although Figure 10 The diagram shows an example block of process 1000, but in some embodiments, process 1000 includes... Figure 10 Compared to the blocks depicted in the text, this also includes additional blocks, fewer blocks, different blocks, or blocks arranged differently.

[0147] Therefore, thermal management components are included on the semiconductor components on both sides of the package substrate of the semiconductor device package to provide a double-sided thermal management system for the semiconductor device package. The semiconductor components can be mounted or attached to the top side of the package substrate, and the semiconductor components can also be mounted or attached to the bottom side of the package substrate. Thermal management components such as heat sinks, fins, vapor chamber structures, and / or other types of thermal management components can be included above the semiconductor components on the top side and the bottom side of the package substrate. Thus, the double-sided thermal management system of the semiconductor device package enables heat dissipation from the semiconductor elements on both sides of the package substrate of the semiconductor device package. This allows the semiconductor components on both sides of the package substrate of the semiconductor device package to operate at lower temperatures, which can improve the performance of the semiconductor components, allow the performance of the semiconductor components to be maintained for a longer period of time, and / or increase the reliability and lifespan of the semiconductor components.

[0148] This utility model provides a semiconductor device package, including a substrate, a plurality of semiconductor dies, a plurality of integrated circuit devices, a first vapor chamber cover structure, and a second vapor chamber cover structure. The plurality of semiconductor dies are located on a first side of the substrate. The plurality of integrated circuit devices are located on a second side of the substrate, opposite to the first side. The first vapor chamber cover structure is located above the semiconductor dies and thermally coupled to them. The second vapor chamber cover structure is located above the integrated circuit devices and thermally coupled to them.

[0149] In some embodiments, the integrated circuit device includes a plurality of voltage regulation module integrated circuit devices. The voltage regulation module integrated circuit devices are thermally coupled to a second vapor chamber cover structure via a thermal interface material. In some embodiments, the second vapor chamber cover structure includes: a base having a continuous closed-loop structure defining a space in which the integrated circuit devices are located; a cover coupled to the base and spanning the space defined by the base, wherein the cover is thermally coupled to the integrated circuit devices; and a vapor chamber located within the cover. In some embodiments, the integrated circuit devices are thermally coupled to a first side of the cover. The second vapor chamber cover structure further includes a plurality of fins physically coupled to a second side of the cover, with the first side opposite to the second side. In some embodiments, the first vapor chamber cover structure includes another base having a continuous closed-loop structure defining a space in which a semiconductor die is located, wherein the outer periphery of the base of the second vapor chamber cover structure is located within the outer periphery of the other base of the first vapor chamber cover structure. In some embodiments, the inner periphery of the base of the second vapor chamber cover structure is located within the inner periphery of the other base of the first vapor chamber cover structure. In some embodiments, a base of the first heat spreader cover structure is coupled to a first side of the substrate, and a base of the second heat spreader cover structure is coupled to a second side of the substrate.

[0150] This utility model provides a semiconductor device package, including a substrate, a plurality of semiconductor dies, a plurality of voltage-regulating integrated circuit devices, a first vapor chamber cover structure, a second vapor chamber cover structure, and one or more package connection elements. The plurality of semiconductor dies are located on a front side of the substrate. The plurality of voltage-regulating integrated circuit devices are located on a back side of the substrate, opposite to the front side. The first vapor chamber cover structure is located above the semiconductor dies and thermally coupled to them. The second vapor chamber cover structure is located above the voltage-regulating integrated circuit devices and thermally coupled to them. One or more package connection elements are located on the back side of the substrate, and one or more package connection elements are located around the second vapor chamber cover structure.

[0151] In some embodiments, the periphery of the second vapor chamber cover structure is at least partially located within a periphery of the first vapor chamber cover structure. In some embodiments, the first vapor chamber cover structure includes a cover wall surrounding the periphery of a substrate and coupled to a portion of the front side of the substrate, wherein one or more package connection elements are located below the portion of the front side of the substrate coupled to the cover wall, such that the cover wall and the one or more package connection elements are vertically aligned within the semiconductor device package. In some embodiments, the semiconductor device package further includes one or more integrated passive devices located on the back side of the substrate and laterally adjacent to a voltage-regulated integrated circuit device. In some embodiments, the one or more integrated passive devices are air-spaced from the second vapor chamber cover structure. In some embodiments, the one or more integrated passive devices are thermally coupled to the second vapor chamber cover structure. In some embodiments, at least a subset of semiconductor dies includes a polycrystalline semiconductor die package, wherein at least two of the semiconductor dies are directly connected to each other and vertically aligned.

[0152] This utility model provides a method for manufacturing a semiconductor device package, including attaching a plurality of semiconductor dies to a first side of a substrate of the semiconductor device package, attaching a heat cover structure to the first side of the substrate such that the heat cover structure is positioned above the semiconductor dies and thermally coupled to the semiconductor dies, attaching a plurality of integrated circuit devices to a second side of the substrate, wherein the first side and the second side are perpendicular to each other, distributing a thermal interface material above the integrated circuit devices, and attaching a heat spreader cover structure to the second side of the substrate such that the heat spreader cover structure is positioned above the integrated circuit devices and thermally coupled to the integrated circuit devices through the thermal interface material.

[0153] In some embodiments, the method of manufacturing a semiconductor device package further includes dispensing an underfill material between an integrated circuit device and a second side of a substrate, wherein dispensing a thermal interface material over the integrated circuit device includes dispensing the thermal interface material over the integrated circuit device after dispensing the underfill material between the integrated circuit device and the second side of the substrate. In some embodiments, the method of manufacturing a semiconductor device package further includes attaching a plurality of passive circuit devices to a second side of a substrate, wherein attaching a vapor chamber cover structure to a second side of the substrate includes attaching the vapor chamber cover structure to a second side of the substrate such that the vapor chamber cover structure is positioned above the passive circuit devices. In some embodiments, the passive circuit devices are positioned between the integrated circuit device and the cover wall of the vapor chamber cover structure. In some embodiments, attaching the integrated circuit device to a second side of the substrate and attaching the vapor chamber cover structure to a second side of the substrate includes attaching the integrated circuit device to a second side of the substrate and attaching the vapor chamber cover structure to a second side of the substrate after attaching a semiconductor die and a thermal cover structure to a first side of the substrate. In some embodiments, the method of manufacturing a semiconductor device package further includes attaching the semiconductor device package to a mounting structure, wherein the vapor chamber cover structure is positioned between the substrate and the mounting structure.

[0154] The terms “approximately” and “substantially” can indicate that the value of a given quantity varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and are not intended to be limiting. It should be understood that, according to this invention, the terms “approximately” and “substantially” can refer to a percentage of the value of a given quantity.

[0155] The foregoing outlines the features of many embodiments, thus enabling those skilled in the art to better understand various aspects of this invention. Those skilled in the art may readily design or modify other processes and structures based on this invention to achieve the same objectives and / or obtain the same advantages as the embodiments of this invention. It should also be understood by those skilled in the art that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this invention, and such equivalent creations do not exceed the spirit and scope of this invention.

Claims

1. A semiconductor device package, characterized in that, include: One substrate; Multiple semiconductor chips are located on a first side of the substrate; Multiple integrated circuit devices are located on a second side of the substrate, the first side being opposite to the second side; A first heat spreader cover structure is located above the plurality of semiconductor chips and is thermally coupled to the plurality of semiconductor chips; as well as A second heat spreader cover structure is located above the plurality of said integrated circuit devices and is thermally coupled to the plurality of said integrated circuit devices.

2. The semiconductor device package as claimed in claim 1, characterized in that, The plurality of said integrated circuit devices include a plurality of voltage regulation module integrated circuit devices; and Multiple voltage regulation module integrated circuit devices are thermally coupled to the second heat spreader cover structure via a thermal interface material.

3. The semiconductor device package as claimed in claim 1, characterized in that, The second heat-equalizing plate cover structure includes: A base has a continuous closed-loop structure that defines a space in which a plurality of said integrated circuit devices are located; A cover, coupled to the base and spanning the space defined by the base, wherein the cover is thermally coupled to a plurality of said integrated circuit devices; and A temperature equalization plate is located inside the cover.

4. The semiconductor device package as claimed in claim 3, characterized in that, The first heat-equalizing plate cover structure includes: The other foot has a continuous closed-loop structure defining a space in which a plurality of said semiconductor grains are located, wherein an outer periphery of the foot of the second heat spreader structure is located within an outer periphery of the other foot of the first heat spreader structure.

5. The semiconductor device package as claimed in claim 4, characterized in that, The inner periphery of the base of the second heat exchanger cover structure is located within the inner periphery of the other base of the first heat exchanger cover structure.

6. The semiconductor device package as claimed in claim 1, characterized in that, A base of the first heat spreader cover structure is coupled to the first side of the substrate; and One base of the second heat spreader cover structure is coupled to the second side of the substrate.

7. A semiconductor device package, characterized in that, include: One substrate; Multiple semiconductor chips are located on one front side of the substrate; Multiple voltage-regulating integrated circuit devices are located on a back side of the substrate, opposite to the front side; A first heat spreader cover structure is located above the plurality of semiconductor chips and is thermally coupled to the plurality of semiconductor chips; A second heat spreader cover structure is located above the plurality of voltage regulation integrated circuit devices and is thermally coupled to the plurality of voltage regulation integrated circuit devices; as well as One or more packaged connection elements are located on the back side of the substrate. The one or more packaged connecting elements are located outside one of the periphery of the second heat spreader cover structure.

8. The semiconductor device package as claimed in claim 7, characterized in that, The periphery of the second heat exchanger cover structure is at least partially located within a periphery of the first heat exchanger cover structure.

9. The semiconductor device package as claimed in claim 7, characterized in that, The first heat spreader cover structure includes a cover wall surrounding a portion of the substrate and coupled to a front portion of the substrate; and The one or more package connection elements are located below the portion of the front side of the substrate coupled to the cover wall, such that the cover wall and the one or more package connection elements are arranged vertically in the semiconductor device package.

10. The semiconductor device package as claimed in claim 7, characterized in that, At least one subset of the plurality of semiconductor dies includes a multi-die semiconductor die package, wherein at least two of the plurality of semiconductor dies are directly connected to each other and arranged vertically.

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