Drive signal interlock module, drive assembly, and hybrid power device

Abstract

The embodiment of the utility model provides a kind of drive signal interlock module, drive assembly and hybrid power device, wherein, drive signal interlock module includes: first primary interlock circuit, first primary interlock circuit includes first high-speed photoelectric coupler, first capacitor and first resistance;Second primary interlock circuit, second primary interlock circuit includes second high-speed photoelectric coupler, second capacitor and second resistance;First signal source and second signal source are complementary pulse width modulation signals;Secondary interlock circuit, secondary interlock circuit includes six-channel inverter, the first pin of six-channel inverter is connected first primary interlock circuit, the thirteenth pin of six-channel inverter is connected second primary interlock circuit.The scheme of the utility model, through the collaborative design of two primary interlock circuits and secondary interlock circuit, realize the hardware level interlock protection and signal waveform shaping of complementary PWM signal.

Description

Technical Field

[0001] This application relates to the field of signal waveform circuit technology, and more specifically, to a drive signal interlock module, a drive component, and a hybrid power device. Background Technology

[0002] Due to differences in material properties, silicon carbide MOSFETs (SiC MOSFETs) and insulated-gate bipolar transistors (IGBTs) present challenges when connected in parallel, in series, or as a hybrid module requiring simultaneous driving. These challenges include signal competition, electromagnetic interference spikes, and drive voltage mismatch. Current traditional interlocking circuits typically employ fixed-delay logic, which is unsuitable for the dynamic switching requirements of SiC / IGBT hybrid modules. Furthermore, traditional drive signal shaping techniques are mostly designed for individual devices, optimizing only SiC or IGBTs independently and failing to address the collaborative driving issues of SiC / IGBT hybrid power devices. Utility Model Content

[0003] The purpose of this application is to provide a drive signal interlock module, a drive component, and a hybrid power device that can solve the problem of coordinated drive of SiC / IGBT hybrid power devices.

[0004] In view of this, an embodiment of the first aspect of this application provides a drive signal interlock module.

[0005] An embodiment of the second aspect of this application provides a driving component.

[0006] An embodiment of the third aspect of this application provides a hybrid power device.

[0007] To achieve the above objectives, an embodiment of the first aspect of this application provides a drive signal interlock module, which includes: a first primary interlock circuit, comprising a first high-speed optocoupler, a first capacitor, and a first resistor; a first terminal of the first resistor being connected to the power supply terminal of the first high-speed optocoupler; a second terminal of the first resistor being connected to the first terminal of the first capacitor; a second terminal of the first capacitor being connected to the ground terminal of the first high-speed optocoupler; the anode of the first high-speed optocoupler being connected to a first signal source; and the cathode of the first high-speed optocoupler being connected to a second signal source; wherein the first signal source and the second signal source are complementary pulse width modulation signals; and a second primary interlock circuit, comprising a second high-speed... The system includes an optocoupler, a second capacitor, and a second resistor. The first end of the second resistor is connected to the power supply terminal of the second high-speed optocoupler, and the second end of the second resistor is connected to the first end of the second capacitor. The second end of the second capacitor is connected to the ground terminal of the second high-speed optocoupler. The anode of the second high-speed optocoupler is connected to a second signal source, and the cathode of the second high-speed optocoupler is connected to a first signal source. A secondary interlock circuit is also included, comprising a six-channel inverter. The first pin of the six-channel inverter is connected to a first primary interlock circuit, and the thirteenth pin of the six-channel inverter is connected to a second primary interlock circuit. The secondary interlock circuit determines the drive signal based on the first modulation signal transmitted by the first primary interlock circuit and the second modulation signal transmitted by the second primary interlock circuit.

[0008] The drive signal interlock module proposed in this application mainly includes a first primary interlock circuit, a second primary interlock circuit, and a secondary interlock circuit. The output terminal of the first high-speed optocoupler in the first primary interlock circuit is connected to the first pin of the six-channel inverter in the secondary interlock circuit, and the output terminal of the second high-speed optocoupler in the second primary interlock circuit is connected to the thirteenth pin of the six-channel inverter in the secondary interlock circuit. Furthermore, the anode of the first high-speed optocoupler is connected to a first signal source, and the cathode of the first high-speed optocoupler is connected to a second signal source. The anode of the second high-speed optocoupler is connected to the second signal source, and the cathode of the second high-speed optocoupler is connected to the first signal source. The first and second signal sources are complementary pulse width modulation (PWM) signals. Both the first and second modulation signals are PWM signals. When the PWM signal corresponding to the first signal source is high, the PWM signal corresponding to the second signal source is low; conversely, when the PWM signal corresponding to the first signal source is low, the PWM signal corresponding to the second signal source is high.

[0009] Understandably, the hardware-level interlocking protection and waveform shaping of complementary PWM signals are achieved through the coordinated design of two primary interlocking circuits and a secondary interlocking circuit. The primary interlocking circuit blocks signal contention and shoot-through short circuits at the source through hardware isolation and dynamic interlocking of high-speed optocouplers; the secondary interlocking circuit achieves signal purification, level adaptation, and complementary output through a six-channel inverter and logic interlocking, thereby improving the accuracy and reliability of the hybrid PWM and ensuring that the drive signal operates strictly according to the set dead time.

[0010] In the above technical solution, optionally, in the six-channel inverter, the first and second pins, the third and fourth pins, the fifth and sixth pins, the eighth and ninth pins, the tenth and eleventh pins, and the twelfth and thirteenth pins each form an input / output channel; the first primary interlock circuit is connected to the first pin through the output terminal of the first high-speed optocoupler, and the second primary interlock circuit is connected to the thirteenth pin through the output terminal of the second high-speed optocoupler; the secondary interlock circuit outputs the first modulation signal transmitted by the first primary interlock circuit through the sixth pin of the six-channel inverter, and outputs the second modulation signal transmitted by the second primary interlock circuit through the eighth pin of the six-channel inverter; the second and third pins are directly connected, and the eleventh and twelfth pins are directly connected; the seventh pin is grounded, and the fourteenth pin is connected to the power supply; wherein, the input / output channel includes a Schmitt trigger inverter.

[0011] In this scheme, the first pin of the six-channel inverter is connected to the output of the first high-speed optocoupler, and the thirteenth pin of the six-channel inverter is connected to the output of the second high-speed optocoupler. The drive signals transmitted by the first and second high-speed optocouplers are transmitted to the six-channel inverter. In the six-channel inverter, a multi-stage signal processing link is formed by Schmitt inverters. Based on the signal complementarity and dead time correction completed by the first and second high-speed optocouplers, the signal edges are further sharpened. Secondary hardware interlocking is achieved through logical path cross-coupling. When a signal in one path is abnormal, the direct path triggers the reverse channel to forcibly pull down the complementary signal, ensuring that the drive signals are strictly mutually exclusive, thus eliminating the risk of bridge arm shoot-through in SiC / IGBT hybrid power devices from a physical level.

[0012] Furthermore, by leveraging the hysteresis characteristics of the Schmitt inverters in the input and output channels, the switching thresholds are dynamically adjusted to accommodate the timing differences between the high-speed switching of SiC MOSFETs and IGBTs, thus preventing voltage overshoot. Moreover, the Schmitt inverters feature dual threshold voltages: when the input signal exceeds the first threshold voltage, the corresponding drive signal output from the input / output channel goes low; when the input signal falls below the second threshold voltage, the corresponding drive signal output from the input / output channel goes high. This dual threshold voltage converts the slowly rising or falling drive signals from the first and second high-speed optocouplers into steep, regular square waves, ensuring clear drive signal edges.

[0013] Optionally, in the above technical solution, the first high-speed optocoupler includes: a first photodiode, the anode of which is connected to a first signal source, and the cathode of which is connected to a second signal source; a first photodiode and a first amplifier, which are connected in parallel; and a first transistor, the base of which is connected to the first terminal of a first resistor through the first amplifier, the collector of which is connected to the first pin of a six-channel inverter, and the emitter of which is connected to the second terminal of a first capacitor.

[0014] In this scheme, the first high-speed optocoupler integrates a first photodiode, a first photodiode, a first amplifier, and a first transistor, forming a photo-to-electric conversion and signal amplification link. The positive terminal of the first photodiode is connected to a first signal source, and the negative terminal is connected to a second signal source. When the first signal source is at a high level, the second signal source is at a low level, the first photodiode conducts and emits light, and the optical signal is received by the first photodiode and converted into a current signal. The first amplifier is connected in parallel with the first photodiode, amplifying the current signal and driving the base of the first transistor, controlling the first transistor to conduct, so that the collector outputs a low-level signal. The first capacitor is connected in parallel between the emitter of the first transistor and ground to filter out high-frequency switching noise and ensure the stability of the output signal. Furthermore, the first resistor is connected in series as a pull-up resistor between the output of the first amplifier and the base of the first transistor to limit the base current.

[0015] Understandably, the isolation design of the first high-speed optocoupler blocks loop interference, and the first amplifier and first transistor enhance the signal driving capability. The first capacitor acts as a filter capacitor to suppress noise. The driving signal output from the first high-speed optocoupler is transmitted to the six-channel inverter. The Schmitt inverter solves the signal jitter problem based on hysteresis characteristics and edge sharpening, ensuring the integrity of the high-speed signal and providing a highly reliable driving signal for SiC / IGBT hybrid power devices.

[0016] Optionally, in the above technical solution, the second high-speed optocoupler includes: a second photodiode, the positive terminal of which is connected to a second signal source, and the negative terminal of which is connected to a first signal source; a second photodiode and a second amplifier, which are connected in parallel; and a second transistor, the base of which is connected to the first terminal of a second resistor through the second amplifier, the collector of which is connected to the thirteenth pin of a six-channel inverter, and the emitter of which is connected to the second terminal of a second capacitor.

[0017] In this design, the second high-speed optocoupler integrates a second photodiode, a second photodiode, a second amplifier, and a second transistor, forming a photo-to-electric conversion and signal amplification link. The positive terminal of the second photodiode is connected to the second signal source, and the negative terminal is connected to the first signal source. When the second signal source is at a high level, the first signal source is at a low level, the second photodiode conducts and emits light, and the optical signal is received by the second photodiode and converted into a current signal. The second amplifier is connected in parallel with the second photodiode, amplifying the current signal to drive the base of the second transistor, controlling the second transistor to conduct and causing the collector to output a low-level signal. The second capacitor is connected in parallel between the emitter of the second transistor and ground to filter out high-frequency switching noise and ensure the stability of the output signal. Furthermore, a second resistor is connected in series between the output of the second amplifier and the base of the second transistor as a pull-up resistor to limit the base current.

[0018] Understandably, the isolation design of the second high-speed optocoupler blocks loop interference, and the second amplifier and second transistor enhance the signal driving capability. The second capacitor acts as a filter capacitor to suppress noise. The driving signal output from the second high-speed optocoupler is transmitted to the six-channel inverter. The Schmitt inverter solves the signal jitter problem based on hysteresis characteristics and edge sharpening, ensuring the integrity of the high-speed signal and providing a highly reliable driving signal for SiC / IGBT hybrid power devices.

[0019] Optionally, in the above technical solution, the secondary interlock circuit includes: a first diode, the anode of which is connected to the third pin of the six-channel inverter, and the cathode of which is connected to the ninth pin of the six-channel inverter; a second diode, the anode of which is connected to the twelfth pin of the six-channel inverter, and the cathode of which is connected to the fifth pin of the six-channel inverter; a third capacitor, the first terminal of which is connected to the power supply, and the second terminal of which is connected to the cathode of the second diode; and a fourth capacitor, the first terminal of which is connected to the power supply, and the second terminal of which is connected to the cathode of the first diode.

[0020] In this design, the anode of the first diode is connected to the third pin of the six-channel inverter, and the cathode of the first diode is connected to the ninth pin of the six-channel inverter. The anode of the second diode is connected to the twelfth pin of the six-channel inverter, and the cathode of the second diode is connected to the fifth pin of the six-channel inverter. When the first high-speed optocoupler outputs a high-level drive signal, the first diode conducts, transmitting the high-level drive signal to the channel input terminal corresponding to the ninth pin, forcing the channel corresponding to the ninth pin to output a low level, ensuring that the drive signal corresponding to the third pin and the drive signal corresponding to the twelfth pin are strictly complementary. Similarly, when the second diode conducts, it forces the channel corresponding to the sixth pin to output a low-level drive signal, forming a bidirectional hardware interlock.

[0021] Optionally, in the above technical solution, the secondary interlock circuit further includes: a fifth resistor, the first end of which is connected to the second end of the third capacitor, and the second end of which is connected to the fourth pin of the six-channel inverter; and a sixth resistor, the first end of which is connected to the second end of the fourth capacitor, and the second end of which is connected to the tenth pin of the six-channel inverter.

[0022] In this design, the fifth and sixth resistors act as current-limiting resistors, connected in series between the third capacitor and the fourth pin of the six-channel inverter, and between the fourth capacitor and the tenth pin of the six-channel inverter, respectively. One end of the fifth resistor is connected to the second terminal of the third capacitor, serving as logic node A, and is connected to the negative terminal of the second diode; the other end is connected to the fourth pin of the six-channel inverter. One end of the sixth resistor is connected to the second terminal of the fourth capacitor, serving as logic node B, and is connected to the negative terminal of the first diode; the other end is connected to the tenth pin of the six-channel inverter. When logic nodes A and B experience instantaneous current spikes due to diode conduction or external interference, the current-limiting resistors limit the current to a safe range, preventing overcurrent damage to the six-channel inverter.

[0023] Optionally, in the above technical solution, the first primary interlock circuit further includes: a third resistor, the first end of which is connected to the first signal source, and the second end of which is connected to the positive terminal of the first photodiode.

[0024] In this scheme, the third resistor, acting as a current-limiting resistor, is connected in series between the first signal source and the positive terminal of the first photodiode. This limits the driving current flowing through the first photodiode, preventing overcurrent damage due to excessively high input signal voltage or transient surges. By limiting the driving current of the photodiode, the luminous intensity on the primary side of the optocoupler is kept stable, avoiding amplitude drift in the output signal of the secondary-side photosensitive device caused by current fluctuations, thereby improving signal transmission consistency.

[0025] Optionally, in the above technical solution, the second primary interlock circuit further includes: a fourth resistor, the first end of which is connected to the second signal source, and the second end of which is connected to the positive terminal of the second photodiode.

[0026] In this scheme, the fourth resistor is connected in series as a current-limiting resistor between the second signal source and the positive terminal of the second photodiode. This limits the driving current flowing through the second photodiode, preventing overcurrent damage to the photodiode due to excessively high input signal voltage or transient impacts. By limiting the driving current of the photodiode, the luminous intensity on the primary side of the optocoupler is kept stable, avoiding amplitude drift of the output signal of the secondary-side photosensitive device due to current fluctuations, thereby improving signal transmission consistency.

[0027] An embodiment of the second aspect of this application provides a driving component, which includes at least one driving chip and the driving signal interlock module of the first aspect; the input terminal of the driving chip is connected to the sixth and eighth pins of the six-channel inverter in the driving signal interlock module, and the driving signal output by the driving signal interlock module is transmitted to the driving chip through the sixth and eighth pins.

[0028] The driver chip proposed in this application receives the interlocked and waveform-shaped drive signal transmitted from the drive signal interlock module through the sixth and eighth pins of the six-channel inverter, and directly drives the SiC / IGBT hybrid power device through the driver chip.

[0029] An embodiment of the third aspect of this application provides a hybrid power device, which includes: a hybrid unit and a driving component as described in the second aspect; the hybrid unit includes a silicon carbide field-effect transistor and an insulated gate bipolar transistor, the input terminal of the driving chip in the driving component is connected to a driving signal interlock module, and the output terminal of the driving chip in the driving component is connected to the hybrid unit.

[0030] In the hybrid power device proposed in this application, the hybrid unit includes SiC MOSFETs and IGBTs, which are connected in series or parallel. Through the coordinated operation of primary and secondary interlocking circuits, hardware-level interlocking protection and waveform shaping are performed on the input complementary PWM signals. The primary interlocking circuit utilizes the physical isolation characteristics of high-speed optocouplers to block signal competition risks and naturally generates the basic dead time through the optocoupler transmission delay. The secondary interlocking circuit filters noise and sharpens edges through the hysteresis characteristics of Schmitt inverters, forcing the dual-channel output drive signals to be strictly complementary. The interlocked and waveform-shaped drive signals are output from the sixth and eighth pins of the six-channel inverter to the first end of the drive component, i.e., the input end of the drive chip. The drive chip converts the logic signals into the high positive voltage drive required by the SiC MOSFETs and the deep negative voltage turn-off required by the IGBTs, directly driving the hybrid unit in the hybrid power device.

[0031] Additional aspects and advantages of this application will become apparent in the following description or may be learned by practice of this application. Attached Figure Description

[0032] Figure 1 A topology diagram of a drive signal interlock module according to an embodiment of this application is shown;

[0033] Figure 2 A topological schematic diagram of a first primary interlock circuit according to an embodiment of this application is shown;

[0034] Figure 3A topological schematic diagram of a second primary interlock circuit according to an embodiment of this application is shown;

[0035] Figure 4 A topological schematic diagram of a secondary interlock circuit according to an embodiment of this application is shown;

[0036] Figure 5 A schematic diagram of a drive signal waveform according to an embodiment of this application is shown;

[0037] Figure 6 A schematic block diagram of a hybrid power device according to an embodiment of this application is shown;

[0038] Figure 7 A schematic diagram of a Schmitt inverter according to an embodiment of this application is shown.

[0039] in, Figures 1 to 4 as well as Figure 6 and Figure 7 The correspondence between the reference numerals and component names in the attached drawings is as follows:

[0040] 1000: Drive signal interlock module; 1002: First primary interlock circuit; 1004: Second primary interlock circuit; 1006: Secondary interlock circuit; 100: First signal source; 200: Second signal source; 102: First high-speed optocoupler; 104: Second high-speed optocoupler; 106: Six-channel inverter; 2000: Hybrid power device; 2002: Hybrid unit; 2004: Drive component; 2006: Drive chip; 204: Silicon carbide field-effect transistor; 206: Insulated gate bipolar transistor; R1: First resistor; R2: Second resistor; C1: First capacitor; C2: Second capacitor; R3: Third resistor; Q1: First photodiode; Q2: First photosensitive diode; D1: First amplifier; Q3: First transistor; R4: Fourth resistor; Q4: Second photodiode; Q5: Second photosensitive diode; D2: Second amplifier; Q6: Second transistor; R5: Fifth resistor; R6: Sixth resistor; C3: Third capacitor; C4: Fourth capacitor; Q7: First diode; Q8: Second diode; 300: Schmitt trigger inverter. Detailed Implementation

[0041] To better understand the above-mentioned objectives, features, and advantages of the embodiments of this application, the embodiments of this application will be further described in detail below with reference to the accompanying drawings and specific implementation methods. It should be noted that, unless otherwise specified, the embodiments of this application and the features within them can be combined with each other.

[0042] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, embodiments of this application may also be implemented in other ways different from those described herein. Therefore, the scope of protection of this application is not limited to the specific embodiments disclosed below.

[0043] The following is in conjunction with the appendix Figures 1 to 7 The drive signal interlock module, drive component, and hybrid power device provided in this application will be described in detail through specific embodiments and application scenarios.

[0044] This application provides a drive signal interlock module, such as... Figure 1 As shown, the drive signal interlock module 1000 includes: a first primary interlock circuit 1002, which includes a first high-speed optocoupler 102, a first capacitor C1, and a first resistor R1. The first end of the first resistor R1 is connected to the power supply terminal (VDD) of the first high-speed optocoupler 102, and the second end of the first resistor R1 is connected to the first end of the first capacitor C1. The second end of the first capacitor C1 is connected to the ground terminal (GND) of the first high-speed optocoupler 102. The anode of the first high-speed optocoupler 102 is connected to a first signal source 100, and the cathode of the first high-speed optocoupler 102 is connected to a second signal source 200. The first signal source 100 and the second signal source 200 are complementary pulse width modulation signals. A second primary interlock circuit 1004 includes a second high-speed optocoupler 104, a second capacitor C2, and a second resistor R2. The first end of the second resistor R2 is connected to the power supply terminal (Voltage Drain) of the second high-speed optocoupler 104. The second resistor R2 (VDD) is connected to the first terminal of the second capacitor C2. The second terminal of the second capacitor C2 is connected to the ground terminal (GND) of the second high-speed optocoupler 104. The anode of the second high-speed optocoupler 104 is connected to the second signal source 200, and the cathode of the second high-speed optocoupler 104 is connected to the first signal source 100. The secondary interlock circuit 1006 includes a six-channel inverter 106. The first pin (pin 1) of the six-channel inverter 106 is connected to the first primary interlock circuit 1002, and the thirteenth pin (pin 13) of the six-channel inverter 106 is connected to the second primary interlock circuit 1004. The secondary interlock circuit 1006 determines the drive signal based on the first modulation signal transmitted by the first primary interlock circuit 1002 and the second modulation signal transmitted by the second primary interlock circuit 1004.

[0045] The drive signal interlock module 1000 proposed in this embodiment mainly includes a first primary interlock circuit 1002, a second primary interlock circuit 1004, and a secondary interlock circuit 1006. The output terminal of the first high-speed optocoupler 102 in the first primary interlock circuit 1002 is connected to the first pin of the six-channel inverter 106 in the secondary interlock circuit 1006, and the output terminal of the second high-speed optocoupler 104 in the second primary interlock circuit 1004 is connected to the thirteenth pin of the six-channel inverter 106 in the secondary interlock circuit 1006. Furthermore, the anode of the first high-speed optocoupler 102 is connected to the first signal source 100, and the cathode of the first high-speed optocoupler 102 is connected to the second signal source 200. The anode of the second high-speed optocoupler 104 is connected to the second signal source 200, and the cathode of the second high-speed optocoupler 104 is connected to the first signal source 100. The first signal source 100 and the second signal source 200 are complementary pulse width modulation (PWM) signals. Both the first modulation signal and the second modulation signal are PWM signals. When the PWM signal corresponding to the first signal source 100 is high, the PWM signal corresponding to the second signal source 200 is low; when the PWM signal corresponding to the first signal source 100 is low, the PWM signal corresponding to the second signal source 200 is high.

[0046] Understandably, the hardware-level interlock protection and signal waveform shaping of complementary PWM signals are achieved through the collaborative design of two primary interlock circuits and the secondary interlock circuit 1006. The primary interlock circuit blocks signal contention and shoot-through short circuits at the source through hardware isolation and dynamic interlocking of high-speed optocouplers; the secondary interlock circuit achieves signal purification, level adaptation, and complementary output through six-channel inverters 106 and logic interlocking, thereby improving the accuracy and reliability of the hybrid PWM and ensuring that the drive signal operates strictly according to the set dead time.

[0047] Specifically, the first capacitor C1 and the second capacitor C2 are filter capacitors. They are connected in parallel between the power supply terminal and ground of the high-speed optocoupler. These capacitors filter out high-frequency noise on the power lines of the first high-speed optocoupler 102 and the second high-speed optocoupler 104, ensuring stable operating voltages for both. During rapid switching of the primary side of the high-speed optocoupler, the first and second capacitors absorb voltage fluctuations caused by sudden current changes, thereby eliminating output signal jitter and transient interference from power supply disturbances. The first resistor R1 and the second resistor R2 are pull-up resistors. They are connected in parallel between the output terminals of the first high-speed optocoupler 102 and the second high-speed optocoupler 104 and the power supply. When the high-speed optocoupler is not conducting, the pull-up resistors pull the output drive signal to a high level, ensuring the accuracy of the drive signal output logic.

[0048] The primary interlock circuit utilizes the physical characteristics of high-speed optocouplers to achieve real-time interlocking of complementary PWM signals (i.e., the first signal source 100 and the second signal source 200). When the input signal is abnormal, i.e., when the first signal source 100 and the second signal source 200 are simultaneously set to a high level, the primary side of the high-speed optocoupler cannot conduct due to the lack of voltage difference, and the secondary side of the optocoupler remains at a high level, blocking the transmission of the drive signal. This hardware-level protection does not rely on software or fixed delay logic. It dynamically adapts to the high-speed switching requirements of the SiC MOSFET through the switching delay of the high-speed optocoupler, thereby eliminating the risk of bridge arm shoot-through short circuit caused by signal competition between the high-speed SiC MOSFET and the low-speed IGBT. The first high-speed optocoupler 102 and the second high-speed optocoupler 104 electrically isolate the control side from the power side, blocking common-mode interference. By reducing the transmission delay through the first high-speed optocoupler 102 and the second high-speed optocoupler 104, a basic dead time is introduced into the drive signal transmission path to cover the hardware switching timing differences of the SiC / IGBT hybrid power device 2000, ensuring that the drive signals of the two are strictly complementary, improving the accuracy of the drive signal of the hybrid power device 2000, and keeping the dead time of the drive signal consistent with the value set by the software.

[0049] Specifically, the secondary interlock circuit 1006 uses a six-channel inverter 106 to perform multi-stage shaping on the drive signals output by the two high-speed optocouplers. The hysteresis characteristic of the six-channel inverter 106 is used to convert the slowly changing edge or noisy signal output by the high-speed optocouplers into a regular square wave, thereby eliminating signal waveform distortion caused by signal jitter or signal noise.

[0050] For example, when the drive signal output by the high-speed optocoupler experiences slight voltage fluctuations due to temperature drift or aging of the high-speed optocoupler, the six-channel inverter 106 can stabilize the output drive signal through multi-stage shaping, ensuring clear edges of the drive signal waveform and avoiding false triggering of the SiC / IGBT hybrid power device 2000 caused by drive signal distortion.

[0051] For example, when the first signal source 100 (ViA) is set to a high level and the second signal source 200 (ViB) is set to a low level, the primary side of the first high-speed optocoupler 102 is turned on, the secondary side of the optocoupler is turned on, and the output terminal of the first high-speed optocoupler 102 is at a low level; the primary side of the second high-speed optocoupler 104 is not turned on, the high-speed optocoupler is not working, and the output terminal of the second high-speed optocoupler 104 is at a high level. That is, when the first signal source 100 is set to a high level and the second signal source 200 is set to a low level, the first high-speed optocoupler 102 works, and the second high-speed optocoupler 104 does not work; when the first signal source 100 is set to a low level and the second signal source 200 is set to a high level, the first high-speed optocoupler 102 does not work, and the second high-speed optocoupler 104 works.

[0052] In one embodiment, alternatively, such as Figure 4 As shown, in the six-channel inverter 106, the first pin (pin 1), the second pin (pin 2), the third pin (pin 3), the fourth pin (pin 4), the fifth pin (pin 5), the sixth pin (pin 6), the eighth pin (pin 8), the ninth pin (pin 9), the tenth pin (pin 10), the eleventh pin (pin 11), and the twelfth pin (pin 12) and the thirteenth pin (pin 13) each form an input / output channel; the first primary interlock circuit 1002 is connected to the first pin through the output terminal of the first high-speed optocoupler 102, and the second primary interlock circuit 10... 04 is connected to the output terminal and the thirteenth pin of the second high-speed optocoupler 104; the secondary interlock circuit 1006 outputs the first modulation signal transmitted by the first primary interlock circuit 1002 through the sixth pin (pin 6) of the six-channel inverter 106, and outputs the second modulation signal transmitted by the second primary interlock circuit 1004 through the eighth pin (pin 8) of the six-channel inverter 106; the second and third pins are directly connected, and the eleventh and twelfth pins are directly connected; the seventh pin (pin 7) is grounded, and the fourteenth pin (pin 14) is connected to the power supply; wherein, the input and output channels include Schmitt inverters.

[0053] In this embodiment, the first pin of the six-channel inverter 106 is connected to the output of the first high-speed optocoupler 102, and the thirteenth pin of the six-channel inverter 106 is connected to the output of the second high-speed optocoupler 104. The drive signals transmitted by the first high-speed optocoupler 102 and the second high-speed optocoupler are transmitted to the six-channel inverter 106. In the six-channel inverter 106, a multi-stage signal processing link is formed by a Schmitt trigger inverter, and the first modulation signal is output through the sixth pin (pin 6) and the second modulation signal is output through the eighth pin (pin 8). Based on the signal complementarity and dead time correction completed by the first high-speed optocoupler 102 and the second high-speed optocoupler 104, the signal edges are further sharpened. Secondary hardware interlocking is achieved through logical path cross-coupling. When a signal in one path is abnormal, the direct path triggers the reverse channel to forcibly pull down the complementary signal, ensuring that the drive signals are strictly mutually exclusive, thus eliminating the risk of bridge arm shoot-through in the SiC / IGBT hybrid power device 2000 from a physical level.

[0054] Furthermore, by utilizing the hysteresis characteristics of the Schmitt inverters in the input and output channels, the switching threshold is dynamically adjusted to meet the timing differences between the high-speed switching of SiC MOSFETs and IGBTs, thus avoiding voltage overshoot. Moreover, the Schmitt inverters have dual threshold voltages. When the input signal is higher than the first threshold voltage, the corresponding drive signal output from the input and output channels jumps to a low level; when the input signal is lower than the second threshold voltage, the corresponding drive signal output from the input and output channels jumps to a high level. Through these dual threshold voltages, the slowly rising or falling drive signals output from the first high-speed optocoupler 102 and the second high-speed optocoupler 104 are converted into steep, regular square waves, thereby ensuring clear edges on the drive signals.

[0055] Specifically, the principle of the Schmitt inverter is common technical knowledge known to those skilled in the art, and the schematic diagram of the Schmitt inverter 300 is as follows: Figure 7 As shown, A represents any input pin, Y represents any output pin, the square represents the reverse hysteresis curve, which suppresses noise through hysteresis characteristics, the circle represents logic inversion, and the triangle represents a buffer. In an input / output channel, the drive signal is inverted and hysteresis by a Schmitt inverter 300, and then inverted twice by a buffer to ensure that the final output drive signal is inverted from the input drive signal.

[0056] For example, when the first high-speed optocoupler 102 is working, the drive signal at the output terminal of the first high-speed optocoupler 102 is low. Since the first pin and the second pin are an input / output channel, and the channel includes a Schmitt inverter 300, the second pin inverts the low level of the first pin to a high level through the Schmitt inverter 300. Furthermore, since the second pin and the third pin are directly connected, the drive signals of the second pin and the third pin are the same, that is, the drive signal corresponding to the third pin is high. Similarly, the drive signal corresponding to the fourth pin is low, the drive signal corresponding to the fifth pin is high, and the drive signal corresponding to the sixth pin is low. The low-level drive signal is transmitted to the driver chip 2006 through the sixth pin.

[0057] When the second high-speed optocoupler 104 is working, the drive signal at its output is low. Since pins 12 and 13 form an input / output channel, and this channel includes a Schmitt inverter 300, pin 12 inverts the low level of pin 13 to a high level via the Schmitt inverter 300. Because pins 12 and 11 are directly connected, their drive signals are the same, meaning pin 11's drive signal is high. Similarly, pin 10's drive signal is low, pin 9's drive signal is high, and pin 8's drive signal is low. The low-level drive signal is then transmitted to the driver chip 2006 via pin 8.

[0058] In one embodiment, alternatively, such as Figure 2 As shown, the first high-speed optocoupler 102 includes: a first photodiode Q1, the anode of the first photodiode Q1 is connected to the first signal source 100, and the cathode of the first photodiode Q1 is connected to the second signal source 200; a first photodiode Q2 and a first amplifier D1, which are connected in parallel; a first transistor Q3, the base of the first transistor Q3 is connected to the first terminal of the first resistor R1 through the first amplifier D1, the collector of the first transistor Q3 is connected to the first pin of the six-channel inverter 106, and the emitter of the first transistor Q3 is connected to the second terminal of the first capacitor C1.

[0059] In this embodiment, the first high-speed optocoupler 102 integrates a first photodiode Q1, a first photodiode Q2, a first amplifier D1, and a first transistor Q3, forming a photo-to-electric conversion and signal amplification link. The positive terminal of the first photodiode Q1 is connected to the first signal source 100, and the negative terminal is connected to the second signal source 200. When the first signal source 100 is at a high level, the second signal source 200 is at a low level, the first photodiode Q1 conducts and emits light, and the light signal is received by the first photodiode Q2 and converted into a current signal. The first amplifier D1 is connected in parallel with the first photodiode Q2, amplifying the current signal and driving the base of the first transistor Q3, controlling the first transistor Q3 to conduct, so that the collector outputs a low-level signal. The first capacitor C1 is connected in parallel between the emitter of the first transistor Q3 and ground to filter out high-frequency switching noise and ensure the stability of the output signal. Furthermore, the first resistor R1 is connected in series as a pull-up resistor between the output terminal of the first amplifier D1 and the base of the first transistor Q3 to limit the base current.

[0060] Understandably, the isolation design of the first high-speed optocoupler 102 blocks loop interference, and the first amplifier D1 and the first transistor Q3 enhance the signal driving capability. The first capacitor C1 acts as a filter capacitor to suppress noise. The driving signal output by the first high-speed optocoupler 102 is transmitted to the six-channel inverter 106. The Schmitt inverter 300 solves the signal jitter problem based on hysteresis characteristics and edge sharpening, ensuring the integrity of the high-speed signal and providing a highly reliable driving signal for the SiC / IGBT hybrid power device 2000.

[0061] In one embodiment, alternatively, such as Figure 3As shown, the second high-speed optocoupler 104 includes: a second photodiode Q4, the positive terminal of which is connected to the second signal source 200, and the negative terminal of which is connected to the first signal source 100; a second photodiode Q5 and a second amplifier D2, which are connected in parallel; and a second transistor Q6, the base of which is connected to the first terminal of the second resistor R2 through the second amplifier D2, the collector of which is connected to the thirteenth pin of the six-channel inverter 106, and the emitter of which is connected to the second terminal of the second capacitor C2.

[0062] In this embodiment, the second high-speed optocoupler 104 integrates a second photodiode Q4, a second photodiode Q5, a second amplifier D2, and a second transistor Q6, forming a photoelectric conversion and signal amplification link. The positive terminal of the second photodiode Q4 is connected to the second signal source 200, and the negative terminal is connected to the first signal source 100. When the second signal source 200 is at a high level, the first signal source 100 is at a low level, the second photodiode Q4 conducts and emits light, and the light signal is received by the second photodiode Q5 and converted into a current signal. The second amplifier D2 is connected in parallel with the second photodiode Q5, amplifying the current signal and driving the base of the second transistor Q6, controlling the second transistor Q6 to conduct, so that the collector outputs a low-level signal. The second capacitor C2 is connected in parallel between the emitter of the second transistor Q6 and ground to filter out high-frequency switching noise and ensure the stability of the output signal. Furthermore, the second resistor R2 is connected in series as a pull-up resistor between the output terminal of the second amplifier D2 and the base of the second transistor Q6 to limit the base current.

[0063] Understandably, the isolation design of the second high-speed optocoupler 104 blocks loop interference, and the signal driving capability is enhanced by the second amplifier D2 and the second transistor Q6. The second capacitor C2 acts as a filter capacitor to suppress noise. The driving signal output by the second high-speed optocoupler 104 is transmitted to the six-channel inverter 106. The Schmitt inverter 300 solves the signal jitter problem based on hysteresis characteristics and edge sharpening, ensuring the integrity of the high-speed signal and providing a highly reliable driving signal for the SiC / IGBT hybrid power device 2000.

[0064] Furthermore, the anode of the first high-speed optocoupler 102 is connected to the first signal source 100, and the cathode of the first high-speed optocoupler 102 is connected to the second signal source 200. The anode of the second high-speed optocoupler 104 is connected to the second signal source 200, and the cathode of the second high-speed optocoupler 104 is connected to the first signal source 100. The first signal source 100 and the second signal source 200 are complementary PWM signals, that is, when the PWM signal corresponding to the first signal source 100 is high, the PWM signal corresponding to the second signal source 200 is low; when the PWM signal corresponding to the first signal source 100 is low, the PWM signal corresponding to the second signal source 200 is high. The first high-speed optocoupler 102 and the second high-speed optocoupler 104 adopt a cross-complementary connection design. The conduction states of the first high-speed optocoupler 102 and the second high-speed optocoupler 104 are completely mutually exclusive. This cross-complementary design forces the complementary logic through hardware physical characteristics. Even if the input PWM drive signals briefly overlap due to software faults or noise interference, such as the first signal source 100 and the second signal source 200 being set to high level at the same time, the primary side of the optocoupler will not conduct due to the lack of voltage difference. The secondary side output will be forced high by the pull-up resistor, blocking the transmission of abnormal signals to the secondary interlock circuit 1006 from the source, thereby completely eliminating the risk of shoot-through short circuit of the SiC / IGBT bridge arm.

[0065] In one embodiment, alternatively, such as Figure 4 As shown, the secondary interlock circuit 1006 includes: a first diode Q7, the anode of the first diode Q7 is connected to the third pin of the six-channel inverter 106, and the cathode of the first diode Q7 is connected to the ninth pin of the six-channel inverter 106; a second diode Q8, the anode of the second diode Q8 is connected to the twelfth pin of the six-channel inverter 106, and the cathode of the second diode Q8 is connected to the fifth pin of the six-channel inverter 106; a third capacitor C3, the first terminal of the third capacitor C3 is connected to the power supply, and the second terminal of the third capacitor C3 is connected to the cathode of the second diode Q8; and a fourth capacitor C4, the first terminal of the fourth capacitor C4 is connected to the power supply, and the second terminal of the fourth capacitor C4 is connected to the cathode of the first diode Q7.

[0066] In this embodiment, the anode of the first diode Q7 is connected to the third pin of the six-channel inverter 106, and the cathode of the first diode Q7 is connected to the ninth pin of the six-channel inverter 106. The anode of the second diode Q8 is connected to the twelfth pin of the six-channel inverter 106, and the cathode of the second diode Q8 is connected to the fifth pin of the six-channel inverter 106. When the first high-speed optocoupler 102 outputs a high-level drive signal, the first diode Q7 is turned on, transmitting the high-level drive signal to the channel input terminal corresponding to the ninth pin, forcing the channel corresponding to the ninth pin to output a low level, ensuring that the drive signal corresponding to the third pin and the drive signal corresponding to the twelfth pin are strictly complementary. Similarly, when the second diode Q8 is turned on, it forces the channel corresponding to the sixth pin to output a low-level drive signal, forming a bidirectional hardware interlock.

[0067] Furthermore, both the third capacitor C3 and the fourth capacitor C4 are filter capacitors. The third capacitor C3 is connected in parallel between the negative terminal of the second diode Q8 and the power supply, and the fourth capacitor C4 is connected in parallel between the negative terminal of the first diode Q7 and the power supply. The third capacitor C3 and the fourth capacitor C4 stabilize the logic node voltage by absorbing high-frequency noise, preventing false triggering caused by power supply fluctuations or coupling interference.

[0068] For example, when the channel drive signal corresponding to the third pin of the six-channel inverter 106 changes and triggers the diode to conduct, the third capacitor C3 can be charged and discharged quickly to suppress the voltage spike of the ninth pin and ensure the purity of the output pin level of the six-channel inverter 106.

[0069] In one embodiment, alternatively, such as Figure 4 As shown, the secondary interlock circuit 1006 further includes: a fifth resistor R5, the first end of which is connected to the second end of the third capacitor C3, and the second end of which is connected to the fourth pin of the six-channel inverter 106; and a sixth resistor R6, the first end of which is connected to the second end of the fourth capacitor C4, and the second end of which is connected to the tenth pin of the six-channel inverter 106.

[0070] In this embodiment, the fifth resistor R5 and the sixth resistor R6 are connected in series as current-limiting resistors between the third capacitor C3 and the fourth pin of the six-channel inverter 106, and between the fourth capacitor C4 and the tenth pin of the six-channel inverter 106, respectively. One end of the fifth resistor R5 is connected to the second terminal of the third capacitor C3, serving as logic node A, and is connected to the negative terminal of the second diode Q8; the other end is connected to the fourth pin of the six-channel inverter 106. One end of the sixth resistor R6 is connected to the second terminal of the fourth capacitor C4, serving as logic node B, and is connected to the negative terminal of the first diode Q7; the other end is connected to the tenth pin of the six-channel inverter 106. When logic nodes A and B experience instantaneous current spikes due to diode conduction or external interference, the current-limiting resistors limit the current to a safe range, preventing overcurrent damage to the six-channel inverter 106.

[0071] Furthermore, the fifth resistor R5, the sixth resistor R6, the third capacitor C3, and the fourth capacitor C4 work together to filter out high-frequency noise, suppress voltage fluctuations between logic nodes, ensure the stability of the input level of the Schmitt inverter 300, avoid inverter misjudgment due to noise, and thus ensure the reliability and timing accuracy of the drive signal in high-voltage, high-frequency, and strong noise environments.

[0072] In one embodiment, alternatively, such as Figure 2 As shown, the first primary interlock circuit 1002 further includes: a third resistor R3, the first end of the third resistor R3 being connected to the first signal source 100, and the second end of the third resistor R3 being connected to the positive terminal of the first photodiode Q1.

[0073] In this embodiment, the third resistor R3 is connected in series as a current-limiting resistor between the first signal source 100 and the positive terminal of the first photodiode Q1, limiting the driving current flowing through the first photodiode Q1 and preventing overcurrent damage to the photodiode due to excessively high input signal voltage or transient impacts. By limiting the driving current of the photodiode, the light emission intensity on the primary side of the optocoupler is kept stable, avoiding amplitude drift of the output signal of the secondary side photosensitive device due to current fluctuations, thereby improving signal transmission consistency.

[0074] Furthermore, under abnormal system conditions, such as when the first signal source 100 and the second signal source 200 are simultaneously high, the third resistor R3 reduces the power consumption of the primary side of the optocoupler by limiting the current, avoids the optocoupler from overheating and failure, enables the secondary interlock circuit to respond quickly and cut off the drive signal, and eliminates the risk of shoot-through short circuit in the SiC / IGBT bridge arm.

[0075] In one embodiment, alternatively, such as Figure 3 As shown, the second primary interlock circuit 1004 further includes: a fourth resistor R4, the first end of the fourth resistor R4 being connected to the second signal source 200, and the second end of the fourth resistor R4 being connected to the positive terminal of the second photodiode Q4.

[0076] In this embodiment, the fourth resistor R4 is connected in series as a current-limiting resistor between the second signal source 200 and the positive terminal of the second photodiode Q4, limiting the driving current flowing through the second photodiode Q4 and preventing overcurrent damage to the photodiode due to excessively high input signal voltage or transient impacts. By limiting the driving current of the photodiode, the light emission intensity on the primary side of the optocoupler is kept stable, avoiding amplitude drift of the output signal of the secondary side photosensitive device due to current fluctuations, thereby improving signal transmission consistency.

[0077] like Figure 6 As shown, an embodiment of this application provides a driving component 2004, which includes at least one driving chip 2006 and a driving signal interlock module 1000 from the first aspect; the input terminal of the driving chip 2006 is connected to the sixth and eighth pins of the six-channel inverter 106 in the driving signal interlock module 1000, and the driving signal output by the driving signal interlock module 1000 is transmitted to the driving chip 2006 through the sixth and eighth pins.

[0078] The driver chip 2006 proposed in this application receives the interlocked and waveform-shaped drive signal transmitted from the drive signal interlock module 1000 through the sixth and eighth pins of the six-channel inverter 106, and directly drives the SiC / IGBT hybrid power device 2000 through the driver chip 2006.

[0079] like Figure 6As shown, an embodiment of this application provides a hybrid power device 2000, which includes a hybrid unit 2002 and a driving component 2004 as described in the second aspect. The hybrid unit 2002 includes a silicon carbide field-effect transistor 204 and an insulated gate bipolar transistor 206. The input terminal of the driving chip 2006 in the driving component 2004 is connected to a driving signal interlock module 1000, and the output terminal of the driving chip 2006 in the driving component 2004 is connected to the hybrid unit 2002.

[0080] In the hybrid power device 2000 proposed in this application, the hybrid unit 2002 includes SiC MOSFETs and IGBTs, which are connected in series or parallel. Through the coordinated operation of the primary interlock circuit and the secondary interlock circuit 1006, the input complementary PWM signals are subjected to hardware-level interlock protection and waveform shaping. The primary interlock circuit utilizes the physical isolation characteristics of the high-speed optocoupler to block signal competition risks and naturally generates the basic dead time through the optocoupler transmission delay. The secondary interlock circuit 1006 filters out noise and sharpens edges through the hysteresis characteristics of the Schmitt inverter 300, forcing the dual-channel output drive signals to be strictly complementary. The interlocked and waveform-shaped drive signals are output from the sixth and eighth pins of the six-channel inverter 106 to the first terminal of the drive component 2004, i.e., the input terminal of the drive chip 2006. The drive chip 2006 converts the logic signal into a high positive voltage drive required by the SiC MOSFET and a deep negative voltage turn-off required by the IGBT, directly driving the hybrid unit 2002 in the hybrid power device 2000 to work.

[0081] In one specific embodiment, the primary interlock circuit consists of current-limiting resistors (third resistor R3 and fourth resistor R4), high-speed optocouplers (first high-speed optocoupler 102 and second high-speed optocoupler 104), and pull-up resistors (first resistor R1 and second resistor R2). The optocoupler inputs ViA (first signal source 100) and ViB (second signal source 200) are complementary PWM signals, which should not be high at the same time in principle. If they are high at the same time, it will cause the complementary bridge arm of the hybrid module to shoot through. The first high-speed optocoupler 102 and the second high-speed optocoupler 104 are OR-M611 type optocouplers.

[0082] Taking the first high-speed optocoupler 102 as an example:

[0083] When ViA is high (3.3V) and ViB is low (0V), the primary diode of the optocoupler is turned on, and the recommended primary current is 5mA. The calculated current flowing through the primary diode is 3.3V / 680R=4.8mA, which meets the requirements. The secondary side of the optocoupler is an open-drain output. The output IN- (output terminal of the first high-speed optocoupler 102) is in a pull-up state when the primary side of the optocoupler is not turned on, that is, the first pin and the thirteenth pin are 5V high level. When ViA is high (3.3V) and ViB is low (0V), the primary diode of the optocoupler is turned on, the secondary side of the optocoupler is turned on, the transistor is turned on, and the output terminal of the first high-speed optocoupler 102 is grounded, which is a low level.

[0084] When ViA is low (0V) and ViB is high (3.3V), the primary diode of the optocoupler is not conducting, the optocoupler is not working, and the output of the first high-speed optocoupler 102 is 5V high.

[0085] When ViA is low (0V) and ViB is low (0V), the primary diode of the optocoupler is not conducting, the optocoupler is not working, and the output of the first high-speed optocoupler 102 is 5V high.

[0086] When ViA is high (3.3V) and ViB is high (3.3V), the primary diode of the optocoupler is not conducting, the optocoupler is not working, and the output of the first high-speed optocoupler 102 is 5V high.

[0087] Therefore, the optocoupler only works when ViA is high (3.3V) and ViB is low (0V).

[0088] The secondary interlocking and shaping circuit mainly consists of switching diodes, resistors, and inverters. The 74HC14MT / MR is a 6-channel inverter that can transform slowly changing input signals into rapidly changing output signals. Its internal principle is as follows... Figure 4 As shown. 74HC14MT / MR device, channels 1 / 2, 3 / 4, 5 / 6, 8 / 9, 10 / 11, and 12 / 13 are input / output channels.

[0089] When the signal at pin 1 is low, pin 2 of the inverter is high. Pins 2 and 3 are directly connected, so pin 3 is high, pin 4 is low, pin 5 is high, and pin 6 is low. The IN1 signal from pin 6 is input to driver chip 2006. This allows the level of the drive signal at pin 6 to match the state when ViA is high (3.3V) and ViB is low (0V). Simultaneously, the high-level drive signal at pin 3 passes through diode 1N4148 (first diode Q7) to pin 9 of the inverter, while pin 8 is low, ensuring an inversion with the level at pin 6. When the signal at pin 13 is low, pin 12 of the inverter is high. Pins 12 and 11 are directly connected, so pin 11 is high, pin 10 is low, pin 9 is high, and pin 8 is low. The drive signal at pin 8 is input to driver chip 2006. This allows the level of pin 8 to match the state when ViB is high (3.3V) and ViA is low (0V). Meanwhile, the high level of pin 12 goes to pin 5 of the inverter through diode 1N4148 (second diode Q8), and the drive signal of pin 6 is low, ensuring that it is inversely related to the level of pin 8.

[0090] The complementary waveform of the driving signal is shown below. Figure 5 As shown, under the effects of primary-secondary complementarity and signal waveform shaping, the SiC gate waveform and IGBT gate waveform are normal. They are gate waveforms with rapidly changing edges after waveform shaping, and the dead time is consistent with the software setting. That is, there is no intersection between the SiC gate waveform and the IGBT gate waveform in the figure, and there is a time interval between the SiC gate waveform and the IGBT gate waveform on the time axis. There is no shoot-through risk between the SiC MOSFET and the IGBT.

[0091] Signal shaping utilizes a Schmitt trigger with a comparison-only function. The Schmitt trigger's signal shaping capability stems from its hysteresis characteristic, which effectively suppresses noise, sharpens edges, and converts non-ideal inputs into regular square waves. This characteristic makes it a key component in digital circuits, sensor interfaces, and communication systems.

[0092] In this application, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term "multiple" refers to two or more unless otherwise expressly defined. The terms "install," "connect," "link," and "fix" should be interpreted broadly. For example, "connect" can mean a fixed connection, a detachable connection, or an integral connection; "link" can mean a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0093] In the description of this application, it should be understood that the terms "upper", "lower", "left", "right", "front", "rear", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0094] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0095] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A drive signal interlock module, characterized in that, include: The first primary interlock circuit includes a first high-speed optocoupler, a first capacitor, and a first resistor. The first end of the first resistor is connected to the power supply terminal of the first high-speed optocoupler, the second end of the first resistor is connected to the first end of the first capacitor, the second end of the first capacitor is connected to the ground terminal of the first high-speed optocoupler, the anode of the first high-speed optocoupler is connected to a first signal source, and the cathode of the first high-speed optocoupler is connected to a second signal source. The first signal source and the second signal source are complementary pulse width modulation signals. The second primary interlock circuit includes a second high-speed optocoupler, a second capacitor, and a second resistor. The first end of the second resistor is connected to the power supply terminal of the second high-speed optocoupler, the second end of the second resistor is connected to the first end of the second capacitor, the second end of the second capacitor is connected to the ground terminal of the second high-speed optocoupler, the anode of the second high-speed optocoupler is connected to the second signal source, and the cathode of the second high-speed optocoupler is connected to the first signal source. The secondary interlock circuit includes a six-channel inverter. The first pin of the six-channel inverter is connected to the first primary interlock circuit, and the thirteenth pin of the six-channel inverter is connected to the second primary interlock circuit. The secondary interlock circuit determines the drive signal based on the first modulation signal transmitted by the first primary interlock circuit and the second modulation signal transmitted by the second primary interlock circuit.

2. The drive signal interlock module according to claim 1, characterized in that, In the six-channel inverter, the first and second pins, the third and fourth pins, the fifth and sixth pins, the eighth and ninth pins, the tenth and eleventh pins, and the twelfth and thirteenth pins each form an input / output channel; The first primary interlock circuit is connected to the first pin through the output terminal of the first high-speed optocoupler, and the second primary interlock circuit is connected to the thirteenth pin through the output terminal of the second high-speed optocoupler. The secondary interlock circuit outputs the first modulation signal transmitted by the first primary interlock circuit through the sixth pin of the six-channel inverter, and outputs the second modulation signal transmitted by the second primary interlock circuit through the eighth pin of the six-channel inverter; The second pin and the third pin are directly connected, and the eleventh pin and the twelfth pin are directly connected; Pin 7 is grounded, and pin 14 is connected to the power supply. The input / output channels include Schmitt inverters.

3. The drive signal interlock module according to claim 1, characterized in that, The first high-speed optocoupler includes: A first photodiode, the positive terminal of which is connected to the first signal source, and the negative terminal of which is connected to the second signal source; A first photodiode and a first amplifier, wherein the first photodiode and the first amplifier are connected in parallel; The base of the first transistor is connected to the first terminal of the first resistor through the first amplifier, the collector of the first transistor is connected to the first pin of the six-channel inverter, and the emitter of the first transistor is connected to the second terminal of the first capacitor.

4. The drive signal interlock module according to claim 1, characterized in that, The second high-speed optocoupler includes: A second photodiode, the positive terminal of which is connected to the second signal source, and the negative terminal of which is connected to the first signal source; A second photodiode and a second amplifier are connected in parallel. The base of the second transistor is connected to the first terminal of the second resistor through the second amplifier, the collector of the second transistor is connected to the thirteenth pin of the six-channel inverter, and the emitter of the second transistor is connected to the second terminal of the second capacitor.

5. The drive signal interlock module according to claim 1, characterized in that, The secondary interlock circuit includes: The first diode has its anode connected to the third pin of the six-channel inverter, and its cathode connected to the ninth pin of the six-channel inverter. The second diode has its anode connected to the twelfth pin of the six-channel inverter and its cathode connected to the fifth pin of the six-channel inverter. The third capacitor has its first terminal connected to a power source and its second terminal connected to the negative terminal of the second diode. The fourth capacitor has its first terminal connected to a power source and its second terminal connected to the negative terminal of the first diode.

6. The drive signal interlock module according to claim 5, characterized in that, The secondary interlock circuit also includes: The fifth resistor has its first end connected to the second end of the third capacitor, and its second end connected to the fourth pin of the six-channel inverter. The sixth resistor has its first end connected to the second end of the fourth capacitor, and its second end connected to the tenth pin of the six-channel inverter.

7. The drive signal interlock module according to claim 3, characterized in that, The first primary interlock circuit further includes: A third resistor, the first end of which is connected to a first signal source, and the second end of which is connected to the positive terminal of the first photodiode.

8. The drive signal interlock module according to claim 4, characterized in that, The second primary interlock circuit also includes: The fourth resistor has its first end connected to the second signal source and its second end connected to the positive terminal of the second photodiode.

9. A driving component, characterized in that, include: At least one driver chip and a drive signal interlock module as described in any one of claims 1 to 8; The input terminal of the driver chip is connected to the sixth and eighth pins of the six-channel inverter in the drive signal interlock module. The drive signal output by the drive signal interlock module is transmitted to the driver chip through the sixth and eighth pins.

10. A hybrid power device, characterized in that, include: The hybrid unit and the drive assembly as described in claim 9; The hybrid unit includes a silicon carbide field-effect transistor and an insulated-gate bipolar transistor; The input terminal of the driver chip in the driving assembly is connected to the driving signal interlock module, and the output terminal of the driver chip in the driving assembly is connected to the mixing unit.

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