A test circuit board for a CTP screen
By adding an LED indicator circuit module to the CTP screen test circuit board and using a PNP transistor to detect the short circuit between VDD and IOVDD, the problems of large detection blind zone and poor compatibility in the existing technology are solved, realizing hardware-level visual feedback and defective product interception.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- DONG GUAN MING WAI DIAN ZI KE JI YOU XIAN GONG SI
- Filing Date
- 2025-07-29
- Publication Date
- 2026-07-17
Smart Images

Figure CN224518906U_ABST
Abstract
Claims
1. A test circuit board for CTP screens, comprising an adapter board, a connecting board, and a control circuit pin connector, characterized in that: An LED indicator circuit module is added, which is connected between the VDD and IOVDD detection points on the test board; The LED indicator circuit module includes a PNP transistor, an LED, resistors R1, R2, and R3; The emitter of the PNP transistor is electrically connected to the VDD detection point via resistor R3; The base of the PNP transistor is electrically connected to the IOVDD detection point via resistor R1. The collector of the PNP transistor is electrically connected to the positive terminal of the LED, and the negative terminal of the LED is grounded through resistor R2.
2. The test circuit board of claim 1, wherein, The resistance of resistor R1 is 500 to 2000 Ω.
3. The test circuit board of claim 1, wherein, The resistance of resistor R2 is 500 to 2000 Ω.
4. The test circuit board of claim 1, wherein, The resistance of resistor R3 is 0 to 500 Ω.
5. The test circuit board of claim 1, wherein, The circuit board is suitable for CTP modules of ST1633I or ST1624 control chips, including models GTF240400-0280C8, GTF7201280-0500C7, GTF480640-0240G3, GTF480640-0240H3, GTF240320-0240D5 and GTF272451-0340A0.
6. The test circuit board of claim 1, wherein, In the FPC routing layout of the adapter board, the VDD and IOVDD pins are set as non-adjacent pins.
7. The test circuit board of claim 1, wherein, In the FPC routing layout of the adapter board, the VDD and IOVDD pins are spaced more than 1mm apart.