Semiconductor structure
By designing a simple loop of trench-conductive layer-electrode layer in the semiconductor structure, the problem of not being able to evaluate GaN/ITO ohmic contacts in the early stage of Micro LED manufacturing was solved, enabling rapid and accurate detection and adjustment, reducing costs and risks, and improving production efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- STAR KEY SEMICONDUCTOR (WUHAN) CO LTD
- Filing Date
- 2025-07-30
- Publication Date
- 2026-07-21
AI Technical Summary
In the Micro LED manufacturing process, existing technologies require the completion of the entire process before testing the ohmic contact between GaN and ITO. When contact degradation is discovered, it cannot be adjusted, leading to the scrapping of the entire batch of products, resulting in high costs and risks.
A semiconductor structure is provided, including a substrate, a buffer layer, an epitaxial layer, a passivation layer, a conductive layer, and an electrode layer. By creating external trenches on the passivation layer, the ohmic performance of GaN/ITO can be quickly evaluated before the light-emitting structure is formed using a simple trench-conductive layer-electrode layer loop. If poor contact is found, the conductive material formulation can be adjusted.
It significantly shortens the process cycle, reduces trial and error costs and reliability risks, improves production efficiency and product yield, enables early identification of potential problems, and avoids batch scrapping.
Smart Images
Figure CN224538659U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and more particularly to a semiconductor structure. Background Technology
[0002] In Micro LED manufacturing, GaN and ITO require a low-resistance ohmic contact to achieve linear IV characteristics and precise brightness control. Current methods require completing the entire process—including chip epitaxy, mesa formation, electrodes, and passivation—before testing. If contact degradation is detected, it's impossible to retrospectively adjust the ITO formulation, resulting in the entire batch being scrapped. Therefore, a simplified testing structure is urgently needed to quickly assess the ohmic performance of GaN / ITO before the light-emitting structure is formed, thereby reducing cost and risk. Summary of the Invention
[0003] To address the above problems, this application provides a semiconductor structure, comprising:
[0004] Substrate;
[0005] Buffer layer; located on the substrate;
[0006] An epitaxial layer is located on the side of the buffer layer away from the substrate, and the material of the epitaxial layer is either N-type doped gallium nitride or P-type doped gallium nitride.
[0007] A passivation layer is located on the side of the epitaxial layer away from the substrate and has an external trench formed thereon; the external trench exposes at least a portion of the epitaxial layer.
[0008] A conductive layer is located on the passivation layer; the conductive layer is at least partially located within the external trench and is in contact with the epitaxial layer.
[0009] An electrode layer is located on the conductive layer, and the electrode layer is electrically connected to the epitaxial layer through the conductive layer.
[0010] In one embodiment, the orthographic projection of the electrode layer on the epitaxial layer at least partially overlaps with the orthographic projection of the conductive layer on the epitaxial layer.
[0011] In one embodiment, the external trench is annular, and the outline of the conductive layer located within the external trench is annular.
[0012] In one embodiment, the outline of the electrode layer is annular, and the orthographic projection of the electrode layer on the epitaxial layer falls entirely within the orthographic projection of the conductive layer on the epitaxial layer.
[0013] In one embodiment, the epitaxial layer includes a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked along the thickness direction; the first semiconductor layer is configured as N-type doped gallium nitride, and the second semiconductor layer is configured as P-type doped gallium nitride; wherein
[0014] The external trench exposes at least a portion of the second semiconductor layer, and the electrode layer is electrically connected to the second semiconductor layer through the conductive layer.
[0015] In one embodiment, the active layer includes a first sub-semiconductor layer and a second sub-semiconductor layer, which are alternately stacked; wherein,
[0016] The first sub-semiconductor layer material is selected from gallium nitride and indium gallium nitride, and the second sub-semiconductor layer material is selected from the other one of gallium nitride and indium gallium nitride.
[0017] In one embodiment, the epitaxial layer further includes an electron blocking layer and a cap layer. The electron blocking layer is located between the active layer and the second semiconductor layer to block electrons. The cap layer is located between the second semiconductor layer and the conductive layer to reduce contact resistance.
[0018] In one embodiment, the electron blocking layer is made of p-type doped aluminum gallium nitride; and / or
[0019] The cap layer can be configured as any one of indium gallium nitride, p-type doped gallium nitride, or indium tin oxide.
[0020] In one embodiment, the substrate is configured as any one of sapphire, silicon, silicon carbide, or gallium nitride; and / or
[0021] The conductive layer is made of any one of indium tin oxide, aluminum-doped zinc oxide, or gallium-doped zinc oxide; and / or
[0022] The electrode layer is made of aluminum; and / or
[0023] The passivation layer material can be either silicon oxide or aluminum oxide.
[0024] In one embodiment, the thickness of the conductive layer is greater than or equal to 80 nm and less than or equal to 300 nm.
[0025] The technical solutions provided by the embodiments of this application may include the following beneficial effects:
[0026] As described in the above embodiments, the semiconductor structure includes a substrate, a buffer layer, an epitaxial layer, a passivation layer, a conductive layer, and an electrode layer stacked sequentially. The epitaxial layer material is either N-type doped gallium nitride or P-type doped gallium nitride. An external trench is formed on the passivation layer, exposing at least a portion of the epitaxial layer. The conductive layer is located on the passivation layer, and at least a portion of the conductive layer is located within the external trench, contacting the epitaxial layer. The electrode layer is electrically connected to the epitaxial layer through the conductive layer. This application simplifies the structure, enabling rapid ohmic contact testing using a simple trench-conductive layer-electrode layer loop before the light-emitting device is formed. If poor contact is found, the conductive material formulation can be adjusted immediately, avoiding the scrapping of the entire batch. This significantly shortens the process cycle and reduces trial-and-error costs and reliability risks.
[0027] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. Attached Figure Description
[0028] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the description are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0029] Figure 1 This is a schematic diagram of the semiconductor structure provided in one embodiment of this application from a single viewpoint.
[0030] Figure 2 This is a partial structural schematic diagram of a semiconductor structure provided in one embodiment of this application from a certain perspective.
[0031] Figure 3 This is another structural schematic diagram of the epitaxial layer provided in one embodiment of this application from a certain perspective.
[0032] Figure 4 This is a schematic diagram of the semiconductor structure provided in one embodiment of this application from another perspective.
[0033] Figure label:
[0034] 10. Substrate; 20. Buffer layer; 30. Epitaxial layer; 301. First semiconductor layer; 302. Active layer; 303. Electron blocking layer; 304. Second semiconductor layer; 305. Cap layer; 40. Passivation layer; 401. External trench; 50. Conductive layer; 60. Electrode layer. Detailed Implementation
[0035] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The manner described in the following exemplary embodiments does not represent all manner consistent with this application. Rather, they are merely examples of apparatuses consistent with some aspects of this application as detailed in the appended claims.
[0036] As described in the background section, in the field of Micro LED manufacturing, establishing a low-resistance ohmic contact between GaN and ITO is crucial to achieving linear IV characteristics and ensuring precise brightness control. However, current manufacturing processes have significant drawbacks. They require a complete set of complex processes, including chip epitaxy, mesa fabrication, electrode fabrication, and passivation, before testing can begin. If contact performance degradation is detected during testing, the process flow is already largely finalized, making it impossible to retrospectively adjust the ITO formulation. This ultimately leads to the scrapping of the entire batch of products, resulting in significant cost waste and risk. To effectively address this dilemma, there is an urgent need to develop an innovative and simplified testing structure that can quickly and accurately evaluate the ohmic performance of GaN / ITO before the light-emitting structure is fully formed. This allows for early identification of potential problems, preventing unnecessary losses and effectively achieving the dual goals of cost and risk reduction.
[0037] Based on this, this application provides a semiconductor structure. The semiconductor structure includes a substrate, a buffer layer, an epitaxial layer, a passivation layer, a conductive layer, and an electrode layer. The buffer layer is located on the substrate. The epitaxial layer is located on the side of the buffer layer away from the substrate, and the epitaxial layer material is either N-type doped gallium nitride or P-type doped gallium nitride. The passivation layer is located on the side of the epitaxial layer away from the substrate and has an external trench formed therein; the external trench exposes at least a portion of the epitaxial layer. The conductive layer is located on the passivation layer. The conductive layer is at least partially located within the external trench and is in contact with the epitaxial layer. The electrode layer is located on the conductive layer, and the electrode layer is electrically connected to the epitaxial layer through the conductive layer. The above semiconductor structure includes a substrate, a buffer layer, an epitaxial layer, a passivation layer, a conductive layer, and an electrode layer stacked sequentially. The epitaxial layer material is either N-type doped gallium nitride or P-type doped gallium nitride. An external trench is formed on the passivation layer, exposing at least a portion of the epitaxial layer. A conductive layer is located on the passivation layer, and at least a portion of the conductive layer is located within the external trench, contacting the epitaxial layer. An electrode layer is electrically connected to the epitaxial layer through the conductive layer. This application simplifies the structure, enabling rapid ohmic contact testing using a simple trench-conductive layer-electrode layer loop before the light-emitting device is formed. If poor contact is detected, the conductive material formulation can be adjusted immediately, avoiding batch scrap. This significantly shortens the process cycle and reduces trial-and-error costs and reliability risks.
[0038] The following is in conjunction with the appendix Figures 1 to 4 The following describes some embodiments of this application in detail. Unless otherwise specified, the embodiments and features described below can be combined with each other.
[0039] Reference Figure 1 and Figure 2 The semiconductor structure includes a substrate 10, a buffer layer 20, an epitaxial layer 30, a passivation layer 40, a conductive layer 50, and an electrode layer 60, which are sequentially stacked. The epitaxial layer 30 is made of either N-type doped gallium nitride or P-type doped gallium nitride. The passivation layer 40 is located on the side of the epitaxial layer 30 away from the substrate 10 and has an external trench 401 formed therein. The external trench 401 exposes at least a portion of the epitaxial layer 30. The conductive layer 50 is at least partially located within the external trench 401 and is in contact with the epitaxial layer 30. The electrode layer 60 is electrically connected to the epitaxial layer 30 through the conductive layer 50.
[0040] Specifically, the substrate 10 is configured as any one of sapphire, silicon, silicon carbide, or gallium nitride. The conductive layer 50 is made of any one of indium tin oxide, aluminum-doped zinc oxide, or gallium-doped zinc oxide. The electrode layer 60 is made of aluminum. The passivation layer 40 is made of any one of silicon oxide or aluminum oxide.
[0041] First, this application simplifies the structure by using a simple loop of trench-conductive layer-electrode layer to quickly complete ohmic contact testing before the light-emitting device is formed. If a problem is found, the conductive material formulation can be adjusted immediately, avoiding the scrapping of the entire batch of products. This early evaluation mechanism significantly shortens the process cycle, eliminating the need to wait for the entire process to be completed before testing, effectively reducing trial-and-error costs and reliability risks, improving production efficiency and product yield, and providing a more flexible and economical solution for semiconductor manufacturing.
[0042] Secondly, this application employs either N-type doped gallium nitride (GaN) or P-type doped GaN in the epitaxial layer 30 to enable individual testing of either type of GaN. This allows for a more accurate evaluation of the ohmic contact performance between each type of epitaxial layer 30 and the conductive layer 50. Individual testing allows for optimization of the formulation and process parameters of the N-type and P-type GaN conductive layers 50, ensuring that each type of epitaxial layer 30 achieves a low-resistance ohmic contact.
[0043] In one embodiment, this application may also test N-type gallium nitride or P-type gallium nitride with different doping concentrations separately. By refining the individual testing, it is helpful to determine the optimal doping concentration range, thereby achieving better ohmic contact performance.
[0044] In some implementations, refer to Figure 1 and Figure 4The orthographic projection of the electrode layer 60 on the epitaxial layer 30 at least partially overlaps with the orthographic projection of the conductive layer 50 on the epitaxial layer 30.
[0045] Partial overlap ensures a reliable electrical connection between the electrode layer 60 and the epitaxial layer 30 via the conductive layer 50, facilitating rapid application of excitation signals and extraction of response signals during testing without requiring complex test structures and equipment, thus simplifying the testing process. Furthermore, it allows for in-situ testing of the ohmic performance of the epitaxial layer 30 and the conductive layer 50 before the light-emitting device is formed, enabling timely detection and adjustment of problems and preventing scrapping after complex subsequent processes.
[0046] Furthermore, multiple conductive layers 50 are provided in the overlapping areas. For example, a highly conductive metal layer is added on the original conductive layer 50 to further reduce contact resistance and enhance conductivity.
[0047] In some implementations, reference continues. Figure 4 The external trench 401 has a ring-shaped structure, and the outline of the conductive layer 50 located in the external trench 401 has a ring-shaped structure.
[0048] First, the ring structure provides multiple test paths, facilitating ohmic performance testing at different locations and improving the comprehensiveness and accuracy of the tests. Simultaneously, this structure facilitates connection to external testing equipment, simplifying testing operations.
[0049] Secondly, the ring structure is easy to combine with the electrical structures of other semiconductor devices (such as ring electrodes or ring interconnects) to achieve more complex circuit functions or improve integration.
[0050] In some embodiments, the number of external trenches 401 is not limited in this application. Specifically, this application forms a plurality of external trenches 401 on the passivation layer 40, and fills each trench with a conductive layer 50 that contacts the epitaxial layer 30, while connecting the electrode layer 60 to different conductive layers 50 respectively.
[0051] By employing a multi-trench setup, the impact of multiple different conductive material formulations or trench geometries on ohmic contact performance can be tested simultaneously on the same chip. For example, trenches of varying widths and depths, as well as conductive layers of different thicknesses 50, can be set up on a single chip, and ohmic contact tests can be performed separately. This allows for a more comprehensive evaluation of the impact of various process parameters on performance. It also helps in quickly identifying the optimal process combination, providing a more optimized solution for mass production.
[0052] Furthermore, the external trench 401 of this application is in the form of multiple concentric ring-shaped external trenches 401. Correspondingly, the conductive layer 50 in this application is in the form of multiple concentric ring-shaped conductive layers 50. The design of multiple concentric ring-shaped external trenches 401 and conductive layers 50 in this application can provide multiple test paths, facilitating a comprehensive evaluation of the uniformity of ohmic contact performance. By testing on concentric rings of different radii, the local characteristics of each region can be analyzed, problems can be identified in a timely manner, and the conductive material formulation can be adjusted to improve test accuracy. At the same time, when this structure is combined with equipment such as microscopes, it is convenient to simultaneously observe the structural morphology and electrical performance, enhancing testing capabilities.
[0053] In some implementations, reference continues. Figure 4 The outline of the electrode layer 60 is a ring structure, and the orthographic projection of the electrode layer 60 on the epitaxial layer 30 falls entirely within the orthographic projection of the conductive layer 50 on the epitaxial layer 30.
[0054] This configuration ensures a precise electrical connection between the electrode layer 60 and the conductive layer 50, resulting in a more uniform current distribution and improved device luminescence uniformity. The fully enclosed electrode layer 60 enhances structural stability, reduces external interference, and improves reliability. It also simplifies the testing process, allowing for rapid evaluation of the ohmic performance of the conductive layer 50 and the epitaxial layer 30 directly through the electrode layer 60.
[0055] In some implementations, refer to Figure 3 The epitaxial layer 30 includes a first semiconductor layer 301, an active layer 302, and a second semiconductor layer 304, which are stacked sequentially along the thickness direction.
[0056] The first semiconductor layer 301 is configured with N-type doped gallium nitride, and the second semiconductor layer 304 is configured with P-type doped gallium nitride. An external trench 401 exposes at least a portion of the second semiconductor layer 304, and the electrode layer 60 is electrically connected to the second semiconductor layer 304 through the conductive layer 50.
[0057] This setup can more accurately reflect the electrical performance of the entire epitaxial layer 30 structure under actual operating conditions. It can not only evaluate the contact between the P-type gallium nitride and the conductive layer 50, but also take into account the impact of the active layer 302 and the N-type layer on the overall performance, thus more realistically simulating the actual operating environment of the device. This detection method helps optimize the electrical performance of the entire epitaxial layer 30 structure, improving the device's luminous efficiency and stability.
[0058] In some embodiments, the active layer 302 includes a first sub-semiconductor layer (not shown) and a second sub-semiconductor layer (not shown), which are stacked alternately. The first sub-semiconductor layer is made of gallium nitride or indium gallium nitride, and the second sub-semiconductor layer is made of gallium nitride or indium gallium nitride.
[0059] It is understood that the active layer 302 in this embodiment can be a quantum well layer. That is, by alternately stacking semiconductor materials (gallium nitride and indium gallium nitride) with different bandgap widths, a potential well is formed, allowing carriers (electrons and holes) to recombine in this region, thereby generating photons.
[0060] The active layer 302 structure, during testing, more realistically reflects the impact of device complexity and diversity on ohmic contact performance. By simulating contact conditions under actual operating conditions, the contact characteristics of the conductive layer 50 with different material interfaces can be more accurately evaluated, identifying potential contact problems. This structure provides more comprehensive test data, offering a reference for material selection and device design.
[0061] Furthermore, the epitaxial layer 30 also includes an electron blocking layer 303 and a cap layer 305. The electron blocking layer 303 is located between the active layer 302 and the second semiconductor layer 304, and is used to block electrons. Specifically, the electron blocking layer 303 is made of p-type doped aluminum gallium nitride. The cap layer 305 is located between the second semiconductor layer and the conductive layer 50, and is used to reduce contact resistance. Specifically, the cap layer 305 can be configured as any one of indium gallium nitride, p-type doped gallium nitride, or indium tin oxide.
[0062] This multi-layered design allows for a more comprehensive evaluation of the interface characteristics and overall electrical performance between layers during device testing. It helps to identify potential contact problems at an early stage and optimize the material and process parameters of each layer, thereby improving the device's performance and reliability.
[0063] In some embodiments, the thickness of the conductive layer 50 is greater than or equal to 80 nm and less than or equal to 300 nm. Specifically, the thickness of the conductive layer 50 is configured to be any one of 100 nm, 120 nm, 140 nm, 160 nm, 180 nm, 200 nm, 220 nm, 240 nm, 260 nm, 280 nm, and 300 nm.
[0064] The terms "first," "second," and similar terms used in this application and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "an" or "a" do not indicate a quantity limitation, but rather indicate the presence of at least one, unless otherwise specified. "A plurality" or "several" indicates two or more. The term "and / or" as used herein refers to and includes any or all possible combinations of one or more associated listed items.
[0065] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
Claims
1. A semiconductor structure, characterized in that, include: Substrate; Buffer layer; located on the substrate; An epitaxial layer is located on the side of the buffer layer away from the substrate, and the material of the epitaxial layer is either N-type doped gallium nitride or P-type doped gallium nitride. Passivation layer; located on the side of the epitaxial layer away from the substrate, and having an external trench; The external trench exposes at least a portion of the epitaxial layer; A conductive layer is located on the passivation layer; the conductive layer is at least partially located within the external trench and is in contact with the epitaxial layer. An electrode layer is located on the conductive layer, and the electrode layer is electrically connected to the epitaxial layer through the conductive layer.
2. The semiconductor structure according to claim 1, characterized in that, The orthographic projection of the electrode layer on the epitaxial layer at least partially overlaps with the orthographic projection of the conductive layer on the epitaxial layer.
3. The semiconductor structure according to claim 2, characterized in that, The external trench has a ring-shaped structure, and the outline of the conductive layer located within the external trench also has a ring-shaped structure.
4. The semiconductor structure according to claim 3, characterized in that, The electrode layer has a ring-shaped outline, and the orthographic projection of the electrode layer on the epitaxial layer falls entirely within the orthographic projection of the conductive layer on the epitaxial layer.
5. The semiconductor structure according to any one of claims 1 to 4, characterized in that, The epitaxial layer includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially along the thickness direction; the first semiconductor layer is configured to be N-type doped gallium nitride, and the second semiconductor layer is configured to be P-type doped gallium nitride. in The external trench exposes at least a portion of the second semiconductor layer, and the electrode layer is electrically connected to the second semiconductor layer through the conductive layer.
6. The semiconductor structure according to claim 5, characterized in that, The active layer includes a first sub-semiconductor layer and a second sub-semiconductor layer, which are alternately stacked; wherein, The first sub-semiconductor layer material is selected from gallium nitride and indium gallium nitride, and the second sub-semiconductor layer material is selected from the other one of gallium nitride and indium gallium nitride.
7. The semiconductor structure according to claim 5, characterized in that, The epitaxial layer further includes an electron blocking layer and a cap layer. The electron blocking layer is located between the active layer and the second semiconductor layer and is used to block electrons. The cap layer is located between the second semiconductor layer and the conductive layer and is used to reduce contact resistance.
8. The semiconductor structure according to claim 7, characterized in that, The electron blocking layer is made of p-type doped aluminum gallium nitride; and / or The cap layer can be configured as any one of indium gallium nitride, p-type doped gallium nitride, or indium tin oxide.
9. The semiconductor structure according to any one of claims 1 to 4, characterized in that, The substrate is configured as any one of sapphire, silicon, silicon carbide, or gallium nitride; and / or The conductive layer is made of any one of indium tin oxide, aluminum-doped zinc oxide, or gallium-doped zinc oxide; and / or The electrode layer is made of aluminum; and / or The passivation layer material can be either silicon oxide or aluminum oxide.
10. The semiconductor structure according to claim 9, characterized in that, The thickness of the conductive layer is greater than or equal to 80 nm and less than or equal to 300 nm.