Semiconductor device

Abstract

Various embodiments of the present utility model relate to a semiconductor device. The semiconductor device includes a first die, a first warpage control layer, a second die, and a second warpage control layer. The first die has a plurality of external electrical connections on a first side. The first warpage control layer is disposed on a second side of the first die opposite the first side, wherein the first warpage control layer restricts bending of the first die while the first die is unsupported on the first side. A first side of the second die is disposed on the first warpage control layer opposite the first die, wherein the second die is electrically connected to the first die. The second warpage control layer is disposed on a second side of the second die opposite the first side, wherein the second warpage control layer restricts bending of the second die while the second die is unsupported on the first side.

Description

Technical Field

[0001] This utility model relates to a semiconductor device. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. In most cases, this increase in integration density is due to iterative reductions in the minimum feature size, allowing more components to be integrated into a given area. As the demand for miniaturized electronic devices continues to grow, so too does the need for smaller, more innovative semiconductor die packaging technologies. One example of such packaging systems is Package-on-Package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology typically enables the production of enhanced, smaller-sized semiconductor devices on printed circuit boards (PCBs).

[0003] System-on-integrated chips (SoICs) have been developed to integrate passive and active chips into system-on-chip (SoC) packages to meet the growing market demand for higher computing efficiency, wider data bandwidth, higher functional package density, lower communication latency, and lower power consumption per bit. However, due to the heterogeneous chip stacking in 3D logic-on-logic or memory-on-logic chiplet stacking technology platforms, a relatively high rate of non-bonding or bonding bulges has been observed at the back silicon interface of the stacked chiplets. The introduction of such non-bonding or bonding bulges in stacked chiplets is due to chip bending after dicing and during unsupported pick-and-place operations. If excessive bending is introduced into the chiplet, it will not be able to straighten sufficiently during the time constraint of successfully bonding the stacked chips together. Therefore, an improved manufacturing method is needed to reduce or eliminate bonding bumps and / or non-bonding at the back silicon interface of vertically stacked chips. Utility Model Content

[0004] This invention provides a semiconductor device. The semiconductor device includes a first die, the first die having a first substrate on a first side and an external electrical connection on a second side opposite to the first side, and the first die having a first width. The semiconductor device further includes a first warp control layer disposed on the first substrate on the first side of the first die, wherein the first warp control layer increases the rigidity of the first die compared to its absence. The semiconductor device also includes a second die disposed on the first warp control layer and opposite to the first die, the second die having a second substrate and a second width. The semiconductor device further includes a second warp control layer disposed on the second die and opposite to the first warp control layer, wherein the second warp control layer increases the rigidity of the second die compared to its absence. The semiconductor device also includes a third substrate disposed on the first die and the second die and having a third width.

[0005] Another aspect of this utility model provides a method for forming a semiconductor device. The method includes applying a first warpage control layer to the back side of a first die, wherein the first warpage control layer increases the rigidity of the first die. The method further includes planarizing the first warpage control layer to flatten the first warpage control layer within process parameters and expose the metal portions of through-silicon vias (TSVs) in the substrate of the first die. The method further includes forming a first bonding layer on the side of the first warpage control layer opposite to the first die, the first bonding layer having a dielectric portion and a metallized pattern electrically connected to the TSVs of the first die. The method further includes forming a second warpage control layer on the back side of a second die, wherein the second warpage control layer increases the rigidity of the second die. The method further includes bonding the front side of the second die to the first bonding layer such that the second die is electrically connected to the first die through the metallized pattern of the first bonding layer and the TSVs of the first die. The method further includes forming a set of external interconnects on the front side of the first die opposite to the second die.

[0006] Another aspect of this utility model provides a semiconductor device. The semiconductor device includes a first die having a plurality of external electrical connections on a first side. The semiconductor device further includes a first warpage control layer disposed on a second side of the first die opposite to the first side, wherein the first warpage control layer restricts bending of the first die when the first side is unsupported. The semiconductor device also includes a second die, with a first side disposed on the first warpage control layer opposite to the first die, wherein the second die is electrically connected to the first die. The semiconductor device further includes a second warpage control layer disposed on the second side of the second die opposite to the first side, wherein the second warpage control layer restricts bending of the second die when the first side is unsupported.

[0007] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0008] Figures 1A to 8 The diagram illustrates the segmentation, fabrication, and application of a first warp control layer on a set of first dies according to some embodiments;

[0009] Figure 9 The transfer of a known good first die to a first reconstructed wafer is illustrated according to some embodiments;

[0010] Figures 10A to 10D The results of a conversion process for bonding a first die to a first carrier are shown according to some embodiments;

[0011] Figures 11 to 18 The illustration shows the segmentation, fabrication, and application of a second warp control layer on a set of second dies according to some embodiments;

[0012] Figure 19 This illustrates the transfer of a known good second die to a second reconstructed wafer according to some embodiments;

[0013] Figure 20 The results of a second conversion process for bonding a second die to a first carrier are shown according to some embodiments;

[0014] Figures 21 to 27 The illustration shows the completion and partitioning of an integrated circuit package including a vertically stacked first die and a second die according to some embodiments;

[0015] Figure 28 The formation of a flip-chip device having an integrated circuit package including a vertically stacked first die and a second die, according to some embodiments, is illustrated; and

[0016] Figure 29 This illustrates the formation of a chip-on-a-substrate (CoWoS) device having an integrated circuit package including a vertically stacked first die and a second die, according to some embodiments. Detailed Implementation

[0017] This utility model provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and arrangements are described below to simplify the utility model. These are, of course, merely examples and are not intended to be limiting. For instance, the following description of a first component being formed on or on a second component may include embodiments in which the first and second components are formed in direct contact, and may also include embodiments in which additional components may be formed between the first and second components, thereby preventing direct contact between the first and second components. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for the purpose of brevity and clarity, and not to indicate any relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one component or feature and another shown in the figures. In addition to the orientations illustrated in the figures, these spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0019] Embodiments will now be discussed with respect to certain embodiments in which one or more dies are vertically bonded. A warp control layer is applied to the back-side substrate of each die to facilitate die-to-die bonding and reduce or eliminate bonding bulges, de-bonding, non-bonding, etc. However, the embodiments presented herein are intended to be illustrative and are not intended to limit the embodiments to the precise descriptions discussed. Rather, the embodiments discussed may be incorporated into a wide variety of implementations, and all such implementations are fully intended to be included within the scope of the embodiments.

[0020] Now for reference Figure 1A and Figure 1B The diagram shows a first wafer 100 having multiple die regions (110a, 110b, etc.), wherein, according to some embodiments, a first die 200 is formed in / on the first wafer 100. Figure 1A It is a cross-sectional view of a die formed on a first wafer 100 according to some embodiments. Figure 1B This is a top view of a first wafer 100 according to some embodiments. For example... Figure 1AAs shown, in some embodiments, a plurality of first dies 200 (see FIG. 2) may be manufactured as part of a larger first wafer 100 or panel-type manufacturing process having a plurality of die regions (e.g., first die regions 110a and 110b (collectively referred to as 110)). For example, Figure 1B A circular wafer 100 with four first die regions 110a to 110d is shown. In the illustrated embodiment, the four first dies are included on the first wafer 100, thereby allowing the four first dies to be fabricated and diced on a single wafer. In other embodiments, fewer or more die regions may be used on a single wafer or panel.

[0021] exist Figure 1A In the specific embodiment shown, the first die fabricated in the first die regions 110a and 110b includes a first substrate 120 and a first interconnect structure 130. The first substrate 120 may be a bulk silicon or other semiconductor material wafer, a silicon-on-insulator (SOI) wafer, etc. The first substrate 120 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The first substrate 120 has an active surface (e.g., an upward-facing surface) and an active surface (e.g., a downward-facing surface). Devices are located at the active surface of the first substrate 120. Devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. Non-active surfaces may not have any devices. The substrate may also contain one or more through silicon vias (TSVs)140.

[0022] A first interconnect structure 130 is located above the active surface of the first substrate 120 and is used to electrically connect means of the first substrate 120 to form one or more integrated circuits. The first interconnect structure 130 may include metallization patterns 150 in one or more dielectric layers 160. Acceptable dielectric materials suitable for the dielectric layers 160 include oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; the like; or combinations thereof, such as silicon oxynitride, silicon carbonoxynitride, silicon carbonitride, silicon carbonitride, etc. Other dielectric materials may also be used, and any suitable means for forming, growing, or depositing the dielectric layers 160 may be used.

[0023] The metallization pattern 150 may include vias and / or wires for interconnecting means of the first substrate 120. The metallization pattern 150 may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, or similar materials. The metallization pattern 150 may be formed by a damascene process, such as a single damascene process, a double damascene process, etc. The first interconnect structure 130 may also include metal pads (e.g., aluminum pads, copper pads, etc.) (not shown) that are connected to the topmost metallization pattern 150 of the first interconnect structure 130 through one or more passivation layers. Additional insulating layers (e.g., passivation layers) may be formed around the metal pads to provide a flat surface for forming additional overlays (e.g., pads and insulating bonding layers) on said flat surface.

[0024] In some embodiments, the first interconnect structure 130 may include optical components, such as optical waveguides (e.g., ridge waveguides, rib waveguides, buried channel waveguides, diffused waveguides, etc.), couplers (e.g., grating couplers, edge couplers (which are narrow waveguides with a width between about 1 nm and about 200 nm), directional couplers, optical modulators (e.g., Mach-Zehnder silicon photonic switches, microelectromechanical switches, microring resonators, etc.), amplifiers, multiplexers, demultiplexers, photoelectric converters (e.g., PN junctions), electro-optic converters, lasers, combinations thereof, etc. Devices on the active surface of the first substrate 120 may be used in conjunction with the optical components in the first interconnect structure 130 to complete the optical components.

[0025] Figure 2AThis illustrates the beginning of a multi-step partitioning of a first die 200 according to some embodiments. In some embodiments, an etching process is used to partially partition the first die 200a and the first die 200b (collectively referred to as the first die 200). In some embodiments, a combination of photolithography and etching processes is used to form trenches 210. For example, trenches can be formed along scribing 220 in a plasma cutting process. The plasma cutting process can include forming a patterned mask over an interconnect structure. The patterned mask can be a photomask deposited on the first interconnect structure 130 using a spin coating process and patterned by photolithography (e.g., exposure and development) to define openings of the first interconnect structure 130 exposed in the scribing 220. The plasma cutting process etches portions of the first interconnect structure 130 and the first substrate 120 through the pattern (e.g., openings) in the patterned mask. Trench 210 can extend through the first interconnect structure 130 to a desired depth in the first substrate 120. However, the trench 210 may not extend completely through the first substrate 120, and the lower portion of the first substrate 120 may be retained to connect the first dies 200 together in the first wafer 100. In some embodiments, the depth of the trench 210 may be between 1 micrometer (μm) and 750 μm into the first substrate 120.

[0026] In some embodiments, the etching process can be performed in multiple steps and can utilize plasma dry etching and / or reactive ion etching (RIE). For example, a first reactive ion etching can be performed using a reactive gas such as CF4, C4F8, CHF3, or CH3F to preferentially etch through the dielectric layer 160 of the first interconnect structure 130. A second reactive ion etching can then be performed using a gas such as SF6 or NF3 to preferentially etch the first substrate 120. The etching depth can be controlled by varying the timing of the etching process, among other process parameters. In some embodiments, a third etching, which is a wet etching, can be performed to eliminate any surface defects in the first die 200 resulting from the dry etching process. In some embodiments, the RIE uses argon-based plasma, oxygen-based plasma, nitrogen-based plasma, etc. However, any suitable method of etching trenches to divide the first die 200 can also be utilized.

[0027] Figure 2B yes Figure 2A A partial enlarged view. In some cases, the width (W1) of the trenches formed by etching between each first die 200 can be between 0.1 μm and 1000 μm. In some embodiments, the width (W1) of the trenches can be narrow enough to exclude subsequent deposition in the trenches. In some embodiments, the width (W1) of the trenches can be 8 μm or less to limit deposition in the trenches.

[0028] Figure 3 The diagram illustrates the formation of a protective layer 310 over a first interconnect structure 130 of a first die 200 according to some embodiments. In some embodiments, a surface treatment may be performed in the trench 210 prior to the formation of the protective layer 310. In some embodiments, the surface treatment is a fluorine-based treatment (e.g., a wet cleaning process using a fluorine-containing solution), a fluorine-based plasma process, etc. In some embodiments, the fluorine-based plasma process may be performed at temperatures ranging from 25°C to 500°C and at a temperature from 0 Torr to 1.316 x 10⁻⁶. -3 The process is performed under a pressure of one atmosphere. Other treatments for forming a hydrophobic surface may be applied in other embodiments. The surface treatment makes the surface of trench 210 hydrophobic, allowing the subsequently formed protective layer 310 to be deposited over the first interconnect structure 130 without being significantly deposited within the trench 210. When the surface treatment is fluorine-based, the resulting surface region may also contain fluorine and is referred to as a fluorinated protective layer. For example, the surface region may contain 5% by weight (wt%) or more of fluorine, which advantageously creates a hydrophobic surface in trench 210. The surface region may also contain carbon, oxygen, silicon, nitrogen, or combinations thereof. The specific material composition of the surface region may depend on the material of the first interconnect structure 130 and / or the first substrate 120 on which the surface region is formed. For example, portions of the surface region on the first substrate 120 may include fluorine and silicon, while portions of the surface region on the first interconnect structure 130 may include a combination of fluorine and carbon, oxygen, nitrogen, and / or silicon.

[0029] Surface treatment can be performed while the patterned mask covers the first interconnect structure 130. As a result, surface regions can be selectively formed within the trench 210 without forming a surface region over the entire first interconnect structure 130. For example, after surface treatment, the top surface of the first interconnect structure 130 can remain hydrophilic, allowing the protective layer 310 to be deposited thereon. The patterned mask can be removed after surface treatment. For example, when the patterned mask is a photomask, an ashing process can be used to remove the patterned mask.

[0030] A protective layer 310 can then be deposited over the first interconnect structure 130. In some embodiments, the protective layer 310 is a back side anti-reflective coating (BARC) layer deposited by a spin coating process or the like. Due to the surface treatment and hydrophobic surface areas, the protective layer 310 does not significantly deposit within the trench 210. Preventing the protective layer 310 from depositing in the trench 210 achieves advantages such as reduced manufacturing defects and increased yield. In other embodiments, the protective layer 310 may be a photoresist or other suitable material deposited or formed using a suitable application process.

[0031] In some embodiments, the thickness of the protective layer 310 can be between 1 nm and 100 nm. A planarization process (e.g., chemical mechanical polishing (CMP)) can be performed to make the top surface of the protective layer 310 coplanar (within the range of process variations). In some embodiments, a spin coating process can be used to control the uniformity of the protective layer 310.

[0032] Figure 4 The application of back-side grinding (BG) tape according to some embodiments is illustrated. As shown, BG tape 410 is adhered to a first wafer 100, for example, to the top surface of a protective layer 310. BG tape 410 supports the first wafer 100 during final dicing of the first die 200 and subsequent preparation. Protective layer 310 acts as an intermediate buffer between the first wafer 100 and BG tape 410. For example, protective layer 310 protects the top surface of the first interconnect structure 130 from direct contact with BG tape 410, thereby reducing the risk of damage to the first interconnect structure 130.

[0033] Figure 5A The thinning of a first substrate 120 of a first die 200 according to some embodiments is illustrated. As shown, a first wafer 100 can be flipped such that the BG tape 410 is generally oriented to the bottom side of the first wafer 100. The first substrate 120 can then be thinned until the TSV 140 has been exposed, and the bonding portions of the first substrate 120 are removed to completely separate the first die 200. In one embodiment, the first substrate 120 can be thinned using, for example, a CMP process, a polishing process, a slicing process, etc. Furthermore, once exposed, the TSV 140 can be further exposed using, for example, one or more etching processes (e.g., a wet etching process) to recess the first substrate 120 such that the TSV 140 extends from the first substrate 120 (e.g., ...). Figure 5B (As shown). In other embodiments, the first die 200 may be segmented using a sawing process alone or in combination with an etching process such as described above.

[0034] Figure 6AA first warpage control layer 610 is shown applied to the back side of a thinned first substrate 120 according to some embodiments. In some embodiments, the first warpage control layer 610 may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, an organic material, or some other dielectric material. The first warpage control layer 610 may be deposited on the first substrate 120, for example, by spin coating, lamination, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), high-density plasma chemical vapor deposition (HDPCVD), thermal oxidation, combinations thereof, and / or similar processes. A planarization process (e.g., chemical mechanical polishing (CMP)) may be performed such that the top surface of the first warpage control layer 610 is coplanar (within the range of process variations). In embodiments where the first substrate 120 has been recessed to expose a portion of the TSV 140, a planarization process may be performed such that the first warpage control layer 610 is coplanar with the top surface of the TSV 140 (within the range of process variations) (e.g., as shown in the example). Figure 6B (As shown).

[0035] In some embodiments, the small width of the trench 210 between the first dies 200 (e.g., less than about 8 μm) and the selected process conditions substantially prevent the interaction of process gases with the etched sidewalls of the first dies 200. For example, a bias power of 1 to 5 kilowatts (kW) can be used to increase vertical bombardment and limit the formation of the first warpage control layer 610 on the sidewalls of the first dies 200. In embodiments where a surface treatment is performed in the trench 210 prior to the formation of the protective layer 310, the surface treatment can further prevent the formation of the first warpage control layer 610 on the etched sidewalls of the first dies 200.

[0036] In other embodiments, such as Figure 6C As shown, the first warpage control layer 610 may encapsulate part or all of the sidewalls of the first die 200. For example, when the first warpage control layer 610 is a silicon oxide layer formed by thermal oxidation, the first warpage control layer 610 will be formed along all exposed portions of the first substrate 120 that are composed of silicon. In some embodiments, the TSV 140 may protrude beyond the first warpage control layer 610 after formation.

[0037] Figure 6D and 6E An alternative embodiment for forming the first warp control layer 610 is shown. Figure 6D In this process, a thick conformal deposition method is used to deposit the first warp control layer 610. Subsequently, a wet etching method using, for example, hydrofluoric acid can be used to reduce the thickness of the first warp control layer 610 and expose the top of the TSV 140, as shown. Figure 6EAs shown. Other methods for planarizing the first warp control layer 610 and exposing the TSV 140 (e.g., a combination of photolithography and etching processes) can be used to form the first warp control layer 610 and are foreseeable.

[0038] In some embodiments, the thickness of the first warp control layer 610 is... to In some embodiments, the first warp control layer 610 may comprise a multilayer of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, organic material, or some other dielectric material deposited or formed using the methods described above or other suitable processing techniques. Once formed, the first warp control layer 610 increases the rigidity of the first die 200 and limits the amount of bending that the first die 200 will experience during subsequent pick-and-place operations (e.g., as described below). By limiting the bending introduced into the die, the die may have already straightened or have time to straighten within the timing parameters of the bonding. For example, a particular moisture content or humidity of the die may be a limiting factor in production, where the die dries over time. By reducing the amount of bending introduced, the die is more likely to be straightened to within tolerances (if it exceeds tolerances after pick-and-place), and non-bonding or bonding protrusions can be reduced. Thus, higher manufacturing yields, lower production costs, reduced material waste, and improved manufacturing efficiency are achieved.

[0039] Figure 7 The diagram illustrates the application of a dicing strip 710 to a first die 200 according to some embodiments. The dicing strip supports the first die 200 and maintains the wafer integrity of the first wafer 100 during the preparation process completion of the first die 200. In some embodiments, the dicing strip may contact the top metal portion of the TSV 140 and the first warp control layer 610.

[0040] Figure 8 The removal of BG tape 410 and the reorientation of the wafer are illustrated according to some embodiments. As shown, the wafer is flipped and BG tape 410 is removed to expose the protective layer 310. The protective layer 310 can also be removed at this time, such as... Figure 8 As shown, or after the pick-and-place operation described below but before the formation of the first bonding layer 1030, it may be removed. In some embodiments, a further planarization process, such as CMP, may be performed on the interconnect layer 130 to remove residues and eliminate defects caused by the removal of BG tape 410 (within the range of process parameters).

[0041] Figure 9The illustration shows, according to some embodiments, placing a known good first die 200 from a first wafer 100 onto a first reconstructed wafer 900 or a film. Before dicing the wafer using the etching process described above, the first wafer 100 can be tested to identify each known good die among the first dies 200. After the dicing process, each known good first die 200 can be moved to the first reconstructed wafer 900 using a pick-and-place device. In some embodiments, the reconstructed wafer may include a release film. Since the first dies 200 are not flipped during the pick-and-place process, the first warpage control layer 610 of each first die 200 will be closest to the first reconstructed wafer 900.

[0042] For simplicity, only one known good first die 200 from the first wafer 100 is shown being transferred to the first reconstructed wafer 900. However, there is no limit to the number of known good first dies 200 that can be diced from the first wafer 100. Similarly, there is no limit to the number of known good first dies 200 that can be transferred from the first wafer 100 to the first reconstructed wafer 900. However, design requirements, space constraints of the first wafer 100, and the first reconstructed wafer 900 will be taken into account.

[0043] During this movement from the first wafer 100 supported by the dicing tape 710 to the first reconstructed wafer 900, the first die (e.g., 200b) is held by the pick-and-place machine 910, but the bottom of the first die 200 is unsupported. Therefore, the natural tendency of the first die is to warp downwards, thus introducing bending into the first die 200. As described above, the warp control layer 610 will significantly reduce or eliminate this warping.

[0044] Figure 10A This diagram illustrates the fabrication structure of a single first die 200 on a first carrier substrate 1010 after a switch process, according to some embodiments. During the switch process, a first reconstructed wafer 900 with associated known good first dies 200 is attached to the first carrier substrate 1010 such that the first warpage control layer 610 on each first die 200 is furthest from the first carrier substrate 1010. Any suitable method of attaching the first carrier substrate 1010 can be used. The first reconstructed wafer 900 can then be de-bonded / released from the known good first dies 200, thereby exposing the first warpage control layer 610 on each known good first die 200. In embodiments, the metal portions of the TSV 140 may also be exposed, for example, when the metal portions of the TSV 140 are substantially coplanar (within the process parameter range).

[0045] The first carrier substrate 1010 may be a bulk silicon or other semiconductor material wafer, a silicon-on-insulator (SOI) wafer, etc. The first carrier substrate 1010 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The first carrier substrate 1010 may also contain one or more TSVs (not shown).

[0046] Figure 10B The diagram illustrates gap filling between first dies 200 on a first carrier substrate according to some embodiments. As shown, a first encapsulation 1020 is formed on the first carrier substrate 1010 and on and around the first dies 200. In some embodiments, the first encapsulation 1020 may comprise one or more layers of non-photo-patternable insulating material, such as silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), combinations thereof, and can be formed using CVD, PVD, ALD, spin coating processes, combinations thereof, etc. In other embodiments, the first encapsulation 1020 may comprise one or more layers of photo-patternable insulating material, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), combinations thereof, and can be formed using spin coating processes, etc. Such photo-patternable insulating materials can be patterned using photolithography methods similar to those used for photoresist materials. In other embodiments, the first encapsulation 1020 may include a molding compound, such as an epoxy resin, a resin, a moldable polymer, or a combination thereof. The molding compound may be applied in a substantially liquid state and then cured by a chemical reaction, for example, in an epoxy resin or a resin. In other embodiments, the molding compound may be an ultraviolet (UV) or thermosetting polymer that can be applied as a gel or plastic solid disposed around and between the first dies 200.

[0047] Figure 10CThe diagram illustrates the structure resulting from a planarization process performed on the first encapsulation 1020. As shown, the first encapsulation 1020 and the first warpage control layer 610 on the first die 200 are planarized such that the exposed surface of the first warpage control layer 610 is substantially flush with or coplanar with the top surface of the first encapsulation 1020. In some embodiments, the planarization process may include a CMP process, a polishing process, an etching process, or a combination thereof. In some embodiments, the planarization process may expose the TSV 140 of the first die 200 such that the exposed surface of the TSV 140 is substantially flush with or coplanar with the top surface of the first warpage control layer 610 and the top surface of the first encapsulation 1020.

[0048] Figure 10D The formation of a first bonding layer 1030 on a first carrier substrate 1010 is described. According to some embodiments, the first bonding layer 1030 is formed of a first dielectric material 1040, such as silicon oxide or silicon nitride. The first dielectric material 1040 can be deposited using any suitable method, such as CVD, high-density plasma chemical vapor deposition (HDPCVD), PVD, atomic layer deposition (ALD), etc. However, any suitable material and deposition process can also be used. The first bonding layer 1030 can then be used for dielectric-to-dielectric and metal-to-metal bonding between the first die 200 and the second die 1200.

[0049] Once the first dielectric material 1040 is formed, openings are formed in the first dielectric material 1040 to expose the top of the TSV 140 in preparation for the formation of the first bonding pad 1050 within the first bonding layer 1030. Once the openings are formed within the first dielectric material 1040, they can be filled with a seed layer (not shown) and a first plated metal to form the first bonding pad 1050 within the first bonding layer 1030. The seed layer can be deposited as a blanket over the top surface of the first dielectric material, the exposed conductive portion of the TSV 140, and the sidewalls of the openings. The seed layer may include a copper layer. Depending on the desired materials, the seed layer can be deposited using processes such as sputtering, evaporation, or plasma-enhanced chemical vapor deposition (PECVD).

[0050] The first plating metal can be deposited over the seed layer (not shown) and the first dielectric material 1040 in the first bonding layer 1030 using a plating process such as electroplating or electroless plating. The first plating metal may include copper, copper alloys, etc. The first plating metal may be a filler material. A barrier layer (not shown separately) may be deposited over the top surface of the first dielectric material 1040 and the sidewalls of the openings in the first bonding layer 1030 before the seed layer. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0051] After the opening is filled with the first plated metal, a planarization process, such as chemical mechanical polishing (CMP), is performed to remove the seed layer and excess portion of the first plated metal, thereby forming the first bonding pad 1050 within the first bonding layer 1030.

[0052] Figure 11 It is a second die 1200 formed on a second wafer 1100 according to some embodiments. Figure 12 A cross-sectional view of the second wafer 1100. The second wafer 1100 may include multiple die regions (1110a, 1110b, 1110c, 1110d, etc.), wherein multiple second dies 1200 may be formed in / on the second wafer 1100. Figure 1B Similarly, the second die 1200 can be formed as part of a manufacturing process for a larger wafer or panel having multiple die regions 1110a, 1110b, etc. Multiple second dies 1200 (see...) Figure 12 This can be manufactured as part of a larger wafer or panel-like fabrication process having multiple die regions in a two-dimensional array. For simplicity, only a row of four second dies 1200 formed in the second die regions 1110a to 1110d (collectively referred to as 1110) is shown. In other embodiments, fewer or more die regions arranged in a two-dimensional array can be used on a single wafer.

[0053] exist Figure 11 In the specific embodiment shown, the second die 1200 manufactured in the second die regions 1110a to 1110d includes a second substrate 1120, a second interconnect structure 1130, and an external interconnect layer 1140.

[0054] The second substrate 1120 may be a bulk silicon or other semiconductor material wafer, a silicon-on-insulator (SOI) wafer, etc. The second substrate 1120 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The second substrate 1120 has an active surface (e.g., an upward-facing surface) and an active surface (e.g., a downward-facing surface). Devices are located on the active surface of the second substrate 1120. Devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. No devices may be disposed on the active surface. The substrate may also contain one or more TSV140s (not shown).

[0055] The second interconnect structure 1130 is located above the active surface of the second substrate 1120 and is used for electrically connecting means of the second substrate 1120 to form one or more integrated circuits. The second interconnect structure 1130 may include metallization patterns 1150 in one or more dielectric layers 1160. Acceptable dielectric materials suitable for the dielectric layers 1160 include oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; the like; or combinations thereof, such as silicon oxynitride, silicon carbonoxynitride, silicon carbonitride, silicon carbonitride, etc. Other dielectric materials may also be used, and any suitable means of forming, growing, or depositing the dielectric layer 1160 may be used.

[0056] The metallization pattern 1150 may include vias and / or wires for interconnecting the second substrate 1120. The metallization pattern 1150 may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, or similar materials. The metallization pattern 1150 may be formed by a damascene process, such as a single damascene process, a double damascene process, etc. The second interconnect structure 1130 may also include metal pads (e.g., aluminum pads, copper pads, etc.) (not shown) that are connected to the topmost metallization pattern 1150 of the second interconnect structure 1130 through one or more passivation layers. Additional insulating layers (e.g., passivation layers) may be formed around the metal pads to provide a flat surface for forming additional overlays (e.g., pads and insulating bonding layers) on said flat surface.

[0057] In some embodiments, the second interconnect structure 1130 may include optical components, such as optical waveguides (e.g., ridge waveguides, rib waveguides, buried channel waveguides, diffused waveguides, etc.), couplers (e.g., grating couplers, edge couplers (which are narrow waveguides with a width between about 1 nm and about 200 nm)), directional couplers, optical modulators (e.g., Mach-Zehnder silicon photonic switches, microelectromechanical switches, microring resonators, etc.), amplifiers, multiplexers, demultiplexers, photoelectric converters (e.g., PN junctions), electro-optic converters, lasers, combinations of these components, etc. Devices on the active surface of the second substrate 1120 may be used in conjunction with the optical components in the second interconnect structure 1130 to complete the optical components.

[0058] The external interconnect layer 1140 facilitates external electrical connections to and from the second die 1200. The external interconnect layer 1140 may include a dielectric layer 1170, a metallization layer 1180, and an external bonding pad 1190. The dielectric layer 1170 and the metallization layer 1180 may be formed in any suitable manner, such as those described above relating to the metallization pattern 1150 and the dielectric layer 1160 in the second interconnect structure 1130.

[0059] Once the dielectric layer 1170 and metallization layer 1180 of the external interconnect layer 1140 are formed, the external bonding pad 1190 can be formed using any suitable method. For example, an opening can be formed in the dielectric layer 1170 of the external interconnect layer 1140 to expose the conductive portion of the metallization layer 1180 in preparation for forming the external bonding pad 1190. Once the opening is formed within the dielectric layer 1170, the opening can be filled with a seed layer (not shown) and plated metal (not shown) to form the external bonding pad 1190 within the external interconnect layer 1140. The seed layer can be blanketed over the top surface of the dielectric layer 1170 and the exposed conductive portion of the metallization layer 1180, as well as the sidewalls of the opening, deposited in the external interconnect layer 1140. The seed layer may include a copper layer. Depending on the desired material, the seed layer can be deposited using processes such as sputtering, evaporation, or plasma-enhanced chemical vapor deposition (PECVD).

[0060] A plating metal can be deposited over the seed layer (not shown) and dielectric layer 1170 in the external interconnect layer 1140 using a plating process such as electroplating or electroless plating. The plating metal may include copper, copper alloys, etc. The plating metal may also be a filler material. Before the seed layer, a barrier layer (not shown separately) may be deposited over the top surface of the dielectric layer 1170 and the sidewalls of the openings in the external interconnect layer 1140. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0061] After filling the opening with plated metal, a planarization process, such as chemical mechanical polishing (CMP), is performed to remove the seed layer and excess plated metal, thereby forming an external bonding pad 1190 within the external interconnect layer 1140. In some embodiments, bonding pad vias may also be used in the external interconnect layer 1140 to connect the external bonding pad 1190 to the conductive portion of the underlying metallization layer 1180.

[0062] Figure 12 This illustrates the beginning of a multi-step partitioning of a second die according to some embodiments. In some embodiments, an etching process is used to partially partition the second die 1200a and the second die 1200b, the second die 1200b and the second die 1200c, and the second die 1200c and the second die 1200d (collectively referred to as the second die 1200). In some embodiments, a combination of photolithography and etching processes is used to form trenches 1210. For example, trenches can be formed along scribing 1220 in a plasma cutting process. The plasma cutting process may include forming a patterned mask over an external interconnect layer 1140. The patterned mask may be a photomask deposited over the external interconnect layer 1140 using a spin coating process and patterned by photolithography (e.g., exposure and development) to define openings in the external interconnect layer 1140 exposed in the scribing 1220. The plasma cutting process etches portions of the external interconnect layer 1140, the second interconnect structure 1130, and the second substrate 1120 through the pattern (e.g., openings) in the patterned mask. Trench 1210 may extend through outer interconnect layer 1140 and second interconnect structure 1130 to a desired depth in second substrate 1120. However, trench 1210 may not extend completely through second substrate 1120, and the lower portion of second substrate 1120 may be retained to connect second dies 1200 together in second wafer 1100. In some embodiments, the depth of trench 1210 may be between 1 micrometer (μm) and 750 μm into second substrate 1120.

[0063] In some embodiments, the etching process can be performed in multiple steps and can utilize plasma dry etching and / or reactive ion etching (RIE). For example, a first reactive ion etching can be performed using a reactive gas such as CF4, C4F8, CHF3, or CH3F to preferentially etch through the dielectric layer 1170 of the outer interconnect layer 1140 and the dielectric layer 1160 of the second interconnect structure 1130. A second reactive ion etching can then be performed using a gas such as SF6 or NF3 to preferentially etch the second substrate 1120. The etching depth can be controlled by varying the timing of the etching process, among other process parameters. In some embodiments, a third etching, which is a wet etching, can be performed to eliminate any surface defects in the second die 1200 resulting from the dry etching process. In some embodiments, the RIE uses argon-based plasma, oxygen-based plasma, nitrogen-based plasma, etc. However, any suitable method for dividing the second die 1200 can also be utilized, such as etch trenches. In some cases, the width (W2) of the trenches formed by etching between each second die 1200 can be between 0.1 μm and 1000 μm. In some embodiments, the width (W2) of the trenches can be narrow enough to exclude subsequent deposition in the trenches. In some embodiments, the width (W2) of the trenches can be 8 μm or less to limit deposition in the trenches.

[0064] Figure 13 The diagram illustrates the formation of a protective layer 1310 over the outer connection layer 1140 of the second die 1200 according to some embodiments. In some embodiments, a surface treatment may be performed in the trench 1210 prior to the formation of the protective layer 1310. In some embodiments, the surface treatment is a fluorine-based treatment (e.g., a wet cleaning process using a fluorine-containing solution), a fluorine-based plasma process, etc. In some embodiments, the fluorine-based plasma process may be performed at temperatures ranging from 25°C to 500°C and at a temperature from 0 Torr to 1.316 x 10⁻⁶. -3The process is performed under a pressure of one atmosphere. Other treatments for forming a hydrophobic surface may be applied in other embodiments. The surface treatment makes the surface of trench 1210 hydrophobic, allowing the subsequently formed protective layer 1310 to be deposited over the external interconnect layer 1140 without being significantly deposited within trench 1210. When the surface treatment is fluorine-based, the resulting surface region may also contain fluorine and is referred to as a fluorinated protective layer. For example, the surface region may contain 5% by weight (wt%) or more of fluorine, which advantageously creates a hydrophobic surface in trench 1210. The surface region may also contain carbon, oxygen, silicon, nitrogen, or combinations thereof. The specific material composition of the surface region may depend on the material of the external interconnect layer 1140, the second interconnect structure 1130, and / or the second substrate 1120 on which the surface region is formed. For example, portions of the surface region on the second substrate 1120 may include fluorine and silicon, while portions of the surface region on the external interconnect layer 1140 and / or the second interconnect structure 1130 may include a combination of fluorine and carbon, oxygen, nitrogen, and / or silicon.

[0065] Surface treatment can be performed while the patterned mask covers the outer interconnect layer 1140. As a result, surface areas can be selectively formed within the trench 1210 without forming a surface area over the entire outer interconnect layer 1140. For example, after surface treatment, the top surface of the outer interconnect layer 1140 can remain hydrophilic, allowing the protective layer 1310 to be deposited thereon. The patterned mask can be removed after surface treatment. For example, when the patterned mask is a photomask, an ashing process can be used to remove the patterned mask.

[0066] A protective layer 1310 can then be deposited over the outer bonding layer 1140. In some embodiments, the protective layer 1310 is a back antireflective coating (BARC) layer deposited by a spin coating process or the like. Due to the surface treatment and hydrophobic surface areas, the protective layer 1310 does not significantly deposit within the trench 1210. Preventing the protective layer 1310 from depositing in the trench 1210 achieves advantages such as reduced manufacturing defects and increased yield. In other embodiments, the protective layer 1310 may be a photoresist or other suitable material deposited or formed using a suitable application process.

[0067] In some embodiments, the thickness of the protective layer 1310 can be between 1 nm and 100 nm. A planarization process (e.g., chemical mechanical polishing (CMP)) can be performed to make the top surface of the protective layer 1310 coplanar (within the range of process variations). In some embodiments, a spin coating process can be used to control the uniformity of the protective layer 1310.

[0068] Figure 14The application of back-grinding (BG) tape according to some embodiments is illustrated. As shown, BG tape 1410 is adhered to a second wafer 1100, for example, to the top surface of a protective layer 1310. BG tape 1410 supports the second wafer 1100 during final dicing of the second die 1200 and during subsequent preparation processes. Protective layer 10 acts as an intermediate buffer between the second wafer 1100 and BG tape 1410. For example, protective layer 1310 protects the top surface of external interconnect layer 1140 from direct contact with BG tape 1410, thereby reducing the risk of damage to external interconnect layer 1140.

[0069] Figure 15 The thinning of the second substrate 1120 of the second die 1200 according to some embodiments is illustrated. As shown, the second wafer 1100 can be flipped such that the BG tape 1410 is generally oriented to the bottom side of the second wafer 1100. The second substrate 1120 can then be thinned to complete the dicing of each second die 1200. In embodiments where the second substrate 1120 includes a TSV, the second substrate 1120 can be thinned until the TSV is exposed. In one embodiment, the second substrate 1120 can be thinned using, for example, a CMP process, a polishing process, a slicing process, etc. Furthermore, once exposed, the TSV can be further exposed using, for example, one or more etching processes (e.g., a wet etching process) to recess the second substrate 1120 such that the TSV extends from the second substrate 1120.

[0070] Figure 16 A second warpage control layer 1610 is shown applied to the front side of a thinned second substrate 1120 according to some embodiments. In some embodiments, the second warpage control layer 1610 may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, an organic material, or some other dielectric material. The second warpage control layer 1610 may be deposited on the second substrate 1120, for example, by spin coating, lamination, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), high-density plasma chemical vapor deposition (HDPCVD), thermal oxidation, combinations thereof, and / or similar processes. A planarization process (e.g., chemical mechanical polishing (CMP), etc.) may be performed such that the top surface of the second warpage control layer 1610 is coplanar (within the range of process variations). In embodiments where the second substrate 1120 is recessed to expose any incorporated TSV portions, a planarization process may be performed such that the second warpage control layer 1610 is coplanar with the top surface of the TSV (not shown) (within the range of process variations). In some embodiments, the second warp control layer 1610 is deposited using the same material as described above with respect to the first warp control layer 610, but this is not a limitation, and different materials and processes can still be used for the respective warp control layers.

[0071] In some embodiments, due to the small width (approximately 8 μm) of the trenches 1210 between the second dies 1200 and due to the selected process conditions, interaction between process gases and the etched sidewalls of the second dies 1200 is substantially eliminated. In embodiments where a surface treatment is performed in the trenches 1210 of the second dies 1200 prior to the formation of the protective layer 1310, the surface treatment can further prevent the formation of the second warpage control layer 1610 on the etched sidewalls of the second dies 1200. In other embodiments, similar to that described for the first warpage control layer 610, portions of the second warpage control layer 1610 may coat the sidewalls of the second dies 1200, but this is not a limitation, and different materials and processes can still be used for the respective second warpage control layer 1610.

[0072] In some embodiments, the thickness of the second warp control layer 1610 is... to In some embodiments, the second warp control layer 1610 may comprise a multilayer of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, organic material, or some other dielectric material deposited or formed using suitable processing techniques. Once formed, the second warp control layer 1610 increases the rigidity of the second die 1200 and limits the amount of bending that the second die 1200 will experience during subsequent pick-and-place operations (e.g., as described below). By limiting the bending introduced into the second die, the die may have already straightened or has had time to straighten within the timing parameters of the bonding. For example, a particular moisture content or humidity of the die may be a limiting factor in production, where the die dries over time. By reducing the amount of bending introduced, the die is more likely to be straightened to within tolerances (if it exceeds tolerances after pick-and-place), and non-bonding or bonding protrusions can be reduced. Thus, higher manufacturing yields, lower production costs, reduced material waste, and improved manufacturing efficiency are achieved.

[0073] Figure 17 The diagram illustrates the application of a dicing strip 1710 to a second die 1200 according to some embodiments. The dicing strip 1710 supports the second die 1200 and maintains the integrity of the second wafer 1100 during the completion of the second die 1200 preparation process. In some embodiments, the dicing strip may contact the top metal portion of the TSV included in the second substrate 1120 and the second warp control layer 1610.

[0074] Figure 18 The removal of BG tape 1410 and the reorientation of the second wafer 1100 are illustrated according to some embodiments. As shown, the second wafer 1100 is flipped and BG tape 1410 is removed to expose the protective layer 1310. The protective layer 1310 may also be removed at this time, such as... Figure 18As shown, or after the pick-and-place operation described below, but before bonding the second die 1200 to the first die 200, it may be removed. In some embodiments, a further planarization process, such as CMP, may be performed on the outer bonding layer 1140 to remove residues and eliminate defects caused by removing the BG tape 1410 (within the process parameters).

[0075] Figure 19 The illustration shows, according to some embodiments, placing a known good second die 1200 from a second wafer 1100 onto a second reconstructed wafer 1900 or a film. Before dicing the second wafer 1100 using the etching process described above, the second wafer 1100 can be tested to identify each known good die among the second dies 1200. After the dicing process, each known good second die 1200 can be moved to the second reconstructed wafer 1900 using a pick-and-place device. In some embodiments, the reconstructed wafer may include a release film. Since the second dies 1200 are not flipped during the pick-and-place process, the second warpage control layer 1610 of each second die 1200 will be closest to the second reconstructed wafer 1900.

[0076] During this movement from the second wafer 1100 supported by the dicing tape 1710 to the second reconstructed wafer 1900, each second die 1200b is held by the pick-and-place machine 910, but the bottom of the second die 1200 is unsupported. Therefore, the natural tendency of the second die 1200 is to warp downwards, thus introducing bending into the second die 1200. As described above, the warp control layer 1610 will significantly reduce or eliminate this warping.

[0077] According to some embodiments, a known good second die 1200 can be placed on the second reconstructed wafer 1900 at a location corresponding to a bonding position in the occupied region 1910 of the first die 200 on the first reconstructed wafer 900. For simplicity, only one occupied region 1910 on the second reconstructed wafer 1900 is shown, and only one known good second die 1200 transferred from the second wafer 1100 to the second reconstructed wafer 1900 is shown. However, there is no limitation on the number of known good second dies 1200 slid from the second wafer 1100. Similarly, there is no limitation on the number of known good second dies 1200 that can be transferred from the second wafer 1100 to the second reconstructed wafer 1900. However, design requirements and space constraints of the second wafer 1100 and the second reconstructed wafer 1900 will be taken into account.

[0078] Figure 20 The diagram illustrates a possible configuration on each of the first dies 200, which has two second dies 1200 stacked on the first carrier substrate 1010 after a second conversion process, according to some embodiments.

[0079] In some embodiments, wafer-to-wafer stacking can be used to position a known good second die 1200 on a known good first die 200 and a first carrier substrate 1010 during a second conversion process. The bonding between the second reconstructed wafer 1900 and the known good second die 1200 can then be removed, thereby exposing a second warp control layer 1610 on each known good second die 1200. In embodiments where the second die 1200 includes a TSV in the second substrate 1120, the metal portion of the TSV will also be exposed.

[0080] In some embodiments, further pick-and-place operations may be performed to transfer a known good second die 1200 to a position on top of the first die 200 and the first carrier substrate 1010. During the transition process from the second reconstructed wafer 1900, the associated known good second die 1200 is placed on the associated first die 200 such that the external interconnect layer 1140 of the second die 1200 is in direct contact with the first bonding layer 1030 on the associated first die 200. The second warpage control layer 1610 on each second die 1200 is furthest from the first carrier substrate 1010.

[0081] In a particular embodiment of a dielectric-to-dielectric and metal-to-metal bonding process between the first die 200 and the second die 1200, this process can be initiated by activating the surfaces of the second die 1200 and the first bonding layer 1030. Activating the top surfaces of the first bonding layer 1030 and the second die 1200 can include dry treatment, wet treatment, plasma treatment, exposure to inert gas plasma, exposure to H2, exposure to N2, exposure to O2, combinations thereof, etc., as examples. In embodiments using wet treatment, for example, RCA cleaning can be used. In another embodiment, the activation process can include other types of treatments. The activation process facilitates the bonding of the second die 1200 and the first die 200.

[0082] After the activation process, the first die 200 and the second die 1200 can be cleaned by, for example, chemical rinsing. Then, the second die 1200 is aligned with the first die 200 and placed in solid contact with the first die 200 such that the front side of each second die 1200 (e.g., the exposed surface of the external interconnect layer 1140) is closest to the back side of each first die 200 (e.g., the first substrate 120).

[0083] The first die 200 and the second die 1200 are then subjected to heat treatment and contact pressure to bond the second die 1200 to the first die 200. For example, the first die 200 and the second die 1200 may be subjected to a pressure of about 200 kPa or less and a temperature between about 25°C and about 250°C to fuse the second die 1200 to the first die 200. Then, the first die 200 and the second die 1200 may be subjected to a temperature at or above the eutectic point of the materials of the first bonding pad 1050 and the outer connecting layer 1140, for example, between about 150°C and about 650°C, to fuse the metals. In this way, the second die 1200 and the first die 200 form a dielectric-to-dielectric and metal-to-metal bonding device. In some embodiments, the bonded dies are subsequently baked, annealed, pressed, or otherwise treated to strengthen or complete the bonding.

[0084] Furthermore, while specific processes for initiating and strengthening the bond have been described, these descriptions are intended to be illustrative and not to limit the embodiments. Instead, any suitable combination or combination of processes, such as baking, annealing, and pressing, may be utilized. All such processes are fully intended to be included within the scope of the embodiments.

[0085] In some embodiments, when the second die 1200 is smaller than the first die 200, for example... Figure 20 As shown, a dummy chip 2010 may be further included on the first die 200 to occupy space and provide support and rigidity for the entire package. According to some embodiments, another pick-and-place operation can be used to place the dummy chip 2010 on the first carrier substrate 1010 and the first die 200. If the dummy chip 2010 is placed on the first die before bonding the second die 1200, the dummy chip 2010 can be included in a dielectric-to-dielectric bonding with the first die 200. The dummy chip 2010 can also be attached to the first carrier substrate 1010 by the packaging process described below, or a combination of methods can be used.

[0086] Figure 21The application of an encapsulation 2110 according to some embodiments is illustrated. As shown, the encapsulation 2110 is formed over and around the first carrier substrate 1010, the first die 200, the second die 1200, and the dummy chip 2010. In some embodiments, the encapsulation 2110 may include one or more layers of non-photographically patternable insulating material, such as silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), combinations thereof, and can be formed using CVD, PVD, ALD, spin coating processes, combinations thereof, etc. In other embodiments, the encapsulation 2110 may include one or more layers of photographically patternable insulating material, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), combinations thereof, and can be formed using spin coating processes, etc. Such photographically patternable insulating materials can be patterned using photolithography methods similar to those used for photoresist materials. In other embodiments, the encapsulation 2110 may include a molding compound, such as an epoxy resin, a resin, a moldable polymer, or a combination thereof. The molding compound may be applied in a substantially liquid state and then cured by a chemical reaction, for example, in an epoxy resin or a resin. In other embodiments, the molding compound may be an ultraviolet (UV) or thermosetting polymer that can be applied as a gel or plastic solid disposed around and between the first die 200, the second die 1200, and the dummy chip 2010.

[0087] Figure 22 The diagram illustrates the structure obtained after performing a planarization process on the encapsulation 2110. As shown, the encapsulation 2110 and the second warp control layer 1610 on the second die 1200 are planarized such that the exposed surface of the second warp control layer 1610 is substantially flush with or coplanar with the top surface of the encapsulation 2110. In some embodiments, the planarization process may include a CMP process, a polishing process, an etching process, or a combination thereof. In some embodiments, the planarization process may expose the TSV of the second die 1200 (where the second die 1200 includes such a TSV) such that the exposed surface of the TSV is substantially flush with or coplanar with the top surface of the second warp control layer 1610 and the top surface of the encapsulation 2110. In some embodiments, after the planarization process, the top surface of the dummy chip 2010 is covered by the encapsulation 2110. In some embodiments that include multiple dummy chips 2010 in a single package, some or all of the dummy chips 2010 may remain covered by the encapsulation 2110 after planarization, while the top surface of some or all of the dummy chips 2010 may be exposed and coplanar with the top surface of the encapsulation 2110 (within the process parameters).

[0088] Figure 23The formation of a bonding layer according to some embodiments is illustrated. The first bonding layer 2310 may be formed of a dielectric material such as silicon oxide, silicon nitride, etc. The dielectric material may be deposited using any suitable method, such as CVD, high-density plasma chemical vapor deposition (HDPCVD), PVD, ALD, etc.

[0089] Figure 24 The following are examples illustrating the implementation of some embodiments. Figure 23 A second carrier substrate 2410 is bonded over the intermediate package shown. A second carrier substrate 2410 is provided having a second bonding layer 2420 made of a dielectric material such as silicon oxide or silicon nitride. Any suitable method can be used to deposit the dielectric material, such as CVD, HDPCVD, PVD, ALD, thermal oxidation, etc. The second carrier substrate is placed... Figure 23 The top of the intermediate package shown is such that the first bonding layer 2310 contacts the second bonding layer 2420.

[0090] The second carrier substrate 2410 may be a bulk silicon or other semiconductor material wafer, a silicon-on-insulator (SOI) wafer, etc. The second carrier substrate 2410 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The second carrier substrate 2410 may also contain one or more TSVs (not shown).

[0091] The bonding process can be initiated by activating the exposed surfaces of the first bonding layer 2310 and / or the second bonding layer 2420. Activating the exposed surfaces of the bonding layers may include dry treatment, wet treatment, plasma treatment, exposure to inert gas plasma, exposure to H2, exposure to N2, exposure to O2, combinations thereof, etc., as examples. In embodiments using wet treatment, for example, RCA cleaning may be used. In another embodiment, the activation process may include other types of treatments. The activation process helps the second carrier substrate 2410 and the package to be in a state such that… Figure 24 The bonding shown is in an intermediate state on the first carrier substrate 1010.

[0092] Following the activation process, the first carrier substrate 1010, the associated die, and the second carrier substrate 2410 can be cleaned using, for example, chemical rinsing. The second carrier substrate 2410 is then aligned and positioned in solid contact over the first carrier substrate 1010, such that the first bonding layer 2310 and the second bonding layer 2420 are in solid contact. In some embodiments, the widths of the first carrier substrate 1010 and the second carrier substrate 2410 are equal. In the language of this disclosure, "equal" refers to a variation within 10%.

[0093] Then make Figure 23 The intermediate package and the second carrier substrate 2410 shown are subjected to heat treatment and contact pressure to bond the second carrier substrate 2410 to... Figure 23 The intermediate package shown. For example, the first carrier substrate 1010 and the second carrier substrate 2410 can withstand a pressure of about 200 kPa or less and a temperature between about 25°C and about 250°C to fuse the second carrier substrate 2410 to the first carrier die stack on the substrate 1010. In some embodiments, the bonded carriers are subsequently baked, annealed, pressed, or otherwise treated to strengthen or complete the bonding.

[0094] Figure 25 The removal of a first carrier according to some embodiments is illustrated. A stack including a first carrier substrate 1010, a first die 200, a second die 1200, one or more dummy chips 2010, and a second carrier substrate 2410 can first be flipped to orient the first carrier substrate 1010 side for processing. The first carrier substrate can then be removed from the stack, leaving the first die 200, the second die 1200, one or more dummy chips 2010, and the second carrier substrate 2410. The first carrier substrate 1010 can be removed by thinning processes, bonding removal processes, etc., exposing the top surface of the first interconnect structure 130 of the first die 200. Thinning processes can be performed, for example, using mechanical polishing, chemical methods, or chemical mechanical polishing (CMP) processes, wherein chemical etchants and abrasives are used to react with and remove the first carrier substrate 1010.

[0095] exist Figure 25In the illustrated embodiment, a topmost metallization pattern 2510 may also be formed to provide electrical connection to the metallization pattern 150 in the first interconnect structure 130 of the first die 200. The topmost metallization pattern 2510 may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, or combinations thereof. The topmost metallization pattern 2510 may be formed by a damascene process, such as a single damascene process, a dual damascene process, etc. However, any suitable method for forming the topmost metallization pattern 2510 may be used. In some embodiments, the topmost metallization pattern 2510 may be formed in an earlier portion of the process, including during the formation of the first die 200. In this case, the removal of the first carrier substrate 1010 may also include removing a portion of the first interconnect structure 130 of the first die 200 to expose the topmost metallization pattern 2510 in the first interconnect structure 130. In this way, within the range of process parameters, the front side of the first die 200 may have a flat surface.

[0096] Furthermore, while the CMP process described above is presented as an illustrative embodiment, it is not intended to limit these embodiments. Any other suitable removal process can be used to thin or remove a portion of the first carrier substrate 1010 and / or the first interconnect structure 130 of the first die 200. For example, a series of chemical etching processes can be utilized. This process and any other suitable processes can be used to planarize the first carrier substrate 1010 and the first interconnect structure 130 of the first die 200 within a range of process parameters, and all such processes are fully intended to be included within the scope of the embodiments.

[0097] Figure 26 The diagram illustrates the formation of a passivation layer 2610 and external connections according to some embodiments. In one embodiment, a metallized contact pad 2620 is formed over the topmost dielectric layer 160 of the first interconnect structure 130 of the first die 200. The metallized contact pad 2620 can be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, or combinations thereof. The metallized contact pad 2620 can be formed by a damascene process, such as a single damascene process, a double damascene process, etc. However, any suitable method can be used to form the metallized contact pad 2620.

[0098] In one embodiment, a passivation layer 2610 may be formed over the topmost dielectric layer 160 of the first interconnect structure 130 of the first die 200 and over the metallized contact pad 2620. The passivation layer 2610 may be a material such as nitride, oxide, polyimide, low-temperature polyimide, solder resist, or combinations thereof. Once formed, the passivation layer 2610 may be patterned (e.g., using suitable photolithography and etching processes) to expose portions of the metallized contact pad 2620.

[0099] In one embodiment, under-bump metallization (UBM) 2630 is formed for external connection to the first die 200. UBM 2630 has a bump portion extending on and along the main surface of the passivation layer 2610, and a through-hole portion extending through the passivation layer 2610 to physically electrically couple to the metallized contact pad 2620. UBM 2630 may be formed from the same material and in a similar manner as the metallized contact pad 2620.

[0100] In one embodiment, a conductive connector 2640 is formed on the UBM 2630. The conductive connector 2640 may be a ball grid array (BGA) connector, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using the electroless nickel-electroless palladium-immersion gold technique (ENEPIG), etc. The conductive connector 2640 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, the conductive connector 2640 is initially formed by evaporation, electroplating, printing, solder transfer, ball placement, etc., to form a solder layer. Once the solder layer is structurally formed, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 2640 includes metal pillars (e.g., copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillar can be solderless and has substantially vertical sidewalls. In some embodiments, a metal capping layer is formed on the top of the metal pillar. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or combinations thereof, and can be formed by an electroplating process.

[0101] Subsequently, in some embodiments, a slitting process may be performed around the periphery of the illustrated package area along scribing line 2650. The slitting process may include, for example, sawing, laser ablation, etching, or a combination thereof. However, in certain areas within the region, the slitting process may not be performed. Figure 27 A system-on-integrated-chip (SoIC) package 2700 is shown according to some embodiments. In some embodiments, similar to the removal or thinning of the first carrier substrate 1010, the second carrier substrate 2410 may be thinned or removed.

[0102] Figure 28According to some embodiments, once a unified SoIC package 2700 is formed, it can be attached to a substrate 2810 for coupling the unified SoIC package 2700 with other devices to form, for example, a flip-chip device 2800. The unified SoIC package 2700 and another other die or package can be bonded to the substrate 2810 using, for example, a conductive connector 2640. In one embodiment, the substrate 2810 can be a package substrate, which can be a system board such as a printed circuit board (PCB). The substrate 2810 may include one or more dielectric layers and conductive components, such as wires and vias. In some embodiments, the second substrate 2810 may include vias, active devices, passive devices, etc. The second substrate 2810 may also include conductive pads 2820 formed on the upper surface (shown) and lower surface (not shown) of the second substrate 2910.

[0103] External connector 2830 may be formed on the side of substrate 2810 opposite to the monolithic SoIC package 2700. External connector 2830 may be a ball grid array (BGA) connector, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-palladium immersion gold (ENEPIG) technology, etc. External connector 2830 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, external connector 2830 is initially formed by forming a solder layer through evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is structurally formed, reflow can be performed to shape the material into the desired bump shape. In another embodiment, external connector 2830 includes metal pillars (e.g., copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillars may be solderless and have substantially vertical sidewalls. In some embodiments, a metal capping layer is formed on top of a metal pillar. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or combinations thereof, and may be formed by an electroplating process.

[0104] External connector 2830 can be aligned with a corresponding conductive connection on the second side of substrate 2810 opposite to the monolithic SoIC package 2700. External connector 2830 can then be subsequently reflowed to bond flip chip device 2800 to another device. However, any suitable bonding process can be used for subsequent connection to flip chip device 2800.

[0105] Figure 29This illustrates that once the monolithic SoIC package 2700 is formed, it can be attached to a substrate 2910. The substrate 2910 is used to couple the monolithic SoIC package 2700 to other devices to form, for example, a chip-on-wafer-on-substrate. Device 2900. A single-unit SOIC package 2700 and any other die or package can be bonded to a first side of the interposer 2940 using, for example, a conductive connector 2640. In one embodiment, the interposer 2940 includes a semiconductor substrate 2950, ​​a through-device via (TDV) 2960, and a first external connector 2970. The semiconductor substrate 2950 may include an active layer of doped or undoped bulk silicon or a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate includes a semiconductor material layer, such as silicon, germanium, silicon-germanium, SOI, silicon-germanium-on-insulator (SGOI), or combinations thereof. Other substrates that can be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0106] Optionally, active devices (not shown separately) may be added to the semiconductor substrate 2950. Active devices may include a variety of active and passive devices, such as capacitors, resistors, inductors, etc., which can be used to generate the desired structural and functional requirements of the semiconductor substrate 2950 design. Active devices may be formed within or on the semiconductor substrate 2950 using any suitable method.

[0107] A metallization layer (not shown) may be formed over the semiconductor substrate 2950 and the active devices, and is designed to connect the devices to form a functional circuit. In one embodiment, the metallization layer may be formed of alternating layers of dielectric (e.g., low-k dielectric, very low-k dielectric, ultra-low-k dielectric, combinations of these dielectrics, etc.) and conductive material, and may be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.). However, any suitable materials and processes may still be used.

[0108] Additionally, the TDV 2960 can be formed within the semiconductor substrate 2950 at any desired point in the manufacturing process, and, if desired, one or more metallization layers (not shown) can be formed to provide electrical connections from the front side to the back side of the semiconductor substrate 2950. In one embodiment, the third TDV 2960 can be formed by initially forming a through-device via (TDV) opening in the semiconductor substrate 2950, ​​and, if desired, any covering metallization layer can be formed (e.g., after the desired third metallization layer has been formed but before the formation of the next covering third metallization layer). The TDV opening can be formed by any suitable method.

[0109] Once the unified SoIC package 2700 and any other dies or packages have been bonded to the interposer 2940, the interposer 2940 can be bonded to the second substrate 2910 using, for example, a first external connector 2970. In one embodiment, the second substrate 2910 can be a package substrate, which can be a system board such as a printed circuit board (PCB). The second substrate 2910 may include one or more dielectric layers and conductive components, such as wires and vias. In some embodiments, the second substrate 2910 may include vias, active devices, passive devices, etc. The second substrate 2910 may also include conductive pads 2920 formed on the upper surface (shown) and lower surface (not shown) of the second substrate 2910.

[0110] The first external connector 2970 can be aligned with a corresponding conductive connection on the second substrate 2910 opposite to the interposer 2940 and the unified SoIC package 2700. Once aligned, the first external connector 2970 can then be reflowed to bond the second substrate 2910 to the interposer 2940. However, any suitable bonding process can still be used to connect the interposer 2940 to the second substrate 2910.

[0111] The second external connector 2930 may be formed on the second side of the second substrate 2910 opposite to the monolithic SoIC package 2700. The second external connector 2930 may be a ball grid array (BGA) connector, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-palladium immersion gold (ENEPIG) technology, etc. The second external connector 2930 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, the second external connector 2930 is initially formed by forming a solder layer through evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is structurally formed, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the second external connector 2930 includes metal pillars (e.g., copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillars may be solderless and have substantially vertical sidewalls. In some embodiments, a metal capping layer is formed on top of a metal pillar. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or combinations thereof, and may be formed by a plating process.

[0112] The second external connector 2930 can be aligned with a corresponding conductive connection on the second side of the substrate 2910 opposite the monolithic SoIC package 2700. The second external connector 2930 can then be subsequently reflowed to bond the CoWoS device 2900 to another device. However, any suitable bonding process can still be used subsequently to connect to the CoWoS device 2900.

[0113] Embodiments have been described for a specific context (i.e., application in a System-on-a-Chip (SoIC) package). However, other embodiments may also be applied to other packages and technologies. The embodiments discussed herein will provide examples of how to make or use the objects targeted by this disclosure, and those skilled in the art will readily understand that modifications can be made while remaining within the intended scope of the different embodiments. Similar reference numerals and characters in the following figures refer to similar components. Although method embodiments may be described as being performed in a particular order, other method embodiments may be performed in any logical order.

[0114] By utilizing the methods and processes described above, the formation of joint protrusions and / or non-joints between vertically stacked dies can be reduced or eliminated. Therefore, greater throughput, increased manufacturing efficiency, reduced waste, and lower manufacturing costs can be achieved.

[0115] In a first embodiment, a semiconductor device is provided, the semiconductor device comprising: a first die having a first substrate on a first side and an external electrical connection on a second side opposite to the first side, the first die having a first width; a first warpage control layer disposed on the first substrate on the first side of the first die, wherein the first warpage control layer increases the rigidity of the first die by a higher rigidity than the first die would have in the absence of the first warpage control layer; a second die disposed on the first warpage control layer and opposite to the first die, the second die having a second substrate and a second width; a second warpage control layer disposed on the second die and opposite to the first warpage control layer, wherein the second warpage control layer increases the rigidity of the second die by a higher rigidity than the second die would have in the absence of the second warpage control layer; and a third substrate disposed on the first die and the second die and having a third width.

[0116] In some embodiments, the second width and the third width are smaller than the first width, and the third width is smaller than the second width. In some embodiments, the thickness of the first warp control layer is 10 angstroms to 1000 angstroms, and the first warp control layer is SiO2. x SiN, SiO x N y SiC x Organic materials or dielectric materials. In some embodiments, the thickness of the second warp control layer is from 10 angstroms to 1000 angstroms, and wherein the second warp control layer is SiO2. x SiN, SiO x N y SiC x Organic materials or dielectric materials. In some embodiments, the semiconductor device further includes: a first bonding layer disposed on top of the second warp control layer and opposite to the second die; and a second bonding layer located on the first side of the third substrate closest to the second die. In some embodiments, the sidewalls of the first die do not have the first warp control layer, and the sidewalls of the second die do not have the second warp control layer. In some embodiments, the semiconductor device further includes a plurality of second dies disposed on the first die.

[0117] In a second embodiment, a method for forming a semiconductor device is provided, the method comprising: applying a first warpage control layer to the back side of a first die, wherein the first warpage control layer increases the rigidity of the first die; planarizing the first warpage control layer to flatten the first warpage control layer within process parameters and expose the metal portion of a through-silicon via (TSV) in a substrate of the first die; forming a first bonding layer on the side of the first warpage control layer opposite to the first die, the first bonding layer having a dielectric portion and a metallization pattern electrically connected to the TSV of the first die; forming a second warpage control layer on the back side of a second die, wherein the second warpage control layer increases the rigidity of the second die; bonding the front side of the second die to the first bonding layer such that the second die is electrically connected to the first die through the metallization pattern of the first bonding layer and the TSV of the first die; and forming a set of external interconnects on the front side of the first die opposite to the second die.

[0118] In some embodiments, the thickness of the first warp control layer is from 10 angstroms to 1000 angstroms, and wherein the first warp control layer is SiO2. x SiN, SiO x N y SiC x Organic materials or dielectric materials. In some embodiments, the thickness of the second warp control layer is from 10 angstroms to 1000 angstroms, and wherein the second warp control layer is SiO2. x SiN, SiO x N y SiC x Organic materials or dielectric materials. In some embodiments, the method further includes: applying a molding compound on and around the second die and over the first die; and removing a portion of the molding compound to expose a second warpage control layer on the second die and planarizing the second warpage control layer and the molding compound within a range of process parameters. In some embodiments, the method further includes: arranging a dummy chip on the side of the first warpage control layer opposite to the first die and the same as the second die before applying the molding compound on and around the second die and over the first die; wherein applying the molding compound on and around the second die and over the first die further includes applying the molding compound on and around the dummy chip. In some embodiments, the first warpage control layer encapsulates a portion of the sidewall of the first die that is less than its entire length. In some embodiments, the second warpage control layer does not encapsulate any portion of the sidewall of the second die.

[0119] In a third embodiment, a semiconductor device is provided, the semiconductor device comprising: a first die having a plurality of external electrical connections on a first side; a first warpage control layer disposed on a second side of the first die opposite to the first side, wherein the first warpage control layer restricts bending of the first die when the first die is unsupported on the first side; a second die having a first side disposed on the first warpage control layer opposite to the first die, wherein the second die is electrically connected to the first die; and a second warpage control layer disposed on the second side of the second die opposite to the first side, wherein the second warpage control layer restricts bending of the second die when the second die is unsupported on the first side.

[0120] In some embodiments, the semiconductor device further includes a molding film that encapsulates the sidewalls of the second die and is located above the first die, but does not encapsulate the sidewalls of the first die. In some embodiments, the thickness of the first warp control layer and the second warp control layer is from 10 angstroms to 1000 angstroms, and wherein the first warp control layer and the second warp control layer are SiO2. x SiN, SiO x N y SiC x Organic materials or dielectric materials. In some embodiments, at least one of the first warp control layer or the second warp control layer is a composite film, the composite film comprising materials selected from SiO2. x SiN, SiO x N y SiC x Two or more layers from the group consisting of organic materials and dielectric materials. In some embodiments, a first portion of the sidewall of the first die, less than its entire length, is encapsulated by a first warp control layer, and a second portion of the sidewall of the second die, less than its entire length, is encapsulated by a second warp control layer. In some embodiments, a dummy chip is disposed on the first warp control layer on the same side as the second die and on the side of the first warp control layer opposite to the first die.

[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A semiconductor device, characterized in that, include: A first die has a first substrate on a first side and an external electrical connection on a second side opposite to the first side, and the first die has a first width; A first warp control layer is disposed on the first substrate on the first side of the first die, wherein the first warp control layer increases the rigidity of the first die by a greater degree than the first die would have in the absence of the first warp control layer. The second die is disposed on the first warpage control layer and is opposite to the first die. The second die has a second substrate and a second width. A second warp control layer is disposed on the second die, opposite to the first warp control layer, wherein the second warp control layer increases the rigidity of the second die by a higher degree than the second die would have in the absence of the second warp control layer; as well as A third substrate is disposed above the first die and the second die and has a third width.

2. The semiconductor device according to claim 1, characterized in that, The second width and the first width are both smaller than the third width, and the second width is smaller than the first width.

3. The semiconductor device according to claim 1, characterized in that, Also includes: The first bonding layer is disposed above the second warp control layer and opposite to the second die; as well as The second bonding layer is located on the first side of the third substrate closest to the second die.

4. The semiconductor device according to claim 3, characterized in that, The first die has no first warp control layer on its sidewall, and the second die has no second warp control layer on its sidewall.

5. The semiconductor device according to claim 1, characterized in that, It also includes a plurality of second dies disposed on top of the first die.

6. A semiconductor device, characterized in that, include: The first die has multiple external electrical connections on a first side; A first warpage control layer is disposed on a second side of the first die opposite to the first side, wherein the first warpage control layer restricts the bending of the first die when the first die is unsupported on the first side; A second die, wherein a first side of the second die is disposed on the first warp control layer opposite to the first die, wherein the second die is electrically connected to the first die; as well as A second warp control layer is disposed on the second side of the second die opposite to the first side, wherein the second warp control layer restricts the bending of the second die when the second die is unsupported on the first side.

7. The semiconductor device according to claim 6, characterized in that, It also includes a molding film that encapsulates the sidewall of the second die and is located above the first die, but does not encapsulate the sidewall of the first die.

8. The semiconductor device according to claim 6, characterized in that, At least one of the first warp control layer or the second warp control layer is a composite film.

9. The semiconductor device according to claim 6, characterized in that, A first portion of the sidewall of the first die, less than the entire length, is encapsulated by the first warp control layer, and a second portion of the sidewall of the second die, less than the entire length, is encapsulated by the second warp control layer.

10. The semiconductor device according to claim 6, characterized in that, The dummy chip is positioned on the same side of the first warp control layer as the second die, and on the side of the first warp control layer opposite to the first die.

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