MOSFET transistor

Abstract

The present disclosure relates to MOSFET transistors. A MOSFET transistor includes a semiconductor body having internal trenches and a pair of edge trenches, the internal trenches having an elongated shape parallel to a first direction and being arranged in succession, the edge trenches having an elongated shape parallel to a second direction. An end of each internal trench communicates with a corresponding edge trench. Each edge trench includes a corresponding dielectric trench region. Each internal trench includes a conductive shield region extending inside the internal trench and having an elongated shape parallel to the first direction. A pair of conductive gate regions extend into the internal trench on opposite sides of the conductive shield region and have an elongated shape parallel to the first direction. An end of each conductive shield region penetrates inside the corresponding edge trench. In each edge trench, the ends of adjacent conductive shield regions are separated from each other.

Description

[0001] Priority requirements

[0002] This application claims priority to Italian Patent Application No. 102024000014395, filed on June 21, 2024, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] This disclosure relates to a shielded gate trench MOSFET transistor with an improved edge structure. Background Technology

[0004] As is known, in the field of field-effect transistors for power applications, such as shielded gate trench MOSFET transistors, transistors with high breakdown voltages are required, particularly the so-called drain-source breakdown voltage (referred to in the art as voltage BV) with the third terminal grounded. DSS ). Utility Model Content

[0005] This disclosure relates to a MOSFET transistor, comprising: a semiconductor body; a plurality of internal trenches extending into the semiconductor body and having an elongated shape parallel to a first direction and arranged sequentially; a pair of edge trenches extending into the semiconductor body and having an elongated shape parallel to a second direction transverse to the first direction; wherein an end of each internal trench communicates with a corresponding edge trench in the pair of edge trenches; for each edge trench in the pair of edge trenches, a corresponding dielectric trench region extends into the edge trench; for each of the plurality of internal trenches: a conductive shielding region extends inside the internal trench and has an elongated shape parallel to the first direction; and a first pair of conductive gate regions extend into the internal trench on opposite sides of the conductive shielding region and have an elongated shape parallel to the first direction; and wherein an end of each conductive shielding region penetrates into the interior of a corresponding edge trench; and wherein, in each edge trench, the ends of adjacent conductive shielding regions are separated from each other.

[0006] In one embodiment, in each edge trench, the ends of adjacent conductive shielding regions are separated by a portion of the corresponding dielectric trench region.

[0007] In one embodiment, each edge groove has a first width measured in a direction perpendicular to the second direction; and each inner groove has a second width measured in a direction perpendicular to the first direction; and the first width is less than the second width.

[0008] In one embodiment, the MOSFET transistor further includes a plurality of annular gate regions, wherein each annular gate region is formed of the same material as the conductive gate regions and includes a corresponding pair of conductive gate regions and a pair of lateral gate regions, wherein each lateral gate region extends into a corresponding edge trench and contacts the corresponding conductive gate region.

[0009] In one embodiment, for each edge trench, there is also a corresponding gate shielding contact area formed of conductive material and directly contacting the corresponding ends of the corresponding lateral gate region and the conductive shielding region.

[0010] In one embodiment, the semiconductor body includes an epitaxial region having a first conductivity type and defined by a front surface, and a plurality of body regions having a second conductivity type and extending from the front surface into the epitaxial region; wherein pairs of adjacent internal trenches laterally define corresponding body regions together with corresponding portions of edge trenches; and wherein pairs of conductive gate regions extending into adjacent internal trenches and arranged facing the same body region are separated from the body regions by corresponding dielectric gate regions; the MOSFET transistor for each body region also includes a corresponding source region of the first conductivity type extending from the front surface into a portion of the body region.

[0011] In one embodiment, the MOSFET transistor further includes: a central trench extending into the semiconductor body and having an elongated shape parallel to a second direction, wherein the central trench is spaced between edge trenches and communicates with an inner trench such that the edge trenches, the inner trench, and the central trench laterally define two successive bodies of semiconductor sub-regions of the semiconductor body, each semiconductor sub-region of one successive body being symmetrically arranged with respect to the central trench relative to a corresponding semiconductor sub-region of the other successive body; and for each inner trench, a second pair of conductive gate regions extending on opposite sides of a corresponding conductive shielding region, relative to a corresponding first pair of conductive gate regions. Symmetrical, each conductive gate region has its ends arranged in opposite directions relative to the intermediate trench at a distance relative to the corresponding edge trench; for each pair of symmetrical semiconductor sub-regions, a corresponding lateral gate region is formed of the same material as the conductive gate region and extends into a portion of the intermediate trench between the two symmetrical semiconductor sub-regions; and wherein a pair of conductive gate regions extending into adjacent internal trenches and arranged facing the same semiconductor sub-region are separated from the same semiconductor sub-region by a corresponding dielectric gate region and contact the corresponding lateral gate region, thereby forming a U-shaped patterned gate region.

[0012] In one embodiment, the MOSFET transistor further includes: for each edge trench, a corresponding shielding contact region, the corresponding shielding contact region being formed of a conductive material and directly contacting the corresponding end of the conductive shielding region; and for each lateral gate region, a corresponding gate contact region, the corresponding gate contact region being formed of a conductive material and directly contacting the corresponding lateral gate region, the gate contact regions being electrically contacting each other.

[0013] In one embodiment, the semiconductor body includes: an epitaxial region having a first conductivity type and defined by a front surface; and a plurality of body regions having a second conductivity type and each extending into a corresponding semiconductor region; the MOSFET transistor further includes, for each body region, a corresponding source region of the first conductivity type extending from the front surface into a portion of the body region.

[0014] In one embodiment, the MOSFET transistor further includes an annular trench, the annular trench including edge trenches and extending into the semiconductor body to define an internal region of the semiconductor body, the internal trench extending into the internal region of the semiconductor body. Attached Figure Description

[0015] To better understand this disclosure, embodiments thereof will now be described by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0016] Figure 1 A schematic top view of the semiconductor body accommodating the trench is shown;

[0017] Figure 2 Schematic illustration along Figure 3 A top view of the cross-section of the transistor taken by section line II-II shown in the figure;

[0018] Figure 3 Schematic illustration along Figure 2 The section line III-III shown is the cut-off point. Figure 2 A portion of the cross-section of the transistor shown;

[0019] Figure 4 Schematic illustration along Figure 2 The section line IV-IV shown cuts out the section. Figure 2 A portion of the cross-section of the transistor shown;

[0020] Figure 5 Schematic illustration along Figure 2 The section line VV shown is cut off Figure 2 A portion of the cross-section of the transistor shown;

[0021] Figure 6 Schematic illustration along Figure 7 The top view of the cross-section of this transistor variant, taken by section line VI-VI as shown;

[0022] Figure 7 Schematic illustration along Figure 6 The section line VII-VII shown intercepts... Figure 6 A portion of the cross-section of the transistor shown;

[0023] Figure 8 Schematic illustration along Figure 6 The section line VIII-VIII shown cuts out Figure 6 A portion of the cross-section of the transistor shown;

[0024] Figures 9A-14A The diagram schematically illustrates a section taken along section line IV-IV during subsequent steps of the manufacturing process. Figures 2-5 A portion of the transistor shown;

[0025] Figures 9B-14B The illustration shows the respective locations in Figures 9A-14A The section taken along section line III-III during the same step of the manufacturing process referred to. Figures 2-5 A portion of the transistor shown;

[0026] Figure 12C It schematically shows that in Figure 12A and Figure 12B During the same step of the manufacturing process referred to Figures 2-5 A top view of a portion of the transistor shown;

[0027] Figure 15A and Figure 15B This schematically illustrates the process during the same step of the manufacturing process. Figures 6-8 A top view of different parts of the transistor shown;

[0028] Figure 15C Schematic illustration along Figure 15B The section line XV-XV shown intercepts... Figure 15A and Figure 15B A portion of the cross-section of the transistor shown; and

[0029] Figure 16 A top view of a portion of a further variant of this transistor is schematically shown, with the portion removed. Detailed Implementation

[0030] A voltage-increasing BV DSS Possible solutions in Figure 1The diagram illustrates and envisions that a gate structure and a shielding structure will be housed within the semiconductor body 2. Figure 1 (not shown) trenches Figure 1 T g The end of the indicator and the surrounding groove ( Figure 1 T p (Instructions) Separate. Specifically, trench T g Each end and the surrounding groove T p A spacing d is used to avoid forming a connecting groove with a "T" shaped profile. However, the distance d needs to be compatible with the manufacturing process used. Furthermore, controlling the distance d can be difficult.

[0031] There is a need in the art to provide a shielded gate trench MOSFET transistor that can at least partially overcome the shortcomings of the prior art.

[0032] Figures 2-5 Transistor 10, a shielded gate trench MOSFET transistor, is shown and illustrated in an orthogonal reference frame XYZ.

[0033] like Figure 3 As shown, transistor 10 includes a semiconductor body 12, which is formed of silicon, for example, and includes a substrate 14 with N++ type doping. The substrate 14 has a thickness between, for example, 20 μm and 200 μm and a thickness between, for example, 3*10. 19 With 8*10 19 atoms / cm 3 The doping levels between them.

[0034] The semiconductor body 12 also includes a first epitaxial layer 16 with N-type doping, which is disposed directly on the substrate 14 and has a thickness between, for example, 1 μm and 15 μm and a diameter between, for example, 2*10. 16 With 7*10 16 atoms / cm 3 The doping levels between them.

[0035] The semiconductor body 12 also includes a second epitaxial layer 18 with N-type doping, which is disposed directly above the first epitaxial layer 16, has a thickness between, for example, 1 μm and 3 μm, and has a surface area between, for example, 9*10. 14 With 10 16 atoms / cm 3 The doping levels between. Furthermore, the second epitaxial layer 18 is topped by the front surface S. top The front surface is defined to be approximately parallel to the XY plane and defines the semiconductor body 12 at the top.

[0036] A pair of first peripheral grooves 19 and a pair of second peripheral grooves 21 from the front surface S top It begins to extend into the interior of the semiconductor body 12.

[0037] Without loss of generality, the first and second peripheral trenches 19, 21 have substantially the same depth (along the Z-axis) such that they completely penetrate the second epitaxial layer 18 and the upper portion of the first epitaxial layer 16, but do not penetrate the substrate 14. In other words, the bottom of each of the first or second peripheral trenches 19, 21 extends into the first epitaxial layer 16 and covers the substrate 14 at a distance.

[0038] Similarly, without loss of generality, transistor 10 is approximately symmetrical with respect to a first symmetry plane SP1 parallel to the XZ plane and with respect to a second symmetry plane SP2 parallel to the YZ plane. As described above, and also without loss of generality, the first peripheral trench 19 extends parallel to the first symmetry plane SP1 and is arranged symmetrically with respect to the first symmetry plane SP1; the second peripheral trench 21 extends parallel to the second symmetry plane SP2 and is arranged symmetrically with respect to the second symmetry plane SP2.

[0039] In practice, in a top view, the first and second peripheral grooves 19, 21 are arranged along the sides of a rectangle. Therefore, the first and second peripheral grooves 19, 21 are arranged alternately at an angle to each other.

[0040] More specifically, and without loss of generality, in the top view, the first peripheral groove 19 has an elongated shape parallel to the X-axis and has the same width W1 (measured along the Y-axis), which is approximately constant with respect to translation along the X-axis. The second peripheral groove 21 has an elongated shape parallel to the Y-axis and has the same width W2 (measured along the X-axis), which is approximately constant with respect to translation along the Y-axis and is greater than the width W1. For example, the width W1 may be between 0.5 μm and 1 μm, while the width W2 may be between 1.5 μm and 2 μm.

[0041] like Figure 2 As can be seen, transistor 10 includes four corner trench portions 23, which extend from the front surface S top It begins to extend into the semiconductor body 12 and has approximately the same depth as the first and second peripheral trenches 19, 21. In addition, each corner trench portion 23 is located between the end of the corresponding first peripheral trench 19 and the end of the corresponding second peripheral trench 21, and the two trenches are connected to each other through the corner trench portion 23.

[0042] In the top view, the corner trench portion 23 has a curved shape. In addition, the first and second peripheral trenches 19, 21 and the corner trench portion 23 form an edge trench 25, which has an annular shape (in particular, in the top view, it has a rectangular shape with a beveled vertex) and laterally defines the internal region 26 of the semiconductor body 12.

[0043] In addition, a plurality of internal trenches 20 extend within the semiconductor body 12; for the sake of simplicity of representation and description only, it is assumed, without loss of generality, that the number of internal trenches 20 is three and that they are substantially equal to each other.

[0044] In detail, the internal groove 20 extends from the front surface S top The trenches begin to extend into the semiconductor body 12 and have approximately the same depth as the first and second peripheral trenches 19, 21, thus traversing a portion of the second epitaxial layer 18 and the first epitaxial layer 16. Furthermore, the internal trenches 20 extend parallel to the second plane of symmetry SP2 and are arranged parallel to and offset from the X-axis within the internal region 26 of the semiconductor body 12.

[0045] More specifically, in the top view, the internal grooves 20 have an elongated shape parallel to the Y-axis and a uniform width W3 (measured along the X-axis), which remains approximately constant with translation along the Y-axis. The relationship W3>W1 applies. Furthermore, the relationship W2>W3 can also apply. For example, the width W3 can be between 1.3 μm and 2 μm. Additionally, each internal groove 20 has a pair of ends, each end communicating with a corresponding first peripheral groove 19.

[0046] The semiconductor body 12 also includes a P-type body region 28, which extends from the front surface S top It begins to extend into the portion of the second epitaxial layer 18 laterally defined by the edge trench 25. The body region 28 has a depth of, for example, between 10... 14 With 6*10 16 atoms / cm 3 The doping level is between 0.3 μm and 0.4 μm and the thickness is less than that of the second epitaxial layer 18. For example, the body region 28 has a thickness between 0.3 μm and 0.4 μm.

[0047] Furthermore, the main region 28 is traversed by an internal trench 20, which divides the main region 28 into spatially separated sub-regions 29. Figures 2-5 In the example shown, the number of main sub-regions 29 is four.

[0048] like Figure 2 and Figure 4As can be seen, the semiconductor body 12 also includes an N++ type source region 30, which extends from the front surface S top It begins to extend within a portion of the main body region 28. The source region 30 has a length between, for example, 10, such that a portion of the main body region 28 extends below the source region 30. 17 With 10 20 atoms / cm 3 The doping levels are between 0.2 μm and 0.3 μm, and the thickness is less than that of the main region 28. For example, the source region 30 has a thickness between 0.2 μm and 0.3 μm.

[0049] More in detail, such as Figure 2 As can be seen in the top view, the source region 30 has an approximately rectangular shape and is elongated parallel to the X-axis. Furthermore, the source region 30 extends between the second peripheral trench 21 in direct contact with it, maintains a certain distance from the first peripheral trench 19, and is traversed by the inner trench 20, which divides the source region 30 into spatially separated source region sub-parts 31. Therefore, the source region 30 leaves two exposed portions of the main body region 28, which extend on opposite sides of the source region 30, facing the front surface S. top Each of them contacts the corresponding first peripheral groove 19.

[0050] The sidewalls and bottom of each first peripheral trench 19, each second peripheral trench 21, and each inner trench 20 are coated with a corresponding outer dielectric layer 32, which is formed, for example, by thermal oxide and has a thickness between, for example, 0.7 μm and 1 μm. Furthermore, within each first peripheral trench 19, each second peripheral trench 21, and each inner trench 20, there exists a corresponding inner dielectric region 34, which is formed, for example, by TEOS oxide and is laterally and bottom-surrounded by the corresponding outer dielectric layer 32, and in direct contact with the corresponding outer dielectric layer 32. In practice, each outer dielectric layer 32 and each inner dielectric region 34 form a corresponding dielectric trench region 35; in this respect, for ease of viewing, Figure 2 The distinction between the outer dielectric layer 32 and the inner dielectric region 34 is not shown. Furthermore, the outer dielectric layers 32 are in contact with each other to form a single thermal oxide structure, while the inner dielectric regions 34 are in contact with each other to form a single TEOS oxide structure.

[0051] In practice, such as Figure 2 As can be seen, on opposite sides of each internal trench 20, a pair of corresponding main body sub-regions 29 and a pair of corresponding source region sub-parts 31 extend, as shown in the figure. Figure 4As can be seen, they are in contact with the corresponding portions of the outer dielectric layer 32 of the inner trench 20; the remaining portions of the outer dielectric layer 32 are in contact with the corresponding portions of the first and second epitaxial layers 16, 18. Alternatively, regarding the first peripheral trench 19, as... Figure 2 and Figure 3 As can be seen, in each first peripheral trench 19 arranged facing the inner region 26, a main body sub-region 29 extends, and the main body sub-region 29 contacts the corresponding portion of the outer dielectric layer 32 of the first peripheral trench 19. Alternatively, regarding the second peripheral trench 21, in each second peripheral trench 21 arranged facing the inner region 26, a corresponding main body sub-region 29 and a corresponding source region sub-region 31 extend, and they contact the corresponding portions of the corresponding portions of the outer dielectric layer 32 arranged facing the inner region 26, such as... Figure 4 As can be seen in the text.

[0052] For example, the front dielectric region 36 formed of oxide and silicon nitride is on the front surface S top Extends upwards.

[0053] For each body sub-region 29, transistor 10 also includes a corresponding body-source contact region 40, which, although not shown, may be formed of one or more corresponding metallic material regions. For example, each body-source contact region 40 may be formed of a corresponding multilayer structure (not shown) comprising a first layer of titanium nitride (TiN) and a second layer of tungsten (W) overlying it. In the top view, the body-source contact region 40 has, for example, an approximately rectangular shape, is elongated parallel to the Y-axis, and is approximately positioned at the center of the corresponding body sub-region 29, maintaining a certain distance from the first peripheral trench 19. Furthermore, when the body sub-region 29 is defined by a pair of internal trenches 20, the body-source contact region 40 extends at a certain distance from the pair of internal trenches 20; when the body sub-region 29 is defined by internal trenches 20 and a second peripheral trench 21, the body-source contact region 40 extends at a certain distance from the internal trenches 20 and the second peripheral trench 21.

[0054] More specifically, each host-source contact region 40 extends vertically into the front dielectric region 36 and into a portion of the corresponding host sub-region 29, but does not contact the second epitaxial layer 18. Therefore, the corresponding portion of the corresponding host sub-region 29 exists below each host-source contact region 40.

[0055] More specifically, the body-source contact region 40 has a shape that is approximately symmetrical with respect to the first symmetry plane SP1. Furthermore, without loss of generality, the extension of the body-source contact region 40 is greater than the extension of the source region 30, parallel to the Y-axis. Additionally, each body-source contact region 40 traverses the corresponding source region sub-section 31 perpendicularly (i.e., parallel to the Z-axis) and parallel to the Y-axis, thus dividing the corresponding source region sub-section 31 into a pair of source sub-regions 37, which are spatially separated and extend on opposite sides of the body-source contact region 40 and directly contact it.

[0056] like Figure 4 As can be seen, a portion of the body-source contact region 40 extends above the front dielectric region 36, thereby forming a single conductive body-source contact structure 41 that brings the body region 28 into contact with the source region 30.

[0057] For each host-source contact region 40, the semiconductor host 12 includes a corresponding P++ type enriched host contact region 42, which has, for example, a value between 10 and 10. 18 With 10 19 atoms / cm 3 The doping levels are between 0.3 μm and 0.4 μm, and the thickness is, for example, between 0.3 μm and 0.4 μm. Specifically, each enriched host contact region 42 extends below the corresponding host-source contact region 40, within the portion of the corresponding host sub-region 29 covered by the corresponding host-source contact region 40, and at a distance from the second epitaxial layer 18; each enriched host contact region 42 directly contacts the host-source contact region 40 overlying it and improves the electrical contact between the latter and the host sub-region 29. Furthermore, the enriched host contact region 42 is separated from the source sub-region 37.

[0058] For each internal trench 20, the transistor 10 further includes: a corresponding shielding region 44 formed of polysilicon and having a thickness (measured along the Z-axis) greater than the thickness of the second epitaxial layer 18; and a pair of elongated gate regions 50 formed of polysilicon and having a thickness at least equal to and preferably greater than the thickness of the body region 28 and less than the thickness of the shielding region 44.

[0059] In detail, as a first approximation, each shielding region 44 faces the front surface S. top And extend vertically into the corresponding inner groove 20. Furthermore, in the top view, each shielding region 44 has an elongated shape parallel to the Y-axis and extends parallel to the Y-axis, such that the ends of the shielding regions 44 each penetrate into the corresponding first peripheral groove 19. Figure 5As can be seen in the diagram. In practice, in each first peripheral trench 19, there are multiple ends of the shielding region 44, which are arranged successively approximately parallel to the X-axis, and the successive adjacent ends are separated from each other by portions of the dielectric trench region 35 present in the first peripheral trench 19.

[0060] More in detail, such as Figure 4 As can be seen, each shielding region 44 extends within a corresponding internal trench 20 such that the lower portion of the shielding region 44 is surrounded laterally and at the bottom by and in direct contact with the corresponding internal dielectric region 34. Furthermore, the dielectric trench region 35 of each internal trench 20 includes a pair of dielectric coatings 39. Figure 2 (Not indicated in the text), these coatings are formed, for example, by thermal oxides and applied to the sidewalls of the upper portion of the shielding region 44. In other words, the dielectric coating 39 extends on the opposite side of the upper portion of the shielding region 44, has an elongated shape parallel to the Y-axis, a thickness (measured along the Z-axis) approximately equal to the thickness of the elongated gate region 50, and contacts the corresponding inner dielectric region 34 at the bottom. Furthermore, as Figure 5 As can be seen, the upper and lower portions of each shielding region 44 are in contact with the internal dielectric region 34 of the first peripheral trench 19. In fact, in each first peripheral trench 19, the corresponding portion of the internal dielectric region 34 is laterally coated with the upper portion of the corresponding end of the shielding region 44 and faces the front surface S. top Furthermore, the other portion of the corresponding internal dielectric region 34 is located on the lower part of the corresponding end of the shielding region 44, which is coated laterally and at the bottom.

[0061] Although not shown, the end portion of the dielectric coating 39 can penetrate into the interior of the first peripheral trench 19.

[0062] In each internal trench 20, the corresponding two elongated gate regions 50 approximately extend from the front surface S. top It begins to extend inside the internal trench 20 so as to extend to the opposite side of the upper portion of the shielding area 44 until it contacts the corresponding internal dielectric area 34 at the bottom.

[0063] More specifically, as a first approximation, the elongated gate region 50 has an elongated shape parallel to the Y-axis. Furthermore, each elongated gate region 50 is laterally contacted on its own first side by a corresponding dielectric coating 39, thus the dielectric coating 39 is located between and in direct contact with the upper portion of the shielding region 44. Additionally, each elongated gate region 50 is in contact with a portion of a corresponding external dielectric layer 32 on its own second side opposite to the first side, thus the external dielectric layer 32 is located between and in direct contact with the elongated gate region 50 and the corresponding body sub-region 29.

[0064] In practice, in each internal trench 20, the corresponding internal dielectric region 34 extends below and in direct contact with the corresponding dielectric coating 39 and the corresponding elongated gate region 50.

[0065] For each second peripheral trench 21, the transistor 10 also includes a corresponding shielding region 46 formed of polysilicon and a corresponding elongated gate region 52.

[0066] As a first approximation, each shielded region 46 faces the front surface S top And extends vertically into the corresponding second peripheral groove 21, its thickness being, for example, equal to the thickness of the shielding region 44. Furthermore, as a first approximation, such that the ends of the shielding regions 46 each extend into the corresponding corner groove portion 23, each shielding region 46 has an elongated shape parallel to the Y-axis and extends parallel to the Y-axis, as... Figure 2 As can be seen in the text.

[0067] More in detail, such as Figure 4 As can be seen, each shielding region 46 extends within a corresponding second peripheral trench 21 such that the lower portion of the shielding region 46 is surrounded and directly contacted by the corresponding internal dielectric region 34 on the sides and bottom. Furthermore, the dielectric trench region 35 of each second peripheral trench 21 includes a corresponding dielectric coating 59. Figure 2 (Not shown in the image), the coating, for example, is formed by thermal oxide and directly contacts the sidewalls of the upper portion of the shielding region 46 facing the inner region 26, while the opposite sidewalls of the upper portion of the shielding region 46 are coated with the corresponding inner dielectric region 34. Specifically, the dielectric coating 59 has an elongated shape parallel to the Y-axis and contacts the corresponding inner dielectric region 34 at its bottom. Although not shown, the end portions of the dielectric coating 59 can penetrate into the corresponding corner groove portion 23.

[0068] Furthermore, each elongated gate region 52 has an elongated shape parallel to the Y-axis and approximately extends from the front surface S. topThe elongated gate region 52 begins to extend within the corresponding second peripheral trench 21, and its thickness is approximately equal to, for example, the thickness of the elongated gate region 50. Furthermore, each elongated gate region 52 extends directly between a corresponding dielectric coating 59 and a portion of a corresponding outer dielectric layer 32, wherein the thickness of the corresponding dielectric coating 59 (measured along the Z-axis) is approximately equal to the thickness of the elongated gate region 52, and this portion of the corresponding outer dielectric layer 32 is therefore directly between the elongated gate region 52 and the corresponding body sub-region 29. Additionally, each elongated gate region 52 extends vertically to contact the corresponding inner dielectric region 34 at its bottom. In other words, in each second peripheral trench 21, a portion of the corresponding inner dielectric region 34 extends below the corresponding dielectric coating 59 and the corresponding elongated gate region 52.

[0069] In practice, each body sub-region 29 and each source sub-region 31 are situated between a pair of corresponding elongated gate regions (each pair is formed by an elongated gate region 52 and an elongated gate region 50 arranged facing the body sub-region 29, or by alternating elongated gate regions 50), and are thus electrically coupled to and partially separated by the external dielectric layer 32. Again, in other words, it is observed that the elongated gate region 52 of the second peripheral trench 21 and the elongated gate region 50 of the inner trench 20 define a successor body of elongated gate regions along the X-axis, with each body sub-region 29 situated between two corresponding adjacent elongated gate regions of this successor body. Furthermore, both the elongated gate region 52 of the second peripheral trench 21 and the elongated gate region 50 of the inner trench 20 have ends that penetrate into the interior of the first peripheral trench 19.

[0070] For each main body sub-region 29, the transistor 10 also includes a corresponding pair of lateral gate regions 60, such that the two lateral gate regions 60 are arranged in an approximately symmetrical manner with respect to the first symmetry plane SP1 on opposite sides of the main body sub-region 29, each lateral gate region 60 being formed of polysilicon and disposed in a corresponding first peripheral trench 19. Furthermore, such that the pair of lateral gate regions 60 together with such elongated gate regions form a single corresponding annular gate region 61, each lateral gate region 60 having an end connected to a corresponding end of the elongated gate region electrically coupled to the main body sub-region 29, the annular gate region 61 having an approximately symmetrical shape with respect to the first symmetry plane SP1 and laterally surrounding the main body sub-region 29.

[0071] More specifically, for the sake of brevity, only a single first peripheral trench 19 is referenced as a first approximation, and the corresponding lateral gate region 60 extends from the front surface S. top It begins to extend into the first peripheral trench 19, having a thickness approximately the same as that of the elongated gate region 50 and the elongated gate region 52. Furthermore, as... Figure 3As can be seen, each lateral gate region 60 is separated from the corresponding body sub-region 29 by a portion of the outer dielectric layer 32 of the first peripheral trench 19. This portion of the outer dielectric layer 32 extends on one side of the lateral gate region 60, while the other side and bottom of the lateral gate region 60 are in contact with the inner dielectric region 34 of the first peripheral trench 19.

[0072] For each first peripheral trench 19, the transistor 10 also includes a corresponding shielding contact region 70 formed of a conductive material. In this respect, although not shown in detail, the shielding contact region 70 can be formed of one or more corresponding metallic material regions, and thus can be formed, for example, of a multilayer structure (not shown) comprising a first layer of titanium nitride (TiN) and a second layer of tungsten (W) overlying it. Without loss of generality, the two shielding contact regions 70 are approximately equal to each other and arranged, for example, in an approximately symmetrical manner with respect to a first plane of symmetry SP1.

[0073] More specifically, in the top view, the shielding contact region 70 has an elongated shape parallel to the Y-axis. Furthermore, each shielding contact region 70 extends into the front dielectric region 36, thereby penetrating into the upper portion of the corresponding first peripheral trench 19 and contacting the ends of the lateral gate region 60 and the shielding region 44 extending into the first peripheral trench 19, as shown below. Figure 3 and Figure 5 As can be seen in the text.

[0074] More specifically, the shielding contact region 70 has an approximately constant thickness with respect to translations parallel to the Y-axis. Furthermore, for simplicity, only a single shielding contact region 70 is referred to, and without loss of generality, this shielding contact region 70 extends within the semiconductor body 12 to a depth approximately equal to the maximum depth reached by the body-source contact region 40 and less than the maximum depth reached by the lateral gate region 60; thus, the shielding contact region 70 extends partially within the corresponding lateral gate region 60 and the corresponding shielding region 44, and also contacts the internal dielectric region 34 of the corresponding first peripheral trench 19.

[0075] The transistor 10 further includes: a lower metallization 100, used as a drain metallization, which is formed, for example, by a multilayer conductive structure (e.g., a three-layer structure of titanium, nickel, vanadium, and silver) and extends directly below the substrate 14; a body-source metallization 140, which is formed, for example, by an aluminum and copper alloy and extends directly above the conductive body-source contact structure 41; and a shield metallization 170 having an annular shape (details not visible), which is formed, for example, by an aluminum and copper alloy and extends directly above the shield contact region 70.

[0076] Transistor 10 also includes four peripheral contacts 69, which are only located on the outermost side of the transistor. Figure 2 Visible and symmetrically arranged with respect to the first and second symmetry planes SP1, SP2. Specifically, although not shown, the four peripheral contacts 69 extend into the front dielectric region 36 in such a manner that the first pair of peripheral contacts 69 penetrates into one of the two second peripheral trenches 21 and the second pair of peripheral contacts 69 penetrates into the other second peripheral trench 21. Each peripheral contact 69 contacts the corresponding shielding region 46 and the corresponding elongated gate region 52. Furthermore, although not shown, the peripheral contacts 69 may be formed of corresponding multilayer conductive structures, each multilayer conductive structure including, for example, a region of titanium nitride (TiN) and a region of tungsten (W) coated thereon. Additionally, the peripheral contacts 69 may contact the shielding metallization 170, thereby short-circuiting each other.

[0077] Transistor 10 also includes a passivation region 101, which is formed, for example, by nitrides and oxides and extends over the body-source metallization 140 and the shield metallization 170.

[0078] In practice, transistor 10 is a vertically conductive device, wherein a conductive channel is formed in the portion of the body sub-region 29 extending below the source region 37 and partially contacting the external dielectric layer 32. Furthermore, it should be noted that, due to the fact that only the ends of the shielding region penetrate into the first peripheral trench 19, and therefore there is no shielding region with an elongated shape parallel to the X-axis inside the first peripheral trench 19, transistor 10 is characterized by a high voltage BV. DSS Furthermore, transistor 10 can be manufactured without employing complex techniques to control the distance between trenches. Additionally, in this embodiment, the shielding contact region 70 serves as both the gate and the shielding contact.

[0079] Figure 6 One possible variant is shown, now referenced with Figures 2-5 The differences shown are used to describe this variant; unless otherwise stated, Figures 2-5 Elements that already exist in the figure are indicated by the same reference numerals.

[0080] In detail, the intermediate trench 200 extends into the semiconductor body 12 in an approximately symmetrical manner with respect to the first symmetry plane SP1. In the top view, the intermediate trench 200 has an elongated shape parallel to the X-axis and a width W4 (measured along the Y-axis) that is approximately constant with respect to translation along the X-axis and, for example, approximately equal to the width W1.

[0081] More specifically, the intermediate groove 200 extends from the front surface S topIt begins to extend inside the semiconductor body 12, with a depth approximately equal to, for example, the depths of the first and second peripheral trenches 19, 21 and the internal trench 20. Furthermore, the ends of the intermediate trench 200 are connected to the second peripheral trench 21.

[0082] The intermediate trench 200 divides each main sub-region 29 into a corresponding pair of basic main regions 229, which are arranged symmetrically with respect to the first symmetry plane SP1. In the example shown, for simplicity, only eight basic main regions 229 exist.

[0083] Furthermore, transistor 10 includes two source regions 230 arranged on opposite sides of intermediate trench 200. Each source region 230 is divided into corresponding source region sub-parts 231 by inner trench 20. Additionally, for each source region 230, transistor 10 includes a plurality of corresponding body-source contact regions 240, the number of which equals the number of corresponding source region sub-parts 231 (four in this example). Regarding the shape and arrangement of these corresponding body-source contact regions 240 relative to source regions 230, reference to body-source contact regions 40 and source regions 30 applies; thus, each body-source contact region 240 divides the corresponding source region sub-part 231 into a pair of source sub-regions 237, which are separated from each other and extend on opposite sides of the body-source contact region 240, directly contacting it. Although not shown, the body-source contact region 240 of each source region 230 achieves electrical contact through a corresponding body-source metallization, for example in the same manner as that already described with reference to the body-source contact region 40 and the body-source metallization 140.

[0084] Within each internal trench 20, instead of each elongated gate region 50, there exists a corresponding pair of elongated gate regions 250. These elongated gate regions 250 are also formed of polysilicon and extend on opposite sides of the intermediate trench 200, symmetrical with respect to the first symmetry plane SP1, and have an elongated shape parallel to the Y-axis and aligned with each other. Although not shown, the elongated gate regions 250 approximately extend from the front surface S top It begins to extend within the corresponding internal groove 20 and has a thickness approximately equal to or greater than the thickness of the main body region 28.

[0085] Inside each second peripheral trench 21, instead of the corresponding elongated gate region 52, there is a corresponding pair of elongated gate regions 252, which are also formed of polysilicon, extend symmetrically with respect to the first symmetry plane SP1 and have elongated shapes aligned with each other parallel to the Y-axis.

[0086] Both the elongated gate region 250 and the elongated gate region 252 have corresponding ends that penetrate into the intermediate trench 200 and opposite ends that face and are arranged at a certain distance from the first peripheral trench 19. Therefore, both the elongated gate region 250 and the elongated gate region 252 are arranged at a certain distance from the first peripheral trench 19.

[0087] More specifically, the basic body region 229 is arranged such that two successors forming the basic body region 229 are arranged on opposite sides of the intermediate trench 200. Furthermore, elongated gate regions 250 and 252 also form two successors along the X-axis, arranged on opposite sides of the intermediate trench 200. Each basic body region 229 is situated between two corresponding adjacent elongated gate regions of the respective successor. Additionally, each source region sub-part 231 is situated between two corresponding adjacent elongated gate regions of the respective successor.

[0088] For each pair of basic body regions 229 symmetrically arranged relative to the intermediate trench 200, the transistor 10 also includes a corresponding lateral gate region 260 extending into the portion of the intermediate trench 200 between the two basic body regions 229 and contacting the four ends of the corresponding elongated gate region near the intermediate trench 200, thereby forming a pair of patterned gate regions 261 that are approximately “U”-shaped in the top view and symmetrically arranged relative to the first symmetry plane SP1, such that the two patterned gate regions 261 are connected to each other and form a single polysilicon region with double “U” shapes, with the two ends of each “U” facing the corresponding first peripheral trench 19 and the two “U” shapes contacting each other.

[0089] In practice, transistor 10 includes a patterned gate region 261 instead of the annular gate region 61, which is separated from the first peripheral trench 19. Therefore, the shielding contact region 70 does not contact the patterned gate region 261. Furthermore, the peripheral contact 69 also does not contact the patterned gate region 261, but only the shielding region 46. Although not shown, the shielding metallization 170 still contacts the peripheral contact 69.

[0090] like Figure 7 As shown, within the intermediate trench 200, there exists a corresponding internal dielectric region 234, which is formed of, for example, TEOS oxide and is directly surrounded on the sides and bottom by a corresponding external dielectric layer 232, which coats the sidewalls and bottom of the intermediate trench 200. For ease of viewing, Figure 6The distinction between the outer dielectric layer 232 and the inner dielectric region 234 is not shown. Although not shown, the outer dielectric layer 232 is in contact with the outer dielectric layer 32 present in the inner trench 20 and the second peripheral trench 21; the inner dielectric region 234 is in contact with the inner dielectric region 34 present in the inner trench 20 and the second peripheral trench 21.

[0091] In addition, such as Figure 7 and Figure 8 As shown, each lateral gate region 260 approximately extends from the front surface S top It begins to extend within the intermediate trench 200 and has approximately the same thickness as the elongated gate regions 250 and 252. Furthermore, each lateral gate region 260 is laterally separated from the two corresponding basic body regions 229 by a corresponding portion of the outer dielectric layer 232 and contacts the inner dielectric region 234 at its bottom.

[0092] like Figures 6-8 As shown, for each lateral gate region 260, the transistor 10 also includes a corresponding gate contact region 270 that extends through the front dielectric region 36, thereby contacting the corresponding lateral gate region 260 at the bottom. Furthermore, as... Figure 8 As can be seen, the gate contact region 270 extends partially over the front dielectric region 36 to form a single conductive gate contact structure 271, which is electrically in contact with the lateral gate region 260 and is directly covered thereon by the gate metallization 370, which is formed, for example, by an aluminum and copper alloy and is further covered thereon by the passivation region 101.

[0093] In practice, the shielding metallization 170 forms electrical contacts for separate shielding regions 44, 46, which are electrically decoupled from the patterned gate region 261. Furthermore, the gate metallization 370 is electrically contacted with the patterned gate region 261, but electrically decoupled from the shielding regions 44, 46. Therefore, in this variant, the transistor 10 has gate and shielding contacts that are independent of each other. Thus, the patterned gate region 261 and the shielding regions 44, 46 can be biased independently of each other while maintaining the previously described condition of increasing voltage BV. DSS They share the same advantages.

[0094] Transistor 10 can be referenced, for example, by the following example. Figures 2-5 The embodiments shown are manufactured using the manufacturing method described. Furthermore, for the sake of brevity, details of the manufacturing process related to the portion of the transistor 10 arranged beneath the substrate 14 are not described or shown below.

[0095] First, such as Figure 9A and Figure 9BAs shown, substrate 14, first and second epitaxial layers 16 and 18 are formed in a manner known per se. In addition, first and second peripheral trenches 19 and 21 and internal trench 20 are formed.

[0096] Then, as Figure 10A and Figure 10B As shown, a thermal oxidation process and a subsequent TEOS oxide deposition process are performed to form an inner dielectric region 34 and an outer dielectric layer 32. The inner dielectric region 34 forms a single TEOS oxide region, and the outer dielectric layer 32, together with the first process layer 82 of the thermal oxidation, forms a single thermal oxide region. This single thermal oxide region extends over the portion of the second epitaxial layer 18 disposed outside the edge trench 25 and over the portion of the second epitaxial layer 18 between the inner trench 20 and the first and second peripheral trenches 19, 21.

[0097] In addition, such as Figure 10B As can be seen, the TEOS oxide deposition process causes the internal dielectric region 34 present in each first peripheral trench 19 to fill the first peripheral trench 19 together with the corresponding external dielectric layer 32. Alternatively, in the second peripheral trench 21 and the internal trench 20, the internal dielectric region 34 does not completely fill the trench, but defines corresponding pre-cavity TP on the sides and bottom, such as... Figure 10A As can be seen in the diagram. Although not shown, the ends of the pre-cavity TP present in the internal trench 20 each partially penetrate the interior of the corresponding first peripheral trench 19. In other words, the TEOS oxide deposition process is performed on the vertical walls of each trench in such a way that the internal dielectric region 34 formed in each first peripheral trench 19 completely closes the portion of the first peripheral trench 19 between the internal trenches 20.

[0098] During this step of the manufacturing process, the internal dielectric region 34 present in the first and second peripheral trenches 19, 21 and the internal trench 20 also occupies the portion of the corresponding trench intended to be occupied by the annular gate region 61.

[0099] Subsequently, as Figure 11A and Figure 11B As shown, shielding regions 44 and 46 are formed within the pre-cavity TP in the inner trench 20 and the pre-cavity TP in the second peripheral trench 21, respectively. For this purpose, for example, polysilicon is deposited within the pre-cavity TP, and then the portion of the deposited polysilicon extending outside the inner trench 20 and the second peripheral trench 21 (not shown) is removed. Since only the end of the pre-cavity TP formed in the inner trench 20 extends into the first peripheral trench 19, only the end of the shielding region 44 penetrates into the first peripheral trench 19, as explained above.

[0100] Furthermore, both the shielding region 44 present in the internal trench 20 and the shielding region 46 present in the second peripheral region 21 are surrounded laterally and at the bottom by corresponding internal dielectric regions 34.

[0101] Then, again Figure 11A and Figure 11B As shown, on the front surface S top A photoresist mask 80 is disposed above, covering: the portion of the shielding region 46 and the corresponding internal dielectric region 34 disposed outside the shielding region 46 (i.e., on the side of the shielding region 46 opposite to the internal region 26 of the semiconductor body 12), and the portion of the external dielectric layer 32 between the aforementioned portion of the corresponding internal dielectric region 34 and the semiconductor body 12; furthermore, as Figure 11B As shown, a portion of the internal dielectric region 34 disposed in the first peripheral trench 19, which faces in the opposite direction to the internal region 26 of the semiconductor body 12, and a corresponding portion of the external dielectric layer 32 adjacent to the internal region 26 of the semiconductor body 12. In practice, in each first peripheral trench 19, the mask 80 exposes a portion of the corresponding internal dielectric region 34, which is disposed facing the internal region 26 of the semiconductor body 12.

[0102] Then, as Figure 12A , Figure 12B and Figure 12CAs shown, etching (e.g., time-etching, wet-type etching, or plasma etching) is performed through mask 80 to selectively remove dielectric material without etching semiconductor material. Specifically, etching allows for the selective removal of portions of the first process layer 82 exposed by mask 80. For each internal trench 20, etching also selectively removes a pair of portions of the corresponding internal dielectric region 34 disposed on opposite sides of the upper portion of the corresponding shielding region 44, and portions of the corresponding external dielectric layer 32 respectively contacting this pair of portions of the corresponding internal dielectric region 34, thereby exposing the upper portion of the corresponding shielding region 44 and the portion of the second epitaxial layer 18 facing the internal trench 20, and forming a pair of corresponding temporary cavities 84 extending on opposite sides of the shielding region 44 and precisely laterally defined by the upper portion of the shielding region 44 and the corresponding exposed portions of the second epitaxial layer 18. Furthermore, for each second peripheral trench 21, etching selectively removes a portion of the corresponding inner dielectric region 34 between the upper portion of the corresponding shielding region 46 and the inner region 26 of the semiconductor body 12, and a portion of the corresponding outer dielectric layer 32 between the aforementioned portion of the corresponding inner dielectric region 34 and the inner region 26 of the semiconductor body 12, to expose one side of the upper portion of the corresponding shielding region 46 and a portion of the second epitaxial layer 18 facing the second peripheral trench 21, and to form a corresponding temporary cavity 85. Moreover, for each first peripheral trench 19, etching selectively removes a portion of the corresponding inner dielectric region 34 exposed by the mask 80 and a portion of the corresponding outer dielectric layer 32 between the portion of the corresponding inner dielectric region 34 exposed by the mask 80 and the inner region 26 of the semiconductor body 12, to expose the portion of the second epitaxial layer 18 facing the first peripheral trench 19, and to form a corresponding temporary cavity 86 in each first peripheral trench 19.

[0103] In practice, the exposure of the aforementioned portion of the second epitaxial layer 18 is achieved, in particular, by removing the corresponding portion of the outer dielectric layer 32. In this regard, etching causes the removal of the dielectric material to occur, for example, in an anisotropic manner. Furthermore, as... Figure 12B and Figure 12C As can be seen, each temporary cavity 86 has an approximately elongated shape parallel to the Y-axis and is defined at its bottom and on its first side by an internal dielectric region 34 of a corresponding first peripheral trench 19, and on its second side opposite to the first side by a portion of the second epitaxial layer 18 facing the first peripheral trench 19.

[0104] More in detail, such as Figure 12CAs can be seen, each temporary cavity 86 is connected to a pair of adjacent temporary cavities 84, or connected to a temporary cavity 85 and connected to a temporary cavity 84 adjacent to the temporary cavity 85. Furthermore, in each first peripheral trench 19, adjacent temporary cavities 86 are separated by corresponding ends of the shielding region 44.

[0105] Then, mask 80 is removed. Furthermore, to improve the interface between silicon and gate oxide, a process for forming and subsequently removing sacrificial oxide (not shown) can be performed on the exposed portions of shielded regions 44, 46, in a manner that is optional and not shown here. For simplicity, it will be assumed below that this process of forming and subsequently removing sacrificial oxide is not performed.

[0106] Subsequently, as Figure 13A and Figure 13B As shown, a thermal oxidation process is performed in such a way that the previously removed portion of the outer dielectric layer 32 is restored and dielectric coatings 39, 59 are formed. This oxidation also requires the formation of a second process layer 89 of thermal oxide, which extends over the second epitaxial layer 18 and shielding regions 44, 46 and is intended to form a portion of the front dielectric region 36. Furthermore, this oxidation also requires that the width (measured along the X-axis) of the upper portion of the shielding regions 44, 46 be reduced relative to the width of the corresponding lower portion.

[0107] Subsequently, as Figure 14A and Figure 14B As shown, an elongated gate region 52, an elongated gate region 50, and a lateral gate region 60 are formed in temporary cavities 85, 84, and 86, respectively. In this way, the annular gate region 60 is formed. For example, the elongated gate region 52, the elongated gate region 50, and the lateral gate region 60 are formed by, for example, depositing polysilicon using N-type doping, and a subsequent "etch-back" process to remove the S-type doped silicon deposited on the front surface. top The polysilicon portion above, and particularly above the second process layer 89 (not shown).

[0108] The manufacturing process is then performed in a manner known per se and therefore not shown, including the formation of the pre-dielectric region 36 (e.g., by front-side deposition of a layer of silicon nitride) and the implantation of P-type dopant to form the host region 28 and enrich the host contact region 42. Then, N-type dopant implantation is performed to form the source region 30. Subsequently, the host-source contact region 40, the shielding contact region 70, and the peripheral contact 69 are formed in a manner known per se.

[0109] Figures 6-8 The embodiments shown can be manufactured using the same manufacturing process described above, but the following modifications are required.

[0110] In particular, such as Figure 15A As shown, the resist mask (indicated here by 580) completely covers the first peripheral trench 19 and the portion of the inner trench 20 adjacent to the first peripheral trench 19 to protect the dielectric material contained therein. In this way, the previously referenced... Figures 12A-12C The etching process described above does not result in the formation of a temporary cavity 86 in the first peripheral trench 19. Furthermore, the temporary cavities (indicated here by 584 and 585) formed in the inner trench 20 and the second peripheral trench 21, respectively, extend a distance from the first peripheral trench 19 and are respectively designed to accommodate the elongated gate region 250 and the elongated gate region 252. Additionally, as... Figure 15B and Figure 15C As can be seen in the previous reference Figures 12A-12C The aforementioned etching process results in the formation of a successor body of a temporary cavity 560 within the intermediate trench 200, the temporary cavity 560 being designed to accommodate the lateral gate region 260 and, as Figure 15C As can be seen, the bottom is defined by corresponding portions of the outer dielectric layer 232 and the inner dielectric region 234, and laterally by corresponding exposed portions of the second epitaxial layer 18. Adjacent temporary cavities 560 are separated by corresponding portions of the shielding region 44.

[0111] Then, the manufacturing process is carried out in the same manner as described above.

[0112] The advantages offered by this transistor are clearly evident from the preceding description, especially regarding the voltage BV. DSS An increase compared to known types of transistors, without the need for complex manufacturing techniques. Voltage BV DSS The increase is achieved because, in each first peripheral trench 19, the ends of adjacent shielding regions 44 are, in any case, laterally separated from each other due to the partial insertion of the corresponding dielectric trench region 35, and Figures 2-5 In the embodiment shown, there is also an insertion of a corresponding lateral gate region 60.

[0113] Finally, it is clear that modifications and variations can be made to the transistors and manufacturing processes described above without departing from the scope of this disclosure as defined in the appended claims.

[0114] For example, the number, shape, and arrangement of the peripheral contact elements 69 may differ from those already described; the identical presence of the peripheral contact elements 69 is optional. The enriched main contact area 42 may not exist.

[0115] The shapes of the shielding region, elongated gate region, and lateral gate region may differ from those already described. For example, in Figures 6-8 In the embodiment shown, the shielding region 44 may include an enlarged region at the internal trench 200, such as Figure 15B As shown in the figure. More generally, the shapes of the shielding region and the elongated gate region may not be approximately invariant with respect to translation along the respective elongated direction.

[0116] The type of doping can be the opposite of what has been described.

[0117] The second epitaxial layer 18 may not exist.

[0118] Finally, as Figure 16 As shown, undeclared variants are possible, and these variants are related to... Figures 6-8 The variants shown differ in that in each first peripheral groove 19 ( Figure 16 (Only one is shown in the image) There is a corresponding polysilicon lateral shielding region 646, which has an elongated shape parallel to the X-axis and contacts shielding regions 44 and 46.

[0119] Although Figure 16 Not shown, but the gate contact region 270 still allows contact with the patterned gate region 261, while the shielding contact region indicated here by 670 ( Figure 16 Only one of the gate contacts (shown as a diagonal dashed line) is visible, and it contacts the lateral shielding region 646 below. In this way, the shielding contact and the gate contact are independent of each other.

[0120] The embodiment includes a shielded gate trench MOSFET transistor.

[0121] Examples include a manufacturing process for fabricating shielded gate trench MOSFET transistors.

[0122] In an embodiment, the MOSFET transistor includes: a semiconductor body; a plurality of internal trenches extending into the semiconductor body, having elongated shapes parallel to a first direction and arranged sequentially; and a pair of edge trenches extending into the semiconductor body and having elongated shapes parallel to a second direction transverse to the first direction, wherein each internal trench has an end communicating with a corresponding edge trench.

[0123] For each edge trench, the MOSFET transistor also includes a corresponding dielectric trench region extending into the edge trench.

[0124] For each internal trench, the MOSFET transistor further includes: a conductive shielding region extending within the internal trench and having an elongated shape parallel to a first direction; and a first pair of conductive gate regions extending into the internal trench on opposite sides of the conductive shielding region and having elongated shapes parallel to the first direction. Each conductive shielding region has an end extending into the interior of a corresponding edge trench. In each edge trench, the ends of adjacent conductive shielding regions are separated from each other.

[0125] In one embodiment, a process for manufacturing a MOSFET transistor includes: forming a plurality of internal trenches extending into a semiconductor body, the internal trenches having an elongated shape parallel to a first direction and being arranged sequentially; and forming a pair of edge trenches extending into the semiconductor body and having an elongated shape parallel to a second direction transverse to the first direction, each internal trench having an end communicating with a corresponding edge trench.

[0126] The manufacturing process also includes forming a corresponding dielectric trench region in each edge trench.

[0127] For each internal trench, the manufacturing process further includes: forming a conductive shielding region extending into the internal trench and having an elongated shape parallel to a first direction; and forming a first pair of conductive gate regions extending into the internal trench on opposite sides of the conductive shielding region and having an elongated shape parallel to the first direction.

[0128] Each conductive shielding region has its own end that penetrates into the corresponding edge trench. At each edge trench, the ends of adjacent conductive shielding regions are separated from each other.

[0129] According to one aspect of this disclosure, a process for manufacturing a MOSFET transistor is provided, comprising: forming a plurality of internal trenches extending into a semiconductor body and having an elongated shape parallel to a first direction and arranged sequentially; and forming a pair of edge trenches extending into the semiconductor body and having an elongated shape parallel to a second direction transverse to the first direction; wherein an end of each internal trench communicates with a corresponding edge trench; forming a corresponding dielectric trench region in each edge trench; for each internal trench: forming a conductive shielding region extending inside the internal trench and having an elongated shape parallel to the first direction; and forming a first pair of conductive gate regions extending into the internal trench from opposite sides of the conductive shielding region and having an elongated shape parallel to the first direction; and wherein an end of each conductive shielding region penetrates into the interior of a corresponding edge trench; and wherein, in each edge trench, the ends of adjacent conductive shielding regions are separated from each other.

[0130] In one embodiment, in each edge trench, the ends of adjacent conductive shielding regions are separated by a portion of the corresponding dielectric trench region.

[0131] In one embodiment, the manufacturing process further includes forming a plurality of annular gate regions made of the same material as the conductive gate regions, each annular gate region including a corresponding pair of conductive gate regions and a pair of lateral gate regions, each lateral gate region extending into a corresponding edge trench and contacting the corresponding conductive gate region.

[0132] In one embodiment, the manufacturing process further includes forming a corresponding gate shielding contact area for each edge trench, the corresponding gate shielding contact area being formed of a conductive material and directly contacting the corresponding ends of the corresponding lateral gate area and the conductive shielding area.

[0133] In one embodiment, the manufacturing process further includes: forming an intermediate trench extending into the semiconductor body and having an elongated shape parallel to a second direction, wherein the intermediate trench is located between an edge trench and an inner trench at a certain distance and communicates with the inner trench, such that the edge trench, the inner trench, and the intermediate trench laterally define two successive bodies of semiconductor sub-regions of the semiconductor body, wherein each semiconductor sub-region of one successive body is symmetrically arranged with respect to the intermediate trench with respect to a corresponding semiconductor sub-region of the other successive body; for each inner trench, forming a second pair of conductive gate regions, the second pair of conductive gate regions extending on opposite sides of a corresponding conductive shielding region, relative to a corresponding first pair of conductive gate regions. The domain is symmetrical, with the ends of each conductive gate region arranged in opposite directions relative to the intermediate trench at a distance relative to the corresponding edge trench; for each pair of symmetrical semiconductor sub-regions, a corresponding lateral gate region is formed, which is made of the same material as the conductive gate region and extends into a portion of the intermediate trench between the two symmetrical semiconductor sub-regions; and wherein pairs of conductive gate regions extending into adjacent internal trenches and arranged facing the same semiconductor sub-region are separated from the same semiconductor sub-region by a corresponding dielectric gate region and contact the corresponding lateral gate region, thereby forming a U-shaped patterned gate region.

[0134] In one embodiment, the manufacturing process further includes: for each edge trench, forming a corresponding shielding contact region made of conductive material and directly contacting the corresponding end of the conductive shielding region; and for each lateral gate region, forming a corresponding gate contact region made of conductive material and directly contacting the corresponding lateral gate region, the gate contact regions being in electrical contact with each other.

[0135] In one embodiment, the edge trench has a first width measured in a direction perpendicular to a second direction; and the inner trench has a second width measured in a direction perpendicular to the first direction, and the first width is less than the second width; the manufacturing process further includes: after forming the edge trench and the inner trench, forming a dielectric material in the edge trench and the inner trench to form a corresponding dielectric trench region in the edge trench, the corresponding dielectric trench region closing the portion of the corresponding edge trench between the inner trenches, and wherein the dielectric material formed in the inner trench laterally defines a corresponding pre-cavity; and forming a conductive shielding region in the pre-cavity.

[0136] In one embodiment, the manufacturing process further includes: after forming the conductive shielding region, selectively removing dielectric material from an internal trench to form a temporary cavity defined by a front portion of the shielding region and laterally by an exposed portion of the semiconductor body; coating the front portion of the shielding region and the exposed portion of the semiconductor body that laterally define the temporary cavity with a corresponding dielectric layer; and then forming a conductive gate region in the temporary cavity.

Claims

1. A MOSFET transistor, characterized in that, include: Semiconductor body; Multiple internal trenches extend into the semiconductor body and have an elongated shape parallel to a first direction and are arranged sequentially. A pair of edge trenches extending into the semiconductor body and having an elongated shape parallel to a second direction transverse to the first direction; The end of each internal groove is connected to the corresponding edge groove in the pair of edge grooves; For each of the pair of edge trenches, the corresponding dielectric trench region extends into that edge trench; For each of the plurality of internal trenches: The conductive shielding region extends within the internal trench and has an elongated shape parallel to the first direction; and The first pair of conductive gate regions extend into the internal trench on opposite sides of the conductive shielding region and have an elongated shape parallel to the first direction; and The end of each conductive shielding region penetrates into the interior of the corresponding edge trench; and In each edge trench, the ends of adjacent conductive shielding regions are separated from each other.

2. The MOSFET transistor according to claim 1, characterized in that, In each edge trench, the ends of adjacent conductive shielding regions are separated by a portion of the corresponding dielectric trench region.

3. The MOSFET transistor according to claim 1, characterized in that, Each edge groove has a first width measured in a direction perpendicular to the second direction; and each inner groove has a second width measured in a direction perpendicular to the first direction; and the first width is less than the second width.

4. The MOSFET transistor according to claim 1, characterized in that, It also includes multiple annular gate regions, each annular gate region being formed of the same material as the conductive gate regions and including a corresponding pair of conductive gate regions and a pair of lateral gate regions, wherein each lateral gate region extends into a corresponding edge trench and contacts the corresponding conductive gate region.

5. The MOSFET transistor according to claim 4, characterized in that, For each edge trench, there is also a corresponding gate shielding contact area formed of conductive material and directly contacting the corresponding ends of the corresponding lateral gate region and conductive shielding region.

6. The MOSFET transistor according to claim 4, characterized in that, The semiconductor body includes an epitaxial region having a first conductivity type and defined by a front surface, and a plurality of body regions having a second conductivity type and extending from the front surface into the epitaxial region; wherein pairs of adjacent internal trenches laterally define corresponding body regions together with corresponding portions of edge trenches; and wherein pairs of conductive gate regions extending into adjacent internal trenches and arranged facing the same body region are separated from the body regions by corresponding dielectric gate regions; the MOSFET transistor further includes, for each body region, a corresponding source region of the first conductivity type extending from the front surface into a portion of the body region.

7. The MOSFET transistor according to claim 1, characterized in that, Also includes: A central trench extends into the semiconductor body and has an elongated shape parallel to a second direction, wherein the central trench is located between edge trenches at a certain distance and communicates with an inner trench, such that the edge trench, the inner trench and the central trench laterally define two successive bodies of semiconductor sub-regions of the semiconductor body, each semiconductor sub-region of one successive body being symmetrically arranged with respect to the corresponding semiconductor sub-region of the other successive body with respect to the central trench. For each internal trench, a second pair of conductive gate regions extends on the opposite side of the corresponding conductive shielding region and is symmetrical with respect to the corresponding first pair of conductive gate regions. The ends of each conductive gate region arranged in the opposite direction to the middle trench are arranged at a certain distance from the corresponding edge trench. For each pair of symmetrical semiconductor sub-regions, the corresponding lateral gate region is formed of the same material as the conductive gate region and extends into a portion of the intermediate trench between the two symmetrical semiconductor sub-regions. as well as In this arrangement, pairs of conductive gate regions extending into adjacent internal trenches and facing the same semiconductor sub-region are separated from the same semiconductor sub-region by corresponding dielectric gate regions and contacted with corresponding lateral gate regions, thereby forming a U-shaped patterned gate region.

8. The MOSFET transistor according to claim 7, characterized in that, Also includes: For each edge groove, the corresponding shielding contact area is formed of conductive material and is directly contacted and covered on the corresponding end of the conductive shielding area; as well as For each lateral gate region, there is a corresponding gate contact region, which is formed of conductive material and directly contacts the corresponding lateral gate region, and the gate contact regions are in electrical contact with each other.

9. The MOSFET transistor according to claim 8, characterized in that, The semiconductor body includes: An epitaxial region having a first conductivity type and defined by a front surface; and Multiple main regions, each having a second conductivity type and extending into a corresponding semiconductor region; The MOSFET transistor also includes a corresponding source region of a first conductivity type for each body region, extending from the front surface into a portion of the body region.

10. The MOSFET transistor according to claim 1, characterized in that, It also includes annular trenches, which include edge trenches and extend into the semiconductor body to define an internal region of the semiconductor body, the internal trenches extending into the internal region of the semiconductor body.

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