A semiconductor structure of a driving chip

Abstract

The application relates to the technical field of semiconductor chips, in particular to a semiconductor structure of a driving chip. The semiconductor structure of the driving chip comprises a substrate, at least one first type of isolation layer, the first type of isolation layer being formed on the substrate, and at least one body region being formed on the first isolation layer; one of the body regions is provided with a main power tube device for driving an external load; the first type of isolation layer is configured in a suspended state or a high resistance state. The semiconductor structure of the driving chip can avoid current absorption from a chip power supply by a load during driving of the load.

Description

Technical Field

[0001] This application relates to the field of semiconductor chip technology, and in particular to a semiconductor structure for a driver chip. Background Technology

[0002] In applications such as DC-DC power supplies, relay drives, and motor drives, driver chips are often used for driving. Different components within the driver chip are often isolated by isolation areas, which are usually configured to be connected to the VDD potential or a specific bias voltage.

[0003] When the load of a driver chip contains a large inductive component, the N-type isolation of the power transistor device used to drive the load inside the driver chip is often designed to be connected to the load output terminal together with the drain of the device. The N-type isolation in other areas is designed to be connected to VDD or a specific bias voltage. However, when the output of the driver chip is in a high-impedance state, due to the freewheeling effect of the inductor, the current on the inductor will not immediately decay to zero, causing the load to draw current from the driver chip for a long time. This will cause the N-type isolation, P-type substrate and other N-type isolation of the power device inside the driver chip to form a parasitic NPN transistor to conduct, directly drawing current from VDD. When the current drawn from VDD exceeds its power supply capacity, it will pull VDD to a voltage close to ground, affecting the chip's operating stability and even causing chip logic disorder and unpredictable results. Utility Model Content

[0004] In order to overcome the shortcomings of the existing technology, the purpose of this application is to provide a semiconductor structure for a driver chip that prevents the load from drawing current from the chip's power supply when driving the load.

[0005] To achieve the above objectives, this application provides a semiconductor structure for a driver chip, comprising: Substrate, At least one type of isolation layer is formed on the substrate, and at least one bulk region is formed on the first isolation layer; One of the body regions has a main power transistor device for driving an external load; The first type of isolation layer is configured to be in a suspended state or in a high-resistivity state.

[0006] Furthermore, at least two of the first type of isolation layers are interconnected.

[0007] Furthermore, each of the first type of isolation layers is separated by the substrate.

[0008] Furthermore, the substrate is a P-type substrate, each of the first type of isolation layers is an N-type isolation layer, and the body region is a P-type body region.

[0009] Furthermore, the main power transistor device is an N-type power transistor device.

[0010] Furthermore, it also includes a second type of isolation layer, which is formed on the substrate and ohmically connected to the first isolation layer.

[0011] Furthermore, each of the first type of isolation layers includes any one or a combination of a buried layer, a deep well, and a well.

[0012] To achieve the above objectives, this application also provides a driver chip that employs the semiconductor structure of the driver chip described above.

[0013] The semiconductor structure of the driver chip provided in this application configures the first isolation layer to be in a floating state or in a high-resistance state. This ensures that when the main power transistor of the driver chip drives the load and the load draws current from the semiconductor structure of the driver chip, the voltage of the first isolation layer will not be affected before the reverse-bias breakdown voltage of the parasitic diode is reached. This avoids the problem that the load draws current from VDD due to the isolation layer being connected to VDD, which affects the operation of the semiconductor structure of the driver chip, and improves the robustness of the semiconductor structure of the driver chip.

[0014] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing this application. Attached Figure Description

[0015] The accompanying drawings are provided to further illustrate the present application and form part of the specification. Together with the embodiments of the present application, they serve to explain the present application but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of the semiconductor structure of a conventional driver chip; Figure 2 This is a schematic diagram of the semiconductor structure of the driver chip in Embodiment 1 of this application; Figure 3 This is a schematic diagram of the semiconductor structure of the driver chip in Embodiment 2 of this application; Figure 4 This is a schematic diagram of the semiconductor structure of the driver chip in Embodiment 3 of this application; Figure 5 This is a schematic diagram of the semiconductor structure of the driver chip in Embodiment 4 of this application; Reference numerals: 100-substrate, 101-first type of isolation layer, 1011-first type of isolation layer, 1012-second type of isolation layer, 102-body region, 103-well, 104-main power transistor device, 105-parasitic transistor, 106-wire, 108-second type of isolation layer, 109-auxiliary semiconductor device. Detailed Implementation

[0016] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.

[0017] It should be understood that the steps described in the method embodiments of this application may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this application is not limited in this respect.

[0018] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0019] It should be noted that the terms "one" and "multiple" used in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless explicitly stated otherwise in the context, they should be understood as "one or more". "Multiple" should be understood as two or more.

[0020] Figure 1 This is a schematic diagram of the semiconductor structure of a conventional driver chip. (See attached diagram) Figure 1It includes a substrate 100, a first type-1 isolation region 1011 and a second type-1 isolation region 1012, a body region 102, a well 103, a main power transistor device 104, and a plurality of auxiliary semiconductor devices 109. The main power transistor device 104 is formed on the body region 102 and is isolated as N-type isolation. The first type-1 isolation region 1011 is configured to be connected to the drain of the main power transistor device 104 formed thereon and connected to the inductor L1 and the load terminal load. The second type-1 isolation region 1012 is configured to be connected to the VDD power supply. When the output of the semiconductor structure of the driver chip is in a high-impedance state, due to the freewheeling effect of inductor L1, the current on inductor L1 will not immediately decay to zero. This causes the load to draw current from the semiconductor structure of the driver chip for a long time. This will cause the parasitic transistor 105 formed by the first type I isolation region 1011, the second type I isolation region 1012 and the substrate 100 inside the semiconductor structure of the driver chip to conduct and directly draw current from the VDD power supply. When the current drawn from the VDD power supply exceeds its power supply capacity, it will pull the VDD power supply to near ground voltage, affecting the working stability of the semiconductor structure of the driver chip, and even causing the chip logic to be disordered and producing unpredictable results.

[0021] To address the aforementioned issues, this application provides a semiconductor structure for a driver chip that avoids the formation of parasitic transistors within the device structure when driving inductive loads, thereby preventing the load from drawing current from the power supply VDD of the driver chip's semiconductor structure.

[0022] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0023] Example 1 One embodiment of this application provides a semiconductor structure for a driver chip. Figure 2 This is a schematic diagram of the semiconductor structure of the driver chip in Embodiment 1 of this application. The following will refer to... Figure 2 The semiconductor structure of the driver chip in this application is described in detail, including: Substrate 100, In this embodiment, the substrate 100 is a P-type substrate.

[0024] A first type of isolation layer 101 is formed on the substrate 100; In this embodiment, the first type of isolation layer 101 is an N-type isolation layer; In this embodiment, the first type of isolation layer 101 includes a burial layer and a well.

[0025] In other embodiments, the first type of isolation layer 101 may also be a combination of any N-type doped structure, for example, a combination of N-type deep wells and N-type wells.

[0026] As can be understood, a buried layer refers to a region with a high doping concentration formed on a substrate through high-energy ion implantation or diffusion, which is then covered and buried by an epitaxial layer grown on top of it. A well refers to a region with a certain depth and doping concentration formed through ion implantation, high-temperature propulsion (annealing), or diffusion. Wells of different depths are used to meet different isolation and device fabrication requirements.

[0027] Body region 102 is a P-type body region, and two of them are formed on the first type of isolation layer 101.

[0028] Among them, a main power transistor device 104 is formed on a body region 102, and the main power transistor device 104 is an N-type power transistor device.

[0029] In some other embodiments, the main power transistor device 104 may also be a P-type power transistor device formed on the bulk region through an N-type well.

[0030] It is understood that other auxiliary semiconductor devices 109, such as resistors, capacitors and power transistors, may also be formed on the substrate 100 and body region 102 to cooperate with the main power transistor device 104 to assist in driving the load.

[0031] It is understood that different body regions 102 can correspond to different operating voltage domains, and auxiliary semiconductor devices 109 can be formed on the corresponding body region 102 or substrate 100 according to the required operating voltage domain. The number of the first type of isolation layer 101, the number of body regions 102, the type and number of auxiliary semiconductor devices 109, etc. are all adaptively set according to the circuit requirements of the actual driver chip.

[0032] In this embodiment, the P-type auxiliary semiconductor device 109 is indirectly formed on the substrate 100 or the body region 102 through the N-type well 103, while the N-type auxiliary semiconductor device 109 is directly formed on the substrate 100 or the body region 102.

[0033] In other embodiments, the substrate may also be an N-type substrate, the first type of isolation layer 101 may be a P-type isolation layer, the body region 102 may be an N-type body region, the well 103 may be a P-type well, and the main power transistor device may be a P-type power transistor device.

[0034] In this embodiment, the first type of isolation layer 101 is configured to be in a floating state, which means that the driver chip is not directly connected to an external potential when in use.

[0035] In this embodiment, the voltage of the first type of isolation layer 101 is determined by the body region with the highest potential connected to it. When the voltage of the body region decreases, the first type of isolation layer 101 will maintain the previous voltage, so that when the main power transistor device 104 drives the load, a parasitic transistor will not be formed inside the driving chip for conduction. The voltage of the first type of isolation layer 101 will only decrease when the reverse bias breakdown voltage of the parasitic diode between the first type of isolation layer 101 and the body region 102 is reached, the charge of the first type of isolation layer 101 is discharged, and the voltage of the first type of isolation layer 101 decreases.

[0036] Example 2 One embodiment of this application provides a semiconductor structure for a driver chip. Figure 3 This is a schematic diagram of the semiconductor structure of the driver chip in Embodiment 2 of this application. The following will refer to... Figure 3 The semiconductor structure of the driver chip in Embodiment 2 of this application is described in detail below: The difference between Embodiment 2 and Embodiment 1 of this application is as follows: In this embodiment, two first-type isolation layers are disposed at intervals on the substrate 100, namely a first first-type isolation region 1011 and a second first-type isolation region 1012, which are connected by a wire 106 ohms.

[0037] In some other embodiments, multiple first-type isolation layers may be provided on the substrate 100 at intervals according to the circuit requirements of the semiconductor structure of the actual driver chip, and two or more of the first-type isolation layers are connected by wires 106 ohms.

[0038] In other embodiments, as long as each of the first type of isolation layers is configured to be in a floating or high-resistance state, it is not necessary to connect it via the wire 106 ohms, but simply to be isolated by the substrate 100.

[0039] Example 3 One embodiment of this application provides a semiconductor structure for a driver chip. Figure 4 This is a schematic diagram of the semiconductor structure of the driver chip in Embodiment 3 of this application. The following will refer to... Figure 4 The semiconductor structure of the driver chip in Embodiment 3 of this application is described in detail below: The difference between Embodiment 3 and Embodiment 1 of this application is as follows: In this embodiment, a second type of isolation layer 108 is also provided on the substrate 100. No bulk region or semiconductor device is formed on the second type of isolation layer 108. The second type of isolation layer 108 is ohm connected to the first type of isolation layer 101 through a wire 106.

[0040] Example 4 One embodiment of this application provides a semiconductor structure for a driver chip. Figure 5 This is a schematic diagram of the semiconductor structure of the driver chip in Embodiment 4 of this application. The following will refer to... Figure 5 The semiconductor structure of the driver chip in Embodiment 4 of this application is described in detail below: The difference between Embodiment 4 and Embodiment 1 in this application is as follows: In this embodiment, the first type of isolation layer 101 is in a high-resistance state after being connected to the bias voltage VB via resistor Rh.

[0041] Understandably, since the first type of isolation layer 101 is configured in a high-impedance state, the connected bias voltage VB does not need to be driven.

[0042] Example 5 One embodiment of this application provides a driver chip that employs the semiconductor structure described above.

[0043] The above description is merely a partial embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

[0044] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in sequential order. Multitasking and parallel processing may be advantageous in certain environments. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this application. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0045] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A semiconductor structure for a driver chip, characterized in that, include: Substrate, At least one type of isolation layer is formed on the substrate, and at least one bulk region is formed on the type of isolation layer; One of the body regions has a main power transistor device for driving an external load; The first type of isolation layer is configured to be in a suspended state or in a high-resistivity state.

2. The semiconductor structure of the driver chip according to claim 1, characterized in that, At least two of the first type of isolation layers are interconnected.

3. The semiconductor structure of the driver chip according to claim 1, characterized in that, Each of the first type of isolation layers is separated by the substrate.

4. The semiconductor structure of the driver chip according to claim 1, characterized in that, The substrate is a P-type substrate, each of the first type of isolation layers is an N-type isolation layer, and the body region is a P-type body region.

5. The semiconductor structure of the driver chip according to claim 4, characterized in that, The main power transistor device is an N-type power transistor device.

6. The semiconductor structure of the driver chip according to claim 1, characterized in that, Also includes: A second type of isolation layer is formed on the substrate and is ohmically connected to the first type of isolation layer.

7. The semiconductor structure of the driver chip according to claim 1, characterized in that, The first type of isolation layer includes any one or a combination of buried layers, deep wells, and wells.

8. A driver chip, characterized in that, The semiconductor structure of the driver chip described in any one of claims 1-6 is adopted.

Images