Memory power supply circuit and electronic device

Abstract

This utility model relates to a memory power supply circuit and electronic device. The memory power supply circuit includes: a trigger module, a power chip, a first power supply module, a second power supply module, and a third power supply module. The trigger module is electrically connected to the processor via the power chip and the first power supply module; the trigger module is electrically connected to the memory via the second power supply module, and also electrically connected to the memory via the third power supply module; the second power supply module and the third power supply module are electrically connected; the trigger module sends a trigger signal, and the power chip controls the first power supply module to provide a first operating voltage to the memory control module in the processor according to the trigger signal; the second power supply module outputs a second operating voltage to the memory according to the trigger signal and sends a control signal to the third power supply module; the third power supply module outputs an enable voltage to the memory according to the trigger signal and the control signal, so that the memory can work normally. This utility model can reduce product costs and improve product efficiency and stability.

Description

Technical Field

[0001] This utility model relates to the field of electronic technology, and in particular to a memory power supply circuit and electronic device. Background Technology

[0002] The motherboard's DDR (Double Data Rate SDRAM) memory is one of the most important components of a computer, serving as a bridge for communication with the CPU. All programs run in memory, therefore, memory performance has a significant impact on the computer's performance. And for the memory to function effectively and fully, the performance of its power supply module plays a crucial role.

[0003] With the continuous upgrading of DDR memory, the new generation of DDR memory (such as DDR5) has become the mainstream of motherboard product design. Compared with the previous generations (such as DDR3 and DDR4) memory, in addition to the difference in working performance, the power supply mode of the new generation of DDR memory has also changed significantly. For example, it requires more paths for working voltage power supply compared to the previous generations.

[0004] However, some existing DDR memory power supply solutions use complex power chip circuits to achieve multi-path power supply, which results in complex peripheral circuit structures for the power chip, a large number of circuit components, and high R&D and material costs; moreover, the complexity of the circuits surrounding the power chip reduces product efficiency and stability. Utility Model Content

[0005] The purpose of this invention is to provide a memory power supply circuit and electronic device, which aims to reduce product costs and improve product efficiency and stability.

[0006] To achieve the above objectives, in a first aspect, the present invention provides a memory power supply circuit, which is configured to supply power to a memory control module and memory in a processor of an electronic device. The memory power supply circuit includes: a trigger module, a power chip, a first power supply module, a second power supply module, and a third power supply module. The trigger module is electrically connected to the processor via the power chip and the first power supply module; the trigger module is electrically connected to the memory via the second power supply module; the trigger module is also electrically connected to the memory via the third power supply module; the second power supply module is electrically connected to the third power supply module.

[0007] The trigger module sends a trigger signal, and the power chip controls the first power supply module to provide a first operating voltage to the memory control module in the processor according to the trigger signal;

[0008] The second power supply module outputs a second operating voltage to the memory according to the trigger signal, and sends a control signal to the third power supply module;

[0009] The third power supply module outputs an enable voltage to the memory according to the trigger signal and the control signal, so that the memory can work normally.

[0010] Optionally, the first power supply module includes at least two transistors. The power chip sends a level signal to the first power supply module according to the trigger signal. The at least two transistors switch according to the level signal and provide a specified first operating voltage to the memory control module in the processor.

[0011] Optionally, the first power supply module includes a first transistor, a second transistor, a first resistor, a second resistor, a third resistor, and an energy storage and filtering unit composed of at least one inductor and a capacitor. The drain of the first transistor is connected to a first power supply; the gate of the first transistor is connected to a first pin of the power supply chip via the first resistor; the source of the first transistor is connected to the gate of the first transistor via the second resistor; the source of the first transistor is also connected to the drain of the second transistor; the gate of the second transistor is connected to a second pin of the power supply chip via the third resistor; the source of the second transistor is grounded; the drain of the second transistor is also connected to a third pin of the power supply chip; the drain of the second transistor is also connected to one end of the inductor in the energy storage and filtering unit; the other end of the inductor in the energy storage and filtering unit is connected to the memory control module in the processor; and the other end of the inductor in the energy storage and filtering unit is grounded via at least one capacitor.

[0012] Optionally, the second power supply module includes a third transistor, a fourth resistor, a fifth resistor, a first capacitor, and a second capacitor. The source of the third transistor is connected to a second power supply. The source of the third transistor is also connected to a first terminal of the first capacitor. The second terminal of the first capacitor is connected to a first terminal of the second capacitor. The second terminal of the second capacitor is grounded. The second terminal of the first capacitor is also connected to the source of the third transistor via the fourth and fifth resistors. The trigger module is connected between the fourth and fifth resistors. The gate of the third transistor is connected to a first terminal of the second capacitor. The drain of the third transistor is connected to the third power supply module. The drain of the third transistor is also connected to the memory.

[0013] Optionally, the third power supply module includes a fourth transistor, a fifth transistor, a sixth transistor, a sixth resistor, a seventh resistor, and an eighth resistor. The drain of the fourth transistor is connected to a third power supply via the sixth resistor. The gate of the fourth transistor is connected to the trigger module. The source of the fourth transistor is grounded. The drain of the fourth transistor is also connected to the memory via the seventh resistor. The drain of the fifth transistor is connected to the memory. The source of the fifth transistor is grounded. The gate of the fifth transistor is connected to a fourth power supply via the eighth resistor. The gate of the fifth transistor is also connected to the drain of the sixth transistor. The gate of the sixth transistor is connected to the second power supply module. The source of the sixth transistor is grounded.

[0014] Optionally, the trigger module includes a seventh transistor and an eighth transistor. The gate of the seventh transistor is connected to a signal control terminal, the source of the seventh transistor is grounded, the drain of the seventh transistor is connected to the gate of the eighth transistor, the source of the eighth transistor is grounded, and the drain of the eighth transistor is connected to the power supply chip.

[0015] Optionally, the memory power supply circuit further includes a first diode and a second diode. The anode of the first diode is connected to a fifth power supply, and the cathode of the first diode is connected to the power supply chip. The anode of the second diode is connected to a sixth power supply, and the cathode of the second diode is connected to the power supply chip, so that the power supply chip can be powered by either the fifth power supply or the sixth power supply. When the power supply of the fifth power supply is turned off, the power supply chip is switched to be powered by the sixth power supply. The power supply of the first power supply module, the second power supply module, and the third power supply module remains unchanged, so that the memory continues to operate normally. The voltage of the fifth power supply is greater than the voltage of the sixth power supply.

[0016] Optionally, the first operating voltage, the second operating voltage, and the enable voltage are all different.

[0017] Optionally, the memory includes DDR5 memory.

[0018] Secondly, this utility model provides an electronic device, including a memory power supply circuit, memory, and processor as described above. The memory power supply circuit is used to supply power to the memory control module in the processor and the memory, so that the electronic device can work normally.

[0019] The beneficial effects of using the above embodiments are:

[0020] Based on the trigger signal issued by the trigger module, the power chip controls the first power supply module to provide operating voltage to the memory control module in the processor. Simultaneously, the second and third power supply modules also output operating voltage and enable voltage to the memory according to the trigger signal, thereby enabling the memory to operate normally. Since the power chip only needs to provide the specified operating voltage to the memory control module in the processor, and the operating voltage and enable voltage of the memory are provided by the other second and third power supply modules, there is no need for complex peripheral circuitry of the power chip, reducing the number of circuit components and eliminating the need for designing cumbersome peripheral circuitry, thus reducing R&D and material costs. Furthermore, by using the power chip and multiple independent power supply paths to provide operating power to the memory, the product's efficiency and stability can be effectively improved. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. These drawings are incorporated in and constitute a part of this specification, illustrating embodiments consistent with this application and serving together with the specification to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0022] Figure 1 A schematic circuit block diagram of an embodiment of the memory power supply circuit provided in this application;

[0023] Figure 2 A circuit diagram of an embodiment of the memory power supply circuit provided in this application;

[0024] Figure 3 A schematic diagram of the CPU +VDD2 power supply in one embodiment of the memory power supply circuit provided in this application;

[0025] Figure 4a A schematic diagram of the 5V power supply and enable power supply on the memory in one embodiment of the memory power supply circuit provided in this application. Figure 1 ;

[0026] Figure 4b A schematic diagram of the 5V power supply and enable power supply on the memory in one embodiment of the memory power supply circuit provided in this application. Figure 2 ;

[0027] Figure 5 A schematic diagram of a circuit board in one embodiment of the memory power supply circuit provided in this application. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without inventive effort are within the scope of protection of this utility model.

[0029] It should be noted that the descriptions involving "first," "second," etc., in this utility model are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope claimed by this utility model.

[0030] With the continuous upgrading of DDR memory, the new generation of memory has become the mainstream of motherboard product design. Compared with previous generations of memory, in addition to differences in performance, the power supply mode of the new generation of memory has also undergone significant changes. For example, the inventors of this application have discovered that in the power supply of the new generation of DDR5 memory, a 5V basic power supply is required, and another 1.1V voltage is also required to provide working power to the DDR5 control module on the CPU side. Furthermore, a DDR5 enable control signal has been added to control the switching of DDR5.

[0031] Based on this, such as Figure 1As shown, this application provides a memory power supply circuit 10, which is configured to supply power to the memory control module 201 and memory 30 in the processor 20 of an electronic device. The memory power supply circuit 10 includes: a trigger module 101, a power chip 102, a first power supply module 103, a second power supply module 104, and a third power supply module 105. The trigger module 101 is electrically connected to the processor 20 via the power chip 102 and the first power supply module 103; the trigger module 101 is electrically connected to the memory via the second power supply module 104; and the trigger module 101 is also electrically connected to the memory via the third power supply module 105. 105 is electrically connected to the memory; the second power supply module 104 is electrically connected to the third power supply module 105; the trigger module 101 sends a trigger signal, and the power chip 102 controls the first power supply module 103 to provide a first operating voltage to the memory control module 201 in the processor 20 according to the trigger signal; the second power supply module 104 outputs a second operating voltage to the memory 30 according to the trigger signal, and sends a control signal to the third power supply module 105; the third power supply module 105 outputs an enable voltage to the memory 30 according to the trigger signal and the control signal, so that the memory 30 can work normally.

[0032] In this embodiment, the memory power supply circuit 10 can output at least a first operating voltage, a second operating voltage, and an enable voltage through multiple paths to support the normal operation of the memory 30. The first operating voltage, second operating voltage, and enable voltage may be partially the same or all different, depending on the multiple power supply voltages required for the normal operation of different memory types, to meet the different power supply requirements of next-generation memory. For example, when the memory 30 is a next-generation DDR5 memory, the first operating voltage may be the 1.1V operating voltage provided to the DDR5 control module 201 at the processor 20 (CPU) end; the second operating voltage may be the 5V basic operating voltage provided to the DDR5 memory; and the enable voltage may be the 3.3V enable operating voltage provided to the DDR5 memory. Of course, the memory 30 is not limited to any other type of memory besides DDR5 memory.

[0033] Based on the trigger signal issued by the trigger module 101, the power chip 102 controls the first power supply module 103 to provide operating voltage to the memory control module 201 in the processor 20. At the same time, the second power supply module 104 and the third power supply module 105 can also output operating voltage and enable voltage to the memory 30 according to the trigger signal, thereby enabling the memory 30 to work normally. Since the power chip 102 only needs to provide the specified operating voltage to the memory control module 201 in the processor 20, the operating voltage and enable voltage of the memory are provided by the other second power supply module 104 and the third power supply module 105. This eliminates the need for complex power chip peripheral circuits, reduces the number of circuit components, and eliminates the need to design cumbersome chip peripheral circuits, thereby reducing R&D and material costs. Furthermore, by using the power chip 102 and multiple independent power supply paths to provide operating power to the memory, the product's operating efficiency and stability can be effectively improved.

[0034] Furthermore, in some embodiments, the first power supply module 103 includes at least two transistors. The power chip 102 sends a level signal to the first power supply module 103 according to the trigger signal. The at least two transistors switch according to the level signal and provide a specified operating voltage to the memory control module 201 in the processor 20. For example, the power chip 102 can provide a PWM signal to the first power supply module 103 to drive at least two transistors to switch. After energy storage and filtering by inductors and output capacitors, the specified operating voltage is output, such as providing a 1.1V operating voltage to the DDR5 control module 201 at the processor 20. In this way, by controlling the frequency and duty cycle of the PWM signal by the power chip 102, the conduction time of the transistors is changed, thereby changing the output voltage to meet the power supply requirements. The circuit structure is simple and efficient.

[0035] Specifically, such as Figure 2As shown, in some embodiments, the first power supply module 103 includes a first transistor QP1, a second transistor QP2, a first resistor RP3, a second resistor RP4, a third resistor RP6, and an energy storage and filtering unit composed of at least one inductor and one capacitor. The drain of the first transistor QP1 is connected to a first power supply (e.g., a 5V power supply), the gate of the first transistor QP1 is connected to a first pin of the power chip 102 (e.g., the second pin of the power chip UP1) via the first resistor RP3, and the source of the first transistor QP1 is connected to its gate via the second resistor RP4. The source of the first transistor QP1 also... The drain of the second transistor QP2 is connected to the third resistor RP6, and the gate of the second transistor QP2 is connected to the second pin of the power chip 102 (e.g., the 4th pin of the power chip UP1) via the third resistor RP6. The source of the second transistor QP2 is grounded. The drain of the second transistor QP2 is also connected to the third pin of the power chip 102 (e.g., the 8th pin of the power chip UP1). The drain of the second transistor QP2 is also connected to one end of the inductor in the energy storage filter unit. The other end of the inductor in the energy storage filter unit is connected to the memory control module 201 in the processor 20. The other end of the inductor in the energy storage filter unit is also grounded via at least one capacitor. The first power supply module 103 may also include a resistor RP8 and a capacitor CP12. One end of the resistor RP8 is connected to the 4th pin of the power chip UP1, and the other end of the resistor RP8 is grounded. The first end of the capacitor CP12 is connected to the gate of the second transistor QP2, and the second end of the capacitor CP12 is grounded. The energy storage and filtering unit includes at least one inductor and one capacitor. Specifically, the first power supply module 103 may further include inductors LP1 and LP2, and capacitors CP2, CP3, CEP1, CEP2, CP6, CP7, CP8, and CP9. One end of inductor LP1 is connected to the first power supply, and the other end of inductor LP1 is connected to the drain of the first transistor QP1. The other end of inductor LP1 is also grounded via capacitors CP2, CP3, and CEP1. One end of inductor LP2 is connected to the drain of the second transistor QP2. One end of inductor LP2 is also grounded via resistor RP7 and capacitor CP11. The other end of inductor LP2 is also grounded via capacitors CEP2, CP6, CP7, CP8, and CP9. The other end of inductor LP2 is also connected to the memory control module 201 in the processor 20, thereby outputting the first operating voltage (e.g., 1.1V operating voltage) after energy storage and filtering to the DDR5 control module 201 at the processor 20. In an optional embodiment, such as... Figure 3 As shown, the first operating voltage +VDD2 output by the first power supply module 103 supplies power to the DDR5 control module 201 at the processor 20 (CPU) end.

[0036] In some embodiments, the second power supply module 104 includes a third transistor QP3, a fourth resistor PR1, a fifth resistor RP14, a first capacitor CP22, and a second capacitor CP23. The source of the third transistor QP3 is connected to a second power supply (e.g., a 5V power supply). The source of the third transistor QP3 is also connected to the first terminal of the first capacitor CP22. The second terminal of the first capacitor CP22 is connected to the first terminal of the second capacitor CP23. The second terminal of the second capacitor CP23 is grounded. The second terminal of the first capacitor CP22 is also connected to the source of the third transistor via the fourth resistor PR1 and the fifth resistor RP14. The trigger module 101 is connected between the fourth resistor PR1 and the fifth resistor RP14. The gate of the third transistor QP3 is connected to the first terminal of the second capacitor CP23. The drain of the third transistor QP3 is connected to the third power supply module 105. The drain of the third transistor QP3 is also connected to the memory 30, such as being connected to the power supply terminal of the DDR5 memory to provide a 5V basic operating voltage for the DDR5 memory. In addition, the second power supply module 104 may also include a capacitor CEP3, and the second power supply (e.g., a 5V power supply) is grounded through capacitor CEP3. The second power supply module 104 may also include capacitors CEP4, CP14, CP15, CP16, CP17, CP18, and CP19, and the drain of the third transistor QP3 is grounded through capacitors CEP4, CP14, CP15, CP16, CP17, CP18, and CP19, respectively, so as to filter the output voltage and provide it to the DDR5 memory.

[0037] In some embodiments, the third power supply module 105 includes a fourth transistor PQ3, a fifth transistor PQ4, a sixth transistor PQ5, a sixth resistor RP11, a seventh resistor RP12, and an eighth resistor RP13. The drain of the fourth transistor PQ3 is connected to a third power supply (e.g., a 3V power supply) via the sixth resistor RP11. The gate of the fourth transistor PQ3 is connected to the trigger module 101. The source of the fourth transistor PQ3 is grounded. The drain of the fourth transistor PQ3 is also connected to the memory via the seventh resistor RP12. The drain of the fifth transistor PQ4 is connected to the memory 30, and can be connected to the enable terminal of the DDR5 memory to provide a 3.3V enable voltage for the DDR5 memory, allowing the DDR5 to enter normal operating mode. The source of the fifth transistor PQ4 is grounded, and the gate of the fifth transistor PQ4 is connected to a fourth power supply (e.g., a 3V power supply) via the eighth resistor RP13. The gate of the fifth transistor PQ4 is also connected to the drain of the sixth transistor PQ5. The gate of the sixth transistor PQ5 is connected to the second power supply module 104, and the source of the sixth transistor PQ5 is grounded.

[0038] In one alternative implementation, such as Figure 4a , 4b As shown, the second operating voltage +V5DUAL_DDR5 output by the second power supply module 104 provides 5V operating power to the DDR5 memory. The enable voltage DDR5_PWR_EN output by the third power supply module 105 provides 3.3V enable startup voltage to the DDR5 memory, and the DDR5 enters normal operating mode.

[0039] In some embodiments, the trigger module 101 includes a seventh transistor PQ2 and an eighth transistor PQ1. The gate of the seventh transistor PQ2 is connected to a signal control terminal (e.g., the signal control terminal of a southbridge chip). The source of the seventh transistor PQ2 is grounded. The drain of the seventh transistor PQ2 is connected to the gate of the eighth transistor PQ1. The source of the eighth transistor PQ1 is grounded. The drain of the eighth transistor PQ1 is connected to the power supply chip 102. The trigger module 101 also includes a resistor RP5 and capacitors CP5, CP13, and CP10. The drain of the eighth transistor PQ1 is grounded via capacitor CP5. The drain of the eighth transistor PQ1 is also grounded via resistor RP5 and capacitor CP10. The gate of the seventh transistor PQ2 is also grounded via capacitor CP13.

[0040] In some embodiments, the memory power supply circuit 10 further includes a first diode DS1 and a second diode DS2. The anode of the first diode DS1 is connected to a fifth power supply (e.g., a 12V power supply), and the cathode of the first diode DS1 is connected to the power chip 102. The anode of the second diode DS2 is connected to a sixth power supply (e.g., a 5V power supply), and the cathode of the second diode DS2 is connected to the power chip 102, so that the power chip 102 can be powered by either the fifth or the sixth power supply. When the power supply of the fifth power supply is turned off, the power chip 102 is powered by the sixth power supply, while the power supply of the first power supply module 103, the second power supply module 104, and the third power supply module 105 remains unchanged, so that the memory 30 continues to operate normally. The voltage of the fifth power supply is greater than the voltage of the sixth power supply. The memory power supply circuit 10 also includes a resistor RP1 and a capacitor CP1. The cathode of the first diode DS1 is connected to the power chip 102 via the resistor RP1. The first terminal of the capacitor CP1 is connected between the resistor RP1 and the power chip 102, and the second terminal of the capacitor CP1 is grounded.

[0041] It should be noted that the transistor in the above embodiments can be selected from any one of field-effect transistors, silicon controlled rectifiers, thyristors, and bipolar transistors. Alternatively, an electronic switch combination of semiconductor devices composed of MOSFETs, silicon controlled rectifiers, thyristors, and bipolar transistors can be used to replace its function, which is not limited here.

[0042] The working principle of the memory power supply circuit 10 provided in this application is described in detail below:

[0043] When the motherboard power switch is turned on, the system +12VS provides 12V operating power to the VCC signal on pin 5 of the power chip UP1 through diode DS1 and resistor RP1. At this time, the southbridge SLP_S4# signal is 3.3V high level, the drain and source of the PQ2 NMOS transistor are connected and grounded, pin 1 of PQ1 is low level and the MOS transistor is not working. The 7th pin of the power chip UP1 is internally high level by default, triggering the power chip UP1 to start working.

[0044] The internal logic management module of the power chip UP1 controls the signal levels of the UGATE signal on pin 2 and the LGATE signal on pin 4, thereby controlling the switching operation of the upper and lower MOSFETs QP1 and QP2. Then, the PHASE switching signal is output from pin 8 of the power chip UP1. After passing through the energy storage and filtering of the LP2 inductor and the output capacitor, the +VDD2 voltage is finally output to provide 1.1V operating power to the DDR5 memory control module on the CPU side.

[0045] At the same time, the gate of the QP3 PMOS transistor is at a low level, and the source and drain of the MOS transistor are turned on, outputting +V5DUAL_DDR5 to provide 5V operating power to the DDR5 memory.

[0046] Meanwhile, with QP3 on, pin 1 (G) of PQ5 is at a high level of 5V, pin 3 (D) and pin 2 (S) of MOSFET PQ5 are pulled to ground, and pin 1 (G) of PQ4 and PQ3 are both at a low level and not working. By pulling up +3VSB level, DDR5_PWR_EN is output to provide DDR5 with a 3.3V enable voltage, and DDR5 enters normal working mode.

[0047] Furthermore, in an optional implementation, the memory power supply circuit 10 provided in this application also supports a system sleep mode. When the motherboard system enters the sleep mode, the +12VS system power supply is turned off, and the 5th pin VCC of the power chip UP1 is switched from the original system +12VS power supply to the Standby +5VD voltage power supply. Other power supplies on the circuit remain unchanged, so that the power supplies of the DDR5 memory are still maintained in a normal power supply state, and switch to normal working mode after the system wakes up.

[0048] Furthermore, in an alternative implementation, such as Figure 5The diagram shows a schematic of the circuit board of the memory power supply circuit 10 of this application. Since the power chip only needs to provide the specified operating voltage to the memory control module in the processor, the operating voltage and enable voltage of the memory are provided by the other second power supply module and third power supply module. There is no need for complex power chip peripheral circuits, which can reduce the number of circuit components and eliminate the need to design complicated chip peripheral circuits. This results in fewer circuit components, less PCB space occupied, saving PCB space, facilitating PCB routing, and reducing R&D and material costs.

[0049] Based on the above embodiments, the circuit of this application is simple, with fewer components, making it easy for engineers to debug and repair. It also boasts strong versatility, high working efficiency, and stable and safe performance. In this application's circuit, components such as the QP3 MOSFET and other small-signal control MOSFETs are common materials with strong substitutability, resulting in lower material and R&D costs.

[0050] This invention also proposes an electronic device including the aforementioned memory power supply circuit, the working principle of which is as described above and will not be repeated here. The electronic device also includes memory and a processor. The memory power supply circuit supplies power to the memory control module in the processor and the memory itself, enabling the electronic device to function normally. In some embodiments, the processor in this electronic device may be a central processing unit (CPU), a controller, a microcontroller, a microprocessor, or other data processing chip.

[0051] The above description is only a preferred embodiment of the present utility model and does not limit the patent scope of the present utility model. Any equivalent structural or procedural changes made based on the contents of the present utility model specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present utility model.

Claims

1. A memory power supply circuit, characterized in that, The memory power supply circuit is configured to supply power to the memory control module and memory in the processor of an electronic device. The memory power supply circuit includes: a trigger module, a power chip, a first power supply module, a second power supply module, and a third power supply module. The trigger module is electrically connected to the processor via the power chip and the first power supply module; the trigger module is electrically connected to the memory via the second power supply module; the trigger module is also electrically connected to the memory via the third power supply module; the second power supply module is electrically connected to the third power supply module. The trigger module sends a trigger signal, and the power chip controls the first power supply module to provide a first operating voltage to the memory control module in the processor according to the trigger signal; The second power supply module outputs a second operating voltage to the memory according to the trigger signal, and sends a control signal to the third power supply module; The third power supply module outputs an enable voltage to the memory according to the trigger signal and the control signal, so that the memory can work normally.

2. The memory power supply circuit as described in claim 1, characterized in that, The first power supply module includes at least two transistors. The power chip sends a level signal to the first power supply module according to the trigger signal. The at least two transistors switch according to the level signal and provide a specified first operating voltage to the memory control module in the processor.

3. The memory power supply circuit as described in claim 2, characterized in that, The first power supply module includes a first transistor, a second transistor, a first resistor, a second resistor, a third resistor, and an energy storage and filtering unit composed of at least one inductor and a capacitor. The drain of the first transistor is connected to a first power supply; the gate of the first transistor is connected to a first pin of the power supply chip via the first resistor; the source of the first transistor is connected to the gate of the first transistor via the second resistor; the source of the first transistor is also connected to the drain of the second transistor; the gate of the second transistor is connected to a second pin of the power supply chip via the third resistor; the source of the second transistor is grounded; the drain of the second transistor is also connected to a third pin of the power supply chip; the drain of the second transistor is also connected to one end of the inductor in the energy storage and filtering unit; the other end of the inductor in the energy storage and filtering unit is connected to the memory control module in the processor; and the other end of the inductor in the energy storage and filtering unit is grounded via at least one capacitor.

4. The memory power supply circuit as described in claim 1, characterized in that, The second power supply module includes a third transistor, a fourth resistor, a fifth resistor, a first capacitor, and a second capacitor. The source of the third transistor is connected to a second power supply. The source of the third transistor is also connected to a first terminal of the first capacitor. The second terminal of the first capacitor is connected to a first terminal of the second capacitor. The second terminal of the second capacitor is grounded. The second terminal of the first capacitor is also connected to the source of the third transistor via the fourth and fifth resistors. The trigger module is connected between the fourth and fifth resistors. The gate of the third transistor is connected to a first terminal of the second capacitor. The drain of the third transistor is connected to the third power supply module. The drain of the third transistor is also connected to the memory.

5. The memory power supply circuit as described in claim 1, characterized in that, The third power supply module includes a fourth transistor, a fifth transistor, a sixth transistor, a sixth resistor, a seventh resistor, and an eighth resistor. The drain of the fourth transistor is connected to a third power supply via the sixth resistor. The gate of the fourth transistor is connected to the trigger module. The source of the fourth transistor is grounded. The drain of the fourth transistor is also connected to the memory via the seventh resistor. The drain of the fifth transistor is connected to the memory. The source of the fifth transistor is grounded. The gate of the fifth transistor is connected to a fourth power supply via the eighth resistor. The gate of the fifth transistor is also connected to the drain of the sixth transistor. The gate of the sixth transistor is connected to the second power supply module. The source of the sixth transistor is grounded.

6. The memory power supply circuit as described in claim 1, characterized in that, The trigger module includes a seventh transistor and an eighth transistor. The gate of the seventh transistor is connected to a signal control terminal, the source of the seventh transistor is grounded, the drain of the seventh transistor is connected to the gate of the eighth transistor, the source of the eighth transistor is grounded, and the drain of the eighth transistor is connected to the power supply chip.

7. The memory power supply circuit as described in claim 1, characterized in that, The memory power supply circuit further includes a first diode and a second diode. The anode of the first diode is connected to a fifth power supply, and the cathode of the first diode is connected to the power supply chip. The anode of the second diode is connected to a sixth power supply, and the cathode of the second diode is connected to the power supply chip, so that the power supply chip can be powered by either the fifth power supply or the sixth power supply. When the power supply of the fifth power supply is turned off, the power supply chip is switched to be powered by the sixth power supply. The power supply of the first power supply module, the second power supply module, and the third power supply module remains unchanged, so that the memory continues to work normally. The voltage of the fifth power supply is greater than the voltage of the sixth power supply.

8. The memory power supply circuit as described in any one of claims 1 to 7, characterized in that, The first operating voltage, the second operating voltage, and the enable voltage are all different.

9. The memory power supply circuit as described in any one of claims 1 to 7, characterized in that, The memory includes DDR5 memory.

10. An electronic device, characterized in that, The device includes a memory power supply circuit, a memory, and a processor as described in any one of claims 1 to 9, wherein the memory power supply circuit is used to supply power to the memory control module in the processor and the memory so that the electronic device can operate normally.

Images