A silicon carbide semiconductor device

Abstract

The utility model provides a kind of silicon carbide semiconductor device, which includes substrate, epitaxial layer, metal layer structure and passivation layer, wherein the epitaxial layer is located on the substrate, and the epitaxial layer is divided into active region and terminal area located at the periphery of the active region, the metal layer structure is located on the active region, and the metal layer structure includes stacked first metal layer and second metal layer, the second metal layer covers part of the first metal layer, so that the first metal layer has an exposed area not covered by the second metal layer, the passivation layer is located on the epitaxial layer and covers the metal layer structure, and at least two through openings are provided in the passivation layer to divide the passivation layer into multiple non-connected regions. The silicon carbide semiconductor device of the utility model can effectively alleviate the accumulation of stress, reduce shear force, avoid cracks or deformation of the passivation layer, and improve the waterproof ability and reliability of the device by providing a passivation layer with through openings.

Description

Technical Field

[0001] This utility model belongs to the field of semiconductor integrated circuit manufacturing technology and relates to a silicon carbide semiconductor device. Background Technology

[0002] Silicon carbide (SiC), as a new generation of wide-bandgap semiconductor material, exhibits extremely superior performance in the field of power semiconductors, representing the forefront and future direction of power semiconductor device development. SiC is a compound semiconductor material composed of silicon (Si) and carbon (C), possessing excellent electrical properties, including a bandgap (2.3–3.3 eV) approximately three times that of Si and a high breakdown field strength (0.8 × 10⁻⁶ eV). 16 ~3×10 16 V / cm) is approximately 10 times that of Si, and has a high saturation drift velocity (2×10). 7 The thermal conductivity (4.9 W / cmK) is approximately 2.7 times that of Si, and the thermal conductivity (4.9 W / cmK) is approximately 3.2 times that of Si. These properties give silicon carbide materials excellent characteristics such as a large bandgap, high breakdown field strength, high thermal conductivity, high saturation velocity, and high maximum operating temperature. These excellent properties enable silicon carbide electronic devices to operate in high-voltage, high-heat-generating, and high-frequency environments. Therefore, silicon carbide is considered the best material for manufacturing high-power electronic devices. Compared with gallium arsenide and silicon, silicon carbide has overwhelmingly superior properties in terms of high voltage and high temperature.

[0003] However, during the packaging process of silicon carbide power devices, the packaged devices need to undergo reliability tests such as Temperature Cycling Test (TCT) and Thermal Shock Test (TS). Due to the mismatch of linear expansion coefficients between the molding compound, dielectric layer, and metal layer, stress will be generated between them due to mutual compression. Excessive stress can cause cracks in the passivation layer structure or metal deformation. This will not only affect the appearance of the device, but also reduce the device's ability to resist water vapor corrosion, thereby affecting the long-term reliability of the device.

[0004] Therefore, how to provide a silicon carbide semiconductor device to avoid cracks or metal deformation in the passivation layer and improve the device's waterproof capability and reliability has become an important problem that needs to be solved by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Utility Model Content

[0006] In view of the shortcomings of the prior art described above, the purpose of this utility model is to provide a silicon carbide semiconductor device to solve the problem that in the prior art, after silicon carbide power devices undergo TCT and TS, the stress caused by the mismatch of the expansion coefficients between the molding compound / dielectric layer / metal layer leads to mutual compression stress, which in turn causes cracks in the passivation layer or metal deformation, reducing the device's waterproof capability and reliability.

[0007] To achieve the above and other related objectives, this utility model provides a silicon carbide semiconductor device, comprising:

[0008] Substrate;

[0009] An epitaxial layer is located on the substrate, and the epitaxial layer is divided into an active region and a terminal region located around the active region;

[0010] A metal layer structure is located on the active region. The metal layer structure includes a stacked first metal layer and a second metal layer, and the second metal layer covers a portion of the first metal layer so that the first metal layer has an exposed area that is not covered by the second metal layer.

[0011] A passivation layer is located on the epitaxial layer and covers the metal layer structure. The passivation layer has at least two through openings that divide the passivation layer into multiple unconnected regions.

[0012] Optionally, it further includes an interlayer dielectric layer located on the epitaxial layer, the interlayer dielectric layer including a first region covering the active region and a second region covering the terminal region, the metal layer structure being located on the first region, and the passivation layer being located on the interlayer dielectric layer and covering the metal layer structure.

[0013] Optionally, the through opening further includes a first opening that exposes the upper surface of the second metal layer, the sidewalls of the second metal layer, and the exposed area of ​​the first metal layer, and a second opening that exposes the exposed area of ​​the first metal layer.

[0014] Optionally, the through opening includes a first opening that exposes the upper surface of the second metal layer and a second opening that exposes the upper surface of the second metal layer, the sidewalls of the second metal layer, and the exposed area of ​​the first metal layer.

[0015] Optionally, the through opening includes a first opening that exposes the upper surface of the second metal layer and a second opening that exposes the exposed area of ​​the first metal layer.

[0016] Optionally, a field oxide layer is provided between the epitaxial layer and the interlayer dielectric layer, and the field oxide layer covers the terminal region.

[0017] Optionally, the field oxide layer extends into the active region and covers a portion of the active region.

[0018] Optionally, the terminal area includes a non-exposed area covered by the second region and an exposed area not covered by the second region. The non-exposed area and the exposed area are arranged along the direction of the second region away from the first region, and a field oxide layer is provided between the second region and the non-exposed area.

[0019] Optionally, the through opening further includes a third opening that exposes the terminal area.

[0020] Optionally, the thickness of the first metal layer is less than the thickness of the second metal layer.

[0021] As described above, the silicon carbide semiconductor device of this invention includes a substrate, an epitaxial layer, a metal layer structure, and a passivation layer. The epitaxial layer is located on the substrate and is divided into an active region and a terminal region surrounding the active region. The metal layer structure is located on the active region and includes a stacked first metal layer and a second metal layer. The second metal layer partially covers the first metal layer, providing an exposed area not covered by the second metal layer. The passivation layer is located on the epitaxial layer and covers the metal layer structure. The passivation layer has at least two through-holes that divide the passivation layer into multiple unconnected regions. By providing a passivation layer with through-holes, the silicon carbide semiconductor device of this invention can effectively alleviate stress accumulation, reduce shear force, prevent cracks or deformation in the passivation layer, and improve the device's waterproof capability and reliability. Attached Figure Description

[0022] Figure 1 The diagram shows the structure of a semiconductor device.

[0023] Figure 2 The diagram shown is a structural schematic of the first type of silicon carbide semiconductor device according to Embodiment 1 of this utility model.

[0024] Figure 3 The diagram shown is a structural schematic of the second type of silicon carbide semiconductor device according to Embodiment 1 of this utility model.

[0025] Figure 4 The diagram shown is a structural schematic of the third silicon carbide semiconductor device according to Embodiment 1 of this utility model.

[0026] Figure 5 The diagram shown is a structural schematic of the fourth silicon carbide semiconductor device according to Embodiment 1 of this utility model.

[0027] Figure 6 The diagram shown is a structural schematic of the fifth type of silicon carbide semiconductor device according to Embodiment 1 of this utility model.

[0028] Figure 7 The diagram shown is a structural schematic of the sixth type of silicon carbide semiconductor device according to Embodiment 1 of this utility model.

[0029] Figure 8 The diagram shown is a structural schematic of the seventh type of silicon carbide semiconductor device according to Embodiment 1 of this utility model.

[0030] Figure 9 The diagram shown is a structural schematic of the first type of silicon carbide semiconductor device according to Embodiment 2 of this utility model.

[0031] Figure 10 The diagram shown is a structural schematic of the second type of silicon carbide semiconductor device according to Embodiment 2 of this utility model.

[0032] Figure 11 The diagram shown is a structural schematic of the third silicon carbide semiconductor device according to Embodiment 2 of this utility model.

[0033] Figure 12 The diagram shown is a structural schematic of the fourth silicon carbide semiconductor device according to Embodiment 2 of this utility model.

[0034] Figure 13 The diagram shown is a structural schematic of the fifth type of silicon carbide semiconductor device according to Embodiment 2 of this utility model.

[0035] Figure 14 The diagram shown is a structural schematic of the sixth type of silicon carbide semiconductor device according to Embodiment 2 of this utility model.

[0036] Figure 15 The diagram shown is a structural schematic of the seventh type of silicon carbide semiconductor device according to Embodiment 2 of this utility model.

[0037] Figure 16 The diagram shown is a structural schematic of the first type of silicon carbide semiconductor device according to Embodiment 3 of this utility model.

[0038] Figure 17 The diagram shown is a structural schematic of the second type of silicon carbide semiconductor device according to Embodiment 3 of this utility model.

[0039] Figure 18 The diagram shown is a structural schematic of the third type of silicon carbide semiconductor device according to Embodiment 3 of this utility model.

[0040] Figure 19 The diagram shown is a structural schematic of the fourth silicon carbide semiconductor device according to Embodiment 3 of this utility model.

[0041] Figure 20 The diagram shown is a structural schematic of the fifth type of silicon carbide semiconductor device according to Embodiment 3 of this utility model.

[0042] Figure 21 The diagram shown is a structural schematic of the sixth type of silicon carbide semiconductor device according to Embodiment 3 of this utility model.

[0043] Figure 22 The diagram shown is a structural schematic of the seventh type of silicon carbide semiconductor device according to Embodiment 3 of this utility model.

[0044] Figure 23 The diagram shown is a structural schematic of the first type of silicon carbide semiconductor device according to Embodiment 4 of this utility model.

[0045] Figure 24 The diagram shown is a structural schematic of the second type of silicon carbide semiconductor device according to Embodiment 4 of this utility model.

[0046] Figure 25 The diagram shown is a structural schematic of the fourth type of silicon carbide semiconductor device according to Embodiment 4 of this utility model.

[0047] Figure 26 The diagram shown is a structural schematic of the fourth type of silicon carbide semiconductor device according to Embodiment 4 of this utility model.

[0048] Figure 27 The diagram shown is a structural schematic of the fifth type of silicon carbide semiconductor device according to Embodiment 4 of this utility model.

[0049] Figure 28 The diagram shown is a structural schematic of the sixth type of silicon carbide semiconductor device according to Embodiment 4 of this utility model.

[0050] Figure 29 The diagram shown is a structural schematic of the seventh type of silicon carbide semiconductor device according to Embodiment 4 of this utility model.

[0051] Explanation of reference numerals in the attached figures

[0052] 101 and 201 substrates

[0053] Epitaxial layers 102 and 202

[0054] Interlayer dielectric layer 103, 206

[0055] 2061 First Region

[0056] 2062 Second Region

[0057] 104 Metal Seed Layer

[0058] 105 Metal Layer

[0059] 106, 204 passivation layers

[0060] 203 Metal Layer Structure

[0061] 2031 First Metal Layer

[0062] 2032 Second Metal Layer

[0063] 205 Through-opening

[0064] 2051 First Opening

[0065] 2052 Second Opening

[0066] 2053 Third Opening

[0067] 207 Field Oxide Layer

[0068] I Active Region

[0069] II Terminal Area Detailed Implementation

[0070] Please see Figure 1 The diagram shows a schematic of a semiconductor device, including a substrate 101, an epitaxial layer 102, an interlayer dielectric layer 103, a metal seed layer 104, a metal layer 105, and a passivation layer 106. The epitaxial layer 102 is located on the substrate 101, the interlayer dielectric layer 103 is located on the epitaxial layer 102, the metal seed layer 104 and the metal layer 105 are sequentially stacked on the interlayer dielectric layer 103, and the passivation layer 106 is located on the interlayer dielectric layer 103 and covers the metal seed layer 104 and the metal layer 105. The passivation layer 106 completely covers the metal layer 105. After undergoing TCT and TS cycles, the passivation layer 106 and the metal layer 105 experience mutual compression due to a mismatch in their coefficients of thermal expansion, resulting in stress on the passivation layer 106 and causing it to crack.

[0071] However, when the passivation layer 106 of the semiconductor device cracks, moisture and mobile ions in the air can enter the device through the cracks, causing performance degradation or even device failure and reducing reliability. Therefore, this invention provides a silicon carbide semiconductor device that, by providing a passivation layer with a through-hole, can effectively alleviate stress accumulation, reduce shear force, and prevent cracks or metal deformation in the passivation layer, thereby improving the device's waterproof capability and reliability.

[0072] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model.

[0073] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0074] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0075] In the detailed description of the embodiments of this utility model, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of this utility model. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0076] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0077] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0078] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0079] Example 1

[0080] Please see Figure 2The diagram shows a schematic of the structure of a first type of silicon carbide semiconductor device according to this embodiment. The silicon carbide semiconductor device includes a substrate 201, an epitaxial layer 202, a metal layer structure 203, and a passivation layer 204. The epitaxial layer 202 is located on the substrate 201 and is divided into an active region I and a terminal region II located around the active region I. The metal layer structure 203 is located on the active region I and includes a first metal layer 2031 and a second metal layer 2032 stacked together. The second metal layer 2032 covers part of the first metal layer 2031 so that the first metal layer 2031 has an exposed area not covered by the second metal layer 2032. The passivation layer 204 is located on the epitaxial layer 202 and covers the metal layer structure 203. The passivation layer 204 has at least two through openings 205, which divide the passivation layer 204 into multiple unconnected regions.

[0081] Specifically, the through opening 205 divides the passivation layer 204 into multiple unconnected regions, that is, the through opening 205 disconnects the passivation layer 204. This can alleviate the stress accumulation caused by the mismatch in the coefficient of thermal expansion between the passivation layer 204 and the metal structure, reduce the shear force on the passivation layer 204, thereby reducing the risk of cracking of the passivation layer 204, preventing deformation of the metal structure, and thus improving the waterproof capability and reliability of the device. It should be noted that, for ease of demonstration of the through opening 205, in Figure 2 Auxiliary dashed lines have been added to the middle. Figure 2 The auxiliary dashed lines in the diagram represent the passivation layer 204 that is not divided by the through opening 205, that is, the passivation layer 204 that does not include the through opening 205. In this application, for the purpose of illustrating different structures of the passivation layer 204, Figures 3 to 8 The schematic method and Figure 2 same.

[0082] Furthermore, in this embodiment, the through opening 205 includes a first opening 2051 that exposes the upper surface of the second metal layer 2032, the sidewall of the second metal layer 2032, and the exposed area of ​​the first metal layer 2031, and a second opening 2052 that exposes the exposed area of ​​the first metal layer 2031. That is, the passivation layer 204 is divided into a first part and a second part by the first opening 2051 and the second opening 2052, wherein the first part covers part of the exposed area of ​​the first metal layer 2031, and the second part covers part of the exposed area of ​​the first metal layer 2031, the sidewall of the first metal layer 2031, and the interlayer dielectric layer 206.

[0083] As an example, the thickness of the first metal layer 2031 is less than the thickness of the second metal layer 2032.

[0084] As an example, the area of ​​the first metal layer 2031 is larger than the area of ​​the second metal layer 2032.

[0085] As an example, the thickness of the passivation layer 204 ranges from 40 nm to 60 nm.

[0086] As an example, the system also includes an interlayer dielectric layer 206 located on the epitaxial layer 202, the interlayer dielectric layer including a first region 2061 covering the active region I and a second region 2062 covering the terminal region II, the metal layer structure 203 located on the first region 2061, and the passivation layer 204 located on the interlayer dielectric layer and covering the metal layer structure 203.

[0087] For example, please refer to Figure 3 The diagram shows a schematic representation of the structure of the second type of silicon carbide semiconductor device in this embodiment. Figure 2 The difference in the structure shown is that the through opening 205 includes a first opening 2051 that exposes the upper surface of the second metal layer 2032 and a second opening 2052 that exposes the upper surface of the second metal layer 2032, the sidewall of the second metal layer 2032 and the exposed area of ​​the first metal layer 2031. That is, the passivation layer 204 is divided into a first part and a second part by the first opening 2051 and the second opening 2052. The first part covers part of the upper surface of the second metal layer 2032, and the second part covers part of the exposed area of ​​the first metal layer 2031, the sidewall of the first metal layer 2031 and the interlayer dielectric layer 206.

[0088] For example, please refer to Figure 4 The diagram shows a structural schematic of the third type of silicon carbide semiconductor device in this embodiment, and... Figure 2 The difference in the structure shown is that the through opening 205 includes a first opening 2051 that exposes the upper surface of the second metal layer 2032 and a second opening 2052 that exposes the exposed area of ​​the first metal layer 2031. That is, the passivation layer 204 is divided into a first part, a second part, and a third part by the first opening 2051 and the second opening 2052. The first part covers part of the second metal layer 2032, the second part covers the sidewall of the second metal layer 2032, and the third part covers part of the exposed area of ​​the first metal layer 2031, the sidewall of the first metal layer 2031, and the interlayer dielectric layer 206.

[0089] For example, please refer to Figure 5The diagram shows the structure of the fourth type of silicon carbide semiconductor device in this embodiment, and... Figure 4 The difference in the structure shown is that the number of the first opening 2051 is one, that is, the passivation layer 204 is divided into a first part and a second part by the first opening 2051 and the second opening 2052. The first part covers the sidewall of the second metal layer 2032 and part of the exposed area of ​​the first metal layer 2031, and the second part covers part of the exposed area of ​​the first metal layer 2031, the sidewall of the first metal layer 2031 and the interlayer dielectric layer 206.

[0090] For example, please refer to Figure 6 The diagram shows the structure of the fifth type of silicon carbide semiconductor device in this embodiment, and... Figure 5 The difference in the structure shown is that the first part of the passivation layer 204 covers part of the upper surface of the second metal layer 2032, the sidewall of the second metal layer 2032, and part of the exposed area of ​​the first metal layer 2031.

[0091] For example, please refer to Figure 7 The diagram shows the structure of the sixth type of silicon carbide semiconductor device in this embodiment, and... Figure 4 The difference in the structure shown is that there are two second openings 2052, that is, the passivation layer 204 is divided into a first part, a second part, a third part and a fourth part by two first openings 2051 and two second openings 2052. The first part covers part of the upper surface of the second metal layer 2032, the second part covers the sidewall of the second metal layer 2032, the third part covers part of the exposed area of ​​the first metal layer 2031, and the fourth part covers the exposed area of ​​the first metal layer 2031, the sidewall of the first metal layer 2031 and the interlayer dielectric layer 206.

[0092] For example, please refer to Figure 8 The diagram shows the structure of the seventh type of silicon carbide semiconductor device in this embodiment, and... Figure 7 The difference in the structure shown is that the number of the first opening 2051 is three.

[0093] As an example, the longitudinal cross-sectional shape of the first opening 2051 is any one of trapezoidal, rectangular or elliptical, and the longitudinal cross-sectional shape of the second opening 2052 is any one of trapezoidal, rectangular or elliptical.

[0094] It should be noted that this embodiment only lists the cases where the number of the first opening 2051 is one, two, or three, and the number of the second opening 2052 is one or two. It is not limited to this embodiment. In other examples, the number of the first opening 2051 and the number of the second opening 2052 can also be set to other numbers as needed.

[0095] The silicon carbide semiconductor device of this embodiment, by providing a passivation layer with through-holes at different locations, can effectively alleviate stress accumulation, reduce shear force, prevent cracks or deformation in the passivation layer, and improve the device's waterproof capability and reliability.

[0096] Example 2

[0097] Please see Figures 9 to 15 This embodiment adopts a technical solution that is basically the same as that in Embodiment 1. The difference is that this embodiment also includes a field oxide layer 207 located between the epitaxial layer 202 and the interlayer dielectric layer 206, and the field oxide layer 207 covers the terminal region II.

[0098] It should be noted that, Figures 9 to 15 The structure of the passivation layer 204 shown is respectively similar to... Figures 2 to 8 The structure of the passivation layer 204 shown is the same. That is to say, Figure 9 and Figure 2 Having the same through opening 205, Figure 10 and Figure 3 Having the same through opening 205, Figure 11 and Figure 4 Having the same through opening 205, Figure 12 and Figure 5 Having the same through opening 205, Figure 13 and Figure 6 Having the same through opening 205, Figure 14 and Figure 7 Having the same through opening 205, Figure 15 and Figure 8 It has the same through opening 205.

[0099] The silicon carbide semiconductor device in this embodiment divides the passivation layer into multiple unconnected regions, which can effectively avoid stress accumulation in the passivation layer, prevent cracks or deformation, and improve the device's waterproof capability and reliability.

[0100] Example 3

[0101] Please see Figures 16 to 22This embodiment adopts the same technical solution as Embodiment 2, except that in this embodiment, the field oxide layer 207 extends to the active region I and covers part of the active region I.

[0102] It should be noted that, Figures 16 to 22 The structure of the passivation layer 204 shown is respectively similar to... Figures 9 to 15 The structure of the passivation layer 204 shown is the same. That is to say, Figure 16 and Figure 9 Having the same through opening 205, Figure 17 and Figure 10 Having the same through opening 205, Figure 18 and Figure 11 Having the same through opening 205, Figure 19 and Figure 12 Having the same through opening 205, Figure 20 and Figure 13 Having the same through opening 205, Figure 21 and Figure 14 Having the same through opening 205, Figure 22 and Figure 15 It has the same through opening 205.

[0103] The passivation layer of the silicon carbide semiconductor device in this embodiment has a through-hole, which can effectively alleviate stress accumulation, reduce shear force, and prevent cracks or deformation of the passivation layer during TCT and TS tests, thereby improving the device's waterproof capability and reliability.

[0104] Example 4

[0105] Please see Figures 23 to 29 This embodiment adopts a technical solution that is basically the same as that in Embodiment 1. The difference is that in this embodiment, the terminal area II includes a non-exposed area covered by the second area 2062 and an exposed area not covered by the second area 2062. The non-exposed area and the exposed area are arranged along the direction of the second area 2062 away from the first area 2061. A field oxide layer 207 is provided between the second area and the non-exposed area. The through opening 205 also includes a third opening 2053 that exposes the exposed area of ​​the terminal area.

[0106] It should be noted that, Figures 23 to 29 The positions of the first opening 2051 and the second opening 2052 shown are respectively... Figures 2 to 8 The first opening 2051 and the second opening 2052 shown are in the same position. That is to say, Figure 23 and Figure 9 Having the same first opening 2051 and second opening 2052, Figure 24 and Figure 10 Having the same first opening 2051 and second opening 2052, Figure 25 and Figure 11 Having the same first opening 2051 and second opening 2052, Figure 26 and Figure 12 Having the same first opening 2051 and second opening 2052, Figure 27 and Figure 13 Having the same first opening 2051 and second opening 2052, Figure 28 and Figure 14 Having the same first opening 2051 and second opening 2052, Figure 29 and Figure 15 They have the same first opening 2051 and second opening 2052.

[0107] The passivation layer of the silicon carbide semiconductor device in this embodiment has multiple through openings located at different positions, which can effectively relieve stress on the passivation layer during TCT and TS tests, thereby reducing the probability of cracks or deformation in the passivation layer and improving the device's waterproof capability and reliability.

[0108] In summary, the silicon carbide semiconductor device of this invention includes a substrate, an epitaxial layer, a metal layer structure, and a passivation layer. The epitaxial layer is located on the substrate and is divided into an active region and a terminal region surrounding the active region. The metal layer structure is located on the active region and includes a stacked first metal layer and a second metal layer. The second metal layer partially covers the first metal layer, providing an exposed area not covered by the second metal layer. The passivation layer is located on the epitaxial layer and covers the metal layer structure. The passivation layer has at least two through-holes that divide the passivation layer into multiple unconnected regions. By providing a passivation layer with through-holes, the silicon carbide semiconductor device of this invention can effectively alleviate stress accumulation, reduce shear force, prevent cracks or deformation in the passivation layer, and improve the device's waterproof capability and reliability. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0109] The above embodiments are merely illustrative of the principles and effects of this utility model and are not intended to limit the scope of this utility model. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this utility model. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this utility model should still be covered by the claims of this utility model.

Claims

1. A silicon carbide semiconductor device, characterized by, include: Substrate; An epitaxial layer is located on the substrate, and the epitaxial layer is divided into an active region and a terminal region located around the active region; A metal layer structure is located on the active region. The metal layer structure includes a stacked first metal layer and a second metal layer, and the second metal layer covers a portion of the first metal layer so that the first metal layer has an exposed area that is not covered by the second metal layer. A passivation layer is located on the epitaxial layer and covers the metal layer structure. The passivation layer has at least two through openings that divide the passivation layer into multiple unconnected regions.

2. The silicon carbide semiconductor device of Claim 1, wherein: It also includes an interlayer dielectric layer located on the epitaxial layer, the interlayer dielectric layer including a first region covering the active region and a second region covering the terminal region, the metal layer structure being located on the first region, and the passivation layer being located on the interlayer dielectric layer and covering the metal layer structure.

3. The silicon carbide semiconductor device of Claim 2, wherein: The through opening further includes a first opening that exposes the upper surface of the second metal layer, the sidewalls of the second metal layer, and the exposed area of ​​the first metal layer, and a second opening that exposes the exposed area of ​​the first metal layer.

4. The silicon carbide semiconductor device of Claim 2, wherein: The through opening includes a first opening that exposes the upper surface of the second metal layer and a second opening that exposes the upper surface of the second metal layer, the sidewalls of the second metal layer, and the exposed area of ​​the first metal layer.

5. The silicon carbide semiconductor device of Claim 2, wherein: The through-hole includes a first opening that exposes the upper surface of the second metal layer and a second opening that exposes the exposed area of ​​the first metal layer.

6. The silicon carbide semiconductor device of any of Claims 3-5, wherein: A field oxide layer is provided between the epitaxial layer and the interlayer dielectric layer, and the field oxide layer covers the terminal region.

7. The silicon carbide semiconductor device of Claim 6, wherein: The field oxide layer extends into the active region and covers a portion of the active region.

8. The silicon carbide semiconductor device of any of Claims 3-5, wherein: The terminal area includes a non-exposed area covered by the second region and an exposed area not covered by the second region. The non-exposed area and the exposed area are arranged along the direction of the second region away from the first region, and a field oxide layer is provided between the second region and the non-exposed area.

9. The silicon carbide semiconductor device of Claim 8, wherein: The through opening also includes a third opening that exposes the terminal area.

10. The silicon carbide semiconductor device of Claim 1, wherein: The thickness of the first metal layer is less than the thickness of the second metal layer.

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