A capacitor current-limiting charging control circuit

Abstract

The utility model discloses a kind of for capacitor current-limiting charging control circuit, belong to charging control circuit technical field, including charging power output circuit, the input end electric connection power supply of this charging power output circuit, the output end coupling charging power tube drive circuit and charging current acquisition circuit and the capacitor to be charged of charging power output circuit, charging power tube drive circuit coupling charging current control circuit, the output end coupling charging current sampling circuit of this charging current control circuit.

Description

Technical Field

[0001] This utility model relates to a charging control circuit, and more particularly to a capacitor current-limiting charging control circuit, belonging to the technical field of charging control circuits. Background Technology

[0002] With the development of technology and the emergence of various new technologies, new requirements have been put forward for power supplies. Some special power supplies have also begun to be created, such as pulse power supplies that can generate high energy in a short time. They are widely used in industrial, medical, scientific research and other fields.

[0003] In the field of electronics, capacitors are often used to store energy and release the stored energy to maintain the expected energy supply when the power supply is insufficient or in other special circumstances. When charging a capacitor, a large current is generated due to the potential difference between the voltage applied to the capacitor and the voltage across the capacitor. The larger the potential difference, the larger the current generated. Typically, the charging current of the capacitor can be limited by using a series current-limiting resistor or a current-limiting inductor.

[0004] In circuit design, there are situations where capacitors are repeatedly charged from a lower voltage to the higher voltage using a higher voltage (such as hundreds of volts or higher). If the power supply is directly applied to the capacitor, the instantaneous current will be very large, posing a risk of burning out the power supply. The conventional solution is to use a series resistor or inductor to limit the current. However, in some cases, when the selected resistor or inductor meets the current requirement, its size is unacceptable. When an acceptable resistor or inductor is selected, the current cannot meet the requirements. Therefore, a capacitor current-limiting charging control circuit is designed to solve the above problems. Utility Model Content

[0005] The main purpose of this invention is to provide a capacitor current-limiting charging control circuit.

[0006] The objective of this utility model can be achieved by adopting the following technical solution:

[0007] A capacitor current-limiting charging control circuit includes a charging power output circuit, the input terminal of which is electrically connected to a power supply.

[0008] The output terminal of the charging power output circuit is coupled to the charging power transistor drive circuit, the charging current acquisition circuit, and the capacitor to be charged.

[0009] The charging power transistor drive circuit is coupled to the charging current control circuit, and the output of the charging current control circuit is coupled to the charging current sampling circuit.

[0010] Preferably, the charging power output circuit includes a power switch Q1, a buffer inductor L1, and a freewheeling diode D1;

[0011] The power switch Q1 is an IGBT or MOS switch. Q1 has at least three terminals. Node C of Q1 is the control node. Applying an appropriate high / low voltage to B controls the conduction and disconnection between A and B. Control node C is connected to the output node E of the charging power transistor drive circuit. Node A of Q1 is connected to the positive terminal of the power supply used to charge the target capacitor C1. Node B of Q1 is connected to the cathode of the freewheeling diode D1 and the output reference point GND_H of the charging power transistor drive circuit. The anode of the freewheeling diode D1 is connected to the negative terminal GND_P of the power supply used to charge the target capacitor C1.

[0012] Preferably, node B of power switch Q1 is electrically connected to one end of resistor Rd2 and one end of air circuit breaker DZ1, and the other end of air circuit breaker DZ1 and the other end of resistor Rd2 are electrically connected to node A of power switch Q1.

[0013] Preferably, the charging current control circuit includes a comparator U1 and resistors R1, R2, R3, R4 and R5;

[0014] The charging current control circuit has an input terminal F and an output terminal G. The input terminal F is connected to the output node H of the charging current sampling circuit and one end of R5. The other end of R5 is connected to the inverting input terminal of the comparator U1. The output terminal G is connected to the output terminal of the comparator U1. The output terminal of the comparator U1 is also connected to the connection node of R1 and R2. One end of R1 is connected to VCC1, and the other end is connected to R2. The other end of R2 is connected to R3, R4 and the non-inverting input terminal of the comparator U1. The other end of R4 is connected to GND, and the other end of R3 is connected to VCC2.

[0015] Preferably, the charging power transistor drive circuit includes at least one input terminal D, one output terminal E, and one output reference point GND_H. The input terminal D is connected to the output terminal G of the charging current control circuit, the output terminal E is connected to the C contact of Q1 in the charging power output circuit, and the output reference point GND_H is connected to the B contact of the power switch Q1 in the charging power output circuit. During operation, the drive signal generated by the output terminal E to the output reference point GND_H is the signal generated by the input signal control of the input terminal D to GND.

[0016] Preferably, the charging current sampling circuit is a sampling or resistance transformer. The charging current sampling circuit has a signal output node H, which can generate a voltage signal to GND that is positively correlated with the charging current of the target capacitor C1. The node H is connected to the input terminal F of the charging current control circuit.

[0017] The beneficial technical effects of this utility model are as follows:

[0018] This utility model provides a current-limiting charging control circuit for capacitors. It has a simple structure, good stability, and the charging current can be flexibly configured according to its own needs. It is a current-limiting solution that can provide a large current for charging similar capacitors. For similar needs that require high voltage and high power to charge capacitors, this solution is a cost-effective, flexible, efficient, stable, and space-saving solution with a very good market prospect. Attached Figure Description

[0019] Figure 1 This is a block diagram of a preferred embodiment of a capacitor current-limiting charging control circuit according to the present invention;

[0020] Figure 2 This is a partial basic schematic diagram of a preferred embodiment of a capacitor current-limiting charging control circuit according to the present invention;

[0021] Figure 3 This is a schematic diagram of a preferred embodiment of a capacitor current-limiting charging control circuit according to the present invention;

[0022] Figure 4 This is a schematic diagram of a preferred embodiment of a capacitor current-limiting charging control circuit according to the present invention;

[0023] Figure 5 This is a schematic diagram of a preferred embodiment three of the capacitor current-limiting charging control circuit according to the present invention. Detailed Implementation

[0024] To enable those skilled in the art to understand the technical solution of this utility model more clearly, the present utility model will be further described in detail below with reference to the embodiments and accompanying drawings, but the implementation of this utility model is not limited thereto.

[0025] like Figures 1-5 As shown, this embodiment provides a capacitor current-limiting charging control circuit, comprising four parts: a charging power output circuit, a charging power transistor driving circuit, a charging current control circuit, and a charging current sampling circuit. (See attached diagram.) Figure 1 .

[0026] As attached Figure 2 The charging power output circuit includes a power switch Q1, a buffer inductor L1, and a freewheeling diode D1. The power switch Q1 includes, but is not limited to, IGBTs and MOSFETs, and is characterized by having at least three contacts, as shown in the attached diagram. Figure 2In the charging power output circuit, there are three terminals A, B, and C. Terminal C of Q1 is the control terminal. Applying an appropriate high or low voltage level to B through C controls the conduction and disconnection between A and B. Terminal C is connected to the output terminal E of the charging power transistor driver circuit. Terminal A of Q1 is connected to the positive terminal of the power supply used to charge the target capacitor C1. Terminal B of Q1, the cathode of the freewheeling diode D1, and the output reference point GND_H of the charging power transistor driver circuit are connected together. The anode of D1 is connected to the negative terminal GND_P of the power supply used to charge the target capacitor C1 (for ease of explanation, if GND_P is connected to GND, it is uniformly labeled GND in the image, as shown in the attached diagram). Figure 3 The buffer inductor L1, the target capacitor C1, and the charging current sampling circuit are connected in series and then in parallel across the freewheeling diode D1. The series connection of the buffer inductor L1, the target capacitor C1, and the charging current sampling circuit is not subject to any particular order, and includes, but is not limited to, the example connections shown in the accompanying drawings.

[0027] As attached Figure 2 The charging current control circuit mainly includes a comparator U1 (U1 includes, but is not limited to, a dedicated comparator and an operational amplifier), resistors R1, R2, R3, R4, and R5. The circuit is characterized by having an input terminal F and an output terminal G. The input terminal F is connected to the output node H of the charging current sampling circuit and one end of R5. The other end of R5 is connected to the inverting input terminal of the comparator U1. Normally, R5 can be reduced to 0 ohms, meaning it can be directly short-circuited and removed. The output terminal G is connected to the output terminal of the comparator U1. The output terminal of the comparator U1 is also connected to the connection node of R1 and R2. One end of R1 is connected to VCC1, and the other end is connected to R2. The other end of R2 is connected to R3, R4, and the non-inverting input terminal of the comparator U1. The other end of R4 is connected to GND, and the other end of R3 is connected to VCC2. VCC1 and VCC2 can be the same or different, depending on the actual operating requirements.

[0028] As attached Figure 2 The charging power transistor drive circuit mainly has at least one input terminal D, one output terminal E, and one output reference point GND_H. The input terminal D is connected to the output terminal G of the charging current control circuit, the output terminal E is connected to the C contact of Q1 in the charging power output circuit, and the output reference point GND_H is connected to the B contact of Q1 in the charging power output circuit. Its characteristic is that, during operation, the drive signal generated by the output terminal E to the output reference point GND_H is a signal generated by controlling the input signal of the input terminal D to GND.

[0029] The charging current sampling circuit can be a sampling resistor, a current transformer, or other current sensor. The characteristic of the charging current sampling circuit is that it has a signal output node H, which can generate a voltage signal to GND that is positively correlated with the charging current of the target capacitor C1 (hereinafter referred to as the charging current). The node H is connected to the input terminal F of the charging current control circuit.

[0030] As attached Figure 2 The charging power output circuit includes a power switch Q1, a buffer inductor L1, and a freewheeling diode D1. The power switch Q1 includes, but is not limited to, IGBTs and MOSFETs, and has at least three contacts, as shown in the attached diagram. Figure 2 In the charging power output circuit, there are three terminals A, B, and C. Terminal C of Q1 is the control terminal. Applying an appropriate high or low voltage level to B through C controls the conduction and disconnection between A and B. Terminal C is connected to the output terminal E of the charging power transistor driver circuit. Terminal A of Q1 is connected to the positive terminal of the power supply used to charge the target capacitor C1. Terminal B of Q1, the cathode of the freewheeling diode D1, and the output reference point GND_H of the charging power transistor driver circuit are connected together. The anode of D1 is connected to the negative terminal GND_P of the power supply used to charge the target capacitor C1 (for ease of explanation, if GND_P is connected to GND, it is uniformly labeled GND in the image, as shown in the attached diagram). Figure 3 The buffer inductor L1, the target capacitor C1, and the charging current sampling circuit are connected in series and then in parallel across the freewheeling diode D1. The series connection of the buffer inductor L1, the target capacitor C1, and the charging current sampling circuit is not subject to any particular order, and includes, but is not limited to, the example connections shown in the accompanying drawings.

[0031] The charging current control circuit mainly includes a comparator U1 (U1 includes, but is not limited to, a dedicated comparator and operational amplifier), resistors R1, R2, R3, R4, and R5. This circuit has one input terminal F and one output terminal G. Input terminal F is connected to the output node H of the charging current sampling circuit and one end of R5. The other end of R5 is connected to the inverting input terminal of comparator U1. Normally, R5 can be reduced to 0 ohms, meaning it can be directly short-circuited and removed. The output terminal G is connected to the output terminal of comparator U1. The output terminal of comparator U1 is also connected to the connection node of R1 and R2. One end of R1 is connected to VCC1, and the other end is connected to R2. The other end of R2 is connected to R3, R4, and the non-inverting input terminal of comparator U1. The other end of R4 is connected to GND, and the other end of R3 is connected to VCC2. VCC1 and VCC2 can be the same or different, depending on the actual operating requirements.

[0032] The charging power transistor drive circuit mainly has at least one input terminal D, one output terminal E, and one output reference point GND_H. The input terminal D is connected to the output terminal G of the charging current control circuit. The output terminal E is connected to the C contact of Q1 in the charging power output circuit. The output reference point GND_H is connected to the B contact of Q1 in the charging power output circuit. During operation, the drive signal generated by the output terminal E to the output reference point GND_H is the signal generated by the input signal control of the input terminal D to GND.

[0033] The charging current sampling circuit can be a sampling resistor, a current transformer, or other current sensor. The characteristic of the charging current sampling circuit is that it has a signal output node H, which can generate a voltage signal to GND that is positively correlated with the charging current of the target capacitor C1 (hereinafter referred to as the charging current). The node H is connected to the input terminal F of the charging current control circuit.

[0034] Appendix Figure 3 Appendix Figure 4 and attached Figure 5 The following are three typical example diagrams provided for this technical solution.

[0035] Explanation of the principle is attached. Figure 3 :

[0036] The EN node in the charging power transistor drive circuit (hereinafter referred to as the drive circuit) in the figure is an extended function. When this point has low resistance with GND, the drive circuit will be turned off. The output terminal E of the drive circuit is low relative to its output reference point GND_H. Since the output point E of the drive circuit is connected to the control terminal C node of Q1 in the charging power output circuit (hereinafter referred to as the power output circuit) in the figure, and the output reference point GND_H of the drive circuit is connected to the B terminal of Q1 in the power output circuit, the drive signal of Q1 is the signal of the E terminal relative to GND_H. Therefore, when the EN of the drive circuit has low resistance with GND, Q1 in the power output circuit will be turned off because its control terminal cannot get a high drive level, and the power supply cannot charge the target capacitor C1 through Q1. Therefore, when EN is low impedance relative to GND, since the target capacitor C1 has no charging current, point H is 0V relative to GND. Because point H is connected to point F of the charging current control circuit (hereinafter referred to as the control circuit), it can be understood that the voltage at the input terminal F of the control circuit is 0V. Due to the presence of VCC2, even if the internal resistance of R3 is set relatively large, the non-inverting input terminal of comparator U1 in the control circuit (U1 can be an op-amp, but it is recommended to use a dedicated voltage comparator for better results. In this case, U1 will be considered a dedicated comparator that only outputs high and low impedance) will also have a small voltage greater than 0V. Clearly, the voltage at the input terminal of the comparator in the diagram is... The voltage at the inverting input of comparator U1 can be considered equal to the voltage at the input F. Therefore, it can be understood that the voltage at the non-inverting input of comparator U1 is greater than the voltage at its inverting input. Hence, U1 outputs high impedance, which further increases the voltage at the non-inverting input of U1 due to the addition of VCC1. This increased voltage is referred to as Vsh. The value of Vsh can be determined by the resistor network formed by R1, R2, R3, R4, and R5 (hereinafter referred to as Rw) and the relevant power supply voltages VCC1 and VCC2. Therefore, the value of Vsh can be adjusted by adjusting the resistance values ​​in VCC1, VCC2, and Rw. When the voltage signal received at the input terminal F of the control circuit causes the inverting input terminal of U1 to be higher than the non-inverting input terminal of U1, U1 will output low impedance. This can be understood as R2 and R4 forming a new resistor Rb1 in parallel. One end of Rb1 is connected to GND, and the other end of Rb1 is connected in series with R3 to VCC2. The voltage across Rb1 from VCC2 through R3 (hereinafter referred to as Vsl) is the voltage at the non-inverting input terminal of the comparator U1 at this time. It is easy to see from the diagram that the voltage signal output by the output node H of the charging current sampling circuit is positively correlated with the charging current through the target capacitor C1, hereinafter referred to as the charging current. Based on the above description, it can be simplified to understand that the voltage signal at the inverting input terminal of U1 is positively correlated with the charging current.Combining the above description and example diagram, it is easy to see that when EN has low resistance to GND, Q2 in the drive circuit is turned off, and there is no current on the primary side of the optocoupler IC1 in the drive circuit. This causes the output terminal of IC1 to output a low level relative to its output reference point GND_H, making point E of the drive circuit low relative to the output reference point GND_H. This causes Q1 in the power output circuit to turn off, and the power supply for charging the target capacitor C1 is cut off. After stabilization, it can be considered that no charging current flows through the target capacitor C1. Since the voltage signal at the inverting input terminal of U1 is positively correlated with the charging current, the inverting input terminal of U1 can be considered to be 0V at this time. U1 outputs high resistance, so the voltage at the non-inverting input terminal of U1 is Vsh.When U1 outputs high impedance, VCC1 pulls up the output of U1 through R1, causing the input terminal D in the power drive circuit to reach a high level under the pull-up effect of R1. It is important to note that the design must ensure that the high level voltage obtained by pulling up input terminal D through R1 is higher than the reference voltage VREF at the inverting terminal of comparator U2 (similar to U1, U2 is also considered a dedicated comparator that only outputs high and low impedance). Under the above conditions, comparator U2 will output high impedance. At this time, if EN turns to high impedance, VCC3 will enable the drive through R6 and R7. In the circuit, Q2, i.e., the collector (c) and emitter (e) of transistor Q2 in the driving circuit, is turned on. Current flows from R9 through the primary side of the optocoupler IC1 connected in series with the collector of Q2 to GND via the primary side of IC1 and the transistor Q2. This causes IC1 to output VCCH1, which is high relative to GND_H. This high level will turn on Q1 of the power output circuit, allowing the power supply for charging the target capacitor C1 to be connected in series with the slow charging inductor L1, the target capacitor C1, and the charging current sampling circuit (hereinafter referred to as the sampling circuit). Because the sampling circuit has a very small internal resistance, the voltage across the capacitor rises slowly when the capacitance is large. Combined with the effect of L1, the charging current flowing through the target capacitor C1 can be considered to gradually increase from 0, as shown in the rising waveform at point F in the figure. This also means that the voltage at the inverting input of U1 rises along with the charging current. When the voltage at the inverting input of U1 rises slightly higher than Vsh, U1 will output low resistance, and the voltage at the non-inverting input of U1 will decrease to Vsl. The voltage at the non-inverting input of U2 will also be less than that connected to the inverting input of U2 due to the low resistance output of U1. The VREF reference voltage at the input terminal also causes U2 to output low impedance, which in turn causes the output point E of the drive circuit to output a low level relative to the output reference point GND_H of the drive circuit, thus turning off Q1 in the power output circuit. The charging current flowing through the target capacitor C1 will continue through the freewheeling diode D1 due to the buffer inductor L1, thus causing the charging current to gradually decrease, as shown in the falling segment of the waveform at point F in the control circuit diagram. When the inverting input terminal of U1 follows the charging current and decreases to slightly below Vsl, the comparator U1 turns on again and continues to the next cycle. Since the current through the target capacitor does not change suddenly but changes in a triangular waveform, the final waveform of the output terminal E of the drive circuit relative to the output reference point GND_H of the drive circuit is the waveform at point E in the diagram. As the voltage of the target capacitor C1 gradually increases due to charging, the charging current rises more and more slowly, resulting in a longer charging current rise time. If an oscilloscope is used to monitor the waveform of point E relative to GND_H and the waveform of point G relative to GND in the figure, it will be found that both waveforms are square waves with a continuously increasing duty cycle. This waveform is entirely generated by the charging current. Therefore, the PWM waves at points G and E can be considered adaptive PWM waves.Based on the above analysis, it can be assumed that after EN in the diagram changes from low resistance to high resistance, the target capacitor C1 begins to charge. Since the comparator gain is very large, the charging current flowing through the target capacitor C1 when the voltage at the inverting input of U1 equals Vsh is considered to be the maximum charging current. Conversely, the charging current when the voltage at the inverting input of U1 equals Vsl is the minimum charging current for generating adaptive PWM.

[0037] In summary, Vsh > Vsl. Since both Vsh and Vsl can be set by configuring VCC1, VCC2, and the resistors in the resistor network Rw, the charging current of the target capacitor C1 can also be controlled accordingly. Furthermore, since the PWM of the entire process is adaptively generated by the charging current, and high-power components can be easily selected in the power output circuit, this solution is applicable to high-power applications and has the characteristics of flexibility and good stability. Therefore, this solution has good market prospects.

[0038] The above description is only a further embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Any equivalent substitutions or changes made by those skilled in the art within the scope disclosed by the present utility model, based on the technical solution and concept of the present utility model, shall fall within the protection scope of the present utility model.

Claims

1. A capacitor current-limiting charging control circuit, characterized in that: It includes a charging power output circuit, the input of which is electrically connected to a power supply. The output terminal of the charging power output circuit is coupled to the charging power transistor drive circuit, the charging current acquisition circuit, and the capacitor to be charged. The charging power transistor drive circuit is coupled to the charging current control circuit, and the output of the charging current control circuit is coupled to the charging current sampling circuit. The charging power output circuit includes a power switch Q1, a buffer inductor L1, and a freewheeling diode D1; The power switch Q1 is an IGBT or MOS switch. Q1 has at least three terminals. Node C of Q1 is the control node. Applying an appropriate high / low voltage to B controls the conduction and disconnection between A and B. Control node C is connected to the output node E of the charging power transistor drive circuit. Node A of Q1 is connected to the positive terminal of the power supply used to charge the target capacitor C1. Node B of Q1 is connected to the cathode of the freewheeling diode D1 and the output reference point GND_H of the charging power transistor drive circuit. The anode of the freewheeling diode D1 is connected to the negative terminal GND_P of the power supply used to charge the target capacitor C1.

2. The capacitor current-limiting charging control circuit according to claim 1, characterized in that: The B node of power switch Q1 is electrically connected to one end of resistor Rd2 and one end of air circuit breaker DZ1. The other end of air circuit breaker DZ1 and the other end of resistor Rd2 are electrically connected to the A node of power switch Q1.

3. The capacitor current-limiting charging control circuit according to claim 1, characterized in that: The charging current control circuit includes comparator U1, resistors R1, R2, R3, R4 and R5; The charging current control circuit has an input terminal F and an output terminal G. The input terminal F is connected to the output node H of the charging current sampling circuit and one end of R5. The other end of R5 is connected to the inverting input terminal of the comparator U1. The output terminal G is connected to the output terminal of the comparator U1. The output terminal of the comparator U1 is also connected to the connection node of R1 and R2. One end of R1 is connected to VCC1, and the other end is connected to R2. The other end of R2 is connected to R3, R4 and the non-inverting input terminal of the comparator U1. The other end of R4 is connected to GND, and the other end of R3 is connected to VCC2.

4. A capacitor current-limiting charging control circuit according to claim 1, characterized in that: The charging power transistor drive circuit includes at least one input terminal D, one output terminal E, and one output reference point GND_H. The input terminal D is connected to the output terminal G of the charging current control circuit. The output terminal E is connected to the C contact of Q1 in the charging power output circuit. The output reference point GND_H is connected to the B contact of the power switch Q1 in the charging power output circuit. During operation, the drive signal generated by the output terminal E to the output reference point GND_H is the signal generated by the input signal control of the input terminal D to GND.

5. A capacitor current-limiting charging control circuit according to claim 4, characterized in that: The charging current sampling circuit is a sampling or resistance transformer. The charging current sampling circuit has a signal output node H, which can generate a voltage signal to GND that is positively correlated with the charging current of the target capacitor C1. The node H is connected to the input terminal F of the charging current control circuit.

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