A reference circuit with high load and low voltage coefficient

Abstract

The application relates to a high-load low-voltage coefficient reference circuit, which comprises a PNP transistor and an operational amplifier; the emitter of the PNP transistor and the non-inverting terminal of the operational amplifier are connected with a current source, the current source is connected with a reference voltage VDD, the non-inverting terminal of the operational amplifier is connected with the emitter of the PNP transistor, the inverting terminal of the operational amplifier is connected between a resistor R1 and a resistor R2 to form a negative feedback, the other end of the resistor R2 is connected with the ground, and the other end of the resistor R1 is connected with VOUT; the base and the collector of the PNP transistor are connected with the ground; and the output terminal of the operational amplifier is connected with VOUT. The reference circuit disclosed by the application sacrifices a slight temperature coefficient to realize significant optimization of area and power consumption.

Description

Technical Field

[0001] This utility model relates to the field of power management technology, specifically to a reference circuit with high load and low voltage coefficient. Background Technology

[0002] Bandgap reference circuits are an essential part of electronic circuits, indispensable modules in analog devices such as ADCs, DACs, and linear voltage regulators, as well as many mixed-signal circuits. As the performance requirements of these circuits become increasingly stringent, higher demands are being placed on bandgap reference circuits. Most existing common bandgap reference circuits use an 8:1 PNP transistor to form the base-emitter voltage difference, which exhibits a positive temperature coefficient. Bipolar transistors, on the other hand, have a negative temperature coefficient for their base-emitter voltage. Utilizing these positive and negative temperature coefficients, a zero-temperature coefficient reference can be designed. However, this circuit uses a total of 10 PNP transistors, consuming a significant amount of area. Furthermore, the reference voltage generated by this circuit is easily affected by the power supply voltage, making it unsuitable for circuits with a wide power supply voltage range and unable to handle large currents. Summary of the Invention

[0003] To address the problems existing in the prior art, this invention proposes a high-load, low-voltage coefficient reference circuit that can maintain good linear regulation and power supply rejection ratio over a wide power supply voltage range.

[0004] The high-load, low-voltage coefficient reference circuit described in this application includes a PNP transistor and an operational amplifier. The emitter of the PNP transistor and the non-inverting input of the operational amplifier are both connected to a current source, which is connected to a reference voltage VDD. The non-inverting input of the operational amplifier is connected to the emitter of the PNP transistor. The inverting input of the operational amplifier is connected between resistors R1 and R2 to form negative feedback. The other end of resistor R2 is grounded, and the other end of resistor R1 is connected to VOUT. The base and collector of the PNP transistor are both grounded. The output of the operational amplifier is connected to VOUT.

[0005] Furthermore, the reference circuit described in this utility model also includes a startup circuit and a PTAT current source; The startup circuit consists of PMOS transistors M1-M4, NMOS transistors M5 and M6, as well as PMOS transistors M7 and M8. The sources of PMOS transistors M1, M7, and M8 are all connected to the reference voltage VDD. The drain of PMOS transistor M1 is connected to the source of PMOS transistor M2, the drain of PMOS transistor M2 is connected to the source of PMOS transistor M3, and the drain of PMOS transistor M3 is connected to the source of PMOS transistor M4. The drain of PMOS transistor M4 is connected to the drain of NMOS transistor M5, and the drain of NMOS transistor M5 is shorted to its gate. The drain of PMOS transistor M7 is connected to both the gate of PMOS transistor M8 and the drain of NMOS transistor M6. The gate of NMOS transistor M6 is connected to the gate of NMOS transistor M5. The gate of PMOS transistor M7 and the drain of PMOS transistor M8 are the outputs of the aforementioned startup circuit. The gates of PMOS transistors M1-M4 are grounded, and the sources of NMOS transistors M5 and M6 are both grounded.

[0006] Furthermore, in the reference circuit described in this utility model, the PTAT current source is composed of PMOS transistors M9, M10, M13, M11, and M12, as well as resistor R3. The sources of PMOS transistors M9, M10, and M13 are all connected to the reference voltage VDD. The gate of PMOS transistor M9 is connected to both the gates of PMOS transistors M10 and M13, and the drain of PMOS transistor M9 is shorted to its gate. The drain of PMOS transistor M9 is connected to the drain of NMOS transistor M11, and the drain of PMOS transistor M10 is connected to the drain of NMOS transistor M12. The source of NMOS transistor M11 is connected to ground via resistor R3, and the source of NMOS transistor M12 is grounded, with its drain shorted to its gate. The gate of NMOS transistor M11 is connected to the gate of NMOS transistor M12 and serves as the A output of the PTAT current source. The drain of PMOS transistor M13 serves as the B output of the PTAT current source and is connected to the emitter of a PNP transistor. The gate of PMOS transistor M7 is connected to the drain of PMOS transistor M9 and the drain of NMOS transistor M11; the drain of PMOS transistor M8 is connected to the gate of NMOS transistor M11 and the gate of NMOS transistor M12.

[0007] The PMOS transistors M13 and M9 form a current mirror to replicate the current of one path of PMOS transistor M9.

[0008] Furthermore, in the reference circuit described in this utility model, the operational amplifier is a two-stage operational amplifier, which is composed of PMOS transistors M14, M15, M16, M17, M18, M19, and M20, as well as capacitor C0 and resistor R0. The sources of PMOS transistors M14, M15, and M19 are all connected to the reference voltage VDD. The drain of PMOS transistor M14 is connected to both the drain of NMOS transistor M16 and the gate of PMOS transistor M19. The gate of NMOS transistor M16 serves as the non-inverting input of the second-stage operational amplifier and is connected to the emitter of the PNP transistor. The drain of PMOS transistor M15 is connected to the drain of NMOS transistor M17, and the gate of PMOS transistor M14 is connected to the gate of PMOS transistor M15, with the drain and gate of PMOS transistor M15 shorted. The source of NMOS transistor M16 is connected to the source of NMOS transistor M17, and the drain of PMOS transistor M19 is connected to the drain of NMOS transistor M20. The A output of the PTAT current source is simultaneously connected to the gate of NMOS transistor M18 and the gate of NMOS transistor M20; the drain of NMOS transistor M18 is simultaneously connected to the source of NMOS transistors M16 and M17; the source of NMOS transistor M20 is connected to VOUT after being connected in series with resistors R2 and R1; the gate of NMOS transistor M17 is connected between resistors R1 and R2 as the inverting input of the second-stage operational amplifier to form negative feedback; the drain of PMOS transistor M19 is connected to VOUT, and a capacitor C0 and a resistor R0 are connected in series between the gate and drain of PMOS transistor M19; The sources of both NMOS transistors M18 and M20 are grounded.

[0009] Furthermore, in the reference circuit described in this utility model, the resistor R1 is a resistor with a positive temperature coefficient, and the resistor R2 is a resistor with a negative temperature coefficient.

[0010] Furthermore, the reference circuit described in this utility model is a reference circuit with a temperature coefficient of VOUT of less than 80ppm / ℃.

[0011] Furthermore, the reference circuit described in this utility model is a reference circuit with a linear regulation rate of less than 1 mV / V.

[0012] Furthermore, the reference circuit described in this utility model is a reference circuit with a power supply rejection ratio greater than 50 dB.

[0013] Compared with the prior art, the present invention has the following beneficial technical effects: This invention constructs a high-load, low-voltage coefficient reference circuit using only a single PNP transistor. Compared to existing typical bandgap reference circuits, this significantly reduces the number of transistors used, substantially lowers chip area, and improves the integration density and cost-effectiveness of the integrated circuit. Simultaneously, by introducing a feedback network composed of positive and negative temperature coefficient resistors, the temperature drift of the base-emitter voltage is effectively compensated, resulting in good stability of the reference voltage over a wide temperature range and achieving a low temperature coefficient output.

[0014] Furthermore, this circuit exhibits excellent voltage stability within a supply voltage range of 1.5V-3.6V, with a linear regulation as low as 0.91 mV / V, effectively suppressing the impact of power supply fluctuations on the reference voltage. It also boasts a high power supply rejection ratio (up to 50.39 dB), making it suitable for noise-sensitive high-precision analog or mixed-signal systems. This design achieves significant optimization of area and power consumption with a slight sacrifice in temperature coefficient while maintaining good electrical performance, making it particularly suitable for applications in portable devices, low-voltage, highly integrated chips. Attached Figure Description

[0015] Figure 1 This is the reference circuit diagram of the high load and low voltage coefficient described in Embodiment 1 of this application; Figure 2 This is the reference circuit diagram of the high load and low voltage coefficient described in Embodiment 2 of this application; Figure 3 This is a DC temperature scan of the reference circuit described in Embodiment 2 of this application; Figure 4 This describes the DC voltage scan of the reference circuit described in Embodiment 2 of this application. Figure 5 This is a simulation of the power supply rejection ratio of the reference circuit described in Embodiment 2 of this application; Figure 6 This is a typical bandgap reference circuit as described in Comparative Example 1 of this application. Detailed Implementation

[0016] To provide a deeper and clearer understanding of the technical content and effects of this invention, detailed embodiments will be described with reference to the accompanying drawings. It should be noted that the embodiments described are merely one possible implementation of the invention and are not limited to all possible implementations. Under the guidance of this invention, those skilled in the art can derive all alternative implementations without inventive effort, and these alternative implementations also fall within the scope of protection covered by this invention. For parts of the derivational embodiments where conditions are not specifically specified, operation should be performed according to industry-standard conditions or conditions recommended by the manufacturer.

[0017] In the following description, unless otherwise specified, the same reference numerals generally refer to the same or similar elements. The embodiments provided herein do not reflect all implementations of the invention, but are merely exemplary embodiments illustrating apparatuses and methods consistent with certain aspects of the invention. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0018] A high-load, low-voltage coefficient reference circuit includes a PNP transistor and an operational amplifier. The emitter of the PNP transistor and the non-inverting input of the operational amplifier are both connected to a current source, which is connected to a reference voltage VDD. The non-inverting input of the operational amplifier is connected to the emitter of the PNP transistor. The inverting input of the operational amplifier is connected between resistors R1 and R2 to form negative feedback. The other end of resistor R2 is grounded, and the other end of resistor R1 is connected to VOUT. The base and collector of the PNP transistor are both grounded. The output of the operational amplifier is connected to VOUT.

[0019] In other embodiments, the reference circuit further includes a startup circuit and a PTAT current source; The startup circuit consists of PMOS transistors M1-M4, NMOS transistors M5 and M6, as well as PMOS transistors M7 and M8. The sources of PMOS transistors M1, M7, and M8 are all connected to the reference voltage VDD. The drain of PMOS transistor M1 is connected to the source of PMOS transistor M2, the drain of PMOS transistor M2 is connected to the source of PMOS transistor M3, and the drain of PMOS transistor M3 is connected to the source of PMOS transistor M4. The drain of PMOS transistor M4 is connected to the drain of NMOS transistor M5, and the drain of NMOS transistor M5 is shorted to its gate. The drain of PMOS transistor M7 is connected to both the gate of PMOS transistor M8 and the drain of NMOS transistor M6. The gate of NMOS transistor M6 is connected to the gate of NMOS transistor M5. The gate of PMOS transistor M7 and the drain of PMOS transistor M8 are the outputs of the aforementioned startup circuit. The gates of PMOS transistors M1-M4 are grounded, and the sources of NMOS transistors M5 and M6 are both grounded.

[0020] In other embodiments, the PTAT current source is composed of PMOS transistors M9, M10, M13, M11, and M12, and resistor R3. The sources of PMOS transistors M9, M10, and M13 are all connected to the reference voltage VDD. The gate of PMOS transistor M9 is connected to both the gates of PMOS transistors M10 and M13, and the drain of PMOS transistor M9 is shorted to its gate. The drain of PMOS transistor M9 is connected to the drain of NMOS transistor M11, and the drain of PMOS transistor M10 is connected to the drain of NMOS transistor M12. The source of NMOS transistor M11 is connected to ground via resistor R3, and the source of NMOS transistor M12 is grounded, with its drain shorted to its gate. The gate of NMOS transistor M11 is connected to the gate of NMOS transistor M12 and serves as the A output of the PTAT current source. The drain of PMOS transistor M13 serves as the B output of the PTAT current source and is connected to the emitter of a PNP transistor. The gate of PMOS transistor M7 is connected to the drain of PMOS transistor M9 and the drain of NMOS transistor M11; the drain of PMOS transistor M8 is connected to the gate of NMOS transistor M11 and the gate of NMOS transistor M12.

[0021] In other embodiments, the operational amplifier is a two-stage operational amplifier, which is composed of PMOS transistors M14, M15, M16, M17, M18, M19, and M20, as well as capacitor C0 and resistor R0. The sources of PMOS transistors M14, M15, and M19 are all connected to the reference voltage VDD. The drain of PMOS transistor M14 is connected to both the drain of NMOS transistor M16 and the gate of PMOS transistor M19. The gate of NMOS transistor M16 serves as the non-inverting input of the second-stage operational amplifier and is connected to the emitter of the PNP transistor. The drain of PMOS transistor M15 is connected to the drain of NMOS transistor M17, and the gate of PMOS transistor M14 is connected to the gate of PMOS transistor M15, with the drain and gate of PMOS transistor M15 shorted. The source of NMOS transistor M16 is connected to the source of NMOS transistor M17, and the drain of PMOS transistor M19 is connected to the drain of NMOS transistor M20. The A output of the PTAT current source is simultaneously connected to the gate of NMOS transistor M18 and the gate of NMOS transistor M20; the drain of NMOS transistor M18 is simultaneously connected to the source of NMOS transistors M16 and M17; the source of NMOS transistor M20 is connected to VOUT after being connected in series with resistors R2 and R1; the gate of NMOS transistor M17 is connected between resistors R1 and R2 as the inverting input of the second-stage operational amplifier to form negative feedback; the drain of PMOS transistor M19 is connected to VOUT, and a capacitor C0 and a resistor R0 are connected in series between the gate and drain of PMOS transistor M19; The sources of both NMOS transistors M18 and M20 are grounded.

[0022] In other embodiments, the resistor R1 is a resistor R1 with a positive temperature coefficient, and the resistor R2 is a resistor R2 with a negative temperature coefficient.

[0023] In other embodiments, the reference circuit is a reference circuit with a temperature coefficient of VOUT of less than 80 ppm / ℃.

[0024] In other embodiments, the reference circuit is a reference circuit with a linear regulation rate of less than 1 mV / V.

[0025] In other embodiments, the reference circuit is a reference circuit with a power supply rejection ratio greater than 50 dB. Example 1

[0026] A reference circuit with high load and low voltage coefficient, such as Figure 1 As shown, the system includes a PNP transistor and an operational amplifier. The emitter of the PNP transistor and the non-inverting input of the operational amplifier are both connected to a current source, which is connected to a reference voltage VDD. The non-inverting input of the operational amplifier is connected to the emitter of the PNP transistor. The inverting input of the operational amplifier is connected between resistors R1 and R2 to form negative feedback. The other end of resistor R2 is grounded, and the other end of resistor R1 is connected to VOUT. The base and collector of the PNP transistor are both grounded. The output of the operational amplifier is connected to VOUT. In this embodiment 1, resistor R1 has a positive temperature coefficient, and resistor R2 has a negative temperature coefficient. Example 2

[0027] A reference circuit with high load and low voltage coefficient, such as Figure 2 As shown, the reference circuit, in addition to that described in Embodiment 1, also includes a startup circuit and a PTAT current source.

[0028] The startup circuit consists of PMOS transistors M1-M4, NMOS transistors M5 and M6, as well as PMOS transistors M7 and M8. The sources of PMOS transistors M1, M7, and M8 are all connected to the reference voltage VDD. The drain of PMOS transistor M1 is connected to the source of PMOS transistor M2, the drain of PMOS transistor M2 is connected to the source of PMOS transistor M3, and the drain of PMOS transistor M3 is connected to the source of PMOS transistor M4. The drain of PMOS transistor M4 is connected to the drain of NMOS transistor M5, and the drain of NMOS transistor M5 is shorted to its gate. The drain of PMOS transistor M7 is connected to both the gate of PMOS transistor M8 and the drain of NMOS transistor M6. The gate of NMOS transistor M6 is connected to the gate of NMOS transistor M5. The gate of PMOS transistor M7 and the drain of PMOS transistor M8 are the outputs of the aforementioned startup circuit. The gates of PMOS transistors M1-M4 are grounded, and the sources of NMOS transistors M5 and M6 are both grounded.

[0029] In this embodiment 2, the PTAT current source is composed of PMOS transistors M9, M10, M13, M11, and M12, as well as resistor R3. The sources of PMOS transistors M9, M10, and M13 are all connected to the reference voltage VDD. The gate of PMOS transistor M9 is connected to both the gates of PMOS transistors M10 and M13, and the drain of PMOS transistor M9 is shorted to its gate. The drain of PMOS transistor M9 is connected to the drain of NMOS transistor M11, and the drain of PMOS transistor M10 is connected to the drain of NMOS transistor M12. The source of NMOS transistor M11 is connected to ground via resistor R3, and the source of NMOS transistor M12 is grounded, with its drain shorted to its gate. The gate of NMOS transistor M11 is connected to the gate of NMOS transistor M12 and serves as the A output of the PTAT current source. The drain of PMOS transistor M13 serves as the B output of the PTAT current source and is connected to the emitter of a PNP transistor. The gate of PMOS transistor M7 is connected to the drain of PMOS transistor M9 and the drain of NMOS transistor M11; the drain of PMOS transistor M8 is connected to the gate of NMOS transistor M11 and the gate of NMOS transistor M12.

[0030] The operational amplifier is a two-stage operational amplifier, which consists of PMOS transistors M14, M15, M16, M17, M18, M19, and M20, as well as capacitor C0 and resistor R0. The sources of PMOS transistors M14, M15, and M19 are all connected to the reference voltage VDD. The drain of PMOS transistor M14 is connected to both the drain of NMOS transistor M16 and the gate of PMOS transistor M19. The gate of NMOS transistor M16 serves as the non-inverting input of the second-stage operational amplifier and is connected to the emitter of the PNP transistor. The drain of PMOS transistor M15 is connected to the drain of NMOS transistor M17, and the gate of PMOS transistor M14 is connected to the gate of PMOS transistor M15, with the drain and gate of PMOS transistor M15 shorted. The source of NMOS transistor M16 is connected to the source of NMOS transistor M17, and the drain of PMOS transistor M19 is connected to the drain of NMOS transistor M20. The A output of the PTAT current source is simultaneously connected to the gate of NMOS transistor M18 and the gate of NMOS transistor M20; the drain of NMOS transistor M18 is simultaneously connected to the source of NMOS transistors M16 and M17; the source of NMOS transistor M20 is connected to VOUT after being connected in series with resistors R2 and R1; the gate of NMOS transistor M17 is connected between resistors R1 and R2 as the inverting input of the second-stage operational amplifier to form negative feedback; the drain of PMOS transistor M19 is connected to VOUT, and a capacitor C0 and a resistor R0 are connected in series between the gate and drain of PMOS transistor M19; The sources of both NMOS transistors M18 and M20 are grounded.

[0031] In this embodiment 2, the reference circuit has a temperature coefficient of VOUT of less than 80 ppm / ℃. The reference circuit also has a linear regulation of less than 1 mV / V and a power supply rejection ratio greater than 50 dB. In this embodiment 2, the reference voltage VDD is 1.8V, and tests have shown excellent voltage stability within a range of 1.8V ± 10%.

[0032] Further testing showed that it exhibited excellent voltage stability within the range of 1.5V-3.6V.

[0033] like Figure 3 As shown, a DC simulation was performed on the reference circuit described in Example 2, scanning the temperature range from -40 to 125°C, observing the output waveform, and measuring the reference temperature coefficient: .

[0034] like Figure 4 As shown, a DC simulation was performed on the reference circuit described in Example 2. The power supply voltage was scanned within the range of 0~3V, and the output waveform was observed. Within the normal operating range of the power supply voltage (1.8V±10%), the linear regulation was measured as follows: .

[0035] like Figure 5As shown, AC simulation was performed on the reference circuit described in Example 2, with the frequency scanning between 1-0.1 GHz. A small signal fluctuation was applied to the power supply voltage, and the measured power supply rejection ratio was 50.39 dB.

[0036] Comparative Example 1: A typical bandgap reference circuit includes 10 PNP transistors, such as... Figure 6 As shown, Q2:Q1 = 8:1, meaning there are 8 Q2 transistors (m=8, equivalent to 8 transistors in parallel). The gates of PMOS transistors M1', M2', and M3' are connected, and their sources are all connected to VDD. The output of the operational amplifier is connected to the gates of PMOS transistors M1' and M2'. The drain of PMOS transistor M1' and the emitter of PNP transistor Q1 are connected to the inverting input of the operational amplifier. The drain of PMOS transistor M2' and the emitter of PNP transistor Q2 are connected through resistor R1'. The drain of M2' and one end of resistor R1' are connected to the non-inverting input of the operational amplifier. The drain of PMOS transistor M3' and the emitter of PNP transistor Q3 are connected through resistor R2'. The drain of PMOS transistor M3' and one end of resistor R2' are connected to the output port VDD. OUT The collectors and bases of PNP transistors Q1, Q2, and Q3 are all connected to GND.

[0037] The typical bandgap reference described in Comparative Example 1 exhibits the following performance characteristics: temperature coefficient of 10-100 ppm / ℃, power supply voltage rejection ratio of approximately 50-80 dB, and linear regulation of approximately 0.1 mV / V to 1 mV / V.

[0038] In summary, the temperature coefficient, power supply voltage rejection ratio, and linear regulation of the high-load, low-voltage coefficient reference circuit described in this application can all reach the level of the prior art. However, by eliminating multiple PNP transistors, the core circuit is simplified, and the chip area is greatly reduced.

Claims

1. A reference circuit with high load and low voltage coefficient, characterized in that, It includes a PNP transistor and an operational amplifier; the emitter of the PNP transistor and the non-inverting input of the operational amplifier are both connected to a current source, the current source is connected to a reference voltage VDD, the non-inverting input of the operational amplifier is connected to the emitter of the PNP transistor, the inverting input of the operational amplifier is connected between resistors R1 and R2 to form negative feedback, the other end of resistor R2 is grounded, and the other end of resistor R1 is connected to VOUT; the base and collector of the PNP transistor are both grounded; the output of the operational amplifier is connected to VOUT.

2. The high-load, low-voltage coefficient reference circuit according to claim 1, characterized in that, The reference circuit also includes a startup circuit and a PTAT current source; The startup circuit consists of PMOS transistors M1-M4, NMOS transistors M5 and M6, as well as PMOS transistors M7 and M8. The sources of PMOS transistors M1, M7, and M8 are all connected to the reference voltage VDD. The drain of PMOS transistor M1 is connected to the source of PMOS transistor M2, the drain of PMOS transistor M2 is connected to the source of PMOS transistor M3, and the drain of PMOS transistor M3 is connected to the source of PMOS transistor M4. The drain of PMOS transistor M4 is connected to the drain of NMOS transistor M5, and the drain of NMOS transistor M5 is shorted to its gate. The drain of PMOS transistor M7 is connected to both the gate of PMOS transistor M8 and the drain of NMOS transistor M6. The gate of NMOS transistor M6 is connected to the gate of NMOS transistor M5. The gate of PMOS transistor M7 and the drain of PMOS transistor M8 are the outputs of the aforementioned startup circuit. The gates of PMOS transistors M1-M4 are grounded, and the sources of NMOS transistors M5 and M6 are both grounded.

3. The high-load, low-voltage coefficient reference circuit according to claim 2, characterized in that, The PTAT current source consists of PMOS transistors M9, M10, M13, M11, and M12, as well as resistor R3. The sources of PMOS transistors M9, M10, and M13 are all connected to the reference voltage VDD. The gate of PMOS transistor M9 is connected to both the gates of PMOS transistors M10 and M13, and the drain of PMOS transistor M9 is shorted to its gate. The drain of PMOS transistor M9 is connected to the drain of NMOS transistor M11, and the drain of PMOS transistor M10 is connected to the drain of NMOS transistor M12. The source of NMOS transistor M11 is connected to ground via resistor R3, and the source of NMOS transistor M12 is grounded, with its drain shorted to its gate. The gate of NMOS transistor M11 is connected to the gate of NMOS transistor M12 and serves as the A output of the PTAT current source. The drain of PMOS transistor M13 serves as the B output of the PTAT current source and is connected to the emitter of a PNP transistor. The gate of PMOS transistor M7 is connected to the drain of PMOS transistor M9 and the drain of NMOS transistor M11; the drain of PMOS transistor M8 is connected to the gate of NMOS transistor M11 and the gate of NMOS transistor M12.

4. The high-load, low-voltage coefficient reference circuit according to claim 2, characterized in that, The operational amplifier is a two-stage operational amplifier, which consists of PMOS transistors M14, M15, M16, M17, M18, M19, and M20, as well as capacitor C0 and resistor R0. The sources of PMOS transistors M14, M15, and M19 are all connected to the reference voltage VDD. The drain of PMOS transistor M14 is connected to both the drain of NMOS transistor M16 and the gate of PMOS transistor M19. The gate of NMOS transistor M16 serves as the non-inverting input of the second-stage operational amplifier and is connected to the emitter of the PNP transistor. The drain of PMOS transistor M15 is connected to the drain of NMOS transistor M17, and the gate of PMOS transistor M14 is connected to the gate of PMOS transistor M15, with the drain and gate of PMOS transistor M15 shorted. The source of NMOS transistor M16 is connected to the source of NMOS transistor M17, and the drain of PMOS transistor M19 is connected to the drain of NMOS transistor M20. The A output of the PTAT current source is simultaneously connected to the gate of NMOS transistor M18 and the gate of NMOS transistor M20; the drain of NMOS transistor M18 is simultaneously connected to the source of NMOS transistors M16 and M17; the source of NMOS transistor M20 is connected to VOUT after being connected in series with resistors R2 and R1; the gate of NMOS transistor M17 is connected between resistors R1 and R2 as the inverting input of the second-stage operational amplifier to form negative feedback; the drain of PMOS transistor M19 is connected to VOUT, and a capacitor C0 and a resistor R0 are connected in series between the gate and drain of PMOS transistor M19; The sources of both NMOS transistors M18 and M20 are grounded.

5. The high-load, low-voltage coefficient reference circuit according to claim 1, characterized in that, The resistor R1 is a resistor with a positive temperature coefficient, and the resistor R2 is a resistor with a negative temperature coefficient.

6. The high-load, low-voltage coefficient reference circuit according to claim 1, characterized in that, The reference circuit is a reference circuit with a temperature coefficient of VOUT of less than 80 ppm / ℃.

7. The high-load, low-voltage coefficient reference circuit according to claim 1, characterized in that, The reference circuit is a reference circuit with a linear regulation rate of less than 1 mV / V.

8. The high-load, low-voltage coefficient reference circuit according to claim 1, characterized in that, The reference circuit is a reference circuit with a power supply rejection ratio greater than 50 dB.

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