A synchronous satellite audio receiving system

Abstract

The utility model discloses a synchronous satellite audio frequency receiving system, include: case and its on setting satellite radio frequency, asynchronous serial, IP network data, external reference clock, digital and analog audio frequency output etc. multiple kind of interface, the clock synchronization module and audio frequency processing module are equipped in the case. Each input interface is electrically connected with audio frequency processing module input end, and external reference clock interface is electrically connected with clock synchronization module input end, and clock synchronization module output end is connected to the clock input end of audio frequency processing module, and audio frequency processing module output end connects each audio frequency output interface. The utility model discloses a synchronous satellite audio frequency receiving system, through the integration of multiple signal access mode and high accuracy clock synchronization framework, solved the traditional equipment interface single, audio frequency output synchronous precision low problem, realized the high fidelity, high synchronous receiving and output of multi -source signal under the professional broadcast scene.

Description

Technical Field

[0001] This utility model relates to the field of satellite broadcasting and receiving technology, and in particular to a synchronous satellite audio receiving system. Background Technology

[0002] In specialized fields such as broadcasting and emergency broadcasting, satellite audio receivers are crucial devices for receiving and decoding audio program content from satellite signals. Traditional satellite audio receivers suffer from numerous limitations in their hardware architecture.

[0003] First, its interface design is relatively simple, typically equipped only with a satellite signal input interface, and at most supplemented by a simple network or ASI interface. This hardware limitation makes it difficult for a single device to simultaneously access and process multiple signal sources from satellite, SDH network (ASI), and IP network, failing to meet the multi-routing and multi-format signal scheduling requirements of modern broadcast systems. When it is necessary to receive signals from different sources, multiple different receiving devices must be deployed, resulting in high system complexity, increased costs, and inconvenient operation and maintenance.

[0004] More critically, the audio output synchronization accuracy of existing equipment is generally low. Internally, they typically rely on a single clock source (such as an internal crystal oscillator or a clock from the transport stream), lacking dedicated high-precision clock synchronization circuitry. When multiple receivers work together to provide synchronized audio broadcasts to different zones, the slight deviations in the clock sources of each device gradually accumulate, easily leading to perceptible delays in the output audio. This results in audio-visual asynchrony and asynchrony between broadcast content in different zones, severely impacting broadcast quality.

[0005] Furthermore, the existing equipment fails to optimize and integrate various interfaces and functional modules in its structural layout, often resulting in a cluttered rear panel layout that hinders rapid installation, identification, and maintenance. Additionally, the status indication function is weak, making it difficult for maintenance personnel to quickly and intuitively determine the equipment's operating status and signal lockout conditions.

[0006] Therefore, there is an urgent need in this field for a new type of synchronous satellite audio receiving system that can innovate in hardware structure, integrate multiple input interfaces, and have a built-in high-precision clock synchronization mechanism to solve the above-mentioned technical problems. Utility Model Content

[0007] To address the issues of limited interface and insufficient audio output synchronization accuracy in existing satellite audio receivers, this invention proposes a synchronous satellite audio receiving system.

[0008] The specific technical solution is as follows:

[0009] A synchronous satellite audio receiving system includes: a chassis, wherein the chassis is provided with a satellite radio frequency signal input interface, at least one asynchronous serial interface, at least one IP network data interface, an external reference clock input interface, at least one digital audio output interface and at least one analog audio output interface;

[0010] The clock synchronization module and audio processing module are located inside the chassis.

[0011] The satellite radio frequency signal input interface, the asynchronous serial interface, and the IP network data interface are all electrically connected to the input terminal of the audio processing module, and are used to input transmission stream signals to the audio processing module;

[0012] The external reference clock input interface is electrically connected to the input terminal of the clock synchronization module;

[0013] The output of the clock synchronization module is electrically connected to the clock input of the audio processing module to provide a synchronization clock signal to the audio processing module.

[0014] The output of the audio processing module is electrically connected to both the digital audio output interface and the analog audio output interface. Hardware integration enables unified access to satellite, ASI, and IP signal sources, and an independent clock synchronization module provides a high-precision clock reference for audio processing, ensuring multi-source signal reception capability and synchronized output audio performance from the system's core.

[0015] Furthermore, the external reference clock input interface includes a 10MHz clock input interface and a 1PPS second pulse input interface, with the 10MHz clock input interface having an input impedance of 50Ω. This provides two industry-standard high-precision clock access methods, enhancing the system's compatibility with external timing systems; the 50Ω impedance matching ensures the integrity of clock signal transmission, reduces reflection loss, and improves synchronization stability.

[0016] Furthermore, the asynchronous serial interface is an ASI interface, using a BNC connector, and the input impedance of the asynchronous serial interface is 75Ω. Adopting a BNC interface and 75Ω impedance, which are standard in the professional broadcasting field, ensures the standardization and signal quality of ASI signal transmission, avoiding signal attenuation and distortion caused by impedance mismatch.

[0017] Furthermore, the digital audio output interface consists of two independent audio output interfaces conforming to the AES / EBU protocol, with XLR connectors as the physical interface. It provides two high-quality, interference-resistant balanced digital audio outputs that can be directly connected to professional audio equipment, meeting the application requirements of two-channel stereo output or two independent mono outputs.

[0018] Furthermore, the system also includes an analog audio output circuit. The input terminal of the analog audio output circuit is electrically connected to the output terminal of the audio processing module, and the output terminal of the analog audio output circuit is electrically connected to the analog audio output interface. In addition to digital output, it provides analog audio output capability, enhancing the compatibility and applicability of the device, allowing connection to traditional or simple devices with only analog input interfaces.

[0019] Furthermore, the clock synchronization module includes a clock switching circuit and an internal oscillator. The first input terminal of the clock switching circuit is electrically connected to an external reference clock input interface, the second input terminal of the clock switching circuit is electrically connected to the internal oscillator, and the output terminal of the clock switching circuit is electrically connected to the clock input terminal of the audio processing module. This constitutes a clock supply system with redundant backup and automatic switching functions. When the external high-precision clock source fails, it can automatically switch to the internal oscillator, ensuring that the system can continue to work under abnormal conditions and improving the reliability and robustness of the system.

[0020] Furthermore, the IP network data interface has two ports: a data input / output port and a network management port. The data input / output port is electrically connected to the audio processing module, and the network management port is used to connect to a remote monitoring terminal. This achieves physical isolation between the data stream and the management stream. The data port is dedicated to high-speed audio stream transmission, ensuring smooth data flow; the independent management port is dedicated to network management operations such as monitoring and configuration, avoiding interference between the management data stream and the real-time audio stream, and also improving network security.

[0021] Furthermore, the chassis is equipped with a status indicator unit, which includes multiple LED indicators. The system also includes a main control module, and the LED indicators are electrically connected to the I / O ports of the main control module to indicate the system status. The LED indicators provide maintenance personnel with intuitive and real-time indications of the system's operating status (such as signal lockout, clock synchronization, power supply, etc.), greatly facilitating on-site monitoring, troubleshooting, and routine maintenance of the equipment.

[0022] The above technical solution has the following advantages or technical effects:

[0023] This utility model integrates multiple signal input, high-precision synchronization processing, multi-style audio output, and status monitoring into a single chassis through an integrated hardware structure design. It solves the core needs of the professional broadcasting field for multi-source signal reception, high-fidelity decoding, high-synchronization-precision output, and convenient operation and maintenance, and significantly improves the system's integration, reliability, and user experience. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the system structure of this utility model;

[0025] Figure 2 This is a flowchart of the clock synchronization module of this utility model. Detailed Implementation

[0026] To make the technical solution of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] like Figure 1 As shown, a synchronous satellite audio receiving system is presented. This system uses a standard 19-inch 1U high metal chassis, providing excellent electromagnetic shielding and heat dissipation. The front panel of the chassis features a power switch, a 40-character x 2-line LCD display, six function buttons, and multiple LED status indicators. The rear panel is the interface area, with all interfaces arranged vertically according to their function.

[0028] The synchronous satellite audio receiving system specifically includes:

[0029] Input interface group: located in the upper middle area of ​​the rear panel:

[0030] Satellite RF signal input interface: adopts an F-type connector for receiving L-band (950MHz-2150MHz) satellite downlink signals.

[0031] Asynchronous serial interface: It adopts two BNC-K female connectors (ASI IN1 / ASI IN2), with an input impedance of 75Ω, conforms to the SMPTE 310M standard, and is used to receive ASI transport streams from SDH networks, etc.

[0032] IP network data interface: Includes two RJ45 Ethernet ports. The data input / output port (LAN2) is used to receive IP multicast / unicast streams; the independent network management port (LAN1 / NMS) is used for remote web management, SNMP monitoring, and software upgrades, achieving physical isolation between data flow and management flow.

[0033] The hardware integration of multiple input interfaces enables a single device to receive signals from three different sources: satellite, private network, and IP network, greatly improving the applicability and flexibility of the device.

[0034] Clock synchronization system:

[0035] External reference clock input interface: Located in the clock synchronization area at the bottom of the rear panel. Includes a 10MHz clock input interface and a 1PPS pulse-per-second input interface.

[0036] Clock synchronization module: Located on the motherboard inside the chassis, its core consists of a clock switching circuit (such as a programmable clock generator chip) and a high-stability temperature-compensated crystal oscillator (TCXO) as the internal oscillator. The two inputs of the switching circuit are connected to an external 10MHz / 1PPS interface and the internal oscillator, respectively, and its output generates the system master clock. The clock synchronization module's operation is as follows: Figure 2 As shown.

[0037] This hardware design constitutes a multi-source clock synchronization architecture. It prioritizes the use of an external high-precision clock source, and automatically and seamlessly switches to an internal oscillator when the external source fails, ensuring that the system can obtain a stable and reliable clock reference under various operating conditions. This is the foundation for achieving high-precision audio synchronization output.

[0038] Core processing and output system:

[0039] Audio processing module: This module uses a large-scale FPGA chip (such as the Xilinx Artix-7 series) as its processing core. Its input receives TS streams from the demodulation chip or UDP packets from the IP network via a high-speed SerDes interface. Internally, the FPGA uses programming logic to implement functions such as transport stream demultiplexing, filtering specific audio packets based on PID, MPEG audio decoding (e.g., MP2), and digital audio gain adjustment.

[0040] Audio output interfaces: Located at the top of the rear panel audio output area, including:

[0041] Digital audio output interface: Provides two independent AES / EBU digital audio outputs, using XLR male (female) connectors, outputting balanced digital audio signals conforming to the AES3 standard;

[0042] Analog audio output interface: Provides one analog stereo output (L OUT / R OUT). The system internally has a high-performance stereo DAC chip (such as TI's PCM1794A) as the analog audio output circuit. Its I2S input is connected to the I2S output pin of the FPGA, and its analog output is amplified by an operational amplifier and then connected to the XLR interface.

[0043] The FPGA hardware processing ensures low latency and high stability in audio decoding. Both digital and analog output interfaces are available to meet the compatibility requirements of connecting to different new and old devices.

[0044] Status indication and control system:

[0045] Status indicator unit: The front panel LED indicators include: ASI (green), satellite reception (green), IP (green), 10M / 1PPS (green), alarm (red), and power (green). The driver terminals of these indicators are connected to the GPIO ports of the main control MCU.

[0046] Main control module: It adopts an ARM Cortex-M series microcontroller as the main control MCU, which is responsible for managing the front panel human-machine interaction, communicating with FPCA to obtain status information, driving the LCD and LED indicators, and communicating with the remote network management system through the network interface.

[0047] The status indication and control system provides both local and remote monitoring methods. LED indicators provide on-site maintenance personnel with the most intuitive and rapid status diagnosis basis, greatly improving the maintainability of the equipment.

[0048] The actual workflow of this system is as follows:

[0049] 1. Signal Input: Satellite signals, ASI signals, or IP network signals enter the device through the corresponding physical interface.

[0050] 2. Signal Demodulation and Extraction: Satellite signals are demodulated into TS streams by a dedicated demodulator chip; ASI signals are restored into TS streams by an interface chip; IP network data packets are received by a PHY chip, processed by the MAC layer, and then restored into TS streams. These three TS streams are then fed into the FPGA.

[0051] 3. Audio Processing: The FPGA selects the corresponding audio ES stream from the specified TS stream according to the user-preset audio PID, and decodes it to obtain PCM audio data.

[0052] 4. Clock Synchronization: The system prioritizes using a clock reference input from an external 10MHz / 1PPS interface. The low-jitter master clock generated by the clock synchronization module drives the audio processing logic within the FPGA and accurately timestamps or manages buffer delays on the decoded audio data to ensure that the output audio is synchronized with the reference clock.

[0053] 5. Audio Output: The processed PCM digital audio data is output as an AES / EBU signal directly through the FPGA's SPDIF encoder; the other path is transmitted to the DAC chip via the I2S bus, where it is converted into an analog audio signal for output.

[0054] 6. Status Monitoring: The main control MCU continuously queries the status of each functional module (demodulator, FPGA, clock synchronization module) and drives the front panel LCD and LEDs to display the status. Simultaneously, it reports the device's operating status to the network management system via the network management port.

[0055] The embodiments described above are merely illustrative of several implementations of this utility model, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of this utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these all fall within the protection scope of this utility model. Therefore, the protection scope of this utility model patent should be determined by the appended claims.

Claims

1. A synchronous satellite audio receiving system, characterized in that, Includes: a chassis, wherein the chassis is provided with a satellite radio frequency signal input interface, at least one asynchronous serial interface, at least one IP network data interface, an external reference clock input interface, at least one digital audio output interface and at least one analog audio output interface; The clock synchronization module and audio processing module are located inside the chassis. The satellite radio frequency signal input interface, the asynchronous serial interface, and the IP network data interface are all electrically connected to the input terminal of the audio processing module, and are used to input transmission stream signals to the audio processing module; The external reference clock input interface is electrically connected to the input terminal of the clock synchronization module; The output of the clock synchronization module is electrically connected to the clock input of the audio processing module to provide a synchronization clock signal to the audio processing module. The output of the audio processing module is electrically connected to the digital audio output interface and the analog audio output interface.

2. The synchronous satellite audio receiving system according to claim 1, characterized in that, The external reference clock input interface includes a 10MHz clock input interface and a 1PPS second pulse input interface, and the input impedance of the 10MHz clock input interface is 50Ω.

3. The synchronous satellite audio receiving system according to claim 1, characterized in that, The asynchronous serial interface is an ASI interface, using a BNC connector, and the input impedance of the asynchronous serial interface is 75Ω.

4. A synchronous satellite audio receiving system according to claim 1, characterized in that, The digital audio output interface consists of two independent audio output interfaces that conform to the AES / EBU protocol, and their physical interface is an XLR connector.

5. A synchronous satellite audio receiving system according to claim 1, characterized in that, The system also includes an analog audio output circuit, the input of which is electrically connected to the output of the audio processing module, and the output of which is electrically connected to the analog audio output interface.

6. A synchronous satellite audio receiving system according to claim 1, characterized in that, The clock synchronization module includes a clock switching circuit and an internal oscillator. The first input terminal of the clock switching circuit is electrically connected to an external reference clock input interface, the second input terminal of the clock switching circuit is electrically connected to the internal oscillator, and the output terminal of the clock switching circuit is electrically connected to the clock input terminal of the audio processing module.

7. A synchronous satellite audio receiving system according to claim 1, characterized in that, The IP network data interface has two ports, including a data input / output port and a network management port. The data input / output port is electrically connected to the audio processing module, and the network management port is used to connect to a remote monitoring terminal.

8. A synchronous satellite audio receiving system according to claim 1, characterized in that, The chassis is also equipped with a status indicator unit, which includes multiple LED indicators. The system also includes a main control module. The LED indicators are electrically connected to the I / O ports of the main control module to indicate the system status.

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