Memory device

Abstract

A memory device includes a substrate; a seven-transistor memory cell including a first fin and a second fin, the first fin being narrower than the second fin; first, second, third, fourth, and fifth gate structures, wherein the second gate structure and the third gate structure are located between the first gate structure and the fourth gate structure, wherein the fourth gate structure and the fifth gate structure extend along the same line, wherein the first gate structure and the fourth gate structure overlap the first fin, the second gate structure and the third gate structure overlap the first fin and the second fin, and the fifth gate structure overlaps the second fin in a top view; a plurality of p-type source / drain regions located on the first fin; and a plurality of n-type source / drain regions located on the second fin.

Description

Technical Field

[0001] This invention relates to semiconductor devices, and more particularly to a seven-transistor memory cell formed using a one-time oxide interposer process. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The fabrication method of semiconductor devices typically involves sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and then using photolithography to pattern the multiple material layers to form circuit components and units on the semiconductor substrate.

[0003] The semiconductor industry continues to shrink minimum structural dimensions to improve the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, or the like, in order to integrate more components into a given area. However, as the minimum structural dimensions shrink, additional problems arise that need to be addressed. Utility Model Content

[0004] In one embodiment, the memory device includes a substrate; and a seven-transistor memory cell including a first fin and a second fin extending above the substrate, wherein the first fin is narrower than the second fin; a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, and a fifth gate structure, wherein the second gate structure and the third gate structure are located between the first gate structure and the fourth gate structure, wherein the fourth gate structure and the fifth gate structure extend along a common line, wherein in the top view, the first gate structure and the fourth gate structure overlap with the first fin, the second gate structure and the third gate structure overlap with the first fin and the second fin, and the fifth gate structure overlaps with the second fin; a plurality of p-type source / drain regions are located on the first fin and on both sides of the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure; and a plurality of n-type source / drain regions are located on the second fin and on both sides of the second gate structure, the third gate structure, and the fifth gate structure.

[0005] In one embodiment, the memory device further includes: a plurality of first channel regions located above a first fin and between a plurality of individual p-type source / drain regions; and a plurality of second channel regions located above a second fin and between a plurality of individual n-type source / drain regions, wherein a first gate structure, a first portion of a second gate structure, a first portion of a third gate structure, and a fourth gate structure surround the plurality of individual first channel regions, wherein a second portion of a second gate structure, a second portion of a third gate structure, and a fifth gate structure surround the plurality of individual second channel regions.

[0006] In one embodiment, the seven-transistor memory cell includes a first write-through transistor located at the intersection of the first gate structure and the first fin.

[0007] In one embodiment, the seven-transistor memory cell includes a first pull-up transistor located at the intersection of a first portion of the second gate structure and the first fin.

[0008] In one embodiment, the seven-transistor memory cell includes a second pull-up transistor located at the intersection of a first portion of the third gate structure and the first fin.

[0009] In one embodiment, the seven-transistor memory cell includes a second write-through transistor located at the intersection of the fourth gate structure and the first fin.

[0010] In one embodiment, the seven-transistor memory cell includes a first pull-down transistor located at the intersection of a second portion of the second gate structure and a second fin.

[0011] In one embodiment, the seven-transistor memory cell includes a second pull-down transistor located at the intersection of a second portion of the third gate structure and a second fin.

[0012] In one embodiment, the seven-transistor memory cell includes a read-through transistor located at the intersection of the fifth gate structure and the second fin.

[0013] In one embodiment, the memory device further includes a dielectric plug separating the fourth gate structure from the fifth gate structure. Attached Figure Description

[0014] Figure 1 These are three-dimensional diagrams of nanostructured field-effect transistor devices in some embodiments.

[0015] Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figures 5A to 5C , Figures 6A to 6C , Figures 7A to 7C , Figures 8A to 8C , Figures 9A to 9C , Figures 10A to 10C , Figures 11A to 11C , Figures 12A to 12C , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figures 19A to 19H , Figure 20A ,and Figure 20B This is one embodiment, with various figures showing the nanostructured field-effect transistor device at various manufacturing stages.

[0016] Figure 21 This is a circuit diagram of a seven-transistor (7T) memory cell in one embodiment.

[0017] Figures 22A to 22E and Figure 23 This is another embodiment, with various figures showing the nanostructured field-effect transistor device at various manufacturing stages.

[0018] Figure 24A and 24B This is a flowchart of a method for forming a seven-transistor memory cell of a semiconductor device in some embodiments.

[0019] The reference numerals in the attached figures are explained as follows:

[0020] AA,A1-A1,A2-A2,A3-A3,BB,B1-B1,B2-B2,CC,DD,EE,FF,GG: Section

[0021] Dg, Dgc, W1, W2: Width

[0022] PD1, PD2: Pull-down transistors

[0023] PU1, PU2: Pull-up transistors

[0024] RBL: Read Bit Line

[0025] RPG: Reading the through-gate transistor

[0026] RWL: Read character lines

[0027] VDD: Power supply voltage

[0028] VSS: Electrical grounding

[0029] WBL: Write Bit Line

[0030] WBLB: Complementary Write Bit Line

[0031] WDP, WMG: Size

[0032] WPG1, WPG2: Write to the gate-through transistor

[0033] WWL: Write character line

[0034] 30, 100, 100A: Nanostructured Field-Effect Transistor Devices

[0035] 50: Substrate

[0036] 50U1, 50U2, 90U: Top surface

[0037] 52, 52A, 52B, 52C: First Semiconductor Materials

[0038] 53, 56: Gap

[0039] 54, 54A, 54B, 54C: Second semiconductor materials

[0040] 54S: Sidewall

[0041] 55: Inner spacer

[0042] 57: Disposable materials

[0043] 58: Side wall depression

[0044] 64: Multi-layer stacking

[0045] 90, 90A, 90B: Fins

[0046] 91: Fin-like structure

[0047] 92: Layered stacking

[0048] 93: Passage Area

[0049] 94,104: Masking

[0050] 94A, 104A: First masking layer

[0051] 94B, 104B: Second masking layer

[0052] 96: Quarantine Zone

[0053] 97: Dummy gate dielectric layer

[0054] 102, 102A, 102B, 102C, 102D: Dummy gates

[0055] 102AM: Part

[0056] 103: Depression

[0057] 106,113: Area

[0058] 108: Gate spacer

[0059] 110,132: Opening

[0060] 112: Source / Drain Region

[0061] 114: First interlayer dielectric layer

[0062] 116: Contact Etching Stop Layer

[0063] 120: Gate dielectric layer

[0064] 122: Gate

[0065] 123, 123A, 123B, 123C, 123D, 123D1, 123D2: Gate structures

[0066] 125, 127: Dielectric plugs

[0067] 129: Dielectric Structure

[0068] 131: Hard mask layer

[0069] 141: Dielectric Materials

[0070] 142: Barrier Layer

[0071] 143: Anisotropic Etching Process

[0072] 145: Contact

[0073] 145A, 145D, 145S: Source / Drain Contacts

[0074] 145G: Gate contact

[0075] 146: Seed layer

[0076] 147, 147A, 147B, 147C, 147D: Through holes

[0077] 148: Filler Metal

[0078] 149, 149A, 149B: Conductive circuits

[0079] 151: Second interlayer dielectric layer

[0080] 153: Dielectric layer

[0081] 155: Internal Wiring Structure

[0082] 161, 163, 165, 171, 173, 175, 177: Transistors

[0083] 1000: Methods

[0084] 1010, 1020, 1030, 1040, 1050, 1060, 1070, 1080: Steps Detailed Implementation

[0085] The following detailed description is illustrated with accompanying drawings to aid in understanding various aspects of this utility model. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be arbitrarily increased or decreased for clarity.

[0086] It is understood that the different embodiments or examples provided below may implement different structures of the present invention. The embodiments of specific components and arrangements are intended to simplify this disclosure and not to limit the present invention. For example, a description of forming a first component on a second component includes situations where the two are in direct contact, or where there are additional components spaced between them that are not in direct contact.

[0087] Furthermore, spatial relative terms such as "below," "under," "slightly below," "above," "slightly above," or similar terms can be used to simplify the description of the relative relationship between one element and another in the illustration. Spatial relative terms can be extended to elements used in other directions, not limited to the illustrated direction. Elements can also be rotated 90 degrees or other angles; therefore, directional terms are only used to describe the direction in the illustration. In the disclosure herein, unless otherwise stated, the same or similar reference numerals in different figures refer to the same or similar components formed using the same or similar materials and through the same or similar forming processes. Furthermore, figures with the same numbers but different letters (such as...) Figures 5A to 5C () indicates different views of the device at the same stage of the process.

[0088] In some embodiments, a one-time oxide interposer process is used when fabricating the nanostructured field-effect transistors of a seven-transistor memory cell. The one-time oxide interposer process uses a sacrificial material such as silicon oxide, silicon oxynitride, aluminum oxide, or the like to replace the first semiconductor material layer, such as the silicon-germanium layer, in a layered stack containing interleaved first semiconductor material layers, such as silicon-germanium layers, and second semiconductor material layers, such as silicon layers. This replacement helps reduce the mixing of silicon and germanium and provides high etch selectivity between the sacrificial material and the second semiconductor material. In this way, the dimensions of the second semiconductor material forming the channel region of the nanostructured field-effect transistor can be retained in subsequent processes to improve drive current and reduce the resistance of the channel region. Using a one-time oxide interposer allows for flexible placement of the read-pause transistors (RPGs) in the seven-transistor memory cell. In one embodiment, the read-pause transistors (RPGs) are formed on an n-type fin as n-type nanostructured field-effect transistors, while the write-pause transistors (WPG1 and WPG2) of the seven-transistor memory cell are formed on a p-type fin as p-type nanostructured field-effect transistors. Since the one-time oxide interposer process can improve the performance of p-type nanostructure field-effect transistors, the disclosed seven-transistor memory cell design can give the seven-transistor memory cell strong read capability, while still having good write capability.

[0089] Figure 1 These are three-dimensional views of a nanostructured field-effect transistor device 30 in some embodiments. The nanostructured field-effect transistor device 30 includes a semiconductor fin 90 protruding above a substrate 50. A gate 122 (such as a metal gate) is located on the fin, and source / drain regions 112 are formed on both sides of the gate 122. Multiple nanostructures (such as nanowires or nanosheets, second semiconductor material 54) are formed on the fin 90 and between the source / drain regions 112. Isolation regions 96 are formed on both sides of the fin 90. A gate dielectric layer 120 is formed around the nanostructures such as the second semiconductor material 54. The gate 122 is located above and around the gate dielectric layer 120.

[0090] Figure 1 The reference cross-sections used in subsequent figures are also shown. Cross-section AA is along the longitudinal axis of the gate 122 and perpendicular to the current direction between the source / drain regions 112 of the nanostructured field-effect transistor device 30. Cross-section BB is perpendicular to cross-section AA, along the longitudinal axis of the fins 90 and in the current direction between the source / drain regions 112 of the nanostructured field-effect transistor device 30. Cross-section CC is parallel to cross-section BB and lies between two adjacent fins 90. Cross-section DD is parallel to cross-section AA and extends through the source / drain regions 112 of the nanostructured field-effect transistor device. These reference cross-sections will be referenced in subsequent figures for clarity.

[0091] Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figures 5A to 5C , Figures 6A to 6C , Figures 7A to 7C , Figures 8A to 8C , Figures 9A to 9C , Figures 10A to 10C , Figures 11A to 11C , Figures 12A to 12C , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figures 19A to 19H , Figure 20A ,and Figure 20BThis is one embodiment of a nanostructured field-effect transistor device 100, shown in various figures (e.g., cross-sectional views and top views) at various manufacturing stages. In this embodiment, the nanostructured field-effect transistor device 100 is a memory device, such as a static random access memory (SRAM) device having a seven-transistor SRAM cell. The seven-transistor SRAM cell here may be simply referred to as a seven-transistor memory cell.

[0092] exist Figure 2 In this embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate such as a substrate semiconductor, a semiconductor-on-insulator (SIA) substrate, or the like, which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer such as a silicon wafer. Generally, a SIA substrate has a semiconductor material layer formed on an insulating layer. For example, the insulating layer may be a buried oxide layer, a silicon oxide layer, or the like. An insulating layer is provided on the substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 includes silicon, germanium, semiconductor compounds (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), semiconductor alloys (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium phosphide indium, and / or gallium arsenide phosphide indium), or combinations thereof.

[0093] A multilayer stack 64 is formed on the substrate 50. The multilayer stack includes an interleaved layer of a first semiconductor material 52 and a second semiconductor material 54. Figure 2 In the above, the layers formed by the first semiconductor material 52 are designated as first semiconductor materials 52A, 52B, and 52C, while the layers formed by the second semiconductor material 54 are designated as second semiconductor materials 54A, 54B, and 54C. Figure 2 The number of layers of the first and second semiconductor materials shown is merely a non-limiting example. Other numbers of layers are also possible and are entirely within the scope of this invention.

[0094] In some embodiments, the first semiconductor material 52 is a first epitaxial material such as silicon-germanium (Si). x Ge 1-x , where x can be 0 to 1), and the second semiconductor material 54 is a second epitaxial material such as silicon. In subsequent processes, the multilayer stack 64 (which can also be regarded as an epitaxial material stack) is patterned to form the channel region of the nanostructure field-effect transistor. Specifically, the multilayer stack 64 is patterned and etched to form horizontal nanostructures (such as nanosheets or nanowires), and the channel region of the final nanostructure field-effect transistor includes multiple horizontal nanostructures.

[0095] The formation of the multilayer stack 64 can be an epitaxial growth process, which can be performed in a growth chamber. In some embodiments, during the epitaxial growth process, the growth chamber may be cyclically exposed to a first set of precursors for selectively growing a first semiconductor material 52, and then exposed to a second set of precursors for selectively growing a second semiconductor material 54. The first set of precursors includes precursors for a first semiconductor material such as silicon-germanium, and the second set of precursors includes precursors for a second semiconductor material 54 such as silicon. In some embodiments, the first set of precursors includes silicon precursors such as silane and germanium precursors such as germanane, and the second set of precursors includes silicon precursors but omits the germanium precursor. The epitaxial growth process may include continuously introducing silicon precursor streams into the growth chamber, followed by cyclical processes such as (1) introducing germanium precursor streams into the growth chamber while growing the first semiconductor material 52; and (2) not introducing germanium precursor streams into the growth chamber while growing the second semiconductor material 54. The cyclic exposure steps may be repeated until a target number of layers are formed.

[0096] In one embodiment, Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figures 5A to 5C , Figures 6A to 6C , Figures 7A to 7C , Figures 8A to 8C , Figures 9A to 9C , Figures 10A to 10C , Figures 11A to 11C , Figures 12A to 12C , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figures 19A to 19H , Figure 20A ,and Figure 20B In one embodiment, various figures (such as cross-sectional views and top views) show the nanostructured field-effect transistor device 100 during subsequent manufacturing stages. Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11B , Figure 12B , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19B , Figure 19C , Figure 19F ,and Figure 20A It is along Figure 1 The sectional view of section BB in the image. Figure 3B , Figure 4B , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B ,and Figures 19D to 19F It is along Figure 1 The sectional view of section AA in the diagram. Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B ,and Figure 10B It is along Figure 1 The sectional view of section DD in the diagram. Figure 11A , Figure 12A , Figure 19A , Figure 19H ,and Figure 20B This is a top view (as in a plan view) of the nanostructured field-effect transistor device 100. The number of fins and gate structures shown in the figure are merely non-limiting examples, and it should be understood that other numbers of fins and other numbers of gate structures may also be formed.

[0097] exist Figure 3A and 3B In the substrate 50, the fin-like structures 91 protrude above the substrate 50. Each fin-like structure 91 includes a semiconductor fin 90 (which can also be considered as a fin) and a layered stack 92 located on the semiconductor fin 90. The layered stack 92 and the semiconductor fin 90 can be formed by etching trenches in the multilayer stack 64 and the substrate 50, respectively. The layered stack 92 and the semiconductor fin 90 can be formed by the same etching process.

[0098] The fin structure 91 can be patterned by any suitable method. For example, the fin structure 91 can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, resulting in a smaller pattern pitch than that obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate, and the sacrificial layer is patterned using a photolithography process. A self-alignment process is used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers are subsequently used to pattern the fin structure 91.

[0099] In some embodiments, the retained spacers are used to pattern a mask 94, which is then used to pattern the fin structure 91. The mask 94 can be a single-layer mask or a multi-layer mask, such as a multi-layer mask containing a first mask layer 94A and a second mask layer 94B. The first mask layer 94A and the second mask layer 94B can each be composed of a dielectric material such as silicon oxide, silicon nitride, a combination thereof, or the like, and can be formed by deposition or thermal growth according to suitable techniques. The first mask layer 94A and the second mask layer 94B can be different materials with high etch selectivity. For example, the first mask layer 94A can be silicon oxide, and the second mask layer 94B can be silicon nitride. The mask 94 can be formed using an acceptable etching process to pattern the first mask layer 94A and the second mask layer 94B. The mask 94 can then be used as an etching mask for etching the substrate 50 and the multilayer stack 64. Etching can be any acceptable etching process, such as reactive ion etching, neutral beam etching, similar processes, or combinations thereof. In some embodiments, etching is an isotropic etching process. After the etching process, patterned multilayer stack 64 forms a layered stack 92, and the patterned portion of substrate 50 forms fins 90 (such as fins 90A and 90B), as... Figure 3A and 3B As shown. The reserved portions of the substrate 50 (such as unpatterned portions) are in... Figure 3A and 3B This can be considered as substrate 50 in the following figures. Therefore, in this embodiment, the layered stack 92 also includes layers of interlaced first semiconductor material 52 and second semiconductor material 54. The fins 90 and substrate 50 may be made of the same material.

[0100] exist Figure 3A and 3BIn the example, fins 90A and 90B are parallel to each other. Fin 90B is wider than fin 90A. In other words, the width W2 of fin 90B is greater than the width W1 of fin 90A. For example, the width W2 can be about 20% to about 90% larger than the width W1, such as about 30% to about 60% larger than the width W1. Masks 94 of different widths can be formed on fins 90A and 90B to achieve widths W1 and W2. As described below, p-type source / drain regions are formed on fin 90A to form a p-type nanostructure field-effect transistor with a seven-transistor memory cell, while n-type source / drain regions are formed on fin 90B to form an n-type nanostructure field-effect transistor with a seven-transistor memory cell. For example, four p-type nanostructure field-effect transistors are formed on fin 90A, and three n-type nanostructure field-effect transistors are formed on fin 90B. These seven nanostructure field-effect transistors constitute the seven transistors of a seven-transistor memory cell. The wider fin 90B allows read-through gate transistors (RPGs) with strong read stability (such as n-type nanostructure field-effect transistors) to be formed on fin 90B. Details will be explained below.

[0101] Then in Figure 4A and 4B Shallow trench isolation regions 96 are formed on the substrate 50 and on both sides of the fin structure 91. In one example of forming the shallow trench isolation regions 96, an insulating material may be formed on the substrate 50. The insulating material may be an oxide such as silicon oxide, a nitride, the like, or a combination thereof, and its formation method may be high-density plasma chemical vapor deposition, flowable chemical vapor deposition (e.g., depositing a chemical vapor-based material in a remote plasma system, followed by curing the material to transform it into another material such as an oxide), similar methods, or combinations thereof. Other insulating materials formed by any acceptable process may be used. In the embodiment described, the insulating material is silicon oxide formed by a flowable chemical vapor deposition process. An annealing process may be performed after the insulating material is formed.

[0102] In some embodiments, an insulating material is formed such that excess insulating material covers the fin structure 91. In some embodiments, a liner is first formed along the surface of the substrate 50 and the fin structure 91, and the aforementioned filler material is formed on the liner. In some embodiments, the liner may be omitted.

[0103] Next, a removal process is performed on the insulating material to remove excess insulating material from the fin structure 91. In some embodiments, a planarization process such as chemical mechanical polishing, etch-back, a combination thereof, or a similar process may be used. The planarization process exposes the layered stack 92, making the layered stack 92 flush with the upper surface of the insulating material after the planarization process. The insulating material is then recessed to form shallow trench isolation regions 96. The insulating material is recessed so that the layered stack 92 protrudes from between adjacent shallow trench isolation regions 96. The top of the semiconductor fin 90 may also protrude from between adjacent shallow trench isolation regions 96. Furthermore, the upper surface of the shallow trench isolation region 96 may be a flat surface, a raised surface, a recessed surface (such as dishing), or a combination thereof, as illustrated. The upper surface of the shallow trench isolation region 96 may be flat, raised, and / or recessed by appropriate etching. The shallow trench compartment 96 can be recessed using an acceptable etching process, such as an etching process selective for insulating materials (e.g., etching the insulating material at a rate greater than etching the material of the fins 90 and the layered stack 92). For example, a suitable etchant such as diluted hydrofluoric acid can be used for chemical oxide removal.

[0104] like Figure 4A and 4B As shown, a dummy gate dielectric layer 97 is formed on the layered stack 92 and the shallow trench isolation region 96. For example, the composition of the dummy gate dielectric layer 97 may be silicon oxide, silicon nitride, a combination thereof, or the like, and its deposition or thermal growth method may be an acceptable technique. In one embodiment, a silicon layer is compliantly formed on the upper surface of the layered stack 92 and the shallow trench isolation region 96, and a thermal oxidation process may be performed to convert the deposited silicon layer into an oxide layer such as the dummy gate dielectric layer 97.

[0105] Then in Figures 5A to 5C In this process, a dummy gate 102 is formed on the fin structure 91. To form the dummy gate 102, a dummy gate layer can be formed on the dummy gate dielectric layer 97. The dummy gate layer can be deposited on the dummy gate dielectric layer 97, and then planarized by methods such as chemical mechanical polishing. The dummy gate layer can be a conductive material, which may be selected from amorphous silicon, polycrystalline silicon, polycrystalline silicon germanium, or the like. The deposition method of the dummy gate layer can be physical vapor deposition, chemical vapor deposition, sputtering deposition, or other known techniques used in this art. The composition of the dummy gate layer may differ from that of the shallow trench isolation region 96 to have high etch selectivity with the shallow trench isolation region 96.

[0106] Next, a mask 104 is formed on the dummy gate layer. The mask 104 may be composed of silicon nitride, silicon oxynitride, a combination thereof, or the like, and may be patterned using suitable photolithography and etching techniques. In the embodiment, the mask 104 includes a first mask layer 104A (e.g., a silicon oxide layer) and a second mask layer 104B (e.g., a silicon nitride layer). The pattern of the mask 104 is then transferred to the dummy gate layer using a suitable etching technique to form a dummy gate 102, and then the pattern of the mask 104 is transferred to the dummy dielectric layer using a suitable etching technique to form a dummy gate dielectric layer 97. The dummy gate 102 covers individual channel regions of the layered stack 92. The pattern of the mask 104 may be used to separate adjacent dummy gates 102. The length direction of the dummy gate 102 may also be substantially perpendicular to the length direction of the fin structure 91. In some embodiments, the dummy gate 102 and the dummy gate dielectric layer 97 may be considered together as a dummy gate structure.

[0107] Next, an insulating material is compliantly deposited on the layered stack 92, the shallow trench isolation region 96, and the dummy gate 102 to form a gate spacer layer. The insulating material may be silicon nitride, silicon carbonitride, a combination thereof, or the like. In some embodiments, the gate spacer layer includes multiple sublayers. For example, the first sublayer (sometimes considered as the gate honeycomb spacer layer) may be formed by thermal oxidation or deposition, and a second sublayer (sometimes considered as the primary gate spacer layer) may be compliantly deposited on the first sublayer.

[0108] Figure 5B and 5C They are respectively Figure 5A The nanostructured field-effect transistor device 100 along Figure 5A The sectional views of sections EE and FF are shown. Sections EE and FF correspond to... Figure 1 Sections DD and AA are shown in the image. It is worth noting that... Figure 5A The sectional views shown are along the longitudinal direction (e.g., the direction of current) of one of the fins 90, while the sectional views along the longitudinal direction (e.g., the direction of current) of the other fins 90 are the same or similar, unless otherwise stated. Furthermore, Figure 5A The two dummy gates 102 shown are non-limiting examples, and the number of dummy gates 102 on the fin 90 can be any suitable number (see [link to documentation]). Figure 11A and 11B ).

[0109] Then in Figures 6A to 6CIn this process, an anisotropic etching process is used to etch the gate spacer layer to form the gate spacer 108. The anisotropic etching process can remove the horizontal portion of the gate spacer layer (such as the portion on the shallow trench isolation region 96 and the dummy gate 102), while the vertical portion of the gate spacer layer (such as the portion along the sidewall of the dummy gate 102 and the dummy gate dielectric layer 97) is retained to form the gate spacer 108.

[0110] After forming the gate spacer 108, the lightly doped source / drain regions (not shown) can be implanted. Impurities of suitable morphology (e.g., p-type or n-type) can be implanted into the exposed layered stack 92 and / or semiconductor fins 90. The n-type impurity can be any suitable n-type impurity such as phosphorus, arsenic, antimony, or the like, while the p-type impurity can be any suitable p-type impurity such as boron, boron difluoride, indium, or the like. The impurity concentration of the lightly doped source / drain regions can be approximately 10⁻⁶. 15 cm -3 To about 10 16 cm -3 Annealing can be used to activate impurities in the fabric.

[0111] Next, an opening 110 (which can also be considered a recess or a source / drain opening) is formed in the layered stack 92. The opening 110 can extend through the layered stack 92 and penetrate the fin 90. The opening 110 can be formed by an isotropic etching process, which uses a dummy gate 102 and a gate spacer 108 as an etching mask. The bottom of the opening 110 exposes the upper surface 90U of the fin 90. The sidewalls of the opening 110 expose the first semiconductor material 52 and the second semiconductor material 54.

[0112] Then in Figures 7A to 7C In this process, the first semiconductor material 52 exposed by the opening 110 and below the dummy gate 102 is removed. The method for removing the first semiconductor material 52 may be an isotropic etching process such as wet etching or a similar process, using an etchant that is selective for the material of the first semiconductor material 52, while the second semiconductor material 54, fins 90, and shallow trench isolation region 96 remain relatively unetched compared to the first semiconductor material 52. In embodiments where the first semiconductor material 52 comprises silicon germanium and the second semiconductor material 54 comprises silicon or silicon carbide, tetramethylammonium hydroxide, ammonium hydroxide, or the like may be used to selectively remove the first semiconductor material 52. After removing the first semiconductor material 52, gaps 56 (such as blank spaces) are formed between adjacent layers of second semiconductor material 54, and between the fins 90 and the bottommost layer of second semiconductor material 54.

[0113] Then in Figures 8A to 8CIn this process, a disposable material 57 (which can also be considered a sacrificial material) is deposited in the opening 110 to line the sidewalls and bottom of the opening 110. The disposable material 57 also fills the gap 56. The deposition method of the disposable material 57 can be a compliant deposition process such as chemical vapor deposition, atomic layer deposition, or a similar process. The disposable material 57 can be a dielectric material. In some embodiments, the disposable material 57 includes one or more layers of silicon oxide, silicon oxynitride, aluminum oxide, or the like. The material selection depends on its properties, such as etch selectivity, to allow for precise removal of the disposable material 57 during the fabrication process without negatively impacting adjacent and underlying structures. The selection of the disposable material 57 depends on the requirements of the semiconductor device being fabricated and the electrical and physical properties of the final product.

[0114] Then in Figures 9A to 9C In the middle, remove the disposable material 57 outside of gap 56 (see Figure 7A Furthermore, the sidewall of the retained portion of the disposable material 57 is recessed from the individual sidewall 54S of the second semiconductor material 54 to form a sidewall recess 58.

[0115] In some embodiments, an anisotropic etching process, such as a dry etching process (e.g., a plasma etching process), is performed to remove disposable material 57 outside the gap 56. An isotropic etching process, such as a wet etching process, is then performed to recess the remaining portion of the disposable material 57, forming a sidewall recess 58. The etchants used in the dry and wet etching processes are selective for the disposable material 57, thus allowing removal of the disposable material 57 without substantially affecting other materials and / or structures. In some embodiments, multiple etching cycles may be performed to remove the disposable material 57 and form the sidewall recess 58, and each etching cycle includes a dry etching process followed by a wet etching process. The etching cycles are repeated until the sidewall of the disposable material 57 is recessed compared to the sidewall 54S of the second semiconductor material 54. In some embodiments, the wet etching process for etching the disposable material 57 uses hydrofluoric acid, diluted hydrofluoric acid, another fluorine-based etchant, or the like as the etchant. The wet etching process is performed until the sidewall of the disposable material 57 is recessed compared to the sidewall 54S of the second semiconductor material 54.

[0116] Replacing the first semiconductor material 52 with a disposable material 57 offers several advantages. To understand these advantages, consider a manufacturing process in which the first semiconductor material 52 is not replaced with disposable material 57. In subsequent source / drain formation steps, one or more high-temperature processes can be performed to activate the dopants in the source / drain regions. When the first semiconductor material 52, such as silicon-germanium, is exposed to high temperatures, the germanium in the first semiconductor material 52 may diffuse into and mix with the second semiconductor material 54, such as silicon, which can be considered as intermixing between germanium and silicon. Intermixing may increase the interface roughness between the first semiconductor material 52 and the second semiconductor material 54 and may cause manufacturing defects that degrade the performance of the final transistor device. Replacing the first semiconductor material 52 with disposable material 57 before high-temperature processes (such as source / drain annealing) avoids intermixing and reduces manufacturing defects, thereby improving device performance.

[0117] Furthermore, in subsequent processes of the reference manufacturing process, the first semiconductor material 52 is removed by an etching process to release the second semiconductor material 54, thereby forming a nanostructure such as the second semiconductor material 54. Mutual mixing causes uneven removal of the exterior of the second semiconductor material 54, resulting in a dumbbell-shaped cross-section of the nanostructure such as the second semiconductor material 54, with the end portions (e.g., the portions contacting the inner spacers 55) being higher and / or wider than the middle portions (e.g., the portions between the end portions). This dumbbell shape may reduce the channel region size of the transistor device, thus limiting (e.g., reducing) the drive current flowing through the channel region and limiting the read or write capability of the static random access memory cell. By replacing the first semiconductor material 52 with a disposable material 57, and selecting a disposable material 57 with good etching selectivity relative to the second semiconductor material 54, the disposable material 57 can be selectively removed with minimal or no etching of the second semiconductor material 54 during subsequent processes forming the nanostructure such as the second semiconductor material 54. In this way, nanostructures such as the second semiconductor material 54 (e.g., the channel region) can have substantially consistent height and width (e.g., a rectangular cross-section), thereby enabling static random access memory devices to have better drive current and improved read and write capabilities.

[0118] Then in Figures 10A to 10C In the middle, an inner spacer 55 is formed in the side wall recess 58. Figure 10B and 10C yes Figure 10AThe nanostructured field-effect transistor device 100 is shown in cross-sectional views along sections EE and FF, respectively. In some embodiments, to form the inner spacer 55, an inner spacer layer may be formed (e.g., compliantly formed) in the opening 110. The inner spacer layer also fills the sidewall recesses 58 of the sacrificial material, such as disposable material 57. The inner spacer layer may be a suitable dielectric material, such as silicon carbonitride, silicon carbonitride oxide, or the like, and its formation method may be a suitable deposition method such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or similar methods. An etching process, such as anisotropic etching, is then performed to remove portions of the inner spacer layer outside the sidewall recesses 58 of the sacrificial material, such as disposable material 57. The remaining portions of the inner spacer layer (e.g., the portions located within the sidewall recesses 58 of the sacrificial material, such as disposable material 57) may form the inner spacer 55. Figure 10A As shown, the opening 110 exposes the sidewall of the second semiconductor material 54 and the upper surface 90U of the fin 90.

[0119] Figures 11A to 11C The process continuity shown Figures 10A to 10C The manufacturing process. Figure 11A This is a top view of a portion of a nanostructured field-effect transistor device 100. Figure 11B It is a nanostructured field-effect transistor device 100 along Figure 11A The sectional view of section B1-B1 in the middle, and Figure 11C It is a nanostructured field-effect transistor device 100 along Figure 11A The sectional view is shown in section A1-A1. It is worth noting that, to simplify the drawings and avoid clutter, Figure 11A The full structure of the nanostructured field-effect transistor device 100 is not shown. For example, Figure 11A Only fins 90A and fins 90B are shown, along with the four dummy gates 102A, 102B, 102C, and 102D on fins 90A and 90B (collectively considered as dummy gate 102), and the gate spacers 108 surrounding the dummy gate 102.

[0120] As detailed below, the seven transistors include four p-type transistors and three n-type transistors, which can be formed in... Figure 11A In region 106. These seven transistors are connected by a subsequently formed interconnect structure to form a seven-transistor static random access memory cell.

[0121] like Figures 11A to 11CAs shown, source / drain regions 112 are formed in opening 110. In the description herein, source / drain regions may be considered individually or together as sources or drains, depending on the context. In the embodiment described, the source / drain regions 112 are composed of epitaxial material and are therefore considered epitaxial source / drain regions. In some embodiments, the epitaxial source / drain regions 112 are formed in opening 110 to apply stress to individual channel regions of the nanostructured field-effect transistor device, thereby improving performance. In some embodiments, the epitaxial source / drain regions 112 allow dummy gates 102 to be located between individual adjacent epitaxial source / drain regions 112. In some embodiments, gate spacers 108 are used to maintain a suitable lateral distance between the epitaxial source / drain regions 112 and the dummy gates 102, preventing the epitaxial source / drain regions 112 from shorting outwards to the subsequently formed gate of the final nanostructured field-effect transistor device.

[0122] The epitaxial source / drain region 112 is epitaxially grown within the opening 110. The epitaxial source / drain region 112 may comprise any acceptable material, such as materials suitable for n-type or p-type devices. For example, the epitaxial source / drain region 112 for forming an n-type device may comprise a material for applying tensile stress to the channel region, such as silicon, silicon carbide, silicon carbide phosphide, silicon phosphide, or the like. Similarly, the epitaxial source / drain region 112 for forming a p-type device may comprise a material for applying compressive stress to the channel region, such as silicon germanium, silicon germanium boride, germanium, germanium tin, or the like. The surface of the epitaxial source / drain region 112 may protrude from individual surfaces of the fin 90 and may have crystal planes.

[0123] Dopant can be implanted into the epitaxial source / drain region 112 and / or fins 90 to form the source / drain region, similar to the process described above for forming lightly doped source / drain regions. Annealing can then be performed. The impurity concentration of the source / drain region can be between approximately 10⁻⁶. 19 cm -3 To about 10 21 cm -3 Between. The n-type and / or p-type impurities used in the source / drain regions can be any of the aforementioned impurities. In some embodiments, the epitaxial source / drain regions 112 can be doped in situ during growth.

[0124] The epitaxial process used to form the epitaxial source / drain regions 112 results in the epitaxial source / drain regions 112 having crystal planes that extend laterally beyond the sidewalls of the fin 90. In some embodiments, adjacent epitaxial source / drain regions 112 remain separated after the epitaxial process is completed. In other embodiments, these crystal planes cause adjacent epitaxial source / drain regions 112 to merge.

[0125] In the described embodiment, an n-type device (such as an n-type transistor, or an n-type nanostructure field-effect transistor) is formed on fin 90B, while a p-type device (such as a p-type transistor, or a p-type nanostructure field-effect transistor) is formed on fin 90A. Therefore, the source / drain regions 112 on fin 90B are doped with n-type dopants, while the source / drain regions 112 on fin 90A are doped with p-type dopants. Fin 90A can be considered a p-type fin, and fin 90B can be considered an n-type fin.

[0126] Next, a contact etch stop layer 116 is formed (e.g., compliantly formed) on the source / drain region 112 and the dummy gate 102, followed by the deposition of a first interlayer dielectric layer 114 on the contact etch stop layer 116. The constituent material of the contact etch stop layer 116 has a different etch rate than the first interlayer dielectric layer 114, such as silicon nitride formed by plasma-assisted chemical vapor deposition, but other dielectric materials such as silicon oxide, silicon oxynitride, combinations thereof, or similar materials may also be used. Other techniques such as low-pressure chemical vapor deposition, physical vapor deposition, or similar techniques may also be used to form the contact etch stop layer 116.

[0127] The first interlayer dielectric layer 114 may be composed of a dielectric material and may be deposited by any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition. The dielectric material of the first interlayer dielectric layer 114 may include silicon oxide, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, or the like. Other insulating materials may be formed using any acceptable process.

[0128] Then in Figures 12A to 12C , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A ,and Figure 16B In the process of replacing the dummy gate structure with the replaced gate structure, a continuous polysilicon on diffusion edge (CPODE) process (which can also be regarded as a polysilicon cutting process on diffusion edge) is performed, which cuts (e.g. removes) a portion of the dummy gate structure (e.g., the portion of dummy gate 102A and dummy gate dielectric layer 97).

[0129] like Figures 12A to 12C As shown, a dielectric plug 125 is formed to cut the dummy gate 102A and the dummy gate dielectric layer 97 into multiple separate portions. Figure 12A Top view of the nanostructured field-effect transistor 100 after the dielectric plug 125 is formed. Figure 12B It is a nanostructured field-effect transistor device 100 along Figure 12AThe sectional view of section B1-B1 in the middle, and Figure 12C It is a nanostructured field-effect transistor device 100 along Figure 12A The sectional view of section A1-A1 in the diagram.

[0130] In some embodiments, the dielectric plug 125 is formed by forming an opening extending through the dummy gate 102A, through the dummy gate dielectric layer 97, through the first interlayer dielectric layer 114, and into the shallow trench isolation region 96, and the opening is formed using photolithography and etching techniques. A dielectric material such as silicon nitride, silicon oxide, a combination thereof, or the like is filled into the opening. A planarization process such as chemical mechanical polishing can then be performed to remove excess dielectric material from the upper surface of the first interlayer dielectric layer 114, and the remaining portion of dielectric material in the opening forms the dielectric plug 125.

[0131] In the example described, dielectric plugs 125 are formed on both sides of the fin 90B. Figure 12A For example, one dielectric plug 125 is formed between fins 90A and 90B, while the other dielectric plug 125 is formed on the opposite side of fin 90B. In this embodiment, the dimension WDP (measured along the direction of section B1-B1) of the dielectric plug 125 is larger than the dimension WMG of the dummy gate 102A to ensure that the dielectric plug 125 cuts the dummy gate 102A into separate portions. Figure 12A In the example, a portion 102AM of the dummy gate 102A is located between dielectric plugs 125. For example... Figure 12C As shown, the dielectric plug 125 extends through the dummy gate 102A, through the dummy gate dielectric layer 97, and into the shallow trench isolation region 96 to ensure separation of different parts of the dummy gate structure. It is noteworthy that the dielectric plug 125 is not... Figure 12A In section B1-B1, therefore not shown in the diagram. Figure 12B .

[0132] Then in Figure 13A and 13B In this process, a hard masking layer 131 (which can also be regarded as a masking layer) is formed on the first interlayer dielectric layer 114 and the dummy gate 102. Figure 13A and 13B Corresponding to Figure 12B and 12CA cross-sectional view. The hard mask layer 131 may be a single-layer hard mask, and its composition may be silicon nitride, silicon oxynitride, or the like, and its formation method may be a suitable formation method such as chemical vapor deposition. In some embodiments, the hard mask layer 131 has a multilayer structure. For example, the hard mask layer 131 may include a silicon layer sandwiched between two silicon nitride layers. An opening 132 is formed in the hard mask layer 131 on a portion 102AM of the dummy gate 102A. The opening 132 may be formed using photolithography and etching techniques, and the opening 132 may expose a portion 102AM of the dummy gate 102A. A top view of some embodiments (see...) Figure 12A In the ), the sidewall of the opening 132 overlaps with the boundary of a portion 102AM of the dummy gate 102A.

[0133] Then in Figure 14A and 14B In this process, a portion 102AM of the dummy gate 102A exposed by opening 132 (e.g., below opening 132) is removed, and the removal method may be an isotropic etching process. In some embodiments, the isotropic etching process is a wet etching process using an etching chemical agent such as an etching liquid. In some embodiments, the isotropic etching process is a dry etching process using an etching gas such as a plasma etching process. The isotropic etching process also removes the dummy gate dielectric layer 97 below opening 132, such as... Figure 14A and 14B As shown. In some embodiments, the isotropic etching process selectively removes a portion of 102AM of the dummy gate 102A and the dummy gate dielectric layer 97 without substantially affecting other materials and structures.

[0134] Then in Figure 15A and 15B In this process, an anisotropic etching process 143 (such as anisotropic plasma etching) is performed to remove portions of the primary material 57 and the second semiconductor material 54 below the opening 132. In some embodiments, the anisotropic etching process 143 is a plasma dry etching process. In some embodiments, the process is omitted. Figure 14A and 14B The isotropic etching process shown is performed, and an anisotropic etching process similar to or the same as the anisotropic etching process 143 is performed to remove portions of the primary material 57 and the second semiconductor material 54 below the opening 132.

[0135] like Figure 15A and 15B As shown, remove the portion 102AM of the dummy gate 102A exposed by the opening 132. Also remove portions of the disposable material 57 and the second semiconductor material 54 below the opening 132. Portions of the disposable material 57 and the second semiconductor material 54 located (e.g., directly below) the gate spacer 108 may be retained, as shown below the opening 132. Figure 15AAs shown. In addition, the fin 90B below opening 132 was also removed. Therefore, as... Figure 15B As shown, the opening 132 extends through the shallow trench isolation region 96 and into the substrate 50. Thus, the upper surface 50U1 of the portion of the substrate 50 below the opening 132 is lower than the upper surface 50U2 of other portions of the substrate 50 (such as unetched portions). In this embodiment, the anisotropic etching process 143 is selective for the materials of the primary material 57 and the second semiconductor material 54 (e.g., having a higher etching rate), and etches the shallow trench isolation region 96 with little or no etching.

[0136] like Figure 15A and 15B As shown, the opening 132 (which can also be considered as a recess) exposes the sidewall of the dielectric plug 125 facing the nanostructure such as the second semiconductor material 54, and exposes the inner sidewall of the gate spacer 108 facing the opening 132.

[0137] Then in Figure 16A and 16B In this process, a dielectric material 141 is formed within the opening 132 and on top of the hard mask layer 131. The dielectric material 141 may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a combination thereof, or multiple layers thereof. Suitable formation methods such as chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or similar methods may be used to form the dielectric material 141. In some embodiments, the dielectric material 141 comprises multiple layers of different dielectric materials. In some embodiments, the dielectric material 141 comprises multiple layers of the same dielectric material (such as silicon oxide or silicon nitride), which may be formed by different formation methods. For example, a layer of dielectric material may be formed by atomic layer deposition, followed by another layer of the same dielectric material formed by chemical vapor deposition to fill the opening 132. The dielectric material formed by atomic layer deposition can be denser and have higher etch resistance, while the dielectric material formed by chemical vapor deposition has a faster formation rate, which can reduce manufacturing time and cost.

[0138] Next, a planarization process such as chemical mechanical polishing is performed to remove the dielectric material 141 and the hard mask layer 131 from the upper surface of the first interlayer dielectric layer 114. The retained portion of the dielectric material 141 in the opening 132 forms a dielectric structure such as the dielectric material 141 (which can also be regarded as an isolation structure). Figure 19A A top view showing the dielectric structure, such as dielectric material 141. Figure 19A As shown, the dielectric structure, such as dielectric material 141, is located between dielectric plugs 125 along the direction of cross section A1-A1, and between gate spacers 108 of the subsequently formed gate structure 123A along the direction of cross section B1-B1.

[0139] like Figure 17A , Figure 17B , Figure 18A , Figure 18B ,and Figures 19A to 19F The gate replacement process shown can remove dummy gate structures (such as dummy gate 102 and dummy gate dielectric layer 97) and replace them with gate structure 123 (such as metal gate structure).

[0140] Then in Figure 17A and 17B In this process, a dummy gate 102 is removed by an etching step to form a recess 103 between the individual gate spacers 108. In some embodiments, the dummy gate 102 is removed using an anisotropic dry etching process. For example, the etching process may include a dry etching process using reactive gases, which may selectively etch the dummy gate 102 without etching the first interlayer dielectric layer 114 and the gate spacers 108. The dummy gate dielectric layer 97 may serve as an etch stop layer during the removal of the dummy gate 102. After the dummy gate 102 is removed, the dummy gate dielectric layer 97 may be removed.

[0141] In some embodiments, the dummy gate dielectric layer 97 in the recess 103 is removed. An etching process, such as an isotropic etching process, can be performed to remove the dummy gate dielectric layer 97. In one embodiment, an isotropic etching process is performed using an etching gas containing hydrofluoric acid and ammonia to remove the dummy gate dielectric layer 97. Figure 17A and 17B As shown, each of the recesses 103 exposes the lower channel region of the nanostructured field-effect transistor. Each channel region is located between adjacent epitaxial source / drain regions 112.

[0142] Then in Figure 18A and 18B In this process, a disposable material 57 (such as the portion exposed in the recess 103) is removed to release the second semiconductor material 54. After the disposable material 57 is removed, the second semiconductor material 54 (such as the portion below the dummy gate 102 before removal of the dummy gate 102) forms multiple horizontally extending nanostructures (e.g., parallel to the main upper surface of the substrate 50). These nanostructures, such as the second semiconductor material 54, can be collectively considered as channel regions 93 or channel layers of the nanostructured field-effect transistor 100. Figure 18A and 18B As shown, gaps 53 (such as blank spaces) are formed between nanostructures such as the second semiconductor material 54 and between the bottommost nanostructure such as the second semiconductor material 54 and the fin 90, and are formed by removing disposable material 57. In some embodiments, the nanostructures such as the second semiconductor material 54 are nanosheets or nanowires, depending on the size (e.g., dimensions and / or aspect ratio) of the nanostructures such as the second semiconductor material 54.

[0143] In some embodiments, the disposable material 57 may be removed by a selective etching process using an etchant that is selective to the disposable material 57 (e.g., has a higher etching rate) to remove the disposable material 57 without substantially affecting the second semiconductor material 54. In some embodiments, an isotropic etching process, such as a wet etching process or a similar process, may be performed to remove the disposable material 57. In embodiments where the disposable material 57 comprises silicon oxide and the second semiconductor material 54 comprises silicon or silicon carbide, hydrofluoric acid, diluted hydrofluoric acid, another fluorine-based etchant, or the like may be used to remove the disposable material 57.

[0144] In some embodiments, the high etch selectivity between the second semiconductor material 54 and the primary material 57 can be greater than or equal to 10,000. In other words, the etch rate at which the isotropic etching process removes the primary material 57 is greater than or equal to 10,000 times the etch rate of the second semiconductor material 54. In this way, the nanostructure, such as the second semiconductor material 54, can have a rectangular cross-section (e.g., uniform width and height), thus avoiding the performance problems associated with dumbbell-shaped nanostructures (e.g., lower drive current and higher channel resistance).

[0145] like Figure 18A As shown, each of the nanostructures, such as the second semiconductor material 54, has a rectangular cross-section along the longitudinal axis of the fin. Similarly, in Figure 18, in its cross-section along a direction perpendicular to the longitudinal axis of the fin and passing through the middle portion of the nanostructure, such as the second semiconductor material 54, each of the nanostructures, such as the second semiconductor material 54, has a rectangular cross-section.

[0146] Then in Figures 19A to 19F In the process, a gate dielectric layer 120 and a gate 122 are formed to form a gate structure 123, such as gate structures 123A, 123B, 123C, and 123D. Figure 19A Showing a top view of the nanostructured field-effect transistor device 100. Figure 19B and 19C respectively along Figure 19A The sectional views of sections B1-B1 and B2-B2 in the figure. Figure 19D , Figure 19E ,and Figure 19F respectively along Figure 19A The sectional views of sections A1-A1, A2-A2, and A3-A3 in the figure.

[0147] A gate dielectric layer 120 is compliantly deposited in a recess 103, such as on the upper surface and sidewalls of the semiconductor fin 90 and on the sidewalls of the gate spacer 108. The gate dielectric layer 120 may also be formed on the upper surface of the first interlayer dielectric layer 114. Notably, the gate dielectric layer 120 encapsulates a nanostructure such as a second semiconductor material 54. In some embodiments, the gate dielectric layer 120 comprises silicon oxide, silicon nitride, or multiple layers as described above. In some embodiments, the gate dielectric layer 120 is composed of a dielectric material with a high dielectric constant. In these embodiments, the dielectric constant of the gate dielectric layer 120 may be greater than about 7.0 and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, lead, or combinations thereof. Methods for forming the gate dielectric layer 120 may include molecular beam deposition, atomic layer deposition, plasma-assisted chemical vapor deposition, or similar methods.

[0148] Gate material is then deposited on and around gate dielectric layer 120, filling the remaining portion of recess 103. Gate material may include metallic materials such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although the gate material in the figures is a single layer, it may include any number of pad layers (such as barrier layers), any number of work function adjustment layers, and filler metallic materials. After filling the gate material, a planarization process such as chemical mechanical polishing may be performed to remove excess portions of gate dielectric layer 120 and gate material from the upper surface of the first interlayer dielectric layer 114. The remaining portions of the gate material and gate dielectric layer 120 thus form the gate 122 and gate dielectric layer 120 of the final nanostructure field-effect transistor device 100's gate structure 123, respectively. Each gate 122 and its corresponding gate dielectric layer 120 may be considered together as gate structure 123, gate stack, displacement gate structure, or metal gate structure. Gate structures 123 each extend around individual nanostructures such as the second semiconductor material 54.

[0149] like Figures 19A to 19F As shown, a dielectric plug 127 (which can also be considered as a dielectric structure) is formed between fins 90A and 90B to divide the gate structure 123D into two partitioned portions, and the two partitioned portions on fins 90A and 90B respectively form gate structures 123D1 and 123D2 (see...). Figure 19A and 19FIn some embodiments, the dielectric plug 127 is formed by using photolithography and etching techniques to form an opening in the gate structure 123D and the first interlayer dielectric layer 114, and filling the opening with a dielectric material such as silicon nitride, silicon oxide, a combination thereof, or the like. A planarization process, such as chemical mechanical polishing, can then be performed to remove excess dielectric material from the upper surface of the first interlayer dielectric layer 114, and the remaining portion of dielectric material in the opening can form the dielectric plug 127. Figure 19F As shown, the dielectric plug 127 extends through the gate structure 123D and into the shallow trench isolation region 96 to ensure separation of different portions of the gate structure 123D. It is worth noting that the dielectric plug 127 is not shown in cross-sections A1-A1 and A2-A2 of FIG. 13C, and therefore is not illustrated. Figure 19D and 19E Dielectric structures, such as dielectric materials 141, etc. Figure 19D As shown. Figure 19A The top view shows a nanostructured field-effect transistor (such as...). Figure 19A The write-through transistor (WPG1) is formed at the intersection of the gate structure 123A and the fin 90A. For example, it is located on a portion of the gate structure 123A on (e.g., directly on) the fin 90A, below it, in the nanostructure such as the second semiconductor material 54, and on the source / drain regions 112 (not shown) on both sides of the portion of the fin and the gate structure 123A. Figure 19A But the illustration is shown Figure 19C A nanostructured field-effect transistor, such as the write-through transistor WPG1, is formed. The source / drain region 112 on the fin 90A is a p-type source / drain; therefore, the nanostructured field-effect transistor, such as the write-through transistor WPG1, is a p-type nanostructured field-effect transistor. It is worth noting that the dielectric structure, such as the dielectric material 141, buried in the gate structure 123A is located (e.g., directly on) the fin 90B; therefore, no nanostructured field-effect transistor is formed at the intersection of the dielectric structure, such as the dielectric material 141, and the fin 90B.

[0150] like Figure 19A As shown, the gate structure 123B intersects with fins 90A and 90B. The first portion of the gate structure 123B on fin 90A forms a p-type nanostructure field-effect transistor (e.g., Figure 19A The pull-up transistor PU1 in the middle has a lower nanostructure such as a second semiconductor material 54 and a p-type source / drain region 112 (see Figure 19C The gate structure 123B is located on both sides of the first portion of the fin 90A. Similarly, the second portion of the gate structure 123B on the fin 90B forms an n-type nanostructure field-effect transistor (e.g., Figure 19AThe pull-down transistor PD1 in the middle has a lower nanostructure such as a second semiconductor material 54 and an n-type source / drain region 112 (see Figure 19B The gate is located on both sides of the second part of the fin 90B and the gate structure 123B. Therefore, the gate terminal of the p-type nanostructure field-effect transistor, such as the pull-up transistor PU1, is connected to the gate terminal of the n-type nanostructure field-effect transistor, such as the pull-up transistor PD1.

[0151] Similarly, the gate structure 123C intersects with fins 90A and 90B. The first portion of the gate structure 123C on fin 90A forms a p-type nanostructure field-effect transistor (e.g., Figure 19A The pull-up transistor PU2 in the middle has a lower nanostructure such as a second semiconductor material 54 and a p-type source / drain region 112 (see Figure 19C The gate structure 123C is located on both sides of the first portion of the fin 90A. The second portion of the gate structure 123C on the fin 90B forms an n-type nanostructure field-effect transistor (e.g., Figure 19A The pull-down transistor PD2 in the middle has a lower nanostructure such as a second semiconductor material 54 and an n-type source / drain region 112 (see Figure 19B The gate is located on both sides of the second part of the fin 90B and the gate structure 123C. Therefore, the gate terminal of the p-type nanostructure field-effect transistor, such as the pull-up transistor PU2, is connected to the gate terminal of the n-type nanostructure field-effect transistor, such as the pull-up transistor PD2.

[0152] Dielectric plug 127 divides (e.g., separates) the gate structure 123D into two separate gate structures 123D1 and 123D2 on fins 90A and 90B. Gate structure 123D1 forms a p-type nanostructure field-effect transistor (e.g., Figure 19A The write-through transistor WPG2 in the middle has a nanostructure such as a second semiconductor material 54 and a p-type source / drain region 112 (see Figure 19C The gate structure 123D2 on the fin 90B is located on top of the fin 90A and on both sides of the gate structure 123D1. The gate structure 123D2 on the fin 90B forms an n-type nanostructure field-effect transistor (e.g., Figure 19A The readout gate-pause transistor (RPG) has a lower nanostructure such as a second semiconductor material 54 and an n-type source / drain region 112 (see Figure 19B It is located on the fin 90B and on both sides of the gate structure 123D2.

[0153] As described above, a total of seven nanostructure field-effect transistors (including four p-type nanostructure field-effect transistors such as write-through transistor WPG1, pull-up transistor PU1, pull-up transistor PU2, and write-through transistor WPG2, and three n-type nanostructure field-effect transistors such as pull-down transistor PD1, pull-down transistor PD2, and read-through transistor RPG) are formed in Figure 19A In region 106. The subsequently formed interconnect structure 155 can further interconnect seven nanostructure field-effect transistors to form a seven-transistor static random access memory cell, the details of which are described below.

[0154] Figure 19G In one embodiment, Figure 19B A magnified view of region 113 in the image. Figure 19G In this example, the protruding inner sidewall of the inner spacer 55 faces the gate 122. In some embodiments, after removing the disposable material 57 and replacing it with a gate structure (such as the gate dielectric layer 120 and gate 122 of the gate structure), some residual portions of the disposable material 57 remain between the inner spacer 55 and the gate structure. The retained portions of the disposable material 57 do not negatively affect device performance. Conversely, if the reference manufacturing process described above is used, the retained portions of the second semiconductor material, such as silicon germanium, are located in... Figure 19G The location of the retained portion of the disposable material 57 is shown. The retained portion of the second semiconductor material (such as silicon-germanium) may negatively impact device performance (e.g., cause leakage current).

[0155] Figure 19H It is part of the nanostructured field-effect transistor device 100 along Figure 19B The sectional view of section GG in the diagram. Therefore Figure 19H A top view showing one of the nanostructures, such as the second semiconductor material 54, and the source / drain regions 112 on both sides of the nanostructure, such as the second semiconductor material 54. For simplicity, the figures are shown below. Figure 19H The full structure of the nanostructured field-effect transistor device 100 is not shown. Figure 19H In the process, the nanostructure adjacent to the source / drain region 112, such as the second semiconductor material 54, has a width Dgc, while the nanostructure located at the midpoint between the source / drain regions 112, such as the second semiconductor material 54, has a width Dg. It is worth noting that... Figure 19HThe difference between the width Dgc and the width Dg is exaggerated. In some embodiments, the ratio between the width Dgc and the width Dg is between about 1 and about 1.05 (such as 1 < Dgc / Dg < 1.05). In other words, the nanostructure such as the second semiconductor material 54 has a substantially rectangular cross-sectional shape, so the dimensions of the nanostructure such as the second semiconductor material 54 can be maintained, such as the width of the middle part of the nanostructure such as the second semiconductor material 54 without loss or with little loss. The disposable oxide interlayer process replaces the first semiconductor material 52 such as silicon germanium with a disposable material 57 (such as an oxide) to provide a good etch selectivity (such as greater than 10,000) between the second semiconductor material 54 such as silicon and the disposable material 57, so the dimensions of the nanostructure such as the second semiconductor material 54 can be maintained. In contrast, for the nanostructure such as the second semiconductor material 54 formed by a method other than the disposable oxide interlayer process, the ratio between the width Dgc and the width Dg can be greater than 1.1 (such as Dgc / Dg > 1.1), and has a dumbbell-shaped cross-section. The nanostructure such as the second semiconductor material 54 formed by the disposable oxide interlayer process can improve the drive current. For example, the drive current can be improved by about 20% for a p-type nanostructure field-effect transistor, and the drive current can be improved by about 5% for an n-type nanostructure field-effect transistor.

[0156] Next, in Figure 20A the second interlayer dielectric layer 151 is formed on the first interlayer dielectric layer 114. The source / drain contact 145S extends through the first interlayer dielectric layer 114 and the second interlayer dielectric layer 151 to electrically couple to the respective source / drain regions 112. The gate contact 145G extends through the second interlayer dielectric layer 151 to electrically couple to the respective gate structures 123. The source / drain contact 145S and the gate contact 145G can be regarded as the contact 145 together. In addition, the interconnect structure 155 includes a dielectric layer 153 and conductive structures (such as conductive lines 149 and vias 147) formed in the dielectric layer 153, and the interconnect structure 155 is formed on the second interlayer dielectric layer 151 for electrical components in and / or on the interconnect substrate 50 to form a functional circuit such as a seven-transistor memory cell.

[0157] The second interlayer dielectric layer 151 and the first interlayer dielectric layer 114 can be composed of the same dielectric material and can be formed by the same method. The contact 145 may include a barrier layer 142 (such as titanium nitride, tantalum nitride, or the like), a seed layer 146 (such as copper), and a filler metal 148 (such as copper, tungsten, cobalt, or the like). In some embodiments, the source / drain contact 145S is formed by forming a patterned mask layer on the second interlayer dielectric layer 151, wherein the opening of the patterned mask layer is located on individual source / drain regions 112, removing a portion of the second interlayer dielectric layer 151 and a portion of the first interlayer dielectric layer 114 below the opening, conformally forming the barrier layer 142 and the seed layer 146 in the opening, and filling the opening with the filler metal 148. The patterned mask layer is then removed by a method such as chemical mechanical polishing. It is worth noting that... Figure 20A In this example, a portion of the first interlayer dielectric layer 114 between individual sidewalls of the contact etch stop layer 116 is completely removed, allowing the barrier layer 142 of the source / drain contact 145S to contact (e.g., physically contact) the sidewalls of the contact etch stop layer 116. The increased volume and decreased resistance of the source / drain contact 145S improve the electrical performance of the device. The formation method of the gate contact 145G can be the same as or similar to that of the source / drain contact 145S, and details are not repeated here. The dielectric layer 153 of the interconnect structure 155 can be composed of a suitable dielectric material, such as silicon oxide or a low dielectric constant dielectric material. The conductive lines 149 and vias 147 of the interconnect structure 155 can be composed of a suitable conductive material such as copper, and their formation can be performed using any suitable method.

[0158] Internal wiring structure 155 is connected to contact 145 Figure 19A The seven transistors in region 106 are used to form a seven-transistor memory cell. It is worth noting that... Figure 20A This is used to show the structure of contact 145 and interconnect structure 155, rather than the specific electrical connection between different nanostructure field-effect transistors. Figure 20B This shows details of the electrical connections between the seven nanostructured field-effect transistors in a seven-transistor memory cell. Figure 21 yes Figure 20B The equivalent circuit diagram of a seven-transistor memory cell.

[0159] Figure 20B The top view of the nanostructured field-effect transistor device 100 shows the electrical connection of seven nanostructured field-effect transistors in a seven-transistor memory cell. Figure 20B It can also be viewed as a layout diagram of a nanostructured field-effect transistor device 100. Figure 20B The seven nanostructured field-effect transistors in the middle correspond to Figure 19ASeven nanostructured field-effect transistors in region 106. To simplify the accompanying drawings, Figure 20B Not all structures of the nanostructured field-effect transistor device 100 are shown. Figure 20B Display fins 90A and 90B, gate structures 123A, 123B, 123C, 123D1, and 123D2, and source / drain contacts 145 (such as source / drain contacts 145A and 145D). Furthermore, Figure 20B The interconnect structure 155 shows through-holes 147 (such as through-holes 147A, 147B, 147C, and 147D) and conductive lines 149 (such as conductive lines 149A and 149B). As described above, the width W1 of fin 90A is smaller than the width W2 of fin 90B.

[0160] exist Figure 20B In the top view, the preceding structure partially obscures the structure behind it, and the preceding structure is positioned higher than the following structure (e.g., at a greater distance from the substrate 50). If multiple structures overlap, the vertical height of each structure can depend on how they obscure each other. Figure 20B For example, conductive line 149 is located on the highest layer, via 147 is below conductive line 149, and source / drain contact 145 is below via 147. Gate structure 123 is also below via 147 and is located via gate contact (e.g., Figure 20A The gate contact 145G is connected to the via 147. For simplicity of the drawings, Figure 20B Gate contact 145G (not shown). Fin 90 is below gate structure 123.

[0161] exist Figure 20B In this context, the overlap (such as intersection) between a structure and the structure directly below it can refer to the electrical connection between the two structures. For example, via 147A is connected to source / drain contact 145A, and source / drain contact 145A is connected to the source / drain region 112 below (formed on fin 90A, not shown). Figure 20B But the illustration is shown Figure 20A Similarly, via 147B is connected to gate structure 123A, while conductive lines 149A and 149B are connected to vias 147C and 147D, respectively. In some embodiments, conductive line 149A is configured to be connected to a reference voltage (such as electrical ground VSS), while conductive line 149B is configured to be connected to a power supply voltage VDD (such as a voltage signal).

[0162] Back Figure 19A and 19BThe dielectric structure, such as dielectric material 141, is embedded in the gate structure 123A and directly located on the fin 90B. Therefore, no nanostructured field-effect transistors are formed at the intersection of the dielectric structure, such as dielectric material 141, and the fin 90B, resulting in seven (instead of eight) nanostructured field-effect transistors being formed. Figure 19A In region 106. Therefore, in Figure 20B In this configuration, the gate structure 123A overlaps with the fin 90A, but not with the fin 90B. In this way, Figure 20B The source / drain contact 145D can be considered as a dummy source / drain contact (e.g., electrically isolated). In some embodiments, the source / drain contact 145D is omitted.

[0163] Figure 21 yes Figure 20B The equivalent circuit diagram shows a seven-transistor static random access memory cell. Figure 21 In the diagram, p-type transistors 171, 173, 175, and 177 correspond to... Figure 19A The p-type nanostructure field-effect transistors include write-through transistor WPG1, pull-up transistor PU1, pull-up transistor PU2, and write-through transistor WPG2. The n-type transistors 161, 163, and 165 correspond to... Figure 19A The n-type nanostructure field-effect transistors in the diagram include pull-down transistors PD1 and PD2, and readout transistor RPG. Figure 21 The electrical connections between the transistors shown can correspond to Figure 20B The electrical connections are shown. Transistors 171, 173, 175, and 177 can be considered as the first write-through transistor, the first pull-up transistor, the second pull-up transistor, and the second write-through transistor, respectively. Transistors 161, 163, and 165 can be considered as the first pull-down transistor, the second pull-down transistor, and the read-through transistor, respectively.

[0164] Figure 21The seven-transistor static random access memory (SRAM) cell comprises two cross-coupled inverters formed by four transistors, such as pull-up transistors PU1 and PU2, and pull-down transistors PD1 and PD2. These inverters are connected to form a latch that stores data bits. The seven-transistor memory cell is powered on by the supply voltage VDD. Two access transistors, such as write bypass transistors WPG1 and WPG2, are connected to the inverter via their source terminals. The gate terminals of the access transistors WPG1 and WPG2 are configured to be connected to the write word line WWL. The drain terminals of the access transistors WPG1 and WPG2 are configured to be connected to the complementary write bit line WBLB and the write bit line WBL, respectively. The signals of the write word line WWL, the complementary write bit line WBLB, and the write bit line WBL control the write operation of the seven-transistor memory cell. An additional read bypass transistor RPG is connected to the memory node of an inverter via its source terminal. The gate and drain terminals of the read bypass transistor RPG are configured to be connected to the signals of the read word line RWL and the read bit line RBL, respectively. The signals of the read word line RWL and the read bit line RBL control the read operation of the seven-transistor memory cell. The presence of the additional read bypass transistor RPG separates the write and read paths, which helps improve the stability of the seven-transistor memory cell and reduce read interference compared to a six-transistor static random access memory cell.

[0165] This invention offers several advantages. By employing a one-time oxide interposer process and forming a read-through transistor RPG on an n-type fin 90B (which provides a stronger drive current due to the larger width W2), the disclosed seven-transistor memory cell achieves strong read capabilities (e.g., fast read speed and fewer read errors) while still maintaining good write capabilities (e.g., fast write speed and fewer write errors). To achieve these advantages, considering the design of the reference seven-transistor memory cell, write-through transistors WPG1 and WPG2, pull-down transistors PD1 and PD2 are formed as n-type nanostructure field-effect transistors on the n-type fin 90B, while pull-up transistors PU1 and PU2, along with the read-through transistor RPG, are formed as p-type nanostructure field-effect transistors on the p-type fin 90A. Furthermore, the method for forming the nanostructured field-effect transistors in the reference seven-transistor memory cell does not employ a one-time oxide interposer process, but instead uses a conventional method (such as selectively removing the first semiconductor material 52 from the layered stack 92 to release other semiconductor materials, such as the second semiconductor material 54, to form the nanostructure). In the design of the reference seven-transistor memory cell, write capability is prioritized to ensure fast write speed and low write error probability. Therefore, transistors related to write operations in the reference seven-transistor memory cell (such as write bypass transistors WPG1 and WPG2) are formed on n-type fins 90B to provide a strong drive current for write operations. Transistors related to read operations (such as read bypass transistors) are formed on p-type fins 90A. Due to the smaller width of the p-type fins 90A and the problem of mixing, dumbbell-shaped nanostructures such as the second semiconductor material 54 (with a narrower central portion resulting in higher resistance and lower drive current) may lead to less than ideal read capability in the reference seven-transistor memory cell. For read-priority designs, simply modifying the design of a reference seven-transistor memory cell (e.g., forming write bypass transistors WPG1 and WPG2 and pull-up transistors PU1 and PU2 on p-type fin 90A, and forming pull-down transistors PD1 and PD2 and read bypass transistor RPG on n-type fin 90B) may not meet write performance requirements because the drive current for write operations is limited. The disclosed embodiments employ a one-time oxide interposer process, avoiding problems caused by the mixing of germanium and silicon, and the final channel region, such as the second semiconductor material 54, has a rectangular cross-section (rather than a dumbbell-shaped cross-section) to improve the drive current for write operations. For example, by employing a one-time oxide interposer process, forming the channel region, such as the second semiconductor material 54, on fin 90A can improve the drive current by 20%.This significant improvement allows the disclosed embodiments to preferentially improve read capability (by forming a read bypass transistor RPG on an n-type fin 90B) while still achieving good write capability (by forming write bypass transistors WPG1 and WPG2 on a p-type fin 90A).

[0166] Additional processes can be performed to fabricate the nanostructured field-effect transistor devices, as is known to those skilled in the art. For example, external interconnects (such as copper pillars or conductive bumps) can be formed to electrically couple to the internal interconnect structure 155. Multiple nanostructured field-effect transistor devices can be diced to separate them into independent devices. Details are not described here.

[0167] Figures 22A to 23 E and Figure 23 This is another embodiment, showing various figures for the nanostructure field-effect transistor device 100A at various manufacturing stages. The nanostructure field-effect transistor device 100A is similar to the nanostructure field-effect transistor device 100, but omits dielectric structures such as dielectric material 141. Furthermore, portions of fin 90B and nanostructures such as the second semiconductor material 54 and source / drain regions 112 on those portions are removed together to form seven nanostructure field-effect transistors for a seven-transistor memory cell.

[0168] In one embodiment, in order to form the nanostructured field-effect transistor device 100A, the following steps can be performed: Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figures 5A to 5C , Figures 6A to 6C , Figures 7A to 7C , Figures 8A to 8C , Figures 9A to 9C , Figures 10A to 10C ,and Figures 11A to 11C The process shown is used to form fins 90A and 90B and dummy gates 102A, 102B, 102C, and 102D on fins 90A and 90B. The dummy gates 102A, 102B, 102C, and 102D, along with the dummy gate dielectric layer 97 beneath them, can then be replaced with gate structures 123A, 123B, 123C, and 123D, respectively, and the replacement method can be the aforementioned gate replacement process.

[0169] Then as Figures 22A to 22EAs shown, a dielectric plug 127 is formed between fins 90A and fins 90B to cut (e.g., separate) the gate structure 123D into two separate gate structures 123D1 and 123D2. Furthermore, the portion of fin 90B located on the side of gate structure 123A away from gate structure 123B, as well as nanostructures such as the second semiconductor material 54 and source / drain regions 112 on the portion of fin 90B, can be removed together and replaced with a dielectric structure 129. Figure 22A Showing a top view of the nanostructured field-effect transistor device 100A. Figure 22B , 22C 22D and 22E respectively show along Figure 22A Sectional views of sections B1-B1, B2-B2, A1-A1, and A3-A3.

[0170] In some embodiments, to form the dielectric structure 129, a patterned mask layer is formed on the gate structure 123 and the first interlayer dielectric layer 114, with the opening of the patterned mask layer located on the portion of the fin 90B to be removed. One or more anisotropic etching processes are then performed to remove the source / drain regions 112, nanostructures such as the second semiconductor material 54, and portions of the fin 90B below the opening. The opening may be extended into the substrate 50 by one or more anisotropic etching processes. One or more layers of dielectric material, such as silicon oxide, silicon nitride, a low-dielectric-constant dielectric material, or the like, may then be formed in the opening to fill it. A planarization process, such as chemical mechanical polishing, may be performed to remove excess portions of one or more layers of dielectric material from the upper surface of the first interlayer dielectric layer 114. The retained portions of the one or more layers of dielectric material in the opening form the dielectric structure 129. The source / drain regions 112 below the opening of the patterned mask layer are removed from the substrate 50. Figure 22A Region 106 effectively removes one nanostructured field-effect transistor, thus forming a total of seven transistors. Figure 22A A seven-transistor memory cell is formed in region 106.

[0171] Next, a second interlayer dielectric layer 151, source / drain contacts 145S, gate contacts 145G, and interconnect structure 155 are formed on the first interlayer dielectric layer 114, and the formation method is the same as... Figure 20A The fabrication process shown is the same or similar. Electrical components within and / or on the interconnect structure 155 and interconnect substrate 50 are used to form functional circuits (such as a seven-transistor memory cell). A top view of the nanostructured field-effect transistor device 100A is shown below. Figure 23 As shown.

[0172] Figure 23 and Figure 20BSimilarly, but the gate structure 123A overlaps with (as intersecting with) fins 90A and 90B. Furthermore, fin 90B is shorter than fin 90A because a portion of fin 90B (and the nanostructures on that portion, such as the second semiconductor material 54 and the source / drain region 112) have been removed as described above. Therefore, although the gate structure 123A overlaps with fins 90A and 90B, only one nanostructured field-effect transistor is formed at the location where the gate structure 123A overlaps with fin 90A. Figure 23 The source / drain contact 145D shown is formed at the location of the removed source / drain region 112. The source / drain contact 145D is a dummy source / drain contact (e.g., electrically isolated) because the source / drain region 112 beneath it has been removed. In some embodiments, the source / drain contact 145D may be omitted. Figure 23 The equivalent circuit diagram of the 100A nanostructured field-effect transistor device and Figure 21 The circuit diagram is the same as the one in the previous section.

[0173] The disclosed embodiments offer several advantages. For example, the use of a one-time oxide interposer reduces the mixing between germanium and silicon, and the etch selectivity between the one-time material 57 and the second semiconductor material 54 is significantly higher (e.g., greater than 10,000). This allows the channel region to maintain its dimensions (e.g., no or minimal loss of channel width) when the second semiconductor material 54 is released to form the channel region, thereby improving the drive current and providing lower channel resistance. Furthermore, by using a one-time oxide interposer and forming a read-through transistor RPG on the n-type fin 90B (which provides a larger drive current due to the wider width W2), the seven-transistor memory cell disclosed herein achieves strong read capabilities (e.g., fast read speeds and fewer read errors) while still maintaining good write capabilities (e.g., fast write speeds and fewer write errors).

[0174] Figure 24A and 24B This is a flowchart of a method 1000 for forming a seven-transistor memory cell of a semiconductor device in some embodiments. It should be understood that... Figure 24A and 24B The method shown in the embodiment is merely one example of many possible embodiments. Those skilled in the art will understand that many variations, substitutions, and modifications are possible. For example, additions, removals, substitutions, rearrangements, or repetitions may be made. Figure 24A and 24B The steps are shown.

[0175] like Figure 24A and 24BAs shown, step 1010 forms a first fin structure and a second fin structure that protrude above the substrate. The first fin structure includes a first fin and a first layered stack on the first fin. The first layered stack includes interlaced first and second semiconductor material layers. The second fin structure includes a second fin and a second layered stack on the second fin. The second layered stack and the first layered stack have the same layered structure. Step 1020 forms a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure on the first and second fin structures. Step 1030 forms a first source / drain opening in the first fin structure and a second source / drain opening in the second fin structure, wherein the first and second source / drain openings expose the first and second semiconductor materials. Step 1040 replaces the exposed first semiconductor material with a sacrificial material. Step 1050: After replacing the exposed first semiconductor material, a p-type source / drain region is formed in the first source / drain opening, and an n-type source / drain region is formed in the second source / drain opening. Step 1060: After forming the p-type and n-type source / drain regions, a portion of the first gate structure located on the second fin is replaced with a first dielectric structure. Step 1070: After replacing the portion of the first gate structure, the sacrificial material is removed, and the remaining portions of the first, second, third, and fourth gate structures are replaced with a first replaced gate structure, a second replaced gate structure, a third replaced gate structure, and a fourth replaced gate structure, respectively. Step 1080: A second dielectric structure is formed in the fourth replaced gate structure between the first and second fins, wherein the second dielectric structure divides the fourth replaced gate structure into a fifth replaced gate structure on the first fin and a sixth replaced gate structure on the second fin.

[0176] In one embodiment, a method for forming a seven-transistor memory cell of a semiconductor device includes: forming a first fin structure and a second fin structure that protrude above a substrate, wherein the first fin structure includes a first fin and a first layered stack located on the first fin, wherein the first layered stack includes interleaved layers of first semiconductor material and second semiconductor material, wherein the second fin structure includes a second fin and a second layered stack located on the second fin, wherein the second layered stack and the first layered stack have the same layered structure; forming a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure on the first fin structure and the second fin structure; forming a plurality of first source / drain openings in the first fin structure, and forming a plurality of second source / drain openings in the second fin structure, wherein the first source / drain openings and the second source / drain openings... Exposing a first semiconductor material and a second semiconductor material; replacing the exposed first semiconductor material with a sacrificial material; forming a plurality of p-type source / drain regions in a first source / drain opening and forming a plurality of n-type source / drain regions in a second source / drain opening; replacing a portion of the first gate structure located on the second fin with a first dielectric structure; removing the sacrificial material and replacing the remaining portions of the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure with a first replaced gate structure, a second replaced gate structure, a third replaced gate structure, and a fourth replaced gate structure, respectively; and forming a second dielectric structure in the fourth replaced gate structure between the first fin and the second fin, wherein the second dielectric structure divides the fourth replaced gate structure into a fifth replaced gate structure on the first fin and a sixth replaced gate structure on the second fin. In one embodiment, the steps of removing the sacrificial material and replacing the retained portions of the first gate structure, second gate structure, third gate structure, and fourth gate structure include: removing the retained portions of the first gate structure, second gate structure, third gate structure, and fourth gate structure to expose the sacrificial material and the second semiconductor material; selectively removing the exposed sacrificial material, wherein after the selective removal step, the second semiconductor material is retained to form a plurality of channel regions of a seven-transistor memory cell; forming a gate dielectric material around the channel regions; and forming a gate material around the gate dielectric material. In one embodiment, the step of replacing the exposed first semiconductor material includes: selectively removing the first semiconductor material to form a plurality of gaps between the layers of the second semiconductor material; forming sacrificial material in the first source / drain opening and the second source / drain opening, wherein the sacrificial material fills the gaps; and performing an anisotropic etching process to remove portions of the sacrificial material outside the gaps. In one embodiment, the sacrificial material is composed of silicon oxide, silicon oxynitride, or aluminum oxide.In one embodiment, the method further includes removing portions of the sacrificial material exposed at the first source / drain opening and the second source / drain opening after replacing the exposed first semiconductor material with sacrificial material and before forming the p-type source / drain region and the n-type source / drain region, to form a plurality of sidewall recesses in the sacrificial material; and forming a plurality of inner spacers in the sidewall recesses. In one embodiment, the step of replacing portions of the first gate structure includes: forming a first dielectric plug and a second dielectric plug in the first gate structure on both sides of the second fin, wherein portions of the first gate structure are sandwiched between the first dielectric plug and the second dielectric plug; after forming the first dielectric plug and the second dielectric plug, removing portions of the first gate structure and portions of the second semiconductor material and sacrificial material below it to form a first recess in the first gate structure; and filling the first recess with a first dielectric material to form a first dielectric structure. In one embodiment, the step of forming the first recess includes: forming a patterned mask layer on the first gate structure, wherein the opening of the patterned mask layer exposes a portion of the first gate structure; performing a first etching process to remove a portion of the first gate structure; and after completing the first etching process, performing a second etching process to remove portions of the second semiconductor material and sacrificial material beneath the portion of the first gate structure, wherein the second etching process is different from the first etching process. In one embodiment, the first etching process is a wet etching process, and the second etching process is a dry etching process. In one embodiment, the step of forming the second dielectric structure includes: forming a second recess in a fourth displacement gate structure between the first fin and the second fin; and filling the second recess with a second dielectric material to form the second dielectric structure. In one embodiment, the first swapped gate structure is located on the first fin, and the method further includes: forming a first write bypass transistor for a seven-transistor memory cell at the intersection of the first swapped gate structure and the first fin, wherein the first write bypass transistor includes the first swapped gate structure and individual p-type source / drain regions located on both sides of the first swapped gate structure; forming a second write bypass transistor for a seven-transistor memory cell at the intersection of the fifth swapped gate structure and the first fin, wherein the second write bypass transistor includes the fifth swapped gate structure and individual p-type source / drain regions located on both sides of the fifth swapped gate structure; and forming a read bypass transistor for a seven-transistor memory cell at the intersection of the sixth swapped gate structure and the second fin, wherein the read bypass transistor includes the sixth swapped gate structure and individual n-type source / drain regions located on both sides of the sixth swapped gate structure.In one embodiment, a first portion of the second replaced gate structure is located on a first fin, a second portion of the second replaced gate structure is located on a second fin, and the method further includes forming a first pull-up transistor for a seven-transistor memory cell at the intersection of the second replaced gate structure and the first fin, wherein the first pull-up transistor includes the first portion of the second replaced gate structure and individual p-type source / drain regions located on both sides of the first portion of the second replaced gate structure; and forming a first pull-down transistor for a seven-transistor memory cell at the intersection of the second replaced gate structure and the second fin, wherein the first pull-down transistor includes the second portion of the second replaced gate structure and individual n-type source / drain regions located on both sides of the second portion of the second replaced gate structure. In one embodiment, a first portion of the third replaced gate structure is located on a first fin, a second portion of the third replaced gate structure is located on a second fin, and the method further includes: forming a second pull-up transistor for a seven-transistor memory cell at the intersection of the third replaced gate structure and the first fin, wherein the second pull-up transistor includes the first portion of the third replaced gate structure and individual p-type source / drain regions located on both sides of the first portion of the third replaced gate structure; and forming a second pull-down transistor for a seven-transistor memory cell at the intersection of the third replaced gate structure and the second fin, wherein the second pull-down transistor includes the second portion of the third replaced gate structure and individual n-type source / drain regions located on both sides of the second portion of the third replaced gate structure.

[0177] In one embodiment, a method for forming a seven-transistor memory cell of a semiconductor device includes forming a first fin structure and a second fin structure that protrude above a substrate, wherein the first fin structure includes a first fin and a first layered stack located on the first fin, wherein the first layered stack includes interleaved layers of first semiconductor material and second semiconductor material, wherein the second fin structure includes a second fin and a second layered stack located on the second fin, wherein the second layered stack and the first layered stack have the same layered structure; forming a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure on the first fin structure and the second fin structure, wherein the second gate structure and the third gate structure are located between the first gate structure and the fourth gate structure; forming a plurality of first source / drain openings in the first fin structure and forming a plurality of second source / drain openings in the second fin structure, wherein the first source / drain openings and the second source / drain openings expose the first semiconductor material and the second semiconductor material; and exposing the exposed... The first semiconductor material is replaced with a sacrificial material; after the exposed first semiconductor material is replaced, a plurality of p-type source / drain regions are formed in the first source / drain opening, and a plurality of n-type source / drain regions are formed in the second source / drain opening; after the p-type source / drain regions and n-type source / drain regions are formed, the sacrificial material is removed and the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure are replaced with a first replaced gate structure, a second replaced gate structure, a third replaced gate structure, and a fourth replaced gate structure, respectively; the first n-type source / drain region of the n-type source / drain region is replaced with a first dielectric structure, wherein the first n-type source / drain region is located on a first side of the first replaced gate structure away from the second replaced gate structure; and a second dielectric structure is formed in the fourth replaced gate structure between the first fin and the second fin, wherein the second dielectric structure divides the fourth replaced gate structure into a fifth replaced gate structure on the first fin and a sixth replaced gate structure on the second fin. In one embodiment, the steps of removing the sacrificial material and replacing the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure include: removing the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure to expose the sacrificial material and the second semiconductor material; selectively removing the exposed sacrificial material, wherein the second semiconductor material remaining after the selective removal of the sacrificial material forms a plurality of channel regions of a seven-transistor memory cell; forming a gate dielectric material around the channel regions; and forming a gate material around the gate dielectric material.In one embodiment, the step of replacing the first n-type source / drain region includes forming a patterned mask layer on the first replaced gate structure, wherein the opening of the patterned mask layer is located on a first side of the first replaced gate structure and on the first n-type source / drain region; using the patterned mask layer as an etching mask and performing one or more etching processes, wherein the etching processes remove the first n-type source / drain region and form a recess extending into the second fin; and filling the recess with dielectric material. In one embodiment, the first replaced gate structure, the second replaced gate structure, the third replaced gate structure, and the fourth replaced gate structure intersect with the first fin at a first position, a second position, a third position, and a fourth position, respectively, wherein the method further includes forming a first write-through transistor, a first pull-up transistor, a second pull-up transistor, and a second write-through transistor of a seven-transistor memory cell at the first position, the second position, the third position, and the fourth position, respectively. In one embodiment, the second, third, and sixth substituted gate structures intersect with the second fin at a fifth, a sixth, and a seventh position, respectively, wherein the method further includes forming a first pull-down transistor, a second pull-down transistor, and a read-through transistor for a seven-transistor memory cell at the fifth, sixth, and seventh positions, respectively.

[0178] In one embodiment, the memory device includes a substrate; and a seven-transistor memory cell including a first fin and a second fin extending above the substrate, wherein the first fin is narrower than the second fin; a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, and a fifth gate structure, wherein the second gate structure and the third gate structure are located between the first gate structure and the fourth gate structure, wherein the fourth gate structure and the fifth gate structure extend along a common line, wherein in the top view, the first gate structure and the fourth gate structure overlap with the first fin, the second gate structure and the third gate structure overlap with the first fin and the second fin, and the fifth gate structure overlaps with the second fin; a plurality of p-type source / drain regions are located on the first fin and on both sides of the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure; and a plurality of n-type source / drain regions are located on the second fin and on both sides of the second gate structure, the third gate structure, and the fifth gate structure. In one embodiment, the memory device further includes a plurality of first channel regions located above a first fin and between individual p-type source / drain regions; and a plurality of second channel regions located above a second fin and between individual n-type source / drain regions, wherein a first gate structure, a first portion of a second gate structure, a first portion of a third gate structure, and a fourth gate structure surround an individual first channel region, wherein a second portion of a second gate structure, a second portion of a third gate structure, and a fifth gate structure surround an individual second channel region. In one embodiment, the first channel regions and the second channel regions are composed of the same semiconductor material. In one embodiment, a seven-transistor memory cell includes a first write-through transistor located at the intersection of the first gate structure and the first fin. In one embodiment, a seven-transistor memory cell includes a first pull-up transistor located at the intersection of the first portion of the second gate structure and the first fin. In one embodiment, a seven-transistor memory cell includes a second pull-up transistor located at the intersection of the first portion of the third gate structure and the first fin. In one embodiment, a seven-transistor memory cell includes a second write-through transistor located at the intersection of the fourth gate structure and the first fin. In one embodiment, the seven-transistor memory cell includes a first pull-down transistor located at the intersection of a second portion of the second gate structure and a second fin. In one embodiment, the seven-transistor memory cell includes a second pull-down transistor located at the intersection of a second portion of the third gate structure and a second fin. In one embodiment, the seven-transistor memory cell includes a read-through transistor located at the intersection of a fifth gate structure and a second fin. In one embodiment, the memory device further includes a dielectric plug separating a fourth gate structure and a fifth gate structure.

[0179] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and modify other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the concept and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the concept and scope of the present invention.

Claims

1. A memory device, characterized in that... include: One substrate; as well as A seven-transistor memory cell includes: A first fin and a second fin extend above the substrate, wherein the first fin is narrower than the second fin; A first gate structure, a second gate structure, a third gate structure, a fourth gate structure, and a fifth gate structure, wherein the second gate structure and the third gate structure are located between the first gate structure and the fourth gate structure, wherein the fourth gate structure and the fifth gate structure extend along the same line, wherein in a top view, the first gate structure and the fourth gate structure overlap with the first fin, the second gate structure and the third gate structure overlap with the first fin and the second fin, and the fifth gate structure overlaps with the second fin; Multiple p-type source / drain regions are located on the first fin and on both sides of the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure; and Multiple n-type source / drain regions are located on the second fin and on both sides of the second gate structure, the third gate structure, and the fifth gate structure.

2. The memory device as claimed in claim 1, characterized in that, Also includes: Multiple first channel regions are located above the first fin and between the individual multiple p-type source / drain regions; as well as Multiple second channel regions are located above the second fin and between the individual multiple n-type source / drain regions, wherein the first gate structure, the first portion of the second gate structure, the first portion of the third gate structure, and the fourth gate structure surround the individual multiple first channel regions, wherein the second portion of the second gate structure, the second portion of the third gate structure, and the fifth gate structure surround the individual multiple second channel regions.

3. The memory device as claimed in claim 1, characterized in that, The seven-transistor memory cell includes a first write-through transistor located at the intersection of the first gate structure and the first fin.

4. The memory device as claimed in claim 1, characterized in that, The seven-transistor memory cell includes a first pull-up transistor located at the intersection of the first portion of the second gate structure and the first fin.

5. The memory device as claimed in claim 1, characterized in that, The seven-transistor memory cell includes a second pull-up transistor located at the intersection of the first portion of the third gate structure and the first fin.

6. The memory device as claimed in claim 1, characterized in that, The seven-transistor memory cell includes a second write-through transistor located at the intersection of the fourth gate structure and the first fin.

7. The memory device as claimed in claim 1, characterized in that, The seven-transistor memory cell includes a first pull-down transistor located at the intersection of the second portion of the second gate structure and the second fin.

8. The memory device as claimed in claim 1, characterized in that, The seven-transistor memory cell includes a second pull-down transistor located at the intersection of the second portion of the third gate structure and the second fin.

9. The memory device as claimed in claim 1, characterized in that, The seven-transistor memory cell includes a read-through transistor located at the intersection of the fifth gate structure and the second fin.

10. The memory device as claimed in claim 1, characterized in that, It also includes a dielectric plug separating the fourth gate structure from the fifth gate structure.

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