A photovoltaic module and photovoltaic power generation system with non-constant current and stabilized voltage

Abstract

The utility model relates to a kind of photovoltaic module and photovoltaic power generation system of non-constant current but stabilized voltage, described photovoltaic module includes multiple high conversion efficiency's crystalline silicon wafer, according to the number of crystalline silicon wafer design the series-parallel array of crystalline silicon wafer, so that the electric flux E of the photovoltaic module meets certain condition;The crystalline silicon wafer includes front and back, the front is provided with grid ring line, multiple horizontal grid lines and multiple vertical grid lines, the grid ring line ring is set in the periphery of the crystalline silicon wafer, and the edge of the crystalline silicon wafer is separated by certain distance;The shading rate of the horizontal grid line and the pitch of vertical grid line meet certain condition.Therefore, the utility model is designed to the surface of crystalline silicon wafer and the structure of the photovoltaic module formed, so that it becomes linear, and high power quality power supply of stable voltage without harmonic and voltage flicker, can greatly save energy, improve efficiency and the security of photovoltaic net.

Description

Technical Field

[0001] This utility model relates to the field of solar photovoltaic module technology, and in particular to a non-constant current but voltage-stabilized photovoltaic module and photovoltaic power generation system. Background Technology

[0002] Crystalline silicon is a typical semiconductor material and one of the most important semiconductors in the modern electronics industry, with a wide range of applications. As early as the 18th century, semiconductors were used to manufacture radio transmitters and radios, demonstrating their ability to receive sound waves. Silicon steel is also used in the manufacture of electric motors and generators. In the field of integrated circuit chip manufacturing, it is also used in language processing and digital information management.

[0003] Today, crystalline silicon wafers are used to receive solar energy, which are then used to assemble photovoltaic (PV) modules, which in turn form PV systems. With the large-scale construction of PV power plants, they have become an important component of the power distribution network. However, due to the instability and intermittency of their power generation, as well as the nonlinear characteristics of key equipment, PV power plants, once connected to the distribution network, seriously impact the safety and stability of the grid. Harmonics, voltage fluctuations, and flicker are the most severe issues. This oscillating power source, after grid connection, causes frequency pollution to the public power grid and also creates the danger of high-voltage leakage. High-voltage leakage is equivalent to a lightning strike; a chain reaction of fires at the PV power plant can instantly paralyze the regional power grid. With increasing emphasis on the safety and stability of the power grid, harmonic and flicker problems urgently need to be addressed.

[0004] For example, current research has found that grid-connected photovoltaic power plants generally suffer from harmonic flicker problems. The peak maximum power of a certain power plant changes by 75% per minute. With a 75% cycle change every minute, it means that the electricity connected to the grid by this photovoltaic power plant contains 25% effective power and 75% reactive power. This high-frequency fluctuation causes impact pollution to the 50 Hz common frequency of the grid's sine wave. The 75% fluctuation cycle every minute makes the grid-connected photovoltaic system operate in an oscillating pattern.

[0005] In existing technologies, the main solutions to the problems of harmonics, voltage fluctuations, and flicker in photovoltaic grid-connected systems include: 1) optimizing the control strategy of photovoltaic grid-connected inverters to improve voltage stability; 2) increasing the short-circuit capacity of substation busbars; and 3) improving the power factor of photovoltaic power plants with a fixed capacity to increase the total active power and thus reduce reactive power fluctuations, meeting the voltage fluctuation limit requirements. However, these methods all neglect the fundamental performance research of the photovoltaic modules themselves. Furthermore, in existing technologies, the photoelectric conversion efficiency of photovoltaic modules has remained low, currently around 24.8%, and below 30%. The efficiency of photovoltaic grid-connected relay loads is currently no higher than 35%, which is a pain point and challenge for the industry, resulting in significant energy and resource waste.

[0006] Since photovoltaic modules are the main light-receiving surfaces of photovoltaic power plants, they are hardware that receives light and components that continuously provide electrons. The conversion efficiency of photovoltaic modules is directly proportional to the light-receiving area of ​​the crystalline silicon wafer. The larger the light-receiving area, the more photons are received, and the smaller the light-receiving area, the fewer photons are received.

[0007] On the surface of single-crystal silicon wafers, gate lines are typically printed with silver paste. The function of the gate lines is to collect electrons and facilitate their transitions; in areas without gate lines, electrons encounter corresponding resistance. However, if the gate lines are too dense, they will block a certain amount of light-receiving area.

[0008] In the applicant's previous patent application 202510123841.X, the spacing design requirements for the electron transition grid lines on the surface of the crystalline silicon wafer were specified under the condition that the electric flux 1≤E≤1.82. However, in subsequent experimental research and development, new design requirements were put forward for the surface structure of the crystalline silicon wafer and the corresponding number and spacing of grid lines.

[0009] The present invention aims not only to eliminate harmonics, voltage fluctuations and flicker, but also to further improve the photoelectric conversion efficiency and performance of crystalline silicon wafers and photovoltaic modules based on previous methods. Utility Model Content

[0010] To overcome the shortcomings of existing technologies, this utility model provides a non-constant current but voltage-stabilized photovoltaic module and photovoltaic power generation system, which can further improve the photoelectric conversion efficiency of crystalline silicon wafers and photovoltaic modules, and eliminate the problems of harmonics, voltage fluctuations and flicker.

[0011] This utility model provides a non-constant current but voltage-stabilized photovoltaic module. The photovoltaic module includes multiple crystalline silicon wafers. The series and parallel array of crystalline silicon wafers is designed according to the number of crystalline silicon wafers. The current flux E of the photovoltaic module, that is, the ratio of the working current to the working voltage, satisfies 1≤E≤1.82.

[0012] Furthermore, the photovoltaic module includes N parallel units, where N is a positive integer greater than 1. Each parallel unit includes M parallel crystalline silicon wafer string units, where M is a positive integer greater than 1. Each string unit is composed of multiple crystalline silicon wafers connected in series. The N parallel units are connected in series sequentially.

[0013] Furthermore, N is 3, there are 72 silicon wafers, and every 12 silicon wafers are connected in series to form 6 string units, and every two string units are connected in parallel to form three parallel units, and the three parallel units are connected in series in sequence.

[0014] Furthermore, each silicon wafer includes a front side and a back side. The front side is provided with a gate ring line, multiple horizontal gate lines, and multiple vertical gate lines. The gate ring line is arranged around the periphery of the silicon wafer and is spaced a certain distance from the edge of the silicon wafer. The multiple horizontal gate lines are arranged horizontally in parallel and at equal intervals inside the gate ring line of the silicon wafer. The horizontal gate lines have a certain diameter and are spaced at a first interval. The multiple vertical gate lines intersect the horizontal gate lines perpendicularly and are arranged vertically in parallel and at equal intervals. The multiple vertical gate lines are spaced at a second interval.

[0015] Furthermore, the back of the silicon wafer is coated with a zinc paste coating;

[0016] Furthermore, the shading rate of the horizontal grid line does not exceed 0.5%. Let the shading rate of the horizontal grid line be w, the number of horizontal grid lines be n, the diameter of each horizontal grid line be a, the length and width of the effective size of the silicon wafer be L and L' respectively, the shading rate of the horizontal grid line w = (a × n / L') × 100%, and the effective size of the silicon wafer be the size enclosed by the grid ring line.

[0017] Furthermore, the second spacing is less than 1 cm;

[0018] Furthermore, the distance between the gate ring line and the edge of the silicon wafer is 1 mm;

[0019] Furthermore, the second spacing is 9.48 mm;

[0020] Furthermore, the first spacing is 2.23mm-2.28mm.

[0021] Furthermore, 80 horizontal gate lines and 18 vertical gate lines are provided on the front side of the 182.2mm×182.2mm silicon wafer;

[0022] Furthermore, six rows of positive electrode solder points printed with silver paste are arranged on the edge of the back side of the 182.2mm×182.2mm silicon wafer, with 18 solder points in each row and a width of 2mm for each solder point.

[0023] Furthermore, the longitudinal grid line and the grid ring line form 18 intersection points, each intersection point is 6mm long and 2mm wide, and the printing surface is treated with silver paste. All intersection points are located inside the grid ring line and lead out the negative electrode.

[0024] This utility model also provides a photovoltaic power generation system, which includes multiple photovoltaic modules connected in series and / or in parallel to form an array, and the power flux of the photovoltaic power generation system satisfies 1≤E≤1.82.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] This invention optimizes the design and manufacturing process of silicon wafers by setting multiple horizontal grid lines and electron transition grid lines (vertical grid lines) on the silicon wafer. A zinc paste coating is applied to the back of the silicon wafer, and silver paste is applied to the front surface—these are highly conductive materials. The grid line design includes increasing the number of grid rings, reducing the shading rate of the horizontal grid lines, and reducing the difficulty of electron transitions through the spacing design of the vertical grid lines. Simultaneously, the current transport path inside the silicon wafer is optimized, reducing the resistance of the silicon wafer itself, thereby reducing the series resistance, increasing the fill factor of the silicon wafer, and ultimately improving the photoelectric conversion efficiency, raising the existing 24.8% photoelectric conversion efficiency to 47.86%.

[0027] This invention also provides a new internal silicon wafer connection circuit structure for photovoltaic modules. By first connecting silicon wafer strings in parallel and then in series, the power generation efficiency of the existing technology is further increased by 24.4% to achieve a power generation efficiency of 49.2%, based on the existing 24.8%. Through the structural design of the silicon wafers and the arrangement of the silicon wafers inside the photovoltaic module, this invention enables the photovoltaic module to meet the requirements of a linear power supply, becoming a non-constant current but voltage-stabilized linear power supply, a harmonic-free and flicker-free relatively voltage-stabilized module, improving the effectiveness of the operating voltage, controlling the fluctuation of reactive voltage, increasing the active voltage utilization rate to 98%, and limiting reactive voltage to below 2%. This is the standard that high-power-quality photovoltaic modules and systems should achieve, which can greatly save energy, improve efficiency, and enhance the security of photovoltaic grid connection. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the front structure of a silicon wafer slice;

[0029] Figure 2 This is a schematic diagram of the back structure of a silicon wafer slice;

[0030] Figure 3 This is a structural schematic diagram of the photovoltaic module of this utility model. Detailed Implementation

[0031] To better understand the technical solution of this utility model, the embodiments of this utility model will be described in detail below with reference to the accompanying drawings.

[0032] It should be understood that the described embodiments are merely some embodiments of this utility model, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model.

[0033] The terminology used in the embodiments of this utility model is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. The singular forms “a,” “the,” and “the” used in the embodiments of this utility model and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0034] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0035] It should be noted that the directional terms such as "upper," "lower," "left," and "right" described in the embodiments of this utility model are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the embodiments of this application. In addition, in the context, it should also be understood that when it is mentioned that an element is connected to another element "upper" or "lower," it can be directly connected to the other element "upper" or "lower," or it can be indirectly connected to the other element "upper" or "lower" through an intermediate element.

[0036] It should be noted that the steps shown in the flowcharts in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Although a logical order is shown in the flowcharts, the order of the steps in each embodiment is not limited to the order arranged in this specification. In some cases, the implementation steps may be adjusted according to specific needs, and the steps shown or described may be performed in a different order than that shown here.

[0037] In the applicant's prior patent application 202510123841.X, the main parameters of a photovoltaic module are described as follows: (rated) power, operating voltage, and operating current. In this invention, the electrical flux E of the photovoltaic module is defined as operating current / operating voltage (unit: amperes / volts), which is the ratio of the photovoltaic module's operating current to its operating voltage. This ratio is an important indicator for measuring the conversion efficiency of the photovoltaic module and whether it is a linear power source. Furthermore, the aforementioned prior patent application 202510123841.X also states that the ideal electrical flux E of a photovoltaic module should be within the range of 1 ≤ E ≤ 1.82 (amperes / volts), which is the electrical flux range for linear power sources. This is because a photovoltaic module (equivalent to a power panel) can be considered an independent power source. Regardless of the size of the light-receiving surface of a silicon crystalline photovoltaic cell, it is a single electrostatic unit. In this original electrostatic unit, with a normal voltage of 0.55 volts suppressed by a constant resistance of 0.55 ohms, the usable current intensity is 1 ampere. That is, the normal current of one electrostatic unit is 1 ampere, the voltage is 0.55 volts, and the resistance is 0.55 ohms. 1 ampere normal current / 0.55 volt normal voltage = 1.82 amperes / volt of current flux, meaning that every 1 volt of voltage quantitatively inspires 1.82 amperes of current. This is the source of the upper limit of the aforementioned current flux. The lower limit of 1 ampere / volt is the reference current flux of the electrostatic field.

[0038] In traditional technologies, photovoltaic modules of varying sizes and specifications exhibit different photoelectric conversion effects and electrical fluxes, as shown in Table 1.

[0039] Table 1. Parameters of various photovoltaic modules in traditional technologies

[0040]

[0041] Ambient temperature: 20℃, irradiance: 1000W / m 2 Wind speed: 1 m / s.

[0042] The photovoltaic module data in Table 1 shows an electrical flux between 0.4664 A / V and 0.4594 A / V, which belongs to the point charge online virtual power source. The virtual power source is the root cause of harmonic flicker oscillations.

[0043] In this utility model, it is necessary to further explain that:

[0044] Only when E = I / U = 1 A / V can the generation of reactive voltage be eliminated and harmonic-free operation be achieved. This is because the voltage can only eliminate harmonic flicker when the point charge initially becomes a linear power source.

[0045] Only when E = I / U = 1.74 A / V can the linearity of power quality meet the Chinese standard, and the DC inverter output can reach a pure sine wave frequency of 50 Hz.

[0046] Only when E = I / U = 1.82 A / V can the linearity of power quality meet the European standard, and the DC inverter output can reach a pure sine wave frequency of 60 Hz.

[0047] Photovoltaic modules can only become regulated power supplies if they meet the linear trajectory condition. In other words, only by manufacturing modules that are not constant current but regulated can high-quality photovoltaic power generation be achieved.

[0048] Therefore, the ideal value of the electrical flux E of a photovoltaic module should be: 1≤E≤1.82 (A / V), and the intrinsic resistance of the photovoltaic module (R=U / I) needs to satisfy the condition 0.55≤R≤1 (Ω); the two conditions of electrical flux and intrinsic resistance are also corresponding.

[0049] In addition, the conversion efficiency of a photovoltaic module is directly proportional to the light-receiving area of ​​the crystalline silicon wafer. The larger the light-receiving area, the more photons are received, and the smaller the light-receiving area, the fewer photons are received.

[0050] like Figure 1 and Figure 2 As shown, this utility model provides a crystalline silicon wafer, the crystalline silicon wafer including a front side ( Figure 1 ) and back ( Figure 2 ),in Figure 1 This is a front view of a crystalline silicon photovoltaic module unit slice (a single crystalline silicon wafer), and also a schematic diagram of surface grid line printing. 1 represents the overall structure of the front of a single crystalline silicon wafer; 2 represents the interconnected grid segments of grid lines printed with silver paste on the front of the single crystalline silicon wafer, also known as horizontal grid lines; 3 represents the electron transition grid lines printed with silver paste along the length direction on the front of the single crystalline silicon wafer, also known as vertical grid lines; all horizontal grid lines 2 are perpendicular to all vertical grid lines 3 and arranged at certain intervals; 4 represents the secondary gradient line at the intersection of horizontal and vertical grid lines; 5 represents the intersection point of vertical grid lines and grid ring lines, leading out the conductive negative electrode of the crystalline silicon wafer; 6 represents the grid ring lines surrounding the electron transition grid lines printed with silver paste on the front of the single crystalline silicon wafer.

[0051] In one specific embodiment of this utility model, a single silicon wafer can be rectangular or rounded square.

[0052] Or circular, this utility model takes a rectangle as an example, such as... Figure 1As shown, the area of ​​a single silicon wafer is 182.2mm × 182.2mm. The gate ring line 6 is arranged around the perimeter of the silicon wafer, spaced a certain distance from the edge of the silicon wafer. Multiple horizontal gate lines 2 are arranged parallel to each other from top to bottom with equal spacing inside the gate ring line of the silicon wafer, totaling 80 horizontal gate lines. Multiple vertical gate lines 3 intersect the horizontal gate lines 2 perpendicularly and are arranged parallel to each other with equal spacing with a second spacing. There are 18 vertical gate lines printed with silver paste on the surface of the single-crystal silicon wafer. The distance between the gate ring line 6 and the edge of the complete silicon wafer 1 is 1mm. This arrangement prevents short circuits caused by the positive and negative electrodes.

[0053] In this invention, the main purposes of setting the gate ring line are twofold: first, to strengthen the silicon wafer's ability to withstand stress during lamination and prevent the edges and corners from becoming fragile; and second, to ensure that electrons at the four corners do not stagnate or get lost.

[0054] Regarding the number of vertical gate lines, in the early fabrication of single-crystal silicon wafers, the conversion efficiency was between 16% and 23%. Since the adoption of nanotechnology, increasing the number of vertical gate lines from 2 to 6 improved the conversion efficiency to 24.8%, and increasing it from 6 to 8 further improved it to 25.3%. In the applicant's earlier patent application 202510123841.X, the number of vertical gate lines was increased to 16, enabling a system conversion efficiency of 40%. Increasing the number of vertical gate lines enhances electron conduction, thereby reducing the resistivity of the silicon wafer.

[0055] The number of horizontal grid lines has been reduced from 168 to 80. Halving the number of horizontal grid lines can reduce the light-blocking surface by 50%, which greatly increases the number of photons filled and the number of electron pairings, thereby improving the light conversion efficiency of silicon semiconductors.

[0056] In this embodiment, after removing the 1mm*2=2mm spacing between the gate ring line and the edge of the silicon wafer, the remaining area of ​​the silicon wafer is approximately 180.2×180.2mm. 2 There are 80 horizontal grid lines, with a line width ranging from 10μm to 50μm. Assuming each horizontal grid line has a line width of 10μm, the total width of the 80 lines is 80 × 10 = 800μm. The total spacing is 180200 - 800 = 179400μm, with 79 intervals. The spacing between each line is approximately 179400 ÷ 81 ≈ 2270.9μm, or about 2.28mm. Alternatively, assuming each line has a width of 50μm, the total width of the 80 lines is 80 × 50 = 4000μm. The total spacing is 180200 - 4000 = 176200μm, with 79 intervals. The spacing between each line is approximately 176200 ÷ 79 ≈ 2230.4μm, or about 2.23mm. Therefore, the spacing range of the horizontal grid lines is 2.23mm–2.28mm. In this embodiment, the spacing between the horizontal grid lines is 2.28 mm.

[0057] In existing technologies, the number of fine grid lines is around 100-200, with a light-blocking rate of 1.2-2%. Increasing the number and area of ​​grid lines increases the light-blocking area and reduces the effective light-receiving area. For example, in a traditional 182mm×182mm silicon wafer, there are 178 horizontal grid lines, each with a width of 0.02mm. The light-blocking rate of the horizontal grid lines is: (0.02×178 / 182)*100%=1.95%.

[0058] In this invention, in a silicon wafer with an effective size of 180.2mm × 180.2mm (the size surrounded by the gate rings), there are 80 horizontal gate lines. Assuming the width of each horizontal gate line is 0.02mm, the light-blocking rate of the horizontal gate lines is: (0.02 × 80 / 180.2) * 100% = 0.89%; if the width of each horizontal gate line is 0.01mm, the light-blocking rate of the horizontal gate lines is: (0.01 × 80 / 180.2) * 100% = 0.44%.

[0059] Therefore, an excessively high shading rate (e.g., 1.95%) indicates that there are too many horizontal grid lines on the surface of the silicon wafer, which will result in an excessively large shaded area, which is not conducive to photon reception. Conversely, an excessively low shading rate indicates that there are too few horizontal grid lines on the surface of the silicon wafer, which will increase the photon reception rate. In this invention, 80 horizontal grid lines are set, and the resulting shading rate of 0.44% will achieve the optimal photon reception rate.

[0060] Let w be the shading rate of the horizontal grid lines, n be the number of horizontal grid lines (n is a positive integer greater than 1), a be the imprint width (diameter width) of each horizontal grid line (a>0), and L×L be the effective size of the silicon wafer (the size enclosed by the grid rings) (the size is a square with the same length and width, L>0). Then the shading rate of the horizontal grid lines w = (a×n / L)×100%.

[0061] If the silicon wafer is not square, the effective size is L (length) × L' (width) (L and L' are both greater than 0). Assuming that the horizontal grid lines are set in the same direction as the length of the silicon wafer and the diameter is in the width direction (length and width are defined in the same direction as the grid lines), then the shading rate of the horizontal grid lines is w = (a × n / L') × 100%.

[0062] In this invention, to increase photoelectric conversion efficiency, it has been determined through experiments and derivation that the shading rate of the horizontal grid lines does not exceed 0.5%.

[0063] This invention reduces the number of horizontal grid lines in the prior art by about half, thereby reducing the shaded area and doubling the photon filling area, thus significantly increasing the photon reception rate.

[0064] In prior patent application 202510123841.X, the spacing of the electron transition gate lines is described as less than or equal to 1.1 cm. In the prior art, the number of vertical gate lines is 2, 4, 6, or 8, and the spacing between them is between 20 mm and 60 mm. A longer spacing results in a longer electron transition path. In this embodiment, 18 vertical gate lines (electron transition lines) are printed with silver paste on the surface within the gate ring of the silicon wafer. The diameter (print width) of the vertical gate lines is between 0.1 mm and 1.5 mm. In this embodiment, preferably, the distance between the vertical gate lines is 9.48 mm (less than 1.1 cm).

[0065] Experiments show that maintaining a 9.48mm interval between parallel vertical grid lines can better prevent the reduction in the number of electrons caused by the lack of power during electron transitions.

[0066] A secondary gradient line 4 is provided at the intersection of the horizontal and vertical grid lines. A segment solder joint 5 is provided at the intersection of each vertical grid line and the grid ring line, for a total of 18 segment solder joints. These 18 segment solder joints are printed with silver paste and are located within the grid ring line and must not exceed the specified boundaries. Each segment solder joint is welded with an electron output guide strip 3mm-6mm long and 1mm-2mm wide, serving as the output negative electrode. In this embodiment, the electron output guide strip is 6mm long and 2mm wide.

[0067] For the same current of 13.1A, if there are 18 longitudinal grid lines, the current carried by each longitudinal grid line as a transmitter is 13.1A / 18 = 0.728A. Compared with the traditional technology where each longitudinal grid line carries a current of 13.1A / 4 = 3.275A, the current carried by each longitudinal grid line in this invention is much smaller, thus overcoming the congestion problem of electron transition.

[0068] See Figure 2 The back surface 7 of the monocrystalline silicon wafer 1 is coated with a zinc paste coating, which serves as the conductive positive electrode of the silicon wafer 1 and is suitable for series or parallel connection of silicon wafer cells. The conductive positive electrode on the back surface includes multiple electrode segments, each of which is connected to an electrode solder joint. In this embodiment, on the 182.2mm×182.2mm monocrystalline silicon wafer, there are 6 rows (from top to bottom) of 18 silver paste-printed positive electrode solder joints 8 on the upper edge of the zinc paste coating. Each positive electrode solder joint 8 in the bottom row is 1mm away from the edge of the silicon wafer. Each positive electrode solder joint is 2mm-4mm long, 0.005mm thick, and 1mm-2mm wide.

[0069] Taking a width of 2mm as an example, the total current-carrying width of the positive electrode welding point = welding point width 2mm × 18 = 36mm. Therefore, the average overload current per unit width of the positive electrode welding point is 13.1A / 36mm = 0.364A. Compared with the traditional technology of 4 welding points (each welding point is 2mm wide), the average overload current per unit width is 13.1A / (2mm×4) = 1.638A. The load of this utility model is reduced by nearly four-fifths, solving the problems of heat generation, efficiency degradation and aging of crystalline silicon wafers.

[0070] Taking the existing technology with 6 positive electrode welding points (thickness calculated at 0.005 mm) as an example, the cross-sectional area of ​​the positive electrode welding points is 0.005 × 2 × 6 = 0.06 mm². 2 In the embodiment of this utility model, the cross-sectional area of ​​the positive electrode welding point is 0.005 × 2 × 18 = 0.18 mm. 2 If the cross-sectional area is increased by 3 times, the current-carrying area will also increase by 3 times, and the maximum overload current will increase from 0.06×6A=0.36A to 0.18×6A=1.08A. The increase in the maximum overload current will completely eliminate the problems of heat generation and aging of the silicon wafer.

[0071] The back surface 7 of the silicon wafer is used to receive sunlight and generate a positive current, serving as the emission area for the fill factor. Existing technologies use aluminum as the conductive positive electrode for silicon wafers. However, aluminum has low density, is brittle, conducts heat quickly, rusts easily, has poor conductivity, is difficult to weld, and lacks good electrical properties, making it unsuitable as a conductive electrode. Therefore, this invention uses a zinc paste coating, which is non-heat-conducting, high-density, highly conductive, and easy to weld, as the conductive positive electrode. In other embodiments, other materials, such as copper or aluminum alloys, can also be selected to meet the requirements of being non-heat-conducting, high-density, highly conductive, and easy to weld.

[0072] As an embodiment of the present invention, the present invention also provides a photovoltaic module, which includes a front cover plate (transparent glass) and a back cover plate, the back cover plate being disposed on one side of the front cover plate in the thickness direction; a plurality of solar crystalline silicon wafers designed in the present invention are included between the front cover plate and the back cover plate, wherein the front cover plate is made of transparent glass and the back cover plate is made of plastic film.

[0073] Existing photovoltaic modules are composed of multiple crystalline silicon wafers connected in series. Each wafer has parameters of 13.1A / 0.58V. For example, 72 wafers connected in series form a photovoltaic module with theoretical parameters of 13.1A / 42V / 550W. However, using the crystalline silicon wafers of this invention for series connection, the actual output relay power is 18.2A / 42.58V / 775W, an increase of 775W - 550W = 225W in power generation capacity. This is achieved by using the technical improvement of this invention, which increases the number of photon and electron pairings, resulting in a 50% increase in power generation, while keeping the light-receiving area unchanged at 182.2mm × 182.2mm.

[0074] To further improve the photoelectric conversion efficiency, grid-connected power, and power generation of photovoltaic modules, this utility model also provides a photovoltaic module comprising several interconnected crystalline silicon wafers, such as... Figure 3 As shown, there are a total of 72 silicon wafers, and every 12 silicon wafers are connected in series from top to bottom to form 6 string units (power supplies). Every two string units (power supplies) are then connected in parallel to form 3 parallel units from left to right, namely the first parallel unit 9, the second parallel unit 10 and the third parallel unit 11. Each parallel unit outputs 26.2A / 6.6V. The three parallel units are connected in series in sequence. Each string unit has a spacing 12 between its silicon wafers. In this embodiment, the length of the spacing 12 is 2mm. The spacing between the six string units is the same width. 13 is the first busbar, and the negative output of the first parallel unit (36 in total) is soldered to the first busbar 13. 14 is the second busbar, and the positive output of the second parallel unit (18 on the back) is soldered to the second busbar 14. The first busbar and the second busbar are connected, that is, the negative output of the first parallel unit and the positive output of the second parallel unit are connected in series. 15 is the third busbar, and the negative output of the second parallel unit (36 in total) is soldered to the third busbar 15. 16 is the fourth busbar, and the positive output of the third parallel unit (18 on the back) is soldered to the fourth busbar 16. The third busbar 15 and the fourth busbar 16 are connected, that is, the negative output of the second parallel unit and the positive output of the third parallel unit are connected in series. 17 is the positive (ten) busbar of the photovoltaic module; 18 is the negative (one) busbar of the photovoltaic module.

[0075] In existing technologies, the circuit structure of photovoltaic modules uses a process of cutting silicon wafers in half and then connecting them in series. However, in this invention, complete square silicon wafers are used, with each string connected in parallel and then in series. Specifically, every 12 silicon wafers are connected in series to form six strings of 13.1A / 7V power. Then, every two 13.1A / 7V strings are connected in parallel to form three parallel power generation units of 26.2A / 7V. Finally, these three 26.2A / 7V power generation units are connected in series to form a 26.2A / 21V / 550W photovoltaic module.

[0076] Under the premise of unchanged total rated power, this technical solution transforms the existing 13.1A / 42V / 550W (6 strings in series) photovoltaic modules into 26.2A / 21V / 550W photovoltaic modules. The improved photovoltaic resistance, R = 21V / 26.2A = 0.802Ω, is less than 1Ω, eliminating the root cause of reactive voltage. The theoretical power and the actual effective load power correspond 100% accurately, while the current flux E = 26.19A / 21V = 1.247 A / V, satisfying 1 ≤ E ≤ 1.82 (A / V) for a linear power supply. Therefore, the linear trajectory of this series-parallel photovoltaic module is a linear regulated power supply, enabling the photovoltaic module to achieve voltage regulation without constant current, eliminating harmonic and flicker defects. The light-receiving area of ​​each silicon wafer in the photovoltaic module remains unchanged, but the series-parallel connection method alters the values ​​of resistance R and E, as well as the output parameter values.

[0077] Using existing technology, 72 silicon wafers are connected in series with parameters of 13.1A / 42V / 550W. Theoretically, using the series-parallel connection method of this utility model, the parameters are 26.2A / 21V / 550W. However, in actual pilot testing, the measured output parameters of this utility model are 38A / 21.6V / 820.8W.

[0078] The 820.8W represents the actual effective load power of the photovoltaic module, which is 270.8W more than the theoretical installed capacity of 550W. The increased power generation is (270.8W / 550W)×100%=49.2%. This technical solution further improves the power conversion efficiency of the existing technology by 24.8%, achieving a power conversion efficiency of 49.2%.

[0079] The original rated current of the crystalline silicon wafer was 26.2A. After optimization, the relay current of the gate lines (including gate ring lines, horizontal gate lines and vertical gate lines) is 38A. The current of the crystalline silicon wafer increases by 11.8A, and the photoelectric conversion efficiency increases by (11.8A / 26.2A)×100%=45%.

[0080] The electrical flux changes from E = 26.2A / 21V = 1.248 A / V to E = 38A / 21.6V = 1.75 A / V, satisfying the standard of a linear power supply with 1 ≤ E ≤ 1.82 (A / V). The original rated operating voltage of 21V increases to 21.6V due to the increased charge density, resulting in an increase in electromotive force. This represents an increase of 0.6V in operating voltage, or (0.6 / 21) × 100% = 2.86%. Therefore, the overall photoelectric conversion efficiency of the silicon wafer is 45% + 2.86% = 47.86%. This improves the existing photoelectric conversion efficiency from 24.8% to 47.86%.

[0081] This invention utilizes a structural design for a single-crystal silicon wafer, including a gate ring structure, horizontal gate lines, and the number of electron transition gate lines (vertical gate lines). The gate ring lines enable electron current collection and shunting, and are maintained at a 1mm distance from the outer edge of the silicon wafer to prevent short circuits between the positive and negative electrodes. The number and spacing of the horizontal gate lines are designed to ensure their shading rate does not exceed 0.5%. The number and spacing of the vertical gate lines are designed to prevent insufficient electron transition distance, thus avoiding a reduction in the number of electrons. Furthermore, a zinc paste coating is applied to the back of the silicon wafer, and highly conductive materials such as silver paste are applied to the surface. These structural designs significantly improve the photoelectric conversion efficiency of the silicon wafer.

[0082] In addition, this utility model also designs a new internal crystalline silicon wafer connection circuit structure for photovoltaic modules. By first connecting the crystalline silicon wafers in parallel and then in series, the power generation efficiency of the existing technology is increased by 24.4% to achieve a power generation efficiency of 49.2%.

[0083] This invention, through structural modifications, enables photovoltaic modules to become linear power sources, harmonic-free, and voltage flicker-free, resulting in relatively stable voltage. This significantly saves energy, improves efficiency, and enhances the security of photovoltaic grids. Furthermore, this invention improves the effectiveness of the operating voltage, controls reactive voltage fluctuations, increases the active voltage utilization rate to 98%, and limits reactive voltage to below 2%, which are standards that high-power-quality photovoltaic modules and systems should meet.

[0084] According to the data from the experiment, the innovative photovoltaic module has achieved voltage stabilization without constant current, breaking through the technical difficulties left over from the history of traditional technology, and is a good start for high-output and high-quality development of electricity.

[0085] As an embodiment of the present invention, the present invention also provides a photovoltaic system, which includes a plurality of the aforementioned photovoltaic modules. The photovoltaic system is composed of a plurality of the aforementioned photovoltaic modules connected in series and / or in parallel, and the electric flux satisfies 1≤E≤1.82.

[0086] In existing technologies, the working principle of general photovoltaic power generation is series connection, high voltage and low current. For example, the parameters of six photovoltaic modules connected in series at 13.1A / 42V / 550W are 13.1A / 252V / 3301W. If this series-connected photovoltaic module is replaced with a power generation and energy storage system composed of parallel photovoltaic modules, the parameters become 78.6A / 42V / 3301W. The voltage is reduced to one-sixth of the original, and the actual current output increases sixfold, making it a low-voltage, high-current power source. In the actual assembly process, the series and parallel connections of the photovoltaic modules are rationally configured according to the parameter requirements to ensure that the current flux meets the condition 1≤E≤1.82 (A / V).

[0087] In summary, this invention improves the photoelectric conversion efficiency and power generation of photovoltaic modules by designing the crystalline silicon wafers and arranging them in series and parallel. It also ensures that the power flux of the photovoltaic system meets the standard of 1≤E≤1.82, making it a low-voltage, high-current power source. This results in a non-constant current and voltage-stabilized power source, free from harmonics and voltage flicker, and a high-power-quality power source with reactive voltage below 2%.

[0088] The same applies to photovoltaic systems. By arranging photovoltaic modules in series and parallel to achieve a power flux of 1≤E≤1.82, the photovoltaic system can achieve a non-constant current and voltage-stabilized power supply, free from harmonics and voltage flicker, and a high power quality power supply with reactive voltage below 2%.

[0089] In other embodiments, the size and area of ​​the silicon wafer can also be other values, such as silicon wafers of 182mm×182mm, 182.2mm×91.1mm, 210mm×210mm, or 210mm×105mm.

[0090] The above are preferred embodiments of this utility model, and this utility model is not limited to the above embodiments. It is understood that other improvements and variations that can be directly derived or conceived by those skilled in the art without departing from the spirit and concept of this utility model should be considered to be included within the protection scope of this utility model.

Claims

1. A non-constant current but voltage-regulated photovoltaic module, characterized in that, The photovoltaic module includes multiple high-conversion-efficiency crystalline silicon wafers. The series and parallel array of crystalline silicon wafers is designed according to the number of crystalline silicon wafers so that the current E of the photovoltaic module, that is, the ratio of the operating current to the operating voltage, satisfies 1 ≤ E ≤ 1.

82. Each silicon wafer includes a front side and a back side. The front side is provided with a gate ring line, multiple horizontal gate lines, and multiple vertical gate lines. The gate ring line is arranged around the perimeter of the silicon wafer and is spaced 1 mm from the edge of the silicon wafer. The multiple horizontal gate lines are arranged horizontally in parallel with equal spacing inside the gate ring line of the silicon wafer, and the spacing between the multiple horizontal gate lines is 2.23 mm to 2.28 mm. The multiple vertical gate lines intersect the horizontal gate lines perpendicularly and are arranged vertically in parallel with equal spacing, and the spacing between the multiple vertical gate lines is less than 1 cm. The front side of a 182.2 mm × 182.2 mm silicon wafer is provided with 80 horizontal gate lines and 18 vertical gate lines.

2. The photovoltaic module according to claim 1, characterized in that, The photovoltaic module includes N parallel units, where N is a positive integer greater than 1. Each parallel unit includes M parallel silicon wafer string units, where M is a positive integer greater than 1. Each string unit is composed of multiple silicon wafers connected in series. The N parallel units are connected in series sequentially.

3. The photovoltaic module according to claim 2, characterized in that, N is 3, there are 72 silicon wafers, and every 12 silicon wafers are connected in series to form 6 string units. Every two string units are connected in parallel to form three parallel units, and the three parallel units are connected in series in sequence.

4. The photovoltaic module according to claim 1, characterized in that, The back of the silicon wafer is coated with a zinc paste coating.

5. The photovoltaic module according to claim 1, characterized in that, The shading rate of the horizontal grid line does not exceed 0.5%. Let the shading rate of the horizontal grid line be w, the number of horizontal grid lines be n, the diameter of each horizontal grid line be a, the length and width of the effective size of the silicon wafer be L and L' respectively, the shading rate of the horizontal grid line w = (a × n / L') × 100%, and the effective size of the silicon wafer be the size enclosed by the grid ring line.

6. The photovoltaic module according to claim 1, characterized in that, The spacing between the multiple longitudinal grid lines is 9.48 mm.

7. The photovoltaic module according to claim 2, characterized in that, The back edge of the 182.2mm×182.2mm silicon wafer has 6 rows of 18 silver paste-printed positive electrode solder points, each solder point is 2mm wide.

8. The photovoltaic module according to claim 1, characterized in that, The longitudinal grid line and the grid ring line form 18 intersection points. Each intersection point is 6mm long and 2mm wide. The printing surface is treated with silver paste. All intersection points are located inside the grid ring line and lead out the negative electrode.

9. A photovoltaic power generation system, characterized in that, The photovoltaic power generation system includes a plurality of photovoltaic modules as described in any one of claims 1-8, which are connected in series and / or in parallel to form an array, and the power flux of the photovoltaic power generation system satisfies 1≤E≤1.82.

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