Semiconductor device

Abstract

A semiconductor device includes a capacitance connection structure including: a first conductive layer; a first dielectric layer in contact with and stacked on the first conductive layer; a second conductive layer in contact with and stacked on the first dielectric layer and separated from the first conductive layer by the first dielectric layer; a second dielectric layer in contact with and stacked on the second conductive layer and separated from the first dielectric layer by the second conductive layer; and a third conductive layer in contact with and stacked on the second dielectric layer and separated from the second conductive layer by the second dielectric layer, the third conductive layer having a columnar portion and a peripheral portion, the columnar portion having a first thickness, and the peripheral portion having a second thickness less than the first thickness.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device, and more particularly to a trench capacitor structure. Background Technology

[0002] Pixels are used to display images on the screen of an electronic device. For example, in the Organic Light-Emitting Diode (OLED) layer of an electronic device, there are multiple pixels within the OLED layer. Each corresponding pixel in the multiple pixels includes multiple sub-pixels. The multiple sub-pixels typically include three sub-pixels: a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. In other words, each corresponding pixel in the multiple pixels includes three sub-pixels, making each corresponding pixel in the multiple pixels a RGB pixel. As electronic devices become smaller (e.g., smaller in overall size and thinner in overall thickness) and the number of complex functions performed simultaneously continues to improve or increase, it becomes increasingly difficult to provide sufficiently high capacitance for the sub-pixels of each corresponding pixel in the multiple pixels. Utility Model Content

[0003] According to some embodiments disclosed herein, a semiconductor device is provided including a capacitor connection structure. The capacitor connection structure includes a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, and a third conductive layer. The first dielectric layer is in contact with and stacked on the first conductive layer. The second conductive layer is in contact with and stacked on the first dielectric layer, and is separated from the first conductive layer by the first dielectric layer. The second dielectric layer is in contact with and stacked on the second conductive layer, and is separated from the first dielectric layer by the second conductive layer. The third conductive layer is in contact with and stacked on the second dielectric layer, and is separated from the second conductive layer by the second dielectric layer. The third conductive layer has a pillar-shaped portion and a peripheral portion, the pillar-shaped portion having a first thickness, and the peripheral portion having a second thickness less than the first thickness.

[0004] According to some embodiments disclosed herein, a semiconductor device is provided. The semiconductor device includes a transistor layer, a first dielectric layer, a first interconnect structure, a second dielectric layer, a capacitor connection structure, a fifth dielectric layer, the second interconnect structure, and a third interconnect structure. The transistor layer contains one or more transistors. The first dielectric layer is located on the transistor layer. The first interconnect structure extends through the first dielectric layer to the transistor layer. The second dielectric layer is located on the first dielectric layer. The capacitor connection structure extends through the second dielectric layer to the first interconnect structure, and the capacitor connection structure is in contact with and coupled to the first interconnect structure. The capacitor connection structure includes a first conductive layer in contact with the first interconnect structure, a third dielectric layer located on the first conductive layer, a second conductive layer located on the third dielectric layer, a fourth dielectric layer located on the second conductive layer, and a third conductive layer located on the fourth dielectric layer. The fifth dielectric layer is located on the third conductive layer and the second conductive layer. The second interconnect structure extends through the fifth dielectric layer, and the second interconnect structure is in contact with and coupled to the second conductive layer. The third interconnect structure extends through the fifth dielectric layer, and the third interconnect structure is in contact with and coupled to the third conductive layer.

[0005] According to some embodiments disclosed herein, a semiconductor device is provided including a capacitor connection structure and an interconnect structure. The capacitor connection structure includes a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, and a third conductive layer. The first dielectric layer is in contact with and stacked on the first conductive layer. The second conductive layer is in contact with and stacked on the first dielectric layer, and is spaced apart from the first conductive layer by the first dielectric layer. The second dielectric layer is in contact with and stacked on the second conductive layer, and is spaced apart from the first dielectric layer by the second conductive layer. The third conductive layer is in contact with and stacked on the second dielectric layer, and is spaced apart from the second conductive layer by the second dielectric layer. The interconnect structure is coupled to the capacitor connection structure. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0007] Figure 1A A simplified image with at least two pixels;

[0008] Figure 1B For along Figure 1A A cross-sectional view of one or more capacitor structures cut by line 1B-1B of at least two sub-pixels shown;

[0009] Figure 2 For along Figure 1A A cross-sectional view of one or more alternative capacitor structures cut by line 1B-1B of at least two sub-pixels shown in the diagram;

[0010] Figure 3A A simplified diagram of at least two pixels according to some embodiments;

[0011] Figure 3B According to some embodiments along Figure 3A A cross-sectional view of one or more capacitor structures cut by line 3B-3B of one of the subpixels of at least two pixels shown;

[0012] Figure 3C According to some embodiments, such as Figure 3B The top view shows one or more capacitor structures that conceal the organic light-emitting diode (OLED) layer.

[0013] Figure 4 A top view of one or more alternative capacitor structures that hide the organic light-emitting diode (OLED) layer according to some embodiments;

[0014] Figure 5 A top view of one or more alternative capacitor structures that hide the organic light-emitting diode (OLED) layer according to some embodiments;

[0015] Figure 6A According to some embodiments, such as Figure 3C An enlarged view of part 6-6 shown;

[0016] Figure 6B According to some embodiments Figure 6A Partial reproduction;

[0017] Figure 6C For representation according to some embodiments, such as Figure 6A and 6B The circuit diagram of the capacitor structure shown is shown.

[0018] Figure 7 For manufacturing according to some embodiments, such as Figures 3A to 3C A flowchart of a method for constructing one or more capacitor structures for the sub-pixels of the shown pixel;

[0019] Figures 8A to 8L For manufacturing according to some embodiments, such as Figures 3A to 3C The method of constructing one or more capacitor structures for the sub-pixels of the shown pixel is as follows: Figure 7 The flowchart shown is a cross-sectional view of each step.

[0020] [Symbol Explanation]

[0021] 1B-1B, 3B-3B: Line

[0022] 6A-6A: Partial

[0023] 100 pixels

[0024] 102a, 102b, 102c: Subpixels

[0025] 104: Transistor layer

[0026] 106: First Surface

[0027] 108: First dielectric layer

[0028] 110: First interconnection structure

[0029] 111: Second Surface

[0030] 112: Second dielectric layer

[0031] 113: Third Surface

[0032] 114a, 114b, 114c: Capacitor Structure

[0033] 116: First capacitor

[0034] 116a: First sidewall

[0035] 116b: Second sidewall

[0036] 116c: Third lateral wall

[0037] 117: Second capacitor

[0038] 118: Third dielectric layer

[0039] 119: Fourth Surface

[0040] 120: Second interconnect structure

[0041] 122: Light-emitting device layer

[0042] 124a: First capacitor / capacitor structure

[0043] 124b: Second capacitor / capacitor structure

[0044] 126, 134: Part One

[0045] 128, 136: Part Two

[0046] 130, 138: Intermediate dielectric layer

[0047] 132: First capacitor

[0048] 140: Second capacitor

[0049] 200 pixels

[0050] 202a, 202b, 202c: Subpixels

[0051] 203: Pixel pitch size

[0052] 204: Transistor layer

[0053] 205: Subpixel pitch size

[0054] 206: First Surface

[0055] 207, 209, 215, 217: Dimensions

[0056] 208: First dielectric layer

[0057] 210: First interconnection structure

[0058] 211: Second Surface

[0059] 212: Second dielectric layer

[0060] 213: Third Surface

[0061] 214: Capacitor Structure

[0062] 216: Lower conductive layer / First conductive layer

[0063] 218: Lower non-conductive layer / dielectric layer

[0064] 219: First dimension

[0065] 220: Intermediate conductive layer

[0066] 221: Second size

[0067] 222: Top non-conductive layer / dielectric layer

[0068] 223: Third size

[0069] 224: Upper conductive layer

[0070] 225: Fourth size

[0071] 226: Third dielectric layer

[0072] 227: Fifth Size

[0073] 228: Fourth Surface

[0074] 229: Sixth Size

[0075] 230: Second interconnect structure

[0076] 231: Upper surface

[0077] 232: Third Interconnect Structure

[0078] 234: Light-emitting device layer / Organic light-emitting diode layer

[0079] 236: First capacitor

[0080] 238: Second capacitor

[0081] 240: First wall surface

[0082] 242: Second wall

[0083] 244: Third wall

[0084] 246: Fourth wall

[0085] 248: First U-shaped section

[0086] 250: Second U-shaped section

[0087] 252: Columnar portion

[0088] 253: Peripheral Area

[0089] 256: Exposed Area

[0090] 258: First side

[0091] 260: Second side

[0092] 261: Third side

[0093] 262: First width

[0094] 264: Fourth side

[0095] 266: Second width

[0096] 268: Fifth Side

[0097] 270: Third width

[0098] 272: Fourth Width

[0099] 300: Flowchart

[0100] 302, 304, 306, 308, 310, 312, 314, 316, 318, 320, 322, 324: Step 325: Width

[0101] 326: Trench

[0102] 327: Surface

[0103] 328: First conductive layer

[0104] 329: Second width

[0105] 330: Sidewall

[0106] 332: First non-conductive layer

[0107] 334: Second conductive layer

[0108] 336: Second non-conductive layer

[0109] 338: Third conductive layer

[0110] 340: Notch

[0111] 344: Upper surface

[0112] 346: Groove

[0113] 348: Stacked Structure

[0114] 350: Area Detailed Implementation

[0115] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements described below are used to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0116] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” and “above” may be used herein to describe the relationship between one element or feature and another, as shown in the figures. In addition to the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0117] Figure 1A A simplified diagram of at least two pixels 100 in a larger pixel array (not shown). Each pixel 100 includes multiple sub-pixels 102a, 102b, and 102c. In other words, each of these pixels 100 has three sub-pixels 102a, 102b, and 102c.

[0118] Figure 1B For sub-pixel 102a ( Figure 1A The leftmost pixel shown is 100. Figure 1A The cross-sectional view of one or more capacitor structures cut by line 1B-1B of the leftmost sub-pixel shown. Although the following discussion will focus on Figure 1A The leftmost sub-pixel 102a is shown, but it is easy to understand that the following discussion will readily apply to it. Figure 1A The other sub-pixels 102a, 102b, and 102c of pixel 100 shown.

[0119] Sub-pixel 102a includes transistor layer 104, transistor layer 104 is Figure 1B The bottommost layer shown. Although not shown, transistor layer 104 includes one or more transistor structures (not shown) and includes a first surface 106. Transistor layer 104 is a front end of line (FEOL) transistor layer. One or more transistor structures (not shown) are packaged within at least one dielectric layer of transistor layer 104. The dielectric layer of the transistor layer is made of at least one of the following materials: undoped silicate glass (USG), silicon nitride (SiN), fluorosilicate glass (FSG), low-K (LK) dielectric, carbon-doped oxygen-rich silicon oxide (ELK), black diamond (BD), or some other suitable or similar dielectric or non-conductive layer.

[0120] A first dielectric layer 108 is stacked on a first surface 106 of a transistor layer 104. The first dielectric layer 108 is in direct contact with the first surface 106 of the transistor layer 104. The first dielectric layer 108 is made of at least one of the following materials: undoped silicate glass (USG), silicon nitride (SiN), fluorosilicate glass (FSG), low-K (LK) dielectric material, carbon-doped oxygen-rich silicon oxide (ELK), black diamond (BD), or some other suitable or similar dielectric or non-conductive layer.

[0121] One or more first interconnect structures 110 are located within the first dielectric layer 108. One or more first interconnect structures 110 extend into and through the first dielectric layer 108 to reach the first surface 106. One or more first interconnect structures 110 are coupled to one or more transistors within the transistor layer 104. One or more first interconnect structures 110 are exposed and accessible at the second surface 111 of the first dielectric layer 108.

[0122] The second dielectric layer 112 is stacked on the second surface 111 of the first dielectric layer 108. The second dielectric layer 112 is in direct contact with the second surface 111 of the first dielectric layer 108. The second dielectric layer 112 includes a third surface 113. The second dielectric layer 112 is made of at least one of the following materials: undoped silicate glass (USG), silicon nitride (SiN), fluorinated silicate glass (FSG), low-K (LK) dielectric material, carbon-doped oxygen-rich silicon oxide (ELK) material, black diamond (BD) material, or some other suitable or similar dielectric or non-conductive layer.

[0123] One or more capacitor structures 114a, 114b, 114c are located within the second dielectric layer 112. The one or more capacitor structures 114a, 114b, 114c extend through the second dielectric layer to one or more first interconnect structures 110, such that each of the one or more capacitor structures 114a, 114b, 114c is coupled to a corresponding first interconnect structure of the one or more first interconnect structures 110. The one or more capacitor structures 114a, 114b, 114c include a first capacitor structure 114a, a second capacitor structure 114b, and a third capacitor structure 114c. The first capacitor structure 114a and the second capacitor structure 114b define a first capacitor 116, and the second capacitor structure 114b and the third capacitor structure 114c define a second capacitor 117. The first capacitor structure 114a, the second capacitor structure 114b, and the third capacitor structure 114c are exposed and accessible from the third surface 113 of the second dielectric layer 112. The first capacitor structure 114a includes one or more first sidewalls 116a, the second capacitor structure 114b includes one or more second sidewalls 116b, and the third capacitor structure 114c includes one or more third sidewalls 116c.

[0124] A third dielectric layer 118 is stacked on the third surface 113 of the second dielectric layer 112. The third dielectric layer 118 is in direct contact with the third surface 113 of the second dielectric layer 112. The third dielectric layer 118 includes a fourth surface 119. The third dielectric layer is made of at least one of the following materials: undoped silicate glass (USG), silicon nitride (SiN), fluorosilicate glass (FSG), low-K (LK) dielectric material, carbon-doped oxygen-rich silicon oxide (ELK), black diamond (BD), or some other suitable or similar dielectric or non-conductive layer.

[0125] One or more second interconnect structures 120 are located within a third dielectric layer 118. The one or more second interconnect structures 120 extend into and through the third dielectric layer to reach one or more capacitor structures 114a, 114b, 114c. The one or more second interconnect structures 120 are coupled to one or more capacitor structures 114a, 114b, 114c within a second dielectric layer 112. In other words, each of the one or more second interconnect structures 120 is coupled to a corresponding capacitor structure of one or more capacitor structures 114a, 114b, 114c. The one or more second interconnect structures 120 are exposed and accessible from a fourth surface 119 of the third dielectric layer 118.

[0126] The light-emitting device layer 122 may be an organic light-emitting diode (OLED) layer, stacked on the fourth surface 119 of the third dielectric layer 118. The light-emitting device layer 122 includes one or more light-emitting devices (i.e., one or more pixels 100) arranged in an array. The one or more pixels 100 within the light-emitting device layer 122 are used to output images on the display of an electronic device (e.g., a smartphone, smart tablet, display, laptop monitor, or some other similar or analog electronic device with a display). Sub-pixels 102a, 102b, 102c and pixel 100 are coupled to one or more second interconnect structures 120. The OLED (not shown) is present within the light-emitting device layer 122. The OLED (not shown) may be located within the dielectric material of the light-emitting device layer 122. The dielectric material of the light-emitting device layer 122 may be at least one of the following materials: undoped silicate glass (USG), silicon nitride (SiN), fluorosilicate glass (FSG), low K (LK) dielectric material, carbon-doped oxygen-rich silicon oxide (ELK), black diamond (BD) material, or some other suitable or similar dielectric or non-conductive layer.

[0127] To improve the resolution or stability of the display current and output more accurate and detailed images, the dimensions of one or more first sidewalls 116a, second sidewalls 116b, and third sidewalls 116c must be increased (e.g., by increasing height and width) to increase the size of the first capacitor 116 and the second capacitor 117, respectively. However, due to the critical dimension (CD), the dimensions of one or more first sidewalls 116a, second sidewalls 116b, and third sidewalls 116c are limited in size, defined by the amount of available space within the electronic device. In other words, when the electronic device is small or thin, the size of one or more first sidewalls 116a, second sidewalls 116b, and third sidewalls 116c can only be made so large because the available space to accommodate such an increase in size is limited. In other words, the first capacitor 116 and the second capacitor 117 are limited by a critical size, which is the size of one or more first sidewalls 116a, second sidewall 116b and third sidewall 116c of the first capacitor structure 114a, the second capacitor structure 114b and the third capacitor structure 114c.

[0128] Figure 2 For sub-pixel 102a ( Figure 1A The leftmost pixel shown is 100. Figure 1A The cross-sectional view of one or more capacitor structures cut by line 1B-1B of the leftmost sub-pixel shown. Although the following discussion will focus on Figure 1A The leftmost sub-pixel 102a is shown, but it is easy to understand that the following discussion will readily apply to it. Figure 1A The other sub-pixels of pixel 100 shown are 102a, 102b, and 120c. Figure 2 The features shown are Figure 1A The features shown are the same or similar. For the sake of simplicity and brevity in this disclosure, Figure 2 Compared to Figure 1A The details of these same or similar features may not be fully reproduced in the following text. Instead, the following about Figure 2 The focus of the discussion will be on relative to Figure 1A Additional or different features.

[0129] Unlike one or more capacitor structures 114a, 114b, 114c, these structures are replaced by one or more capacitor structures 124a, 124b, such as Figure 2 As shown. One or more capacitor structures 124a, 124b include a pair of capacitor structures 124a, 124b, having a first capacitor structure 124a and a second capacitor structure 124b.

[0130] The first capacitor structure 124a includes a first portion 126 located at or near the second surface 111 of the first dielectric layer 108 and a second portion 128 located at or near the third surface 113 of the second dielectric layer 112. An intermediate dielectric layer 130 is located between and sandwiched between the first portion 126 and the second portion 128. When an electrical signal is applied to the first capacitor structure 124a, a first capacitance 132 exists between the first portion 126 and the second portion 128. The intermediate dielectric layer 130 may be a high-K (HK) dielectric material.

[0131] The second capacitor structure 124b includes a first portion 134 located at or near the second surface 111 of the first dielectric layer 108 and a second portion 136 located at or near the third surface 113 of the second dielectric layer 112. An intermediate dielectric layer 138 is located between and sandwiched between the first portion 134 and the second portion 136. When an electrical signal is applied to the second capacitor structure 124b, a second capacitance 140 exists between the first portion 134 and the second portion 136.

[0132] The first capacitor 132 and the second capacitor 140 are controlled or adjusted by applying electrical signals to the first capacitor 124a and the second capacitor 124b. However, to generate high or large capacitance, large electrical signals must be applied to the first capacitor 124a and the second capacitor 124b. Increasing the size of the first capacitor 124a and the second capacitor 124b can reduce some of the power required to generate high or large capacitance, but similar to increasing the size of the first capacitor structure 114a, the second capacitor structure 114b, and the third capacitor structure 114c, the first capacitor 124a and the second capacitor 124b can only be made this large, otherwise they would be limited by critical dimensions. In other words, when the electronic device is small or thin, the first capacitor 116 and the second capacitor 117 can only be made this large due to the available space to accommodate such an increase in size. In other words, the first capacitor 116 and the second capacitor 117 are limited by critical dimensions, which limit the dimensions of one or more first sidewalls 116a, second sidewall 116b and third sidewall 116c of the first capacitor structure 114a, the second capacitor structure 114b and the third capacitor structure 114c.

[0133] As described below, this disclosure aims to provide and manufacture one or more embodiments of one or more capacitor structures for one or more sub-pixels of one or more pixels, in order to prevent or avoid the aforementioned specific embodiments. Figure 1A , Figure 1B , Figure 2The issue under discussion is that, in the semiconductor industry, as display resolutions increase, capacitors with increasingly higher capacitance are required to provide higher resolution displays. Typically, providing capacitors with higher capacitance occupies more space. However, embodiments of one or more capacitor structures for one or more subpixels of one or more pixels allow for a large amount of high capacitance within each subpixel of one or more pixels. Typically, each pixel includes three subpixels (e.g., a red (R) subpixel, a green (G) subpixel, and a blue (B) subpixel), and each subpixel includes one or more capacitor structures for allowing one or more pixels to display images on the display of an electronic system or device (e.g., a smartphone, tablet, monitor, laptop monitor, or other similar or analog displays).

[0134] Figure 3A This is a simplified diagram of at least two pixels 200 in a larger pixel array (not shown). According to some embodiments, each pixel 200 includes a plurality of sub-pixels 202a, 202b, 202c. In other words, each pixel 200 has three sub-pixels 202a, 202b, 202c. Each pixel 200 has a pixel pitch size 203 extending to all sub-pixels 202a, 202b, 202c of the corresponding pixel 200. In this embodiment, the pixel pitch size 203 is equal to 60 micrometers (μm).

[0135] Since each pixel 200 in this embodiment has three sub-pixels 202a, 202b, and 202c, each sub-pixel 202a, 202b, and 202c has a sub-pixel pitch size 205, which is one-third of the pixel pitch size 203. In this embodiment, the sub-pixel pitch size is equal to 20 micrometers (μm).

[0136] In some embodiments, the pixel pitch size 203 is selected from the range of 2 nanometers (nm) to 1000 micrometers (μm), or equal to the upper and lower limits of this range. The subpixel pitch size 205 is selected from the range of 2 nanometers (nm) to 1000 micrometers (μm), or equal to the upper and lower limits of this range.

[0137] Figure 3B According to some embodiments along Figure 3A Neutron Pixel 202a ( Figure 3A The leftmost pixel 200 shown Figure 3A The cross-sectional view of one or more capacitor structures cut by line 3B-3B of the leftmost sub-pixel shown. Although the following discussion will focus on Figure 3A The leftmost sub-pixel 202a is shown, but it is easy to understand that the following discussion will readily apply to it. Figure 3AOther sub-pixels 202a, 202b, and 202c of pixel 200 shown.

[0138] Sub-pixel 202a includes a transistor layer 204, which is... Figure 3B The bottommost layer shown. Although not shown, transistor layer 204 includes one or more transistor structures (not shown) and includes a first surface 206. Transistor layer 204 is a front end of line (FEOL) transistor layer. One or more transistor structures (not shown) are packaged within at least one dielectric layer of transistor layer 204. The dielectric layer of the transistor layer is made of at least one of the following materials: undoped silicate glass (USG), silicon nitride (SiN), fluorosilicate glass (FSG), low-K (LK) dielectric, carbon-doped oxygen-rich silicon oxide (ELK), black diamond (BD), or some other suitable or similar dielectric or non-conductive layer.

[0139] A first dielectric layer 208 is stacked on the first surface 206 of the transistor layer 204. The first dielectric layer 208 is in direct contact with the first surface 206 of the transistor layer 204. The first dielectric layer 208 is made of at least one of the following materials: undoped silicate glass (USG), silicon nitride (SiN), fluorosilicate glass (FSG), low-K (LK) dielectric material, carbon-doped oxygen-rich silicon oxide (ELK), black diamond (BD), or some other suitable or similar dielectric or non-conductive layer.

[0140] One or more first interconnect structures 210 are located within the first dielectric layer 208. One or more first interconnect structures 210 extend into and through the first dielectric layer 208 to reach the first surface 206. One or more first interconnect structures 210 are coupled to one or more transistors within the transistor layer 204. One or more first interconnect structures 210 are exposed and accessible at the second surface 211 of the first dielectric layer 208.

[0141] The second dielectric layer 212 is stacked on the second surface 211 of the first dielectric layer 208. The second dielectric layer 212 is in direct contact with the second surface 211 of the first dielectric layer 208. The second dielectric layer 212 includes a third surface 213. The second dielectric layer 212 is made of at least one of the following materials: undoped silicate glass (USG), silicon nitride (SiN), fluorosilicate glass (FSG), low-K (LK) dielectric material, carbon-doped oxygen-rich silicon oxide (ELK), black diamond (BD), or some other suitable or similar dielectric or non-conductive layer.

[0142] One or more capacitor structures 214 are located within the second dielectric layer 212. The one or more capacitor structures 214 extend through the second dielectric layer 212 such that each of the one or more capacitor structures 214 is coupled to a corresponding first interconnect structure of the first interconnect structure 210. For example... Figure 3B As shown, one or more capacitor structures 214 include eight capacitor structures. In other alternative embodiments, the number of one or more capacitor structures 214 may be greater than or less than eight capacitor structures, depending on the resolution or functionality of one or more pixels 200. Each corresponding capacitor structure of one or more capacitor structures 214 includes a lower conductive layer 216, a lower non-conductive layer 218 (or dielectric layer 218) on the lower conductive layer 216, an intermediate conductive layer 220 on the lower non-conductive layer 218 (or dielectric layer 218), an upper non-conductive layer 222 (or dielectric layer 222) on the intermediate conductive layer 220, and an upper conductive layer 224 on the upper non-conductive layer 222 (or dielectric layer 222). The lower conductive layer 216 of one or more capacitor structures 214 is in direct contact with and coupled to one or more first interconnect structures 210. One or more capacitor structures 214 are located on and protrude outward from the third surface 213 of the second dielectric layer 212. The details of these layers and their interrelationships will be discussed below. Figures 6A to 6C Let's have a more detailed discussion.

[0143] A third dielectric layer 226 is stacked on the third surface 213 of the second dielectric layer 212. The third dielectric layer 226 is in direct contact with the third surface 213 of the second dielectric layer 212. The third dielectric layer 226 includes a fourth surface 228. The third dielectric layer 226 is located on one or more capacitor structures 214, on the third surface 213 of the second dielectric layer 212, and protrudes outward from the third surface 213. The third dielectric layer 226 is made of at least one of the following materials: undoped silicon glass (USG), silicon nitride (SiN), fluorosilicate glass (FSG), low-K (LK) dielectric material, carbon-doped oxygen-rich silicon oxide (ELK), black diamond (BD), or some other suitable or similar dielectric or non-conductive layer.

[0144] One or more capacitor structures 214 have a dimension 217 extending from a corresponding surface of the first interconnect structure 210 to a corresponding uppermost surface of the one or more capacitor structures 214. In at least some embodiments, the dimension 217 is selected from the range of 5 nanometers (nm) to 50 micrometers (μm), or equal to the upper and lower limits of this range.

[0145] One or more second interconnect structures 230 and one or more third interconnect structures 232 are located within a third dielectric layer 226. The one or more second interconnect structures 230 and one or more third interconnect structures 232 extend into and through the third dielectric layer 226 to reach one or more capacitor structures 214. The one or more second interconnect structures 230 are slightly longer than the one or more third interconnect structures 232. The one or more second interconnect structures 230 and one or more third interconnect structures 232 are coupled to one or more capacitor structures 214 within the second dielectric layer 212 and the third dielectric layer 226. In other words, each second interconnect structure of the one or more second interconnect structures 230 is coupled to a corresponding capacitor structure of the one or more capacitor structures 214, and each third interconnect structure of the one or more third interconnect structures 232 is coupled to a corresponding capacitor structure of the one or more capacitor structures 214. One or more second interconnect structures 230 and one or more third interconnect structures 232 are exposed and accessible at the fourth surface 228 of the third dielectric layer 226.

[0146] The light-emitting device layer 234 may be an organic light-emitting diode (OLED) layer, stacked on the fourth surface 228 of the third dielectric layer 226. The light-emitting device layer 234 includes one or more light-emitting devices (i.e., one or more pixels 200) arranged in an array. The one or more pixels 200 within the light-emitting device layer 234 are used to output images on the display of an electronic device (e.g., a smartphone, smart tablet, display, laptop monitor, or some other similar or analog electronic device with a display). Sub-pixels 202a, 202b, 202c and pixel 200 are coupled to one or more second interconnect structures 230 and one or more third interconnect structures 232.

[0147] Figure 3C This is a top view of one or more capacitor structures 214 according to some embodiments, wherein the organic light-emitting diode (OLED) layer 234, the third dielectric layer 226, one or more second interconnect structures 230, and one or more third interconnect structures 232 are as follows: Figure 3B As shown, it is hidden. In, as... Figure 3C In the illustrated embodiment, one or more capacitor structures 214 have a cylindrical profile, such that the upper ends of the one or more capacitor structures 214 have a circular profile. Each of the one or more capacitor structures 214 has a dimension 207. Based on... Figure 3C As shown in the orientation, each capacitor structure in one or more capacitor structures 214 is spaced 209 units apart from its adjacent corresponding capacitor structure in the X direction. Each capacitor structure in one or more capacitor structures 214 is also spaced 215 units apart from its adjacent corresponding capacitor structure.

[0148] exist Figure 3C In one embodiment of the one or more capacitor structures 214 shown, the dimension 207 is equal to 200 nanometers (nm). In one embodiment of the one or more capacitor structures 214, the dimension 209 is equal to 200 nanometers (nm).

[0149] In at least some embodiments, size 207 is selected from the range of 2 nanometers (nm) to 70 micrometers (μm), or equal to the upper and lower limits of this range. In at least some embodiments, size 209 is selected from the range of 2 nanometers (nm) to 70 micrometers (μm), or equal to the upper and lower limits of this range. In at least some embodiments, size 215 is selected from the range of 2 nanometers (nm) to 70 micrometers (μm), or equal to the upper and lower limits of this range.

[0150] Figure 4This is a top view of one or more capacitor structures 214 according to some embodiments, wherein the organic light-emitting diode (OLED) layer 234, the third dielectric layer 226, one or more second interconnect structures 230, and one or more third interconnect structures 232 are as follows: Figure 4 As shown, it is hidden. In, as... Figure 4 In the illustrated embodiment, one or more capacitor structures 214 have a triangular prism profile, such that the upper end of one or more capacitor structures 214 has a triangular profile.

[0151] Figure 5 This is a top view of one or more capacitor structures 214 according to some embodiments, wherein the organic light-emitting diode (OLED) layer 234, the third dielectric layer 226, one or more second interconnect structures 230, and one or more third interconnect structures 232 are as follows: Figure 5 As shown, it is hidden. In, as... Figure 5 In the illustrated embodiment, one or more capacitor structures 214 have a trapezoidal prism profile, such that the upper end of one or more capacitor structures 214 has a trapezoidal profile.

[0152] Figure 6A According to some embodiments, such as Figure 3B The image shows an enlarged view of portion 6A-6A. In other words, Figure 6A for Figure 3B An enlarged view of one or more capacitor structures 214 shown. Figure 6A In the embodiment shown, the first capacitor 236 exists between the lower conductive layer 216 and the middle conductive layer 220, spanning the lower non-conductive layer 218, and the second capacitor 238 exists between the upper conductive layer 224 and the middle conductive layer 220, spanning the upper non-conductive layer 222. Figure 6A The total capacitance of the capacitor structure 214 shown is the sum of the first capacitor 236 and the second capacitor 238, because the first and second capacitors are connected in parallel (see [link]). Figure 6C The circuit diagram of capacitor structure 214 shown is shown.

[0153] The lower conductive layer 216 includes one or more first walls 240, the intermediate conductive layer 220 includes one or more second walls 242 and one or more third walls 244, and the upper conductive layer 224 includes one or more fourth walls 246. The one or more second walls 242 are opposite to the one or more third walls 244. A first capacitor 236 exists between the one or more first walls 240 and the one or more second walls 242, and a second capacitor 238 exists between the one or more third walls 244 and the one or more fourth walls 246.

[0154] The lower conductive layer 216 includes a first U-shaped portion 248 defining a first groove, the intermediate conductive layer 220 includes a second U-shaped portion 250 defining a second groove, and the upper conductive layer 224 includes a columnar portion 252, such that the upper conductive layer 224 has a T-shaped profile. The second U-shaped portion 250 is located within the first groove defined by the first U-shaped portion 248. The columnar portion 252 is located within the second groove defined by the second U-shaped portion 250. The first groove defined by the first U-shaped portion 248 is defined by corresponding first walls of one or more first walls 240. The second groove defined by the second U-shaped portion 250 is defined by corresponding third walls of one or more third walls 244.

[0155] The upper conductive layer 224, including the columnar portion 252, further includes a peripheral portion 253 extending outward from the columnar portion 252. The thickness of the peripheral portion 253 is less than that of the columnar portion 252.

[0156] like Figure 6A The second interconnect structure 230 shown is coupled to the exposed region 256 of the intermediate conductive layer 220. The exposed region 256 is exposed from the upper non-conductive layer 222 and the upper conductive layer 224. In other words, the upper non-conductive layer 222 and the upper conductive layer 224 are not present on the exposed region 256 of the intermediate conductive layer 220. Figure 6A The third interconnect structure 232 shown is coupled to the upper conductive layer 224.

[0157] and Figure 1B The one or more capacitor structures 114a, 114b, 114c shown are Figure 2 Unlike the one or more capacitor structures 124a, 124b shown (where the overall and total capacitance of capacitor structures 114a, 114b, 114c, 124a, 124b are limited due to the critical dimension (CD) problem discussed earlier in this paper), one or more capacitor structures 214 have a higher overall and total capacitance than these corresponding one or more capacitor structures 114a, 114b, 114c. Furthermore, in relation to... Figure 1B The one or more capacitor structures 114a, 114b, 114c shown are Figure 2In the same amount of space, one or more capacitor structures 124a, 124b can be provided with a greater number of capacitor structures 214. Due to the first U-shaped portion 248 of the lower conductive layer 216, the second U-shaped portion 250 of the intermediate conductive layer 220, and the columnar portion 252 of the upper conductive layer 224, one or more capacitor structures 214 have a higher overall or total capacitance relative to one or more capacitor structures 114a, 114b, 114c, 124a, 124b in the same or less space. The first U-shaped portion 248, the second U-shaped portion 250, and the columnar portion 252 allow for the maximization of the dimensions of one or more first walls 240, one or more second walls 242, one or more third walls 244, and one or more fourth walls 246, such that the first capacitor 236 and the second capacitor 238 are higher than the first capacitors 116, 132 and the second capacitors 117, 140, respectively.

[0158] The first U-shaped portion 248, the second U-shaped portion 250, and the columnar portion 252 allow one or more capacitor structures 214 to be smaller than one or more capacitor structures 114a, 114b, 114c, 124a, 124b, thereby enabling a greater number of one or more capacitor structures 214 to be provided within the same amount of space as one or more capacitor structures 114a, 114b, 114c, 124a, 124b. For example, since sub-pixel 202a has a sub-pixel pitch size 205 equal to 20 micrometers (μm), and the size 207 of each capacitor structure 214 is equal to 200 nanometers (nm), the total number of capacitor structures 214 that can be provided within sub-pixel 202a is equal to one hundred, which is greater than when using one or more capacitor structures 114a, 114b, 114c, 124a, 124b (e.g., ...). Figure 1B and Figure 2 The total number of capacitors is shown in the figure. Because one or more capacitor structures 214 have higher capacitance and can provide more capacitor structures within each sub-pixel 202a, 202b, 202c of each pixel 200, when using one or more capacitor structures 114a, 114b, 114c, 124a, 124b, the one or more capacitor structures 214 allow the electronic device to have a more stable and better resolution display. In other words, and in summary, one or more capacitor structures 214 provide higher capacitance, while relative to... Figure 1B and Figure 2The one or more capacitor structures 114a, 114b, 114c, 124a, 124b shown can provide a greater number of capacitor structures within the same space. By having higher capacitance and being able to provide a greater number of one or more capacitor structures 214 in sub-pixel 202a relative to one or more capacitor structures 114a, 114b, 114c, 124a, 124b, the one or more capacitor structures 214 can be used in the display to provide greater stability and functionality.

[0159] The first capacitor 236 ranges from 0.005 pF to 100 F. The second capacitor 238 ranges from 0.005 pF to 100 F. The total capacitance of the capacitor structure is equal to the sum of the first capacitor 236 and the second capacitor 238. In some embodiments, the total capacitance ranges from 0.01 pF to 200 F, or equal to the upper and lower limits of this range.

[0160] The first interconnect structure 210, the second interconnect structure 230, and the third interconnect structure 232 may be made of at least one of the following materials: copper, copper alloy, tungsten, tungsten alloy, or other similar or equivalent conductive materials. The lower conductive layer 216, the intermediate conductive layer 220, and the upper conductive layer 224 may be made of at least one of the following materials: copper, copper alloy, tungsten, tungsten alloy, or other similar or equivalent conductive materials. The lower non-conductive layer 218 and the upper non-conductive layer 222 may be made of at least one high-K (HK) dielectric material selected from the following: SiO2, SiN... x HfSiO4, ZrO2, HfO2, TiO2 or other similar or equivalent high K (HK) dielectric materials.

[0161] Figure 6B for Figure 6A Partial reproduction, to provide information about such Figure 6A Further details of the dimensions of the capacitor structure 214 shown. In other words, relative to... Figure 6A , Figure 6B Only the capacitor structure 214 and the first interconnect structure 210 are reproduced in the middle, while Figure 6B The second interconnect structure 230 and the third interconnect structure 232 are not reproduced in the middle.

[0162] The first dimension 219 is the thickness of the lower conductive layer 216, extending from a corresponding surface of the first interconnect structure 210 to a corresponding first wall of one or more first walls 240. In at least this embodiment, the first dimension 219 is in the range of 0.5 nanometers to 50 micrometers (μm), or equal to the upper and lower limits of this range.

[0163] The second dimension 221 is the thickness of the lower non-conductive layer 218, extending from the first conductive layer 216 to the intermediate conductive layer 220. In at least this embodiment, the second dimension is in the range of 0.5 nanometers (nm) to 50 micrometers (μm), or equal to the upper and lower limits of this range.

[0164] The third dimension 223 is the thickness of the intermediate conductive layer 220, extending from the lower non-conductive layer 218 to the upper non-conductive layer 222. In at least this embodiment, the third dimension is in the range of 0.5 nanometers (nm) to 50 micrometers (μm), or equal to the upper and lower limits of this range.

[0165] The fourth dimension 225 is the thickness of the upper non-conductive layer 222, extending from the intermediate conductive layer 220 to the upper conductive layer 224. In at least this embodiment, the fourth dimension 225 is in the range of 0.5 nanometers (nm) to 50 micrometers (μm), or equal to the upper and lower limits of this range.

[0166] The fifth dimension 227 is the thickness of the columnar portion 252 of the upper conductive layer 224, extending from the end of the columnar portion 252 to the corresponding upper surface of the upper conductive layer 224. The corresponding upper surface 231 of the upper conductive layer 224 faces away from the first interconnect structure 210. In at least this embodiment, the fifth dimension 227 is in the range of 2.5 nanometers (nm) to 250 micrometers (μm), or equal to the upper and lower limits of this range.

[0167] The sixth dimension 229 is the thickness of the upper conductive layer 224, extending from the upper non-conductive layer 222 to the corresponding upper surface 231 of the upper conductive layer 224. The sixth dimension 229 is smaller than the fifth dimension 227. In at least this embodiment, the sixth dimension 229 is in the range of 0.5 nanometers (nm) to 50 micrometers (μm), or equal to the upper and lower limits of this range.

[0168] The columnar portion 252 of the upper conductive layer 224 of the capacitor structure 214 has a fifth dimension 227. The peripheral portion 253 of the upper conductive layer 224 of the capacitor structure 214 has a sixth dimension 229.

[0169] Figure 6B The capacitor structure 214 shown further includes a first side 258 and a second side 260 opposite to the first side 258. A first width 262 extends from the first side 258 to the second side 260. The first width 262 is in the range of 2 nanometers (nm) to 500 micrometers (μm), or equal to the upper and lower limits of this range.

[0170] Figure 6BThe capacitor structure 214 shown further includes a third side 261 and a fourth side 264 opposite to the third side 261. The third side 261 is spaced outward from the first side 258, and the fourth side 264 is spaced outward from the second side 260. A second width 266 extends from the third side 261 to the fourth side 264. The second width 266 is greater than the first width 262. The second width 266 is in the range of 2 nanometers (nm) to 500 micrometers (μm), or equal to the upper and lower limits of this range.

[0171] like Figure 6B As shown, capacitor structure 214 further includes a fifth side 268, which is spaced inwardly from the third side 261. A third width 270 extends from the fifth side 268 to the fourth side 264. The third width 270 is smaller than the second width 266. The third width 270 is in the range of 2 nanometers (nm) to 500 micrometers (μm), or equal to the upper and lower limits of this range.

[0172] like Figure 6B As shown, the fourth width 272 extends from the opposite side or end of the first interconnect structure 210. The fourth width 272 is greater than the first width 262 and less than the second width 266. The fourth width 272 is in the range of 2 nanometers (nm) to 500 micrometers (μm), or equal to the upper and lower limits of this range.

[0173] Figure 7 For manufacturing according to some embodiments, such as Figures 3A to 3C A flowchart 300 illustrates a method for creating one or more capacitor structures 214 for sub-pixel 202a of pixel 200. Flowchart 300 includes multiple steps, including a first step 302, a second step 304, a third step 306, a fourth step 308, a fifth step 310, a sixth step 312, a seventh step 314, an eighth step 316, a ninth step 318, a tenth step 320, an eleventh step 322, and a twelfth step 324.

[0174] Figures 8A to 8L For manufacturing according to some embodiments, such as Figures 3A to 3C The method of one or more capacitor structures 214 of sub-pixel 202a of pixel 200 shown is as follows: Figure 7 The flowchart 300 shown is a cross-sectional view of each step. Details of each step 302, 304, 306, 308, 310, 312, 314, 316, 318, 320, 322, and 324 will be presented in conjunction with... Figures 8A to 8L The details shown will be discussed. As will be easily understood, with Figures 3A to 3C Features that are the same as or similar to those shown will have the same characteristics as Figures 8A to 8L The same or similar component symbols shown. Furthermore, for the sake of simplicity and brevity in this disclosure, detailed descriptions of elements already referred to herein may not be repeated below. Figures 3A to 3C The details of these characteristics are described.

[0175] exist Figure 8A In the first step 302 shown, one or more trenches 326 are formed extending to the third surface 213 of the second dielectric layer 212. The one or more trenches 326 expose corresponding surfaces of one or more first interconnect structures 210. In other words, the one or more first interconnect structures 210 and the one or more trenches 326 generally have a one-to-one correspondence.

[0176] One or more trenches 326 are formed within the second dielectric layer 212 using a technique known in the semiconductor industry. For example, in at least one embodiment, one or more trenches 326 are formed by dry etching of corresponding regions of the second dielectric layer 212. One or more regions of the second dielectric layer 212 are exposed to a photoresist patterning process. For example, after forming a photoresist material around one or more regions along the third surface 213 of the second dielectric layer 212, one or more regions are exposed to a dry etching process in which a chemical etchant is applied to one or more regions of the second dielectric layer 212 to remove corresponding portions of the second dielectric layer 212, thereby forming one or more trenches 326 and exposing corresponding surfaces of one or more first interconnect structures 210 from the second dielectric layer 212. Once the dry etching has occurred and is complete, the photoresist material is removed from the third surface 213 of the second dielectric layer 212, thereby producing a result such as Figure 8A The structure or component shown. For example... Figure 8A As shown, the width 325 of each corresponding trench in one or more trenches 326 is less than the second width 329 of the corresponding surface 327 of each corresponding first interconnect structure in one or more first interconnect structures 210. In at least this embodiment, the width 325 is in the range of 2 nanometers (nm) to 20 micrometers (μm), or equal to the upper and lower limits of this range. In at least this embodiment, the second width 329 is in the range of 2 nanometers (nm) to 20 micrometers (μm), or equal to the upper and lower limits of this range. In other words, the second width 329 is the same as the fourth width 272 discussed above herein.

[0177] In at least one embodiment, the width 325 is equal to the first width 262, such as Figure 6B As shown. In at least one embodiment, the second width 329 is equal to the second width 266, as... Figure 6B As shown.

[0178] After forming one or more trenches 326 in the first step 302, in such a way Figure 8BIn the second step 304 shown, a first conductive layer 328 is formed on the third surface 213 of the second dielectric layer 212, on one or more sidewalls 330 of the second dielectric layer 212 demarcating one or more trenches 326, and on the corresponding surfaces of one or more first interconnect structures 210 exposed by forming one or more trenches 326. The first conductive layer 328 corresponds to... Figure 6A The lower conductive layer 216 of the capacitor structure 214 shown. The first conductive layer 328 is formed by deposition techniques known in the semiconductor industry. For example, the first conductive layer 328 is formed using a physical vapor deposition process (PVD), wherein the first conductive layer 328 is formed thinly along the third surface 213, one or more sidewalls 330, and the corresponding surfaces of one or more first interconnect structures 210.

[0179] After forming the first conductive layer 328 in the second step 304, as follows Figure 8C In the third step 306 shown, a first non-conductive layer 332 is formed on the first conductive layer 328. The first non-conductive layer 332 is formed to cover the entire first conductive layer 328. The first non-conductive layer 332 corresponds to... Figure 6A The lower non-conductive layer 218 is shown. The first non-conductive layer 332 is formed using deposition techniques known in the semiconductor industry. For example, in at least one embodiment, the first non-conductive layer 332 is formed using an atomic layer deposition process (ALD), such that the first non-conductive layer 332 is thinly formed on all surfaces and sidewalls of the entire first conductive layer 328.

[0180] After the third step 306 (forming the first non-conductive layer 332 on the first conductive layer 328), as follows Figure 8D In the fourth step 308 shown, a second conductive layer 334 is formed on the first non-conductive layer 332. The second conductive layer 334 is formed to cover the entire first non-conductive layer 332. The second conductive layer 334 corresponds to... Figure 6A The intermediate conductive layer 220 is shown. The second conductive layer 334 is formed using deposition techniques known in the semiconductor industry. For example, in at least one embodiment, the second conductive layer 334 is formed using a physical vapor deposition process (PVD), wherein the second conductive layer 334 is thinly formed on each surface and sidewall of the entire first non-conductive layer 332.

[0181] After the fourth step 308 (forming the second conductive layer 334 on the first non-conductive layer 332), as follows Figure 8EIn the fifth step 310 shown, a second non-conductive layer 336 is formed on the second conductive layer 334. The second non-conductive layer 336 corresponds to, as shown in the figure, Figure 6A The capacitor structure 214 shown has an upper non-conductive layer 222. A second non-conductive layer 336 is formed using deposition techniques known in the semiconductor industry. For example, in at least one embodiment, the second non-conductive layer 336 is formed using an atomic layer deposition process (ALD), wherein the second non-conductive layer 336 is thinly formed on the corresponding surface and sidewalls of the entire second conductive layer 334.

[0182] After the fifth step 310 of forming the second non-conductive layer 336, in such a way... Figure 8F In the sixth step 312 shown, a third conductive layer 338 is formed on the second non-conductive layer 336. The third conductive layer 338 corresponds to... Figure 6A The capacitor structure 214 shown has an upper conductive layer 224. A third conductive layer 338 is formed using deposition techniques known in the semiconductor industry. For example, in at least one embodiment, the third conductive layer 338 is formed using a physical vapor deposition (PVD) process, wherein the third conductive layer 338 is thinly formed on the corresponding surface and sidewalls of the entire second non-conductive layer 336. Figure 8F As shown, after the formation of the third conductive layer 338, one or more trenches 326 are completely filled by the first conductive layer 328, the first non-conductive layer 332, the second conductive layer 334, the second non-conductive layer 336, and the third conductive layer 338. After the formation of the third conductive layer 338, one or more notches 340 are present in the third conductive layer 338 and aligned with the one or more previously unfilled trenches 326. The one or more notches 340 are formed when the third conductive layer 338 fills the remaining portions of the one or more trenches 326 that were not previously filled by the first conductive layer 328, the first non-conductive layer 332, the second conductive layer 334, and the second non-conductive layer 336.

[0183] After the sixth step 312 of forming the third conductive layer 338, as follows Figure 8GIn the seventh step 314 shown, the third conductive layer 338 is polished and planarized to form the upper surface 344 of the third conductive layer 338. The polishing or planarization of the third conductive layer 338 is performed using techniques known in the semiconductor industry. For example, in at least one embodiment, a chemical mechanical polishing (CMP) process is used to polish or planarize the third conductive layer 338, thereby forming the upper surface 344. When the upper surface 344 of the third conductive layer 338 is formed using the CMP process, one or more notches 340 are removed after sufficient polishing of the third conductive layer 338, thereby making the upper surface 344 flat and smooth.

[0184] After step 314 (grinding and planarizing the third conductive layer 338 to refine and form the upper surface 344 of the third conductive layer 338), as follows Figure 8H In step 316, as shown, the first conductive layer 328, the first non-conductive layer 332, the second conductive layer 334, the second non-conductive layer 336, and the third conductive layer 338 are patterned, thereby removing portions of the first conductive layer 328, the first non-conductive layer 332, the second conductive layer 334, the second non-conductive layer 336, and the third conductive layer 338. Removing these corresponding portions of the first conductive layer 328, the first non-conductive layer 332, the second conductive layer 334, the second non-conductive layer 336, and the third conductive layer 338 results in the formation of recesses 346 around and adjacent to one or more stacked structures 348. One or more stacked structures 348 are formed as portions of one or more capacitor structures 214, as discussed in detail earlier herein. The one or more recesses 346 are formed using one or more forming processes known in the semiconductor industry to define the one or more stacked structures 348. For example, in at least one embodiment, a groove 346 is formed by forming a photoresist material on one or more regions of the upper surface 344 of the third conductive layer 338, the one or more regions corresponding to one or more stacked structures 348 to be formed. Once the photoresist material is formed at one or more regions of the upper surface 344 corresponding to one or more stacked structures 348, the first conductive layer 328, the first non-conductive layer 332, the second conductive layer 334, the second non-conductive layer 336, and the third conductive layer 338 are exposed to a chemical etchant (e.g., during a dry etching process), resulting in the removal of the first conductive layer 328, the first non-conductive layer 332, the second conductive layer 334, the second non-conductive layer 336, and the third conductive layer 338, thereby forming one or more grooves 346 and defining one or more stacked structures 348. Figure 8H As shown, one or more stacked structures 348 have a T-shape.

[0185] After the eighth step 316, in which one or more grooves 346 and one or more stacked structures 348 are formed, as follows Figure 8I In the ninth step 318 shown, one or more regions 350 of the second conductive layer 334 are exposed from the second non-conductive layer 336 and the third conductive layer 338. One or more regions 350 correspond to... Figure 6A The capacitor structure 214 shown has an exposed region 256. One or more regions 350 are formed using one or more process techniques known in the semiconductor industry. For example, in at least one embodiment, one or more regions 350 are formed by applying photoresist material along the upper surface of the third conductive layer 338 of one or more stacked structures 348 to one or more regions, while keeping the respective regions of the third conductive layer 338 corresponding to the one or more regions 350 to be formed exposed. The photoresist material is also formed on the third surface 213 of the second dielectric layer 212. The corresponding regions of the third conductive layer 338 and the second non-conductive layer 336 are exposed to a chemical etchant (e.g., during a dry etching process), thereby removing the corresponding portions of the third conductive layer 338 and the second non-conductive layer 336 at the corresponding regions, thereby forming one or more regions 350 of the second conductive layer 334 exposed from the third conductive layer 338 and the second non-conductive layer 336 of the stacked structure 348. The formation of one or more regions 350 of the second conductive layer 334 results in one or more stacked structures 348 now becoming one or more fully formed and completed capacitor structures 214 (e.g., those disclosed herein). Figure 6A Once one or more regions 350 of the second conductive layer 334 are exposed from the third conductive layer 338 and the second non-conductive layer 336 of the stacked structure 348, the photoresist material is removed, thereby obtaining the following... Figure 8I The structure or component shown.

[0186] After the ninth step 318, where one or more stacked structures 348 are now one or more capacitor structures 214, in such a way... Figure 8J In the tenth step 320 shown, a third dielectric layer 226 is formed on the third surface 213 of the second dielectric layer 212 and on one or more stacked structures 348. The third dielectric layer is formed using deposition techniques known in the semiconductor industry. For example, in at least one embodiment, the third dielectric layer 226 is formed by a physical vapor deposition (PVD) process, wherein the third dielectric layer 226 is formed to completely cover one or more stacked structures 348 and the third surface 213 of the second dielectric layer 212.

[0187] After step 320 (forming a third dielectric layer 226 on the third surface 213 of the second dielectric layer 212 and one or more stacked structures 348), as follows Figure 8KIn the eleventh step 322 shown, one or more second interconnect structures 230 and one or more third interconnect structures 232 are formed, extending into and through the third dielectric layer 226 to reach one or more stacked structures 348 (i.e., one or more capacitor structures 214). The one or more second interconnect structures 230 and third interconnect structures 232 are formed using one or more process technologies known in the semiconductor industry. For example, in at least one embodiment, the one or more second interconnect structures 230 and third interconnect structures 232 are formed by sequentially performing one or more etching and conductive forming techniques. The one or more second interconnect structures 230 are coupled to one or more regions 350 of the second conductive layer 334 of the one or more stacked structures 348, and the one or more third interconnect structures 232 are coupled to the third conductive layer 338 of the one or more stacked structures 348.

[0188] After step 322, which forms the second interconnect structure 230 and the third interconnect structure 232, in the following... Figure 8L In the twelfth step 324 shown, a light-emitting device layer 234 is formed on the fourth surface 228 of one or more second interconnect structures 230, one or more third interconnect structures 232, and the third dielectric layer 226. The light-emitting device layer 234 is formed by performing one or more processes and forming techniques and steps to form one or more sub-pixels 202a, 202b, 202c of the pixel array 200 on the fourth surface 228 of one or more second interconnect structures 230, one or more third interconnect structures 232, and the third dielectric layer 226.

[0189] As discussed in detail earlier in this article, with Figure 1B The one or more capacitor structures 114a, 114b, 114c shown are Figure 2 Unlike the one or more capacitor structures 124a, 124b shown (where the overall and total capacitance of capacitor structures 114a, 114b, 114c, 124a, 124b are limited due to the critical dimension (CD) issue discussed earlier), one or more capacitor structures 214 have a higher overall and total capacitance than the corresponding one or more capacitor structures 114a, 114b, 114c. Furthermore, in relation to... Figure 1B The one or more capacitor structures 114a, 114b, 114c shown are Figure 2In the same amount of space, one or more capacitor structures 124a, 124b can be provided with a greater number of capacitor structures 214. Due to the first U-shaped portion 248 of the lower conductive layer 216, the second U-shaped portion 250 of the intermediate conductive layer 220, and the columnar portion 252 of the upper conductive layer 224, one or more capacitor structures 214 have a higher overall or total capacitance relative to one or more capacitor structures 114a, 114b, 114c, 124a, 124b in the same or less space. The first U-shaped portion 248, the second U-shaped portion 250, and the columnar portion 252 allow for the maximization of the dimensions of one or more first walls 240, one or more second walls 242, one or more third walls 244, and one or more fourth walls 246, such that the first capacitor 236 and the second capacitor 238 are higher than the first capacitors 116, 132 and the second capacitors 117, 140, respectively.

[0190] The first U-shaped portion 248, the second U-shaped portion 250, and the columnar portion 252 allow one or more capacitor structures 214 to be smaller than one or more capacitor structures 114a, 114b, 114c, 124a, 124b, thereby enabling a greater number of one or more capacitor structures 214 to be provided within the same amount of space as one or more capacitor structures 114a, 114b, 114c, 124a, 124b. For example, since sub-pixel 202a has a sub-pixel pitch size 205 equal to 20 micrometers (μm), and the size 207 of each capacitor structure 214 is equal to 200 nanometers (nm), the total number of capacitor structures 214 that can be provided within sub-pixel 202a is equal to one hundred, which is greater than when using one or more capacitor structures 114a, 114b, 114c, 124a, 124b (e.g., ...). Figure 1B and Figure 2 The total number of capacitors is shown in the figure. Because one or more capacitor structures 214 have higher capacitance and can provide more capacitor structures within each sub-pixel 202a, 202b, 202c of each pixel 200, when using one or more capacitor structures 114a, 114b, 114c, 124a, 124b, the one or more capacitor structures 214 allow the electronic device to have a more stable and better resolution display. In other words, and in summary, one or more capacitor structures 214 provide higher capacitance, while relative to... Figure 1B and Figure 2The one or more capacitor structures 114a, 114b, 114c, 124a, 124b shown can provide a greater number of capacitor structures within the same space. By having higher capacitance and being able to provide a greater number of one or more capacitor structures 214 in sub-pixel 202a relative to one or more capacitor structures 114a, 114b, 114c, 124a, 124b, the one or more capacitor structures 214 can be used in the display to provide greater stability and functionality.

[0191] At least one embodiment of the apparatus disclosed herein is generally summarized as including: a transistor layer containing one or more transistors; a first dielectric layer located on the transistor layer; a plurality of first interconnect structures extending into the first dielectric layer to reach the transistor layer and coupled to one or more transistors; a second dielectric layer located on the first dielectric layer; and a plurality of capacitive connection structures extending into the second dielectric layer and passing through the second dielectric layer to reach the first interconnect structures, each corresponding capacitive connection structure being coupled to a corresponding first interconnect structure of the first interconnect structure, and each corresponding capacitive connection structure including: a connection to the first interconnect structure. The first conductive layer is in contact with and stacked on the first interconnect structure; the third dielectric layer is in contact with and stacked on the first conductive layer; the second conductive layer is in contact with and stacked on the third dielectric layer; the fourth dielectric layer is in contact with and stacked on the second conductive layer; and the third conductive layer is in contact with and stacked on the fourth dielectric layer; a fifth dielectric layer is located on the second dielectric layer and the capacitor connection structure; a plurality of second interconnect structures extend into the fifth dielectric layer and pass through the fifth dielectric layer to reach the capacitor connection structure and are coupled to the capacitor connection structure; and a light-emitting device layer is located on the fifth dielectric layer and the plurality of second interconnect structures.

[0192] At least one embodiment of the apparatus disclosed herein generally includes: a transistor layer containing one or more transistors; a first dielectric layer located on the transistor layer; a first interconnect structure extending through the first dielectric layer to the transistor layer; a second dielectric layer located on the first dielectric layer; a capacitor connection structure extending through the second dielectric layer to the first interconnect structure, the capacitor connection structure being in contact with and coupled to the first interconnect structure, the capacitor connection structure including a first conductive layer in contact with the first interconnect structure, a third dielectric layer located on the first conductive layer, a second conductive layer located on the third dielectric layer, a fourth dielectric layer located on the second conductive layer, and a third conductive layer located on the fourth dielectric layer; a fifth dielectric layer located on the third conductive layer and the second conductive layer; a second interconnect structure extending through the fifth dielectric layer, the second interconnect structure being in contact with and coupled to the second conductive layer; and a third interconnect structure extending through the fifth dielectric layer, the third interconnect structure being in contact with and coupled to the third conductive layer.

[0193] At least one embodiment of the semiconductor device manufacturing method disclosed herein is summarized as including the following steps: forming a plurality of trenches through a first dielectric layer to expose a first surface of a plurality of first interconnect structures located within a second dielectric layer containing the first dielectric layer; forming a first conductive layer on a second surface of the first dielectric layer, in the trenches, and on the first surface of the first interconnect structures; forming a third dielectric layer on the first conductive layer; forming a second conductive layer on the third dielectric layer; forming a fourth dielectric layer on the second conductive layer; forming a third conductive layer on the fourth dielectric layer; removing the first conductive layer, the third dielectric layer, the second conductive layer, the fourth dielectric layer, and a first portion of the third conductive layer to define a plurality of capacitor connection structures; removing the fourth dielectric layer of the capacitor connection structures and... The second portion of the third conductive layer exposes the region of the second conductive layer of the capacitor connection structure; a fifth dielectric layer is formed on the first dielectric layer and the capacitor connection structure; a plurality of second interconnect structures are formed, the second interconnect structures extending into and through the fifth dielectric layer to the region of the second conductive layer of the capacitor connection structure, each corresponding second interconnect structure contacting and coupling with a corresponding exposed region in the exposed region of the second conductive layer of the capacitor connection structure; and a plurality of third interconnect structures are formed, the third interconnect structures extending into and through the fifth dielectric layer to the third conductive layer of the capacitor connection structure, each corresponding third interconnect structure coupling to a corresponding third conductive layer in the third conductive layer of the capacitor connection structure.

[0194] In some embodiments, a semiconductor device includes a capacitor connection structure. The capacitor connection structure includes a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, and a third conductive layer. The first dielectric layer is in contact with and stacked on the first conductive layer. The second conductive layer is in contact with and stacked on the first dielectric layer, and is spaced apart from the first conductive layer by the first dielectric layer. The second dielectric layer is in contact with and stacked on the second conductive layer, and is spaced apart from the first dielectric layer by the second conductive layer. The third conductive layer is in contact with and stacked on the second dielectric layer, and is spaced apart from the second conductive layer by the second dielectric layer. The third conductive layer has a pillar-shaped portion and a peripheral portion, the pillar-shaped portion having a first thickness, and the peripheral portion having a second thickness less than the first thickness.

[0195] In some embodiments, the semiconductor device further includes a transistor layer, a third dielectric layer, a first interconnect structure, a fourth dielectric layer, a fifth dielectric layer, a second interconnect structure, and a light-emitting device layer. The transistor layer contains at least one transistor. The third dielectric layer is located on the transistor layer. The first interconnect structure extends into the third dielectric layer to reach the transistor layer and is coupled to at least one transistor, and is coupled to a capacitive connection structure. The fourth dielectric layer is located on the third dielectric layer and extends around the capacitive connection structure. The fifth dielectric layer is located on the fourth dielectric layer and the capacitive connection structure. The second interconnect structure extends into and through the fifth dielectric layer to reach the capacitive connection structure and is coupled to the capacitive connection structure. The light-emitting device layer is located on the fifth dielectric layer and the second interconnect structure, wherein the light-emitting device layer includes a plurality of pixels, each corresponding pixel including at least three sub-pixels. In some embodiments, each pixel has a first pitch selected from a first range of 2 nanometers to 70 micrometers (inclusive), and each sub-pixel has a second pitch selected from a second range of 2 nanometers to 70 micrometers (inclusive). In some embodiments, the capacitive connection structure has a third pitch smaller than the second pitch. In some embodiments, the capacitive connection structure further includes a first capacitor and a second capacitor. The first capacitor exists between a first conductive layer and a second conductive layer, spanning a first dielectric layer. The second capacitor exists between a third conductive layer and a second conductive layer, spanning a second dielectric layer. In some embodiments, the total capacitance of the capacitive connection structure is the sum of the first capacitor and the second capacitor. In some embodiments, the total capacitance ranges from 0.01 picofarads to 200 farads, or equal to the upper and lower limits of the range. In some embodiments, the semiconductor device further includes an interconnect structure coupled to the capacitive connection structure, wherein a region of the second conductive layer of the capacitive connection structure is exposed from the second dielectric layer and the third conductive layer of the capacitive connection structure, and a region of the second conductive layer is coupled to the interconnect structure.

[0196] In some embodiments, a semiconductor device is provided. The semiconductor device includes a transistor layer, a first dielectric layer, a first interconnect structure, a second dielectric layer, a capacitive connection structure, a fifth dielectric layer, a second interconnect structure, and a third interconnect structure. The transistor layer contains one or more transistors. The first dielectric layer is located on the transistor layer. The first interconnect structure extends through the first dielectric layer to the transistor layer. The second dielectric layer is located on the first dielectric layer. The capacitive connection structure extends through the second dielectric layer to the first interconnect structure, and the capacitive connection structure is in contact with and coupled to the first interconnect structure. The capacitive connection structure includes a first conductive layer in contact with the first interconnect structure, a third dielectric layer located on the first conductive layer, a second conductive layer located on the third dielectric layer, a fourth dielectric layer located on the second conductive layer, and a third conductive layer located on the fourth dielectric layer. The fifth dielectric layer is located on the third conductive layer and the second conductive layer. The second interconnect structure extends through the fifth dielectric layer, and the second interconnect structure is in contact with and coupled to the second conductive layer. The third interconnect structure extends through the fifth dielectric layer, and the third interconnect structure is in contact with and coupled to the third conductive layer.

[0197] In some embodiments, the semiconductor device further includes a light-emitting device layer, the light-emitting device being located on the fifth dielectric layer, the second interconnect structure, and the third interconnect structure. In some embodiments, the light-emitting device layer is an organic light-emitting diode layer. In some embodiments, the capacitor connection structure has a cylindrical profile, a triangular prism profile, a rectangular profile, a square profile, or a trapezoidal profile. In some embodiments, a region of the second conductive layer is exposed from the fourth dielectric layer and the third conductive layer, and the region of the second conductive layer is in contact with and coupled to the second interconnect structure. In some embodiments, the first interconnect structure includes a first portion and a second portion, the second portion being wider than the first portion and in contact with and coupled to the first conductive layer; the second interconnect structure includes a third portion and a fourth portion, the fourth portion being wider than the third portion and in contact with and coupled to the second conductive layer; and the third interconnect structure includes a fifth portion and a sixth portion, the sixth portion being wider than the fifth portion and in contact with and coupled to the second conductive layer.

[0198] In some embodiments, a method for manufacturing a semiconductor device is provided. The method includes the following steps: forming a plurality of trenches on a first dielectric layer to expose a plurality of first surfaces of a plurality of first interconnect structures located within a second dielectric layer, the first dielectric layer being located on the second dielectric layer; forming a first conductive layer on a second surface of the first dielectric layer, in the plurality of trenches, and on the plurality of first surfaces of the plurality of first interconnect structures; forming a third dielectric layer on the first conductive layer; forming a second conductive layer on the third dielectric layer; forming a fourth dielectric layer on the second conductive layer; forming a third conductive layer on the fourth dielectric layer; removing the first conductive layer, the third dielectric layer, the second conductive layer, the fourth dielectric layer, and a plurality of first portions of the third conductive layer to define a plurality of capacitive connection structures; removing the fourth dielectric layer and a plurality of second portions of the third conductive layer of the plurality of capacitive connection structures to expose a plurality of regions of the second conductive layer of the plurality of capacitive connection structures; and forming a fifth dielectric layer on the first dielectric layer and the plurality of capacitive connection structures. Multiple second interconnect structures are formed, extending into and through the fifth dielectric layer to multiple regions of the second conductive layer of the multiple capacitive connection structures. Corresponding second interconnect structures of the multiple second interconnect structures contact and couple with corresponding exposed regions of the multiple exposed regions of the second conductive layer of the multiple capacitive connection structures. Multiple third interconnect structures are formed, extending into and through the fifth dielectric layer to the third conductive layer of the multiple capacitive connection structures. Corresponding third interconnect structures of the multiple third interconnect structures couple to corresponding third conductive layers of the multiple capacitive connection structures.

[0199] In some embodiments, the step of forming trenches includes etching a first dielectric layer. In some embodiments, the step of removing a plurality of first portions of a first conductive layer, a third dielectric layer, a fourth dielectric layer, and a third conductive layer to define a plurality of capacitive interconnect structures includes the steps of: defining a first pattern using a photoresist process; and performing dry etching to remove the plurality of first portions. In some embodiments, the step of removing a plurality of second portions of the fourth dielectric layer and the third conductive layer of the plurality of capacitive interconnect structures to expose a plurality of regions of the second conductive layer of the plurality of capacitive interconnect structures includes defining a second pattern using a photoresist process; and performing dry etching to remove the plurality of second portions. In some embodiments, the method further includes forming a light-emitting device layer on a fifth dielectric layer and a plurality of third interconnect structures. In some embodiments, the step of forming a light-emitting device layer on the fifth dielectric layer and the plurality of third interconnect structures further includes the steps of: forming one or more pixels, each pixel having a first pitch selected from a range of 2 nanometers to 100 micrometers (inclusive), and each pixel including three sub-pixels having a second pitch smaller than the first pitch.

[0200] In some embodiments, a semiconductor device is provided including a capacitor connection structure and an interconnect structure. The capacitor connection structure includes a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, and a third conductive layer. The first dielectric layer is in contact with and stacked on the first conductive layer. The second conductive layer is in contact with and stacked on the first dielectric layer, and is spaced apart from the first conductive layer by the first dielectric layer. The second dielectric layer is in contact with and stacked on the second conductive layer, and is spaced apart from the first dielectric layer by the second conductive layer. The third conductive layer is in contact with and stacked on the second dielectric layer, and is spaced apart from the second conductive layer by the second dielectric layer. An interconnect structure is coupled to the capacitor connection structure. In some embodiments, a region of the second conductive layer of the capacitor connection structure is exposed from the second dielectric layer and the third conductive layer of the capacitor connection structure, and a region of the second conductive layer is coupled to the interconnect structure.

[0201] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: A capacitor connection structure includes: First conductive layer; A first dielectric layer is in contact with the first conductive layer and is stacked on the first conductive layer; A second conductive layer is in contact with the first dielectric layer and stacked on the first dielectric layer, and is separated from the first conductive layer by the first dielectric layer; A second dielectric layer, in contact with and stacked on the second conductive layer, and separated from the first dielectric layer by the second conductive layer; and A third conductive layer is in contact with and stacked on the second dielectric layer, and is separated from the second conductive layer by the second dielectric layer. The third conductive layer has a columnar portion and a peripheral portion. The columnar portion has a first thickness, and the peripheral portion has a second thickness that is smaller than the first thickness.

2. The semiconductor device as claimed in claim 1, characterized in that, Further includes: A transistor layer containing at least one transistor; A third dielectric layer is located on the transistor layer; A first interconnect structure extends into the third dielectric layer to reach the transistor layer and is coupled to the at least one transistor, and the first interconnect structure is coupled to the capacitor connection structure; A fourth dielectric layer is located on the third dielectric layer and extends around the capacitor connection structure; A fifth dielectric layer is located on the fourth dielectric layer and the capacitor connection structure; A second interconnect structure extends into and through the fifth dielectric layer to reach the capacitor connection structure and is coupled to the capacitor connection structure. and A light-emitting device layer is located on the fifth dielectric layer and the second interconnect structure, wherein: The light-emitting device layer includes multiple pixels, and each corresponding pixel of the multiple pixels includes at least three sub-pixels.

3. The semiconductor device as claimed in claim 2, characterized in that: Each of the plurality of pixels has a first pitch selected from a first range of 2 nanometers to 70 micrometers; and Each of the plurality of pixels has a second pitch selected from a second range of 2 nanometers to 70 micrometers.

4. The semiconductor device as claimed in claim 3, characterized in that, The capacitor connection structure has a third pitch that is smaller than the second pitch.

5. A semiconductor device, characterized in that, Include: A transistor layer containing one or more transistors; A first dielectric layer is located on the transistor layer; A first interconnect structure extends through the first dielectric layer to the transistor layer; A second dielectric layer is located on the first dielectric layer; A capacitive connection structure extends through the second dielectric layer to the first interconnect structure, the capacitive connection structure being in contact with and coupled to the first interconnect structure, the capacitive connection structure comprising: A first conductive layer is in contact with the first interconnect structure; A third dielectric layer is located on the first conductive layer; A second conductive layer is located on the third dielectric layer; A fourth dielectric layer is located on the second conductive layer; and A third conductive layer is located on the fourth dielectric layer; A fifth dielectric layer is located on the third conductive layer and the second conductive layer; A second interconnect structure extends through the fifth dielectric layer, and the second interconnect structure is in contact with and coupled to the second conductive layer; and A third interconnect structure extends through the fifth dielectric layer, and the third interconnect structure is in contact with and coupled to the third conductive layer.

6. The semiconductor device as claimed in claim 5, characterized in that, It further includes a light-emitting device layer located on the fifth dielectric layer, the second interconnect structure, and the third interconnect structure.

7. The semiconductor device as claimed in claim 6, characterized in that, The light-emitting device layer is an organic light-emitting diode layer.

8. The semiconductor device of claim 5, wherein the capacitor connection structure has a cylindrical profile, a triangular prism profile, a rectangular profile, a square profile, or a trapezoidal profile.

9. A semiconductor device, characterized in that, Include: A capacitor connection structure includes: First conductive layer; A first dielectric layer is in contact with the first conductive layer and is stacked on the first conductive layer; A second conductive layer is in contact with the first dielectric layer and stacked on the first dielectric layer, and is separated from the first conductive layer by the first dielectric layer; A second dielectric layer, in contact with and stacked on the second conductive layer, and separated from the first dielectric layer by the second conductive layer; and A third conductive layer, which is in contact with and stacked on the second dielectric layer, and is separated from the second conductive layer by the second dielectric layer; and An interconnect structure is coupled to the capacitor connection structure.

10. The semiconductor device as claimed in claim 9, characterized in that, A region of the second conductive layer of the capacitor connection structure is exposed from the second dielectric layer and the third conductive layer of the capacitor connection structure, and the region of the second conductive layer is coupled to the interconnect structure.

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