Semiconductor device

Abstract

The present utility model provides a kind of semiconductor device, the trench of the trench capacitor structure of semiconductor device is formed to have uneven plan view width along the length of trench.Uniform plan view width makes that the sidewall of trench has zigzag arrangement, semicircular or arc arrangement, or another non-linear arrangement along the length of trench.This provides greater surface area along the sidewall for the electrode layer and insulator layer of the trench capacitor structure, thereby increasing the capacitance value of the trench capacitor structure.

Description

Technical Field

[0001] This utility model relates to an integrated circuit, and more particularly to a semiconductor device. Background Technology

[0002] A semiconductor device may include one or more capacitor structures in an interconnect layer (e.g., a back-end process (BEOL) region or a back-end region) located above the device layer. The capacitor structures may perform and / or support one or more functions in the semiconductor device, such as memory (e.g., dynamic random access memory (DRAM)), charge decoupling, analog-to-digital (A / D) conversion, and / or other functions. Utility Model Content

[0003] According to the present invention, a semiconductor device includes: one or more dielectric layers and a trench capacitor structure. A trench is formed within the one or more dielectric layers, wherein the trench has a non-uniform top width along its length between a first end and a second opposite end, and wherein the difference between the widest and narrowest portions of the trench along its length is at least about 10% of the average value of the top width along its length. The trench capacitor structure, within the one or more dielectric layers, includes: a bottom electrode layer disposed along the sidewalls and bottom surface of the trench, an insulator on the bottom electrode layer, and a top electrode layer on the insulator layer.

[0004] According to the present invention, a semiconductor device includes: one or more dielectric layers and a trench capacitor structure. The one or more dielectric layers have trenches formed therein, wherein the trenches have a plurality of sidewalls and a bottom surface connecting the plurality of sidewalls, wherein one sidewall of the plurality of sidewalls includes: a first plurality of planar view segments; and a second plurality of planar view segments, alternately arranged along the length of the trench in a first direction, wherein the first plurality of planar view segments and the second plurality of planar view segments are substantially mirror images in a second direction. The trench capacitor structure, within the one or more dielectric layers, includes: a bottom electrode layer disposed along the plurality of sidewalls and the bottom surface of the trench, an insulating layer on the bottom electrode layer, and a top electrode layer on the insulating layer.

[0005] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of the example semiconductor device described in this article.

[0007] Figure 2A-2CThis is a schematic diagram of an example implementation of the trench capacitor structure described in this article.

[0008] Figures 3A-3E This is a schematic diagram illustrating an example embodiment of the semiconductor device described herein.

[0009] Figure 4A-4Q This is a schematic diagram of an example embodiment of the trench capacitor structure described herein.

[0010] Figure 5A-5K This is a schematic diagram of an example embodiment of the trench capacitor structure described herein.

[0011] Figures 6A-6C This is a schematic diagram of an example implementation of the trench capacitor structure described in this article.

[0012] Figure 7A and 7B This is a schematic diagram of an example implementation of the trench capacitor structure described in this article.

[0013] Figure 8 This is a flowchart of an example process related to the formation of the trench capacitor structure described in this article. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or above a second feature may include embodiments in which the first and second features are directly formed in a contact element, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not directly contact each other. Additionally, reference numerals and / or letters may be repeated in various examples of this disclosure. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or architectures discussed.

[0015] Furthermore, for ease of description, this document uses spatially relative terms such as "below," "under," "down," "above," and "upper" to describe the relationship between one component or feature and another, as shown in the figure. In addition to the orientations depicted in the figure, the spatially relative terms are intended to cover different orientations of the device or operation in use. The device may be oriented in other ways (rotated 90° or otherwise), and the spatially relative descriptors used herein can be interpreted accordingly.

[0016] Capacitor structures can include metal-insulator-metal (MIM) structures, where an insulating layer is sandwiched between two conductive electrode layers. The capacitance of a capacitor structure (e.g., the amount of charge it can store) depends directly on the geometry of the conductive electrode layers. The larger the area of ​​the conductive electrode layers, the larger the capacitance. Therefore, increasing the size of the metal electrode layers can increase the capacitance of the capacitor structure.

[0017] Increasing the lateral dimensions of a capacitor structure directly conflicts with semiconductor design principles in the semiconductor industry, which aim to reduce semiconductor device size to achieve lower power consumption, greater operational performance and efficiency, and / or enable semiconductor devices for increasingly smaller applications. Therefore, in some cases, the size of the capacitor structure can be increased in the vertical direction of the semiconductor device so that the capacitor structure extends through multiple layers within the semiconductor device. Deep trench capacitors (DTCs) are a type of capacitor structure formed in a deep trench within a semiconductor device, allowing the electrode and insulating layers to extend along and conform to the contour of the deep trench. This allows for an increase in the area of ​​the conductive electrode layers (thus increasing the capacitance) while minimizing the increase in the lateral dimensions of the capacitor structure.

[0018] In some embodiments described herein, the trenches of the trench capacitor structure (e.g., a DTC structure) are formed with a non-uniform planar width along the length of the trench. The non-uniform planar width results in the sidewalls of the trench having a zigzag, semi-circular, or arcuate arrangement, or another non-linear arrangement, along the length of the trench. This provides a larger surface area along the sidewalls for the electrode and insulating layers of the trench capacitor structure, thereby increasing the capacitance value of the trench capacitor structure. In some embodiments, the trench capacitor structure may include multiple trenches, each having a non-uniform planar width, and the arrangement of the trenches and the sidewalls of the trenches may further increase the capacitance value while maintaining minimal spacing between the trenches and without increasing (or minimally increasing) the lateral coverage area of ​​the trench capacitor structure. Various masking and etching techniques described herein can be used to form the trenches or trench capacitor structures with non-uniform planar widths.

[0019] Figure 1 This is a schematic diagram of an example semiconductor device 100 described herein. Semiconductor device 100 may include a system-on-a-chip (SoC) device, a logic device (e.g., a central processing unit (CPU) or a display adapter processing unit (GPU)), a memory device (e.g., a high-bandwidth memory (HBM) device), an image sensor device (e.g., a complementary metal-oxide-semiconductor (CMOS) image sensor device), and / or another type of semiconductor device.

[0020] Figure 1A cross-sectional view of the semiconductor device 100 is shown. Figure 1 As shown, the semiconductor device 100 may include a device layer 102 and an interconnect layer 104 arranged in the z-direction. For example, the interconnect layer 104 may be located above the device layer 102. As another example, the interconnect layer 104 may be located below the device layer 102.

[0021] Device layer 102 may also be referred to as the front-end region or front-end process (FEOL) region of semiconductor device 100. Interconnect layer 104 may also be referred to as the back-end region or back-end process (BEOL) region of semiconductor device 100, and may include and may include conductive structures arranged to transmit signals and / or provide power distribution throughout semiconductor device 100. In some embodiments, semiconductor device 100 includes interconnect layers 104 above and below device layer 102. A first interconnect layer 104 on a first side of device layer 102 may be used for signal propagation throughout semiconductor device 100, while a second interconnect layer 104 on an opposite second side of device layer 102 may be used for power distribution within semiconductor device 100.

[0022] Device layer 102 includes a substrate 106 of semiconductor device 100. Substrate 106 may correspond to a portion thereon on which a semiconductor wafer of semiconductor device 100 is formed. Substrate 106 may include a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, or another type of substrate. Substrate 106 may extend in the x-direction and / or y-direction of semiconductor device 100 such that the top and bottom surfaces of substrate 106 are substantially orthogonal to the z-direction of semiconductor device 100.

[0023] The integrated circuit device 108 may be contained within and / or on the substrate 106, device layer 102, and semiconductor device 100. The integrated circuit device 108 may include front-end transistor structures (e.g., front-end planar transistor structures, front-end fin field-effect transistor (fin FET) structures, front-end gate-all-around (GAA) transistor structures), pixel sensors, capacitors, resistors, sensors, photosensors, transceivers, transmitters, receivers, optical circuits, and / or other types of front-end semiconductor devices.

[0024] The front-end transistor structure may include multiple source / drain regions, which may correspond to doped regions in the substrate 106 and are separated by a channel region of the substrate 106. In some embodiments, the source / drain regions are doped with a type-1 dopant (e.g., p-type dopant such as boron (B) and / or gallium (gas), n-type dopant such as phosphorus (P) and / or arsenic (As)), and the channel region is doped with a type-2 dopant different from the type-1 dopant. The front-end transistor structure may include a gate structure above and / or around the channel region. The gate dielectric layer of the front-end transistor structure may be contained between the gate structure and the channel region. The gate structure may include a polysilicon gate, a metal gate with a high dielectric constant (high dielectric constant), such as hafnium oxide (HfO). x For example, metal gates (such as HfO2), and / or another type of gate structure.

[0025] A dielectric layer 110 may be included on the substrate 106. The dielectric layer 110 includes an intermediate layer dielectric (interlayer dielectric, etch stop layer (ESL), and / or other types of dielectric layers). The dielectric layer 110 includes a dielectric material that allows for selective etching or protection against etching of portions of the substrate 106 and / or the integrated circuit device 108, and / or electrical isolation of the integrated circuit device 108 in the device layer 102. The dielectric layer 110 includes silicon nitride (Si). x N y ), oxides (e.g., silicon dioxide (SiO2) x The dielectric layer 110 may extend in the x-direction and / or y-direction of the semiconductor device 100. Contacts 112 (e.g., source / drain contacts, gate contacts) may extend through the dielectric layer 110 and between the integrated circuit device 108 and the interconnect layer 104. The contacts may electrically connect the integrated circuit device 108 to the interconnect layer 104. Contacts 112 may include vias, plugs, and / or other types of elongated electrically conductive structures. Contacts 112 may include electrically conductive materials such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), and / or gold (Au).

[0026] The interconnect layer 104 includes a plurality of dielectric layers (e.g., back-end dielectric layers) disposed along a direction generally perpendicular to the top surface of the substrate 106 (e.g., the z-direction). The dielectric layers may include interlayer dielectric (ILD) layers 114 and ESL 116 disposed alternately in the z-direction. The interlayer dielectric layers 114 and ESL 116 may extend in the x-direction and / or y-direction of the semiconductor device 100.

[0027] Interlayer dielectric layers 114 may each comprise a low-dielectric-constant (low-dielectric-constant) oxide material, such as silicon oxide (SiOx) or undoped silicate glass (USG). Additionally and / or alternatively, interlayer dielectric layers 114 may each comprise borosilicate glass (BSG), fluorinated silicate glass (FSG), tetraethyl orthosilicate (TEOS), hydrosilsesquioxane (HSQ), and / or another suitable dielectric material. In some embodiments, interlayer dielectric layers 114 comprise an extremely low dielectric constant (ELK) dielectric material having a dielectric constant less than about 2.5. Examples of ELK dielectric materials include carbon-doped silicon oxide (C-SiOx). x ), amorphous fluorinated carbon (aC) x F y ), parylene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silica (SiOC) polymers, porous HSQ, porous methylsilsesquioxane (MSQ), porous polyarylene ether (PAE), and / or porous silica (SiO2) x )wait.

[0028] ESL116 can each include silicon nitride (Si) x N y The interlayer dielectric layer 114 and ESL 116 may each comprise different dielectric materials to provide etching selectivity, thereby enabling the formation of various structures within the interconnect layer 104. For example, interlayer dielectric layer 114 may each comprise a low dielectric constant dielectric material such as USG, while ESL 116 may each comprise a low dielectric constant dielectric material such as silicon nitride (SiO2). x N y High dielectric constant dielectric materials such as silicon carbide (SiC) or other high dielectric constant materials. Additionally and / or alternatively, two or more ESL116s may comprise different materials. For example, one or more first ESL116s may comprise silicon nitride (SiC). x N y One or more second ESL116 may include silicon carbide (SiC).

[0029] Interconnect layer 104 includes multiple conductive structures disposed in multiple layers. The conductive structures may be electrically coupled and / or physically coupled to one or more integrated circuit devices 108 in device layer 102. The conductive structures provide electrical wiring that enables and / or allows signals and / or power to be supplied to and / or obtained from integrated circuit devices 108.

[0030] The conductive structure may include multiple layers 118a-118e (e.g., vertically alternating) arranged vertically in the z-direction and alternating with multiple layers 120a-120d. Each of layers 118a-118e includes a layer of metallization structure 122, while each of layers 120a-120d includes a layer of interconnection structure 124.

[0031] Layers 118a-118e of the metallization structure 122 can be referred to as M layers. For example, layer 118a of the metallization structure 122 (referred to as metal-0 (M0) layer) can be located at the bottom of the interconnect layer 104 and can be coupled to the device layer 102. Specifically, the M0 layer of the metallization structure 122 can be coupled to the contact 112 (e.g., a contact layer referred to as "CO" layer) of the integrated circuit device 108 of the device layer 102. Layer 118b of the metallization structure 122 (referred to as metal-1 layer (M1) layer) can be located above layer 118a of the metallization structure 122 of the interconnect layer 104, and layer 118c of the metallization structure 122 (referred to as metal-2 layer (M2) layer) can be located above layer 118b of the metallization structure 122, and so on.

[0032] Between layers M0 and M1, there may be a layer 120a of interconnecting structure 124 (called via-1 (V0) layer) to connect layers M0 and M1, and between layers M1 and M2, there may be a layer 120b of interconnecting structure 124 (called via-2 (V1) layer) to connect layers M1 and M2, and so on.

[0033] Metallization structure 122 may include trenches, metallization layers, conductive traces, and / or combinations of other types of conductive structures. Interconnection structure 124 may include vias, interconnects, and / or combinations of other types of conductive structures. In other examples of electrically conductive materials, metallization structure 122 and interconnection structure 124 may include one or more electrically conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof. In some embodiments, one or more substrates may be included in the dielectric layer between interconnection layer 104 and metallization structure 122 and / or within the dielectric layer between interconnection layer 104 and interconnection structure 124. The one or more substrates may include barrier substrates, adhesive substrates, and / or another type of substrate. Examples of materials for the one or more substrates include tantalum nitride (TaN) and / or titanium nitride (TiN).

[0034] In some embodiments, the top layer of the conductive structure (e.g., the top layer of metallization structure 122, the top layer of interconnect structure 124) may be coupled to an interconnect structure on top of the semiconductor device 100. The interconnect structure may include solder balls, solder bumps, contact pads (e.g., planar grid array (LGA) pads), contact pins (e.g., pin grid array (PGA) pins), bottom bump metallization (bump-to-metal) connections, microbumps, ball grid array (BGA) balls, controlled collapse die connection (C4) bumps, and / or other types of interconnect structures. In some embodiments, the top layer of the conductive structure (e.g., the top layer of metallization structure 122, the top layer of interconnect structure 124) may be coupled to a bonding structure, such as a bonding pad and / or a bonding via.

[0035] Further as Figure 1 As shown, a trench capacitor structure 126 is included in the interconnect layer 104 or the semiconductor device 100. The trench capacitor structure 126 may extend through one or more dielectric layers in the interconnect layer 104 and / or may be included in one or more dielectric layers in the interconnect layer 104, such as one or more interlayer dielectric layers 114 and / or one or more ESLs 116. In some embodiments, an integrated circuit device 108 is electrically coupled to the trench capacitor structure 126 to form a memory cell (e.g., a dynamic random access memory (DRAM) cell or another type of capacitor-type memory cell) in the semiconductor device 100. In some embodiments, the trench capacitor structure 126 is configured to provide charge decoupling for one or more integrated circuit devices 108. In some embodiments, the trench capacitor structure 126 is configured to store charge (e.g., photocurrent) for use in the integrated circuit device 108 of the semiconductor device 100 (e.g., a pixel sensor). In some embodiments, the trench capacitor structure 126 is configured to perform another function of the semiconductor device 100.

[0036] The trench capacitor structure 126 may be electrically and / or physically coupled to the bottom contact 128 and electrically and / or physically coupled to the top contact 130 at the top. Alternatively, the trench capacitor structure 126 may be electrically and / or physically coupled to multiple top contacts at the top of the trench capacitor structure 126. In other examples, the bottom contact 128 and the top contact 130 may each include one or more conductive structures in the interconnect layer 104, such as one or more metallized structures 122 and / or one or more interconnect structures 124.

[0037] As mentioned above, with Figure 1 As an example. Other examples may be similar. Figure 1 The descriptions differ from those in the text.

[0038] Figure 2A-2CThis is an example embodiment 200 of the trench capacitor structure 126 described herein. Example embodiment 200 of the trench capacitor structure 126 may be included in the interconnect layer 104 (or another region) of the semiconductor device 100 and / or another semiconductor device. Figure 2A-2C As shown, the trench capacitor structure 126 has a non-uniform width along its length, which increases the surface area of ​​the MIM layer of the trench capacitor structure 126 (and thus increases the capacitance value). Specifically, in example embodiment 200, the trench capacitor structure 126 has a Z-shaped arrangement for its sidewalls, which results in the trench having a repeating pattern of approximately hexagons in the top view of the trench.

[0039] Figure 2A A top view of an example embodiment 200 of the trench capacitor structure 126 is shown. Figure 2A As shown, the trench capacitor structure 126 includes one or more trenches, such as trench 202a, trench 202b, and / or trench 202c, etc. The number of trenches is merely an example, and other trenches or numbers of trench capacitor structures 126 are also within the scope of this disclosure.

[0040] The trench capacitor structure 126 also includes multiple layers extending along the z-direction into trenches 202a-202c and laterally extending in the x-direction and / or y-direction of the semiconductor device 100. These layers include a bottom electrode layer 204, an insulating layer 206 above the bottom electrode layer 204, and a top electrode layer 208 on the insulating layer 206. The bottom electrode layer 204, the insulating layer 206, and the top electrode layer 208 correspond to the MIM structure of the trench capacitor structure 126. Therefore, the trench capacitor structure 126 can also be referred to as a MIM capacitor structure.

[0041] The bottom electrode layer 204 (also referred to as capacitor bottom metal (CBM)) and the top electrode layer 208 (also referred to as capacitor top metal (CTM)) may each comprise one or more electrically conductive metals, one or more materials containing electrically conductive metals, one or more electrically conductive metallic materials, one or more electrically conductive ceramic materials, and / or other types of electrically conductive materials. Examples include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), titanium nitride (TiN), and / or tantalum nitride (TaN). In some embodiments, the bottom electrode layer 204 and the top electrode layer 208 comprise the same material or the same material composition. In some embodiments, the bottom electrode layer 204 and the top electrode layer 208 comprise different materials or different material compositions.

[0042] The insulating layer 206 may include one or more electrically insulating materials. In some embodiments, the insulating layer 206 includes one or more low-dielectric-constant dielectric materials, such as silicon oxide (SiO2). x (e.g., SiO2). In other examples, additionally and / or alternatively, the insulating layer 206 may comprise one or more high dielectric constant dielectric materials such as zirconium oxide (ZrO2). x For example, ZrO2), aluminum oxide (Al) x O y For example, Al2O3), silicon nitride (Si) x N y For example, Si3N4), yttrium oxide (Y). x O y For example, Y₂O₃), lanthanum oxide (LaxOy such as La₂O₃), and / or hafnium oxide (HfO) x (e.g., HfO2). In some embodiments, the insulating layer 206 is a multilayer stack comprising multiple dielectric layers. For example, the insulating layer 206 may comprise a ZrO2 / Al2O3 / ZrO2 (ZAZ) layer stack.

[0043] In an embodiment where the trench capacitor structure 126 includes multiple trenches 202a-202c, the MIM structure of the trench capacitor structure 126 (e.g., bottom electrode layer 204, insulating layer 206, and top electrode layer 208) can extend continuously along the sidewalls 210 and 212 of the trenches 202a-202c, along the bottom surface of the trenches 202a-202c, and between the multiple trenches 202a-202c. The trenches 202a-202c can be laterally arranged in the x-direction and spaced apart in the x-direction. The length of the trenches 202a-202c can extend in the y-direction between the opposite ends 214 and 216 of the 202a-202c. The trench capacitor structure 126 includes multiple trenches 202a-202c, which allows the area of ​​the MIM of the trench capacitor structure 126 (e.g., bottom electrode layer 204, insulating layer 206 and top electrode layer 208) to extend across the multiple trenches 202a-202c, thereby increasing the capacitance value of the trench capacitor structure 126.

[0044] like Figure 2AAs further shown, the ditches 202a-202c have a non-uniform width in the x-direction along their length (e.g., along the y-direction) between the opposing ends 214 and 216. This non-uniform width in the x-direction is achieved by arranging the sidewalls 210 and / or 212 of the ditches 202a-202c in an approximately zigzag pattern, as opposed to the sidewalls 210 and / or 212 extending in a uniform straight line between the opposing ends 214 and 216. Therefore, the width in the x-direction of the ditches 202a transitions between a narrow portion (where the x-direction width is denoted by dimension D1) and a wide portion (where the x-direction width is denoted by dimension D2) between the ends 214 and 216. Similarly, the x-direction width of ditch 202b changes between the narrow portion (where the x-direction width is denoted as dimension D3) and the wide portion (where the x-direction width is denoted as dimension D4) of ditch 20 between ends 214 and 216, and the x-direction width of ditch 202c changes between the narrow portion (where the x-direction width is denoted as dimension D5) and the wide portion (where the x-direction width is denoted as dimension D6) of ditch 202c between ends 214 and 216.

[0045] The transition between the narrowest and widest portions of ditch 202a (and ditches 202b and 202c) can occur within a portion of ditch 202a. For example, ditch 202a (and ditches 202b and 202c) may include multiple top-view portions 218 and multiple top-view portions 220. Top-view portions 218 and 220 may be arranged alternately in the y-direction between ends 214 and 216, thereby forming a repeating pattern in the y-direction. In other words, top-view portions 218 and top-view portions 220 alternate. In the repeating pattern, opposite ends of top-view portions 218 are coupled to the ends of top-view portions 220 at opposite ends of laterally adjacent top-view portions 218. In other words, top-view portions 218 may include a first end (e.g., the x-direction width of ditch 202a corresponds to dimension D1) and an opposite second end (e.g., the x-direction width of ditch 202a corresponds to dimension D1). The first end can be coupled to an end of the first top-view portion 220, and the second end can be coupled to an end of the second top-view portion 220. The top-view portion 220 can be coupled to the top-view portion 218 in the y-direction in a similar manner.

[0046] The connection point between top-view portion 218 and top-view portion 220 may correspond to the inflection point where the x-direction width of ditch 202a-202c changes between increasing and decreasing. The x-direction width of top-view portion 218 may increase along the y-direction from end 214 of ditch 202a-202c to end 216 of ditch 202a-202c. Conversely, the x-direction width of top-view portion 220 may decrease along the y-direction from end 214 of ditch 202a-202c to end 216 of ditch 202a-202c. Top-view portions 218 and 220 may have mirror-image top-view shapes along the x-direction. For example, top-view portion 218 may have an approximately trapezoidal top-view shape, while top-view portion 220 may have an approximately trapezoidal top-view shape, which is a mirror image of the approximately trapezoidal top-view shape of top-view portion 218 along the x-direction. However, other top-view shapes and arrangements are also within the scope of this disclosure.

[0047] Additionally and / or alternatively, dimension D1 (or dimension D3 or dimension D5) may correspond to the widest portion of ditch 202a (or ditch 202b or ditch 202c), dimension D2 (or dimension D3 or dimension D5) may correspond to the narrowest portion of ditch 202a (or ditch 202b or ditch 202c), and ditch 202a (or ditch 202b or ditch 202c) may have additional local inflection points, wherein the width in the x-direction changes between an increase and a decrease in the width in the x-direction, which is less than the width at the widest portion of ditch 202a (or ditch 202b or ditch 202c) and greater than the width at the narrowest portion of ditch 202a (or ditch 202b or ditch 202c).

[0048] In some embodiments, the difference between the widest and narrowest portions of the trench 202a (or 202b or 202c) along the y-direction length of the trench 202a between ends 214 and 216 is at least about 10% of the average value of the top x-direction width (e.g., the x-direction width at the top of the trench) along the length of the trench 202a. This difference in the x-direction width at the top of the trench 202a is at least about 10% of the average value of the top x-direction width along the length of the trench 202a to ensure that the area of ​​the sidewalls 210 and 212 is sufficiently increased on uniformly straight sidewalls to achieve an increase in the capacitance value of the trench capacitor structure 126 (e.g., an increase in capacitance of at least about 2% or more). However, other values ​​are also within the scope of this disclosure.

[0049] In some embodiments, the difference between the widest portion and the narrowest portion of the trench 202a (or trench 202b or trench 202c) along the length of the trench 202a is in the range of approximately 10 nanometers to approximately 40 nanometers. This allows the difference in the x-direction width at the top of the trench 202a to be at least approximately 10% of the average x-direction width at the top along the length of the trench 202a. For example, if the average x-direction width at the top of the trench 202a is approximately 113 nanometers, then the x-direction width at the top of the trench 202a along the length of the trench 202a can range from approximately 103 nanometers to approximately 123 nanometers at the lower end and as high as approximately 73 nanometers to approximately 153 nanometers at the higher end. However, other values ​​and ranges are also within the scope of this disclosure.

[0050] like Figure 2A As further shown, each top view portion 218 may include multiple top view segments 222, and each top view portion 220 may include multiple top view segments 224. Therefore, the sidewalls 210 and 212 of ditch 202a (or ditch 202b or ditch 202c) may each include an alternating arrangement of top view segments 222 and 224 along the length of ditch 202a in the y-direction between opposite ends 214 and 216 of ditch 202a. Top view segments 222 may be mirror images of top view segments 224 in the x-direction. This results in the sidewalls 210 and 212 of ditch 202a (or ditch 202b or ditch 202c) each having an approximately sawtooth top view profile in the y-direction.

[0051] Furthermore, the top view portions 218 and 222 are arranged alternately along the length of the ditch 202a in the y-direction, such that the top view outline of the ditch 202a includes multiple repeating top view portions 226. Each top view portion 226 includes a top view portion 218 and an adjacent top view portion 220. In example embodiment 200, the combination of the top view portion 218 and the adjacent top view portion 220 results in each top view portion 226 having an approximately hexagonal top view shape. Therefore, the top view portion 226 is a convex top view portion with convex sidewalls. The x-direction width of the ditch 202a can increase from the opposite ends of the top view portion 226 toward the middle of the top view portion 226. The ditch 202c can be arranged in a similar manner. However, the ditch 202b between the ditch 202a and the ditch 202c can have a different top view portion arrangement than that of the ditch 202a and the ditch 202c. For example, ditch 202b may include multiple repeating top-view portions 228 having an irregular hexagonal top-view shape. Thus, the top-view portion 228 is a concave top-view portion with concave sidewalls. The x-direction width of ditch 202b may decrease from opposite ends of the top-view portion 228 toward the middle of the top-view portion 228.

[0052] Ditches 202a-202c can be aligned in the y-direction such that the top view portion 218 of ditches 202a and 202c is aligned in the y-direction with the top view portion 220 of ditch 202b. Furthermore, ditches 202a-202c can be aligned in the y-direction such that the top view portion 226 of ditches 202a and 202c is aligned in the y-direction with the top view portion 228 of ditch 202b. Therefore, ditch 202b can have a top view profile that is inverted relative to the top view profiles of ditches 202a and 202c. This results in the sidewalls 212 of ditch 202a and 210 of ditch 202b having substantially the same serrated profile, which allows for maintaining a substantially consistent and uniform distance between ditches 202a and 202b. Furthermore, this results in the sidewalls 212 of ditch 202b and 210 of ditch 202c having approximately the same serrated profile, which makes it possible to maintain a consistent and uniform physical and spatial distance between ditch 202b and 202c.

[0053] Figure 2B Show along Figure 2A A detailed cross-sectional view of an example embodiment 200 of the trench capacitor structure 126 of line AA in the figure. Figure 2C Show along Figure 2A A detailed cross-sectional view of an example embodiment 200 of the line BB trench capacitor structure 126. (See attached image.) Figure 2B and 2C As shown, trenches 202a-202c can extend in the z-direction of semiconductor device 100 and can be included on bottom contact 128. Bottom contact 128 can be included in ILD layer 114a of interconnect layer 104 of semiconductor device 100. Trenches 202a-202c can extend through one or more dielectric layers in interconnect layer 104 of semiconductor device 100, including through ESL 116a, ILD layer 114a, ESL 116b, ILD layer 114c, ESL 116c and / or ILD layer 114d, etc. In some embodiments, trenches 202a-202c may have a high aspect ratio, i.e., the ratio of the depth (or height) of trenches 202a-202c to the lateral width (or critical dimension) of trenches 202a-202c. Therefore, trench capacitor structure 126 can be referred to as DTC structure. In some embodiments, the aspect ratio of ditches 202a-202c may be approximately 10:1 or greater. In some embodiments, ditches 202a-202c may have an aspect ratio ranging from approximately 20:1 to approximately 50:1. However, other values ​​and ranges are also within the scope of this disclosure.

[0054] like Figure 2B and 2CAs further shown, the trench capacitor structure 126 includes a plurality of conformal layers that conform to the cross-sectional profile of trenches 202a-202c. The conformal layers may include a bottom electrode layer 204 and an insulating layer 206 on the bottom electrode layer 204. In some embodiments, an adhesive layer is included between the bottom electrode layer 204 and the sidewalls and bottom surface of trenches 202a-202c. The bottom electrode layer 204 and the insulating layer 206 may each conform to the cross-sectional profile of trenches 202a-202c, such that the bottom electrode layer 204 and the insulating layer 206 conform to the sidewalls and bottom surface of trenches 202a-202c. A top electrode layer 208 may be included on the insulating layer 206. In some embodiments, the top electrode layer 208 is a filler layer that fills the remaining areas of trenches 202a-202c. Alternatively, the top electrode layer 208 may be a conformal layer conforming to the sidewalls and bottom surface of the trenches 202a-202c, and the remaining areas of the trenches 202a-202c may also include a dielectric plug layer or a filler layer. The top contact 130 may be contained above the top electrode layer 208 and in electrical and physical contact with the top electrode layer 208.

[0055] like Figure 2B Further, as shown in the cross-sectional view along line AA, the width of ditch 202a in the x-direction ( Figure 2B The dimension D2) and the x-direction width of the ditch 202c ( Figure 2B The dimension D6 in the middle is greater than the width of the ditch 202b in the x direction ( Figure 2B Dimension D3 in the middle). Distance between ditches 202a and 202b (in the middle). Figure 2B The distance between the dimensions D7 and ditches 202b and 202c is shown in the figure. Figure 2B The distances (denoted as dimension D8) can be approximately the same because ditch 202b has a top view profile that is opposite to that of ditches 202a and 202c. Alternatively, the distances between ditches 202a and 202b and between ditches 202b and 202c can be different. In some embodiments, the distances between ditches 202a and 202b and between ditches 202b and 202c can each be contained within the range of about 145 nanometers to about 175 nanometers. However, other values ​​within this range are also within the scope of this disclosure.

[0056] like Figure 2C Further, as shown in the cross-sectional view along line BB, the width of ditch 202a in the x-direction ( Figure 2C The dimension D1) and the x-direction width of ditch 202c ( Figure 2C The dimension D5 in the middle is smaller than the width of the ditch 202b in the x direction ( Figure 2C The dimension D4 in the middle). The distance between ditches 202a and 202b (in Figure 2BThe dimensions are represented as D9) and the distance between ditches 202b and 202c (in the diagram). Figure 2B The distances (denoted as dimension D10) can be approximately the same because ditch 202b has a top view profile that is opposite to that of ditches 202a and 202c. Alternatively, the distances between ditches 202a and 202b and between ditches 202b and 202c can be different. In some embodiments, the distances between ditches 202a and 202b and between ditches 202b and 202c can each be included in the range of about 145 nanometers to about 175 nanometers. However, other values ​​within this range are also within the scope of this disclosure.

[0057] As mentioned above, with Figure 2A-2C As an example. Other examples may be related to... Figure 2A-2C The descriptions differ. For example, one or more of the ditches 202a-202c may have a non-uniform width in the x-direction, which is generated by the ditch sidewalls having a non-uniform (or non-repeating) serrated profile, or another type of non-uniform profile. Furthermore, the top view profile of one or more of the ditches 202a-202c may have a non-uniform (or non-repeating) top view portion.

[0058] Figures 3A-3E This is an illustrated embodiment 300 that forms the semiconductor device 100 described herein. In some embodiments, combined with Figures 3A-3E One or more of the described semiconductor processing operations may be performed using one or more semiconductor processing equipment, such as deposition equipment, exposure equipment, developing equipment, etching equipment, planarization equipment, ion implantation equipment, wafer / die transport equipment and / or other types of semiconductor processing equipment.

[0059] Turning Figure 3A A substrate 106 is provided. The substrate 106 may be provided in the form of a semiconductor wafer, such as a silicon (Si) wafer, an SOI wafer, and / or other types of semiconductor workpieces. The semiconductor device 100 may be formed on the semiconductor wafer together with other semiconductor devices.

[0060] like Figure 3BAs shown, an integrated circuit device 108 may be formed in and / or on a substrate 106 in a device layer 102 of a semiconductor device 100. One or more semiconductor processing equipment may be used to form one or more portions of the integrated circuit device 108. For example, an ion implantation equipment may be used to dope one or more regions in the substrate 106 with one or more types of dopants to form well regions, implantation regions, and / or other types of doped regions in the substrate 106 for the integrated circuit device 108. As another example, a deposition equipment may be used to perform various deposition operations to deposit layers and / or structures of the integrated circuit device 108, and / or deposit photoresist layers for etching the substrate 106 and / or etching a portion of the deposited layers. As another example, an exposure equipment may be used to expose the photoresist layer to form a pattern in the photoresist layer. As another example, a development equipment may develop the pattern in the photoresist layer. As another example, an etching equipment may be used to etch the substrate 106 and / or etch a portion of the deposited layer to form the integrated circuit device 108. As another example, a planarization machine can be used to planarize portions of the integrated circuit device 108. As another example, an electroplating machine can be used to deposit the metal structure and / or layers of the integrated circuit device 108.

[0061] like Figure 3B As further shown, the deposition equipment is used to deposit the dielectric layer 110 on and / or on the substrate 106 and on and / or on the integrated circuit device 108. The deposition equipment can be used to deposit the dielectric layer 110 using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, and / or another suitable deposition technique. In some embodiments, a planarization equipment can be used to perform a planarization operation, such as chemical mechanical planarization (CMP), to plan the dielectric layer 110 after deposition.

[0062] As further shown in Figures 1 and 3B, contacts 112 of the integrated circuit device 108 can be formed through the dielectric layer 110. Contacts 112 can be formed in grooves within the dielectric layer 110. In some embodiments, a pattern in the photoresist layer is used to etch the dielectric layer 110 to form grooves. In these embodiments, a deposition equipment can be used to form the photoresist layer on the dielectric layer 110. An exposure equipment can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developing equipment can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching equipment can be used to etch the dielectric layer based on the pattern to form grooves. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or another type of etching operation. In some embodiments, a photoresist removal equipment can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique to form grooves based on pattern etching of the dielectric layer 110.

[0063] Contact 112 may be formed in a recess. In some embodiments, contact 112 (e.g., gate contact) is formed on the gate structure of integrated circuit device 108. In some embodiments, contact 112 (e.g., source / drain contact) is formed on the source / drain region of integrated circuit device 108. A deposition equipment may be used to deposit material of contact 112 in the recess using CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. The material of contact 112 may be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and the material of contact 112 is deposited on the seed layer. In some embodiments, after depositing contact 112, a planarization operation (e.g., CMP operation) is performed on contact 112 using a planarization equipment to planarize contact 112 such that the top of contact 112 is substantially coplanar with the top of dielectric layer 110.

[0064] like Figure 3CAs shown, a first portion of the interconnect layer 104 of the semiconductor device 100 is formed above the dielectric layer 110. Alternating layers of ILD layers 114 and ESL 116 are deposited on the first portion of the interconnect layer 104 of the semiconductor device 100 using one or more deposition equipment. Accordingly, the ILD layers 114 and ESL 116 can be arranged in the z-direction of the semiconductor device 100. Each ILD layer 114 and each ESL 116 can be deposited using PVD, ALD, CVD, oxidation, and / or another suitable deposition technique using one or more deposition equipment. In some embodiments, after depositing the ILD layers 114 and / or ESL 116, a planarization equipment can be used to planarize the ILD layers 114 and / or ESL 116.

[0065] like Figure 3C As further shown, various operating equipment can be used, such as deposition equipment, exposure equipment, developing equipment, etching equipment, planarization equipment, electroplating equipment, and / or another semiconductor processing equipment, to perform various operations, thereby forming a metallization structure 122 and an interconnect structure 124 in the first portion of the interconnect layer 104 of the semiconductor device 100. The bottom contact 128 of the trench capacitor structure 126 can also be formed in the first portion of the interconnect layer 104.

[0066] In some embodiments, the first portion of the interconnect layer 104 may be formed as multiple layers. For example, ILD layers 114 and ESL 116 may be formed (e.g., using one or more deposition stations and / or one or more planarization stations), grooves may be formed in and / or through ILD layers 114 and ESL 116 (e.g., using an exposure station, development station, and / or etching station), and a layer 118a (e.g., a MO layer) of the metallization structure 122 may be formed in ILD layers 114 and ESL 116 (e.g., using one or more deposition stations and / or one or more planarization stations). Another ILD layer 114 and another ESL 116 may be formed, and a layer 120a (e.g., a VO layer) of the interconnect structure 124 may be formed in ILD layers 114 and ESL 116. Layers 118b, 118c, 120b, and 120c may be formed in a similar manner.

[0067] One or more deposition equipment can be used to deposit the metallized structure 122, the interconnect structure 124, and / or the bottom contact 128 using PVD, ALD, CVD, electroplating (e.g., electrochemical plating) and / or another suitable equipment. In some embodiments, after depositing the metallized structure 122, the interconnect structure 124, and / or the bottom contact 128, a planarization equipment can be used to planarize the metallized structure 122, the interconnect structure 124, and / or the bottom contact 128.

[0068] like Figure 3D As shown, the trench capacitor structure 126 can be formed in one or more dielectric layers within the interconnect layer 104. The trench capacitor structure 126 can be formed such that the trenches 202a-202c of the trench capacitor structure 126 are located on the bottom contact 128 in the interconnect layer 104. Figure 4A-4Q and Figure 5A-5K An example process for forming the trench capacitor structure 126 is shown and described.

[0069] like Figure 3E As shown, a second portion of the interconnect layer 104 of the semiconductor device 100 is formed over the first portion of the interconnect layer 104, and also includes a portion formed over the trench capacitor structure 126. The second portion of the interconnect layer 104 can be coupled with... Figure 3C The first portion of the interconnect layer 104 described herein is formed in a similar manner. The top contact 130 of the trench capacitor structure 126 may be formed in the second portion of the interconnect layer 104.

[0070] As mentioned above, with Figures 3A-3E As an example. Other examples may be related to... Figures 3A-3E The descriptions are different.

[0071] Figure 4A-4Q This is a schematic diagram of an exemplary embodiment 400 forming the trench capacitor structure 126 described herein. Although combined with... Figure 4A-4Q The described semiconductor processing operations are illustrated in the example embodiment 200 with the trench capacitor structure 126, but in other embodiments, combinations may be performed. Figure 4A-4Q The semiconductor processing operations described are used to form other trench capacitor structures 126 with non-uniform top-view trench widths, for example... Figure 4A-4Q Embodiment 600 of the trench capacitor structure 126 in the middle, and / or Figure 7A and 7B Examples of implementations of the trench capacitor structure 126 include 700, etc.

[0072] In some implementations, combined Figure 4A-4Q The described one or more semiconductor processing operations can be performed using one or more semiconductor processing equipment, such as deposition equipment, exposure equipment, developing equipment, etching equipment, planarization equipment, wafer / die transport equipment, and / or other types of semiconductor processing equipment. In some embodiments, a combination of Figure 4A-4Q The described one or more semiconductor processing operations can be used to form a bond. Figures 3A-3E The process of the described semiconductor device 100 is performed as part of the process.

[0073] like Figure 4AAs shown, a mask layer 402 can be formed on the ILD layer 114d in the interconnect layer 104 of the semiconductor device 100. The mask layer 402 may include a dielectric material, such as silicon oxynitride (SiON) and / or another suitable dielectric material. Additionally and / or alternatively, the mask layer 402 may include a polymer material, such as an organic polymer material and / or an inorganic polymer material.

[0074] The deposition equipment can be used to deposit material for mask layer 402 using CVD, PVD, ALD, electroplating, dispensing, spin coating, and / or other suitable deposition techniques. In some embodiments, after depositing mask layer 402, a planarization equipment is used to perform a planarization operation (e.g., CMP operation) to planarize mask layer 402.

[0075] like Figure 4B and 4C As shown, a pattern 404 can be formed in the mask layer 402. The pattern 404 may include a plurality of openings 406a-406c through the mask layer 402. To form the pattern 404 in the mask layer 402, a photoresist layer can be formed on the mask layer 402 using a deposition equipment (e.g., using spin coating or another suitable deposition technique). In some embodiments, a bottom anti-reflective coating (BARC) is first deposited on the mask layer 402, and then a photoresist layer is deposited on the BARC. An exposure equipment can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development equipment can be used to develop and remove portions of the photoresist layer to expose the pattern 404.

[0076] An etching apparatus can be used to etch the mask layer 402 based on the pattern 40 of the photoresist layer to transfer the pattern to the mask layer 402. In some embodiments, the etching operation includes dry etching operations (e.g., plasma etching operations, gas etching operations), wet chemical etching operations, and / or another type of etching operation. In some embodiments, a photoresist removal apparatus can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique).

[0077] like Figure 4D and 4E As shown, another etching operation is performed to etch through ILD layers 114b, 114c, 114d, ESL 116b, and 116c to form trenches 202a-202c of the trench capacitor structure 126. ILD layers 114b, 114c, 114d, and ESL 116b and 116c are etched through openings 406a-406c in mask layer 402 to form trenches 202a-202c.

[0078] In some implementations, multiple etching operations are performed to form trenches 202a-202c or trench capacitor structures 126. Figure 4D and 4E The trenches 202a-202c are shown after a first etching operation (referred to as the "master etching" or ME operation), which can be performed to form trenches 202a-202c to ESL116a. In other words, the etching of the first etching operation stops at ESL116a, such that ESL116a remains between the bottom of trenches 202a-202c and the underlying bottom contact 128. ESL116a remains above the bottom contact 128 to prevent the bottom contact 128 from being exposed to oxygen and other contaminants that could otherwise cause oxidation of the bottom contact 128.

[0079] In some embodiments, the first etching operation may include a first plasma-type dry etching operation, wherein an oxide etchant such as a fluorine-based etchant (e.g., fluorinated carbon type (CF4)) is used. x (e.g., CF4 gas etchant). In some embodiments, the plasma power level of the first plasma-type dry etching operation is in the range of about 300 watts to about 500 watts. However, other values ​​in this range are also within the range disclosed herein.

[0080] Figure 4F-4H The diagram shows trenches 202a-202c after a second etching operation (referred to as "over-etching" or OE operation), which can be performed after the first etching operation to shape trenches 202a-202c. Specifically, the second etching operation can be performed to create an irregular top-view profile in trenches 202a-202c. This results in one or more trenches 202a-202c having a non-uniform top-view width along the x-direction of the length of the one or more trenches 202a-202c.

[0081] In some embodiments, the second etching operation may include a second plasma-type dry etching operation, wherein an oxide etchant, such as a fluorine-based etchant (e.g., fluorinated carbon type (CF3)), is used. x(e.g., CF4 gas etchant). In some embodiments, the plasma power level of the second plasma-type dry etching operation differs from the plasma power level used in the first plasma-type dry etching operation. Specifically, the second plasma-type dry etching operation can have a higher plasma power level than that used in the first plasma-type dry etching operation. For example, the plasma power level used in the second plasma-type dry etching operation can range from about 1400 watts to about 2000 watts. The use of a higher plasma power level in the second plasma-type dry etching operation allows the trenches 202a-202c to achieve irregular top-view profiles without etching through the mask layer 402 in areas not exposed to the openings 406a-406c. However, other values ​​within this range are also within the scope of this disclosure.

[0082] like Figure 4I-4K As shown, a third etching operation (referred to as "linear removal" or LRM etching operation) is performed to etch through ESL116a at the bottom of trenches 202a-202c, extending trenches 202a-202c through ESL116a and reaching the underlying bottom contact 128. Therefore, after the third etching operation, the bottom contact 128 is exposed through trenches 202a-202c. The third etching operation can use a fluorine-based etchant, such as a fluorocarbon-type gas (CF3). x For example, CF4) etchant is used.

[0083] like Figure 4L-4N As shown, a bottom electrode layer 204 can be deposited on the sidewalls and bottom surface of trenches 202a-202c (which correspond to the top surface of the bottom contact 128). The bottom electrode layer 204 can also be deposited on the ILD layer 114d between adjacent trenches 202a-202c. In some embodiments, the bottom electrode layer 204 is conformally deposited using a deposition apparatus, such that the bottom electrode layer 204 conforms to the contour of the trenches 202a-202c. In some embodiments, conformal CVD, GLONASS, and / or ALD techniques are used to deposit the bottom electrode layer 204.

[0084] like Figure 4L-4N As further shown, an insulating layer 206 can be deposited on the bottom electrode layer 204. Therefore, the insulating layer 206 is deposited on the sidewalls and bottom surface (corresponding to the top surface of the bottom contact 128) of the trenches 202a-202c. The insulating layer 206 can also be deposited on the ILD layer 114d between adjacent trenches 202a-202c. In some embodiments, the insulating layer 206 is conformally deposited using a deposition apparatus, such that the insulating layer 206 conforms to the contour of the trenches 202a-202c. In some embodiments, conformal CVD, FLAG, and / or ALD techniques are used to deposit the insulating layer 206.

[0085] like Figure 4L and 4M As further shown, a top electrode layer 208 can be deposited on the insulating layer 206. The top electrode layer 208 can be deposited such that it fills the remaining area of ​​trenches 202a-202c. The top electrode layer 208 can also be deposited on the ILD layer 114d between adjacent trenches 202a-202c. In some embodiments, the deposition equipment is used to conformally deposit the top electrode layer 208 using PVD, CVD, ALD, and / or other suitable deposition techniques.

[0086] like Figure 4N As shown, additional material can be formed on the ILD layer 114d to encapsulate the trench capacitor structure 126. A deposition apparatus can be used to deposit the additional material on the ILD layer 114d using PVD, ALD, CVD, epitaxial, oxidation, and / or another suitable deposition technique. The additional material on the ILD layer 114d can be deposited in one or more deposition operations. In some embodiments, after the deposition of additional material or the ILD layer 114d, a planarization apparatus can be used to perform a planarization operation (e.g., a CMP operation) to planarize the ILD layer 114d.

[0087] like Figure 4O As shown, a groove 408 can be formed in the top electrode layer 208 of the ILD layer 114d to the trench capacitor structure 126. Therefore, the top electrode layer 208 can be exposed through the groove 408. In some embodiments, a pattern of the photoresist layer is used to etch the ILD layer 114d. In these embodiments, a deposition equipment can be used to form the photoresist layer on the ILD layer 114d. An exposure equipment can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development equipment can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching equipment can be used to etch the ILD layer 114d based on the pattern to form the groove 408. One or more etching operations, etching, and etching of the ILD layer 114d are performed in some embodiments. In some embodiments, one or more etching operations may include dry etching operations (e.g., plasma etching operations, gas etching operations), wet chemical etching operations, and / or another type of etching operation. In some embodiments, a photoresist removal machine can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to pattern-forming the groove 408.

[0088] like Figure 4P and 4QAs shown, a top contact 130 can be formed in the groove 408. A deposition equipment can be used to deposit material for the top contact 130 using CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. The top contact 130 can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and the top contact 130 is deposited on the seed layer. In some embodiments, after depositing the top contact 130, a planarization operation (e.g., CMP operation) is performed using a planarization equipment to planarize the top contact 130.

[0089] As mentioned above, with Figure 4A-4Q As an example. Other examples may be related to... Figure 4A-4Q The descriptions are different.

[0090] Figure 5A-5K This is an example embodiment 500 that forms the trench capacitor structure 126 described herein. Although combined with… Figure 5A-5K The described semiconductor processing operations are illustrated in the example embodiment 200 with the trench capacitor structure 126; however, other operations can be performed with... Figure 5A-5K Other embodiments of the described semiconductor processing operations for forming additional trench capacitor structures 126 with non-uniform top-view trench widths, such as... Figures 6A-6C Exemplary embodiments 600 and / or of the trench capacitor structure 126 in the middle Figure 7A and 7B Exemplary embodiments of the trench capacitor structure 126, such as 700.

[0091] In some implementations, combined Figure 5A-5K The one or more semiconductor processing operations described herein can be performed using one or more semiconductor processing equipment, such as deposition equipment, exposure equipment, developing equipment, etching equipment, planarization equipment, wafer / die transport equipment, and / or other types of semiconductor processing equipment. In some embodiments, combined with Figure 5A-5K The described one or more semiconductor processing operations can be used to form a bond. Figures 3A-3E A part of the process of the described semiconductor device 100.

[0092] like Figure 5A As shown, mask layer 402 can be combined with Figure 4A A similar manner as described is formed on ILD layer 114d.

[0093] like Figures 5B-5D As shown, in combination with Figure 4B and 4CPattern 504 is formed in a similar manner to the described pattern 404 in photomask layer 402. However, pattern 504 includes openings 506a-506c with irregular top-view profiles. Specifically, openings 506a-506c have non-uniform widths along the y-direction. Figure 5C Middle Figure 5B As shown in the cross-sectional view of line AA, opening 506a can have a width in the x-direction (in Figure 5C The dimension (represented as D12) is greater than the width of the opening 506b in the x-direction (in Figure 5C (This is represented as dimension D13). Furthermore, opening 506c in the cross-section along line AA can have a larger x-direction width than opening 506b (dimension D13). Figure 5C (represented as dimension D14).

[0094] like Figure 5D Middle Figure 5B As shown in the cross-sectional view of line BB, opening 506a can have a width in the x-direction (in Figure 5D The x-direction width of opening 506b in the section along line BB (denoted as dimension D16) is smaller than the x-direction width of opening 506b in the section along line BB. The x-direction width of opening 506a in the section along line BB (dimension D15) is smaller than the x-direction width of opening 506a in the section along line AA (dimension D12). Furthermore, the x-direction width of opening 506c (in... Figure 5D The width of opening 506b in the x-direction along the section of line BB (dimension D16) can be smaller than the width of opening 506c in the x-direction along the section of line BB (dimension D17). The width of opening 506c in the x-direction along the section of line BB (dimension D14) is smaller than the width of opening 506b in the x-direction along the section of line AA (dimension D13).

[0095] like Figure 5E-5G As shown, one or more etching operations are performed to etch through ILD layers 114b, 114c, and 114d, and through ESL layers 116a, 116b, and 116c, to form trenches 202a-202c of the trench capacitor structure 126. ILD layers 114b, 114c, and 114d can be etched through openings 506a-506c of mask layer 502, and through ESL layers 116a, 116b, and 116c, to form trenches 202a-202c. Thus, the pattern 504 in mask layer 402 allows trenches 202a-202c to achieve an irregular top-view profile. This irregular top-view profile can correspond to... Figure 2A , 6A The irregular top view profile shown in 7A, and / or may include another irregular top view profile.

[0096] In some implementations, multiple etching operations are performed to form the trenches 202a-202c of the trench capacitor structure 126. For example, a first etching operation (e.g., an ME operation) may be performed to form the trenches 202a-202c to ESL 116a based on the pattern 504 in the mask layer. After the first etching operation, a second etching operation (e.g., an OE operation) may be performed to shape the trenches 202a-202c (e.g., increasing the aspect ratio and / or increasing the verticality of the sidewalls of the trenches 202a-202c). As another example, a third etching operation (e.g., an LRM etching operation) may be performed to etch through the ESL 116a at the bottom of the trenches 202a-202c so that the trenches 202a-202c extend through the ESL 116a and reach the bottom contact 128 below.

[0097] like Figure 5H and 5I As shown, bonding can be achieved on grooves 20a-202c and ILD layer 114d. Figure 4L-4N The bottom electrode layer 204, the insulating layer 206, and the top electrode layer 208 of the trench capacitor structure 126 are formed in a manner similar to that described in the paper.

[0098] like Figure 5J and 5K As shown, a top contact 130 can be formed on the top electrode layer 208. To form the top contact 130, a groove 408 can be formed through the ILD layer 114d to reach the top electrode layer 208, and the top contact 130 can be formed in the groove 408, such as in combination. Figure 4O-4Q As described.

[0099] As mentioned above, with Figure 5A-5K As an example. Other examples may be similar. Figure 5A-5K The descriptions are different.

[0100] Figures 6A-6C This is an example embodiment 600 of the trench capacitor structure 126 described herein. The example embodiment 600 of the trench capacitor structure 126 may include an interconnect layer 104 (or another region) in semiconductor device 100 and / or another semiconductor device. Furthermore, in other embodiments, Figures 6A-6C The trench capacitor structure 126 can be used in combination Figure 4A-4Q Manufactured using the techniques and processes described in 5A-5K (e.g., having a non-uniform top-view width along the length of the trench capacitor structure 126).

[0101] like Figure 6A As shown in the top view, the example embodiment 600 of the trench capacitor structure 126 is similar to... Figure 2AThe illustrated trench capacitor structure 126 is an example embodiment 200. For example, the trench capacitor structure 126 of example embodiment 600 includes trenches 202a-202c, which have a non-uniform width in the x-direction along the length (e.g., along the y-direction) of the trenches 202a-202c between opposite ends 214 and 216. However, in example embodiment 600 of the trench capacitor structure 126, the non-uniform width in the x-direction is achieved by arranging the sidewalls 210 and / or 212 of the trenches 202a-202c in an approximately repeating semi-circular top view pattern, rather than a repeating zigzag pattern. Therefore, the top view segments 222 and 224 are arcuate segments, rather than straight segments. This allows the top view segments 222 and 224 to connect to form a top view portion 226 with an approximately barrel-shaped top view, and also allows the top view segments 222 and 224 to connect to form a top view portion 228 with an approximately hourglass-shaped top view.

[0102] Therefore, the x-direction width of ditch 202a changes between the narrow portion (x-direction width denoted as dimension D18) and the wide portion (x-direction width denoted as dimension D19) of ditch 202a between ends 214 and 216. Similarly, the x-direction width of ditch 202b changes between the narrow portion (x-direction width denoted as dimension D20) and the wide portion (x-direction width denoted as dimension D21) of ditch 202b between ends 214 and 216. The x-direction width of ditch 202c changes between the narrow portion (x-direction width denoted as dimension D22) and the wide portion (x-direction width denoted as dimension D23) of ditch 202c between ends 214 and 216.

[0103] Figure 6B An example embodiment 600 of the trench capacitor structure 126 is shown along... Figure 6A Detailed sectional view of line AA in the diagram. Figure 6C An example embodiment 600 of the channel capacitor structure 126 is shown along... Figure 6A Detailed sectional view of line BB in the diagram.

[0104] like Figure 6B As shown, in the cross-sectional view along line AA, the width of ditch 202a in the x-direction is ( Figure 6B The dimension D19) and the x-direction width of ditch 202c ( Figure 6B The dimension D23 in the middle is greater than the width in the x direction of ditch 202b. Figure 6B (Dimension D20 in the text). Figure 6C As shown, in the cross-sectional view along line BB, the width of ditch 202a in the x-direction is ( Figure 6C The dimension D18) and the x-direction width of ditch 202c ( Figure 6CThe dimension D22 in the middle is smaller than the width in the x direction of ditch 202b. Figure 6C (Dimension D21 in the middle).

[0105] As mentioned above, with Figures 6A-6C As an example. Other examples may be related to... Figures 6A-6C The descriptions differ. For example, one or more of ditches 202a-202c may have a non-uniform (or non-repeating) curved profile resulting in a non-uniform x-direction width, or another type of non-uniform profile. Furthermore, the top view profile of one or more of ditches 202a-202c may have a non-uniform (or non-repeating) top view portion.

[0106] Figure 7A and 7B This is a schematic diagram of an exemplary embodiment 700 of the trench capacitor structure 126 described herein. The exemplary embodiment 700 of the trench capacitor structure 126 may include an interconnect layer 104 (or another region) within a semiconductor device 100 and / or another semiconductor device. Furthermore, in other embodiments, a combination of... Figure 4A-4Q Manufactured using the technology and / or processes described in 5A-5K. Figure 7A and 7B The trench capacitor structure 126 in the middle (e.g., having a non-uniform top view width along the length of the trench capacitor structure 126).

[0107] like Figure 7A As shown in the top view, the example embodiment 700 of the trench capacitor structure 126 is similar to... Figure 2A The example embodiment 200 shows the trench capacitor structure 126. For example, the trench capacitor structure 126 of example embodiment 700 includes trenches 202a-202c, which have a non-uniform width in the x-direction along the length of the trenches 202a-202c (e.g., along the y-direction). However, as... Figure 7A As shown, the sidewalls 210 and 212 of the trenches 202a-202c in the example embodiment 700 of the trench capacitor structure 126 can be wavy and non-uniform, so that each of the trenches 202a-202c has an irregular and non-repeating top view shape.

[0108] In some embodiments, along the length of trench 202a in the y-direction between ends 214 and 216, the difference between the widest and narrowest portions of trench 202a (or trench 202b or trench 202c) is at least about 10% of the average of the top x-direction width (e.g., the x-direction width at the top of the trench) along the length of trench 202a. This difference in x-direction width at the top of trench 202a, at least about 10% of the average of the top x-direction width along the length of trench 202a, ensures that the area of ​​sidewalls 210 and 212 is significantly increased compared to uniform straight sidewalls, thereby increasing the capacitance value of trench capacitor structure 126 (e.g., increasing the capacitance value by at least about 2% or more). The same applies to trenches 202b and 202c. However, other values ​​are also within the scope of this disclosure.

[0109] Figure 7B Show along Figure 7A A cross-sectional view of line CC. (See figure) Figure 7B As shown, each trench 202a-202c is contained on a corresponding bottom contact 128. However, in other embodiments, two or more of the trenches 202a-202c may be connected to the same bottom contact 128. Figure 7B In the sectional view, the width of ditch 202a in the x direction ( Figure 7B The dimension D24) and the x-direction width of ditch 202c ( Figure 7B The dimension D25 in the middle is greater than the width of the ditch 202b in the x direction ( Figure 7B (Dimension D26 in the diagram). However, in other sectional views along ditch 202a-202c, the x-direction width of ditch 202b may be greater than the x-direction width of ditch 202a and / or may be greater than the x-direction width of ditch 202c.

[0110] As mentioned above, with Figure 7A and 7B As an example. Other examples may be related to... Figure 7A and 7B The descriptions are different.

[0111] Figure 8 This is a flowchart of an example process 800 related to the formation of the trench capacitor structure described herein. In some embodiments, Figure 8 One or more process blocks are performed using one or more semiconductor processing equipment, such as deposition equipment, exposure equipment, developing equipment, etching equipment, planarization equipment, ion implantation equipment, annealing equipment, wafer / die transport equipment and / or other types of semiconductor processing equipment.

[0112] like Figure 8As shown, process 800 may include forming a mask layer (block 810) on a dielectric layer of a semiconductor device. For example, one or more semiconductor processing equipment may be used to form a mask layer (e.g., mask layer 402) on a dielectric layer (e.g., ILD layer 114d) of a semiconductor device (e.g., semiconductor device 100), as described herein.

[0113] like Figure 8 As further shown, process 800 may include forming a pattern (block 820) in the mask layer. For example, as described herein, one or more semiconductor processing units may be used to form the pattern (e.g., pattern 404) in the mask layer.

[0114] Further as Figure 8 As shown, process 800 may include performing multiple plasma-based etching operations at different plasma power levels based on a pattern to form trenches in a dielectric layer, such that the trenches have a non-uniform planar width along their length (block 830). For example, as described herein, one or more semiconductor processing equipment may be used to perform multiple plasma-based etching operations at different plasma power levels based on a pattern to form trenches (e.g., trenches 202a-202c) in a dielectric layer, such that the trenches have a non-uniform planar width along their length.

[0115] like Figure 8 As further shown, process 800 may include forming a MIM capacitor structure (block 840) of a semiconductor device in a trench. For example, as described herein, one or more semiconductor processing instruments may be used to form the MIM capacitor structure of the semiconductor device in the trench (e.g., trench capacitor structure 126).

[0116] Process 800 may include other implementations, such as any single implementation or any combination of implementations of one or more other process-related implementations described below and / or other processes described elsewhere herein.

[0117] In a first embodiment, performing multiple plasma-based etching operations includes performing a first plasma-based etching operation at a first plasma power level to form a trench in a dielectric layer, and performing a second plasma-based etching operation at a second plasma power level to shape a top view of the trench such that the trench has a non-uniform top view width along the length of the trench, wherein the second plasma power level is different from the first plasma power level.

[0118] In the second embodiment, the second plasma power level is greater than the first plasma power level, either alone or in combination with the first embodiment.

[0119] In the third embodiment, either alone or in combination with one or more of the first and second embodiments, the first plasma power level includes a range of about 300 watts to about 500 watts, and the second plasma power level includes a range of about 1400 watts to about 2000 watts.

[0120] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, process 800 includes performing another etching operation after a plurality of plasma-based etching operations to etch through the dielectric layer to the conductive structure (e.g., bottom contact 128), wherein forming the MIM capacitor structure includes forming a bottom electrode layer (e.g., bottom electrode layer 204) on the conductive structure.

[0121] In the fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the ditch includes a plurality of first portions with increasing top view width (e.g., top view portion 226 whose width increases from opposite ends of top view portion 226 to the middle of top view portion 226) and a plurality of second portions with decreasing top view width (e.g., top view portion 228 whose width decreases from opposite ends of top view portion 228 to the middle of top view portion 228).

[0122] In the sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, the difference between the widest part and the narrowest part of the ditch along the length of the ditch includes a range of about 10 nanometers to about 40 nanometers.

[0123] although Figure 8 The example block for process 800 is shown, but in some embodiments, process 800 may include... Figure 8 The depiction may include additional blocks, fewer blocks, different blocks, or blocks with different arrangements. Alternatively, two or more blocks in process 800 can be executed in parallel.

[0124] In this manner, the trenches of the trench capacitor structure are formed with a non-uniform planar width along the length of the trench. The non-uniform planar width allows the sidewalls of the trenches to have a zigzag, semi-circular, or arcuate arrangement, or another non-linear arrangement along the length of the trench. This provides a larger surface area along the sidewalls for the electrode and insulating layers of the trench capacitor structure, thereby increasing the capacitance value of the trench capacitor structure. In some embodiments, the trench capacitor structure may include multiple trenches, each having a non-uniform planar width, and the arrangement of the trenches and the arrangement of the sidewalls further increases the capacitance value while keeping the spacing between the trenches to a minimum and not increasing (or minimally increasing) the lateral coverage area of ​​the trench capacitor structure. Various masking and etching techniques described herein can be used to form the trenches of the trench capacitor structure with a non-uniform planar width.

[0125] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes one or more dielectric layers. A trench is included in the one or more dielectric layers and has a non-uniform top width along the length of the trench between a first end and a second opposing end. The difference between the widest and narrowest portions of the trench along its length is at least about 10% of the average top width along the length of the trench. The trench capacitor structure includes a bottom electrode layer along the sidewalls and bottom surface of the trench, an insulating layer on the bottom electrode layer, and a top electrode layer on the insulating layer.

[0126] In some embodiments, the difference between the widest portion and the narrowest portion of the trench along the length of the trench includes a range of about 10 nanometers to about 40 nanometers. In some embodiments, the trench includes a first plurality of top-view portions along the length of the trench and a second plurality of top-view portions alternating with the first plurality of top-view portions. In some embodiments, a first end of a first top-view portion of the first plurality of top-view portions is laterally adjacent to a second top-view portion of the plurality of second plurality of top-view portions; and a second end of a first top-view portion opposite to the first end of the first top-view portion is laterally adjacent to a third top-view portion of the second plurality of top-view portions. In some embodiments, the top width of the trench at the first end of the first top-view portion is greater than the top width of the trench at the second end of the first top-view portion. In some embodiments, the second end of the first top view portion is a third end laterally adjacent to the third top view portion; wherein the fourth end of the third top view portion opposite to the third end of the third top view portion is laterally adjacent to the fourth top view portion of the first plurality of top view portions; and wherein the top width of the ditch at the fourth end of the third top view portion is greater than the top width of the ditch at the third end of the third top view portion. In some embodiments, the first sidewall of the ditch includes a serrated top view pattern along the length of the ditch; and wherein the ditch capacitor structure further includes: other ditches adjacent to the ditch, wherein the other ditches have second sidewalls adjacent to the first sidewalls of the ditch, and wherein the second sidewalls have the same serrated top view pattern as the first sidewalls.

[0127] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes one or more dielectric layers. A trench is included in the one or more dielectric layers and has a bottom surface with a plurality of sidewalls connected to the plurality of sidewalls. The sidewalls include a first plurality of planar view segments and a second plurality of planar view segments arranged alternately along the length of the trench in a first direction, wherein the first plurality of planar view segments and the second plurality of planar view segments are mirror images in a second direction. The trench capacitor structure includes a bottom electrode layer along the plurality of sidewalls and located on the bottom surface of the trench, an insulating layer on the bottom electrode layer, and a top electrode layer on the insulating layer.

[0128] In some embodiments, the first plurality of top-view segments and the second plurality of top-view segments are arranged in a zigzag top-view pattern in the first direction. In some embodiments, the first plurality of top-view segments and the second plurality of top-view segments are arranged in a repeating semi-circular top-view pattern in the first direction. In some embodiments, the trench includes a plurality of arcuate top-view portions arranged along the length of the trench. In some embodiments, the trench capacitor structure further includes: other trenches adjacent to the trench, wherein the other trenches include a plurality of concave top-view portions arranged along the length of the other trenches. In some embodiments, the arcuate top-view portions of the plurality of convex top-view portions are substantially aligned with the concave top-view portions of the plurality of concave top-view portions in the second direction.

[0129] The terms "approximately" and "substantially" can mean that a given quantity of value varies within a range of 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and are not intended to be limiting. It should be understood that the terms "approximately" and "substantially" can refer to a percentage of the value of a given quantity disclosed herein.

[0130] Several features of the embodiments have been summarized above to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to obtain the embodiments described herein, achieving the same purposes and / or the same advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure.

[0131] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A semiconductor device, characterized in that, include: One or more dielectric layers, in which trenches are formed, The ditch has a non-uniform top width along its length between a first end and a second opposite end, and The difference between the widest and narrowest parts of the ditch along its length is at least 10% of the average value of the top width along its length. as well as A trench capacitor structure, comprising, within one or more dielectric layers: A bottom electrode layer is provided along the sidewalls and bottom surface of the trench; An insulating layer is placed on the bottom electrode layer; and The top electrode layer is located on the insulating layer.

2. The semiconductor device according to claim 1, characterized in that, The difference between the widest part and the narrowest part of the ditch along the length of the ditch is in the range of 10 nanometers to 40 nanometers.

3. The semiconductor device according to claim 1, characterized in that, The ditch includes a first plurality of top-view portions along the length of the ditch and a second plurality of top-view portions alternating with the first plurality of top-view portions.

4. The semiconductor device according to claim 3, characterized in that, Wherein, the first end of the first top-view portion of the plurality of top-view portions is laterally adjacent to the second top-view portion of the plurality of second top-view portions; and The second end of the first top-view portion, which is opposite to the first end of the first top-view portion, is laterally adjacent to the third top-view portion of the second plurality of top-view portions.

5. The semiconductor device according to claim 4, characterized in that, The top width of the ditch at the first end of the first top view portion is greater than the top width of the ditch at the second end of the first top view portion.

6. The semiconductor device according to claim 4, characterized in that, The second end in the first top view portion is the third end that is laterally adjacent to the third top view portion; The fourth end of the third top-view portion, which is opposite to the third end of the third top-view portion, is laterally adjacent to the fourth top-view portion of the first plurality of top-view portions; and The top width of the ditch at the fourth end of the third top view portion is greater than the top width of the ditch at the third end of the third top view portion.

7. The semiconductor device according to claim 1, characterized in that, The first sidewall of the ditch includes a sawtooth top view pattern along the length of the ditch; as well as The trench capacitor structure further includes: Other ditches, adjacent to the aforementioned ditches The other ditches have a second sidewall adjacent to the first sidewall of the ditch, and The second sidewall has the same serrated top view pattern as the first sidewall.

8. A semiconductor device, characterized in that, include: One or more dielectric layers, in which trenches are formed, The ditch has multiple sidewalls and a bottom surface connecting the multiple sidewalls. One of the plurality of sidewalls includes: The first multiple overhead view segments; and The second plurality of overhead view segments are arranged alternately along the length of the ditch in the first direction. Wherein the first plurality of top-view segments and the second plurality of top-view segments are substantially mirror images in the second direction; and A trench capacitor structure, comprising, within one or more dielectric layers: A bottom electrode layer is disposed along the plurality of sidewalls and the bottom surface of the trench; An insulating layer is placed on the bottom electrode layer; and The top electrode layer is located on the insulating layer.

9. The semiconductor device according to claim 8, characterized in that, The first plurality of top-view segments and the second plurality of top-view segments are arranged in a sawtooth top-view pattern in the first direction.

10. The semiconductor device according to claim 8, characterized in that, The first plurality of top-view segments and the second plurality of top-view segments are arranged in a repeating semi-circular top-view pattern in the first direction, or the ditch includes a plurality of arc-shaped top-view portions arranged along the length of the ditch.

Images