A 2P2M wafer-level packaging structure based on PI insulating layer enhancement

Abstract

This invention discloses a 2P2M wafer-level packaging structure based on a PI insulating layer, relating to the field of semiconductor technology. It includes a wafer substrate layer, the top surface of which is coated with a first polyimide insulating layer. A first UBM layer is formed on the top of the first polyimide insulating layer via physical vapor deposition. A first metal interconnect layer is formed on the top of the first UBM layer via electroplating. A second polyimide insulating layer is coated on the top surface of the first metal interconnect layer. A second UBM layer is formed on the top of the second polyimide insulating layer via physical vapor deposition. This invention, by employing a specially formulated photosensitive PI material, optimized interface processing technology, and an innovative stepped curing method, effectively solves the stress management and reliability problems of multilayer structures while increasing interconnect density. This technology is particularly suitable for advanced packaging applications requiring high I / O density, excellent high-frequency performance, and long-term thermal stability.

Description

Technical Field

[0001] This utility model specifically relates to the field of semiconductor technology, and specifically to a 2P2M wafer-level packaging structure based on PI insulating layer enhancement. Background Technology

[0002] As semiconductor devices evolve towards higher performance, miniaturization, and higher integration, wafer-level packaging (WLP) faces numerous challenges. Traditional 1P1M (single-layer polymer + single-layer metal) packaging structures are increasingly failing to meet the demands of advanced applications such as 5G communication, artificial intelligence, and high-performance computing in terms of I / O density, high-frequency performance, and thermal stability. Dielectric materials commonly used in existing technologies, such as benzocyclobutene (BCB), suffer from inherent defects such as high dielectric constant (K > 3.9) and insufficient thermal stability (long-term operating temperature < 200℃), severely restricting further improvements in packaging performance.

[0003] Polyimide (PI) materials are considered ideal alternative materials due to their excellent dielectric properties (K=2.9-3.5), outstanding thermal stability (>350℃), and good mechanical strength. However, existing PI-based packaging technologies still face the following technical bottlenecks: First, single-layer PI structures are difficult to achieve high-density interconnect requirements; second, multi-layer PI stacking is prone to stress accumulation, leading to wafer warpage (>100µm) and interface delamination; third, insufficient metal / PI interface adhesion affects long-term reliability; and finally, the patterning process of traditional non-photosensitive PI is complex and difficult to meet the processing requirements of micro-interconnects (<5µm). Utility Model Content

[0004] The purpose of this invention is to provide a 2P2M wafer-level packaging structure based on PI insulation layer reinforcement. By using a specially formulated photosensitive PI material, optimized interface processing technology, and innovative stepped curing method, the interconnect density is improved while effectively solving the stress management and reliability problems of multilayer structures, thereby addressing the aforementioned issues in the background technology.

[0005] To achieve the above objectives, this utility model provides the following technical solution: A 2P2M wafer-level packaging structure based on PI insulating layer reinforcement includes a wafer substrate layer. The top surface of the wafer substrate layer is coated with a first polyimide insulating layer, and the top of the first polyimide insulating layer is formed by physical vapor deposition to form a first UBM layer. The top of the first UBM layer is formed by electroplating to form a first metal interconnect layer, and the top surface of the first metal interconnect layer is coated with a second polyimide insulating layer. The top of the second polyimide insulating layer is formed by physical vapor deposition to form a second UBM layer, and the top of the second UBM layer is connected to a second metal interconnect layer.

[0006] As a further technical solution of this utility model, an aluminum pad is provided on the surface of the wafer substrate layer, and the first polyimide insulating layer is coated on the surface of the aluminum pad; As a further technical solution of this utility model, the first polyimide insulating layer and the second polyimide insulating layer are respectively coated with aluminum pads and the first metal interconnect layer, and the first through hole is formed by photolithography and curing process; As a further technical solution of this utility model, the curing process is carried out in a nitrogen atmosphere with an oxygen content of less than 10% ppm, and the temperature is raised in stages. The three temperatures are 80℃, 200℃ and 300℃ respectively, and the processing time is three hours. As a further technical solution of this utility model, the first metal interconnect layer is an RDL layer, which is prepared by electroplating on the surface of the first UBM layer.

[0007] As a further technical solution of this utility model, the second metal interconnect layer is a BUMP layer, which is mounted on the surface of the second UBM layer by flip-chip technology.

[0008] Compared with the prior art, the beneficial effects of this utility model are: This invention, by employing a specially formulated photosensitive PI material, optimized interface treatment process, and innovative stepped curing method, effectively solves the stress management and reliability problems of multilayer structures while increasing interconnect density. This technology is particularly suitable for advanced packaging applications requiring high I / O density, excellent high-frequency performance, and long-term thermal stability. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the overall structure of this utility model.

[0010] In the figure: 1-Wafer substrate layer, 2-First polyimide insulating layer, 3-First UBM layer, 4-First metal interconnect layer, 5-Second polyimide insulating layer, 6-Second UBM layer, 7-Second metal interconnect layer. Detailed Implementation

[0011] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0012] Please see Figure 1In this embodiment of the present invention, a 2P2M wafer-level packaging structure based on PI insulating layer reinforcement includes a wafer substrate layer 1. The top surface of the wafer substrate layer 1 is coated with a first polyimide insulating layer 2, and the top of the first polyimide insulating layer 2 is formed by physical vapor deposition to form a first UBM layer 3. The top of the first UBM layer 3 is prepared by electroplating to form a first metal interconnect layer 4, and the top surface of the first metal interconnect layer 4 is coated with a second polyimide insulating layer 5. The top of the second polyimide insulating layer 5 is formed by physical vapor deposition to form a second UBM layer 6, and the top of the second UBM layer 6 is connected to a second metal interconnect layer 7.

[0013] In this example, aluminum pads are provided on the surface of the wafer substrate layer 1, and the first polyimide insulating layer 2 is coated on the surface of the aluminum pads. In this example, the first polyimide insulating layer 2 and the second polyimide insulating layer 5 are respectively coated to act on the aluminum pad and the first metal interconnect layer 4, and the first through hole is formed by photolithography and curing process. In this example, the curing process is carried out in a nitrogen atmosphere with an oxygen content of less than 10% ppm, with staged heating. The three stages are 80℃, 200℃, and 300℃, and the processing time is three hours. In this example, the first metal interconnect layer 4 is an RDL layer, which is prepared by electroplating on the surface of the first UBM layer 3; By adopting the above technical solution, a photoresist layer is first coated on the first UBM layer 3, and then the desired pattern is imprinted on the photoresist through photolithography to form a pattern window, while exposing the bottom UBM layer metal, which facilitates the preparation of the RDL layer metal. Finally, the RDL layer metal (selected as copper, gold, palladium or other metals with good conductivity) is directly deposited in the pattern window of the photoresist through electroplating.

[0014] In this example, the second metal interconnect layer 7 is a BUMP layer, which is mounted on the surface of the second UBM layer 6 using flip-chip technology; By adopting the above technical solution, the preparation method of the BUMP bump layer is consistent with the preparation process of the RDL layer. The UMP layer can adopt a multi-layer metal structure, such as a combination of multiple metals such as Pd / Au, Ni / Au, Cu / Ni / Au, Cu / Ni / Sn / Ag.

[0015] In this example, the process of forming the first polyimide insulating layer 2 includes the following steps: Step 1: Surface pretreatment of wafer substrate 1, using a 4:1 mixture of oxygen and argon to brush away organic contaminants from the surface of the wafer substrate.

[0016] Step 2: Spin coating of the first polyimide insulating layer 2. A photosensitive polyimide material is selected and applied to the surface of the wafer substrate layer 1. The spin coating speed is 2000 rpm × 30 s. Step 3: Step-by-step softening: The material with the above spin coating number is softened in a step-by-step manner using 80℃ / 2min + 120℃ / 3min. Step 4: Exposure and development. A stepper lithography device with a 365nm wavelength light source and an exposure dose range of 400 to 800 millijoules / square centimeter is used to perform the lithography process on the softened product. The product is then developed using TMAH solution to form the desired pattern. Step 5: Curing; Under N2 atmosphere (oxygen content less than 10% ppm), the temperature is increased in stages (80℃-200℃-300℃) for a total time of about 3 hours.

[0017] Furthermore, the processing of the second polyimide insulating layer 5 is the same as that of the first polyimide insulating layer 2, and the material of the second polyimide insulating layer 5 during spin coating is photosensitive PI + 5wt% alumina nanoparticles.

[0018] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0019] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A 2P2M wafer-level packaging structure based on PI insulating layer reinforcement, characterized in that: The wafer substrate (1) is coated with a first polyimide insulating layer (2) on its top surface. A first UBM layer (3) is formed on the top surface of the first polyimide insulating layer (2) by physical vapor deposition. A first metal interconnect layer (4) is formed on the top surface of the first UBM layer (3) by electroplating. A second polyimide insulating layer (5) is coated on the top surface of the first metal interconnect layer (4). A second UBM layer (6) is formed on the top surface of the second polyimide insulating layer (5) by physical vapor deposition. A second metal interconnect layer (7) is connected to the top surface of the second UBM layer (6).

2. The 2P2M wafer-level packaging structure based on PI insulating layer reinforcement according to claim 1, characterized in that: The surface of the wafer substrate layer (1) is provided with aluminum pads, and the first polyimide insulating layer (2) is coated on the surface of the aluminum pads.

3. The 2P2M wafer-level packaging structure based on PI insulating layer reinforcement according to claim 2, characterized in that: The first polyimide insulating layer (2) and the second polyimide insulating layer (5) are coated with aluminum pads and the first metal interconnect layer (4) respectively, and the first through hole is formed by photolithography and curing process.

4. The 2P2M wafer-level packaging structure based on PI insulating layer reinforcement according to claim 1, characterized in that: The first metal interconnect layer (4) is an RDL layer, which is prepared by electroplating on the surface of the first UBM layer (3).

5. The 2P2M wafer-level packaging structure based on PI insulating layer reinforcement according to claim 1, characterized in that: The second metal interconnect layer (7) is a BUMP bump layer, which is mounted on the surface of the second UBM layer (6) by flip chip technology.

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