A scheduling aggregation circuit structure and a network card chip
Patent Information
- Application Number
- CN202621119972.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-23
- Publication Date
- 2026-09-04
- Estimated Expiration
- 2036-07-23
AI Technical Summary
一、队列绑定导致资源固化
本申请提供一种用于调度聚合电路结构及网卡芯片，基于比较器阵列的硬连线并行比对释放存储资源固化。聚合判断电路通过比较器阵列、与门阵列和或门阵列的级联连接，将当前事件流标识与第一寄存器组输出的N位并行流标识信号进行单周期并行电平比对，并结合第二寄存器组输出的尾标识状态产生聚合使能信号。该信号直接控制第一多路选择器的选通路径，使事件信息在写数据输入端前即被导向聚合处理电路或直通写入，不再依赖哈希运算电路对存储体进行固定地址绑定，从物理层面消除特定存储体过载而其他存储体空闲的资源浪费。
Smart Images
Figure CN224721889U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of circuit structure technology for network interface card (NIC) chips, and more particularly to a scheduling aggregation circuit structure and a NIC chip. Background Technology
[0002] For a network interface card (NIC) chip that supports RDMA, there are typically two main types of components: one type is implemented by dedicated hardware logic, such as packet transmission protocol processing or direct memory access; the other type is implemented by a programmable microprocessor, such as congestion control. The data units that are processed and interacted between these two types of components are called events, and those sent from the dedicated hardware to the microprocessor are called event requests.
[0003] Between the two types of components, an intermediate module is typically set up to implement the scheduling and aggregation processing of event requests. A typical scheduling processing circuit structure in the prior art is as follows: Figure 1 As shown.
[0004] exist Figure 1 In the circuit shown, the event buffer is a static random access memory array used to cache event request information. The event queue is a first-in, first-out (FIFO) memory used to perform ordered scheduling of event requests with the same stream identifier. Event requests with different stream identifiers are mapped to different event queues via a hash operation circuit.
[0005] When each event request arrives, an available address is pre-allocated by the address allocation circuit. The event information is written to the event buffer, and the address is then written to the corresponding event queue. The event queue outputs the event address according to a preset timing sequence, reads the event content from the event buffer, and sends it to the microprocessor for processing. Since multiple event requests with the same stream identifier need to be processed serially, the event queue adopts a blocking scheduling method. That is, after scheduling an event request, it is necessary to wait for the response corresponding to that event request to return before continuing to schedule the next event in the queue.
[0006] However, in the aforementioned prior art, the event queue is a first-in-first-out storage, and its hardware structure has the following shortcomings: 1. Queue binding leads to resource fixation. After a stream identifier is mapped to a queue identifier via hashing, all event requests for the same stream identifier are forcibly bound to the same event queue by the hardware, making it impossible to dynamically adjust based on the real-time occupancy status of each queue. When the hash mapping results of multiple streams converge to the same event queue, that queue runs at full capacity continuously, while other event queues and their corresponding microprocessors and data paths are idle, resulting in an inherent waste of chip hardware resources.
[0007] II. Blocking scheduling leads to read / write imbalance. The first-in, first-out (FIFO) structure dictates that event addresses are read from the head of the queue in the order they are written. Under blocking scheduling, once the event at the head of the queue is scheduled, read operations on that queue are locked by a hardware gating signal until a response is returned. During this period, event writing continues, while read operations are blocked, causing the corresponding event buffer storage space to be in a write-only state, continuously consuming address space until it overflows.
[0008] Third, the hash mapping is fixed and the queue depth is fixed. The mapping relationship of the hash operation circuit is fixed by the hardware interconnection logic and cannot be adjusted after the chip is fabricated; the event queue depth is determined by the number of words in the storage array and is also not scalable. When a single stream occupies the entire bandwidth, the event request generation rate reaches its peak, but the queue depth remains at a fixed upper limit, making it impossible to utilize the storage space of other idle queues, resulting in storage overflow. Utility Model Content
[0009] This application aims to overcome existing technical problems and provide a scheduling aggregation circuit structure and network card chip, which can improve the utilization efficiency of internal hardware resources and the overall throughput of data processing paths.
[0010] To address the aforementioned technical problems, as one aspect of this application, a scheduling aggregation circuit structure is provided, comprising: An event buffer, which is a static random access memory array, includes at least a chip select terminal, a write data input terminal, and a read data output terminal, and is used to cache event information in hardware; wherein, the event information contains multiple bit fields, including at least a stream identifier field and a data field to be processed; The first register group is a register array consisting of N registers, each register storing a stream identifier. The output terminals of each bit of the first register group output N-bit parallel stream identifier signals. The second register group is a register array consisting of N registers. Each register stores the tail flag corresponding to each stream identifier. Registers with the same index position in the first register group and the second register group correspond to the same stream identifier. The output terminals of each bit of the second register group output N-bit parallel tail flag signals. The aggregation decision circuit includes a cascaded comparator array, an AND gate array, and an OR gate array. One input is connected to the output of the first register group via a parallel bus to receive the N-bit parallel stream identifier signal. Another input is connected to an externally input current event stream identifier signal via a parallel bus. A third input is connected to the output of the second register group via a parallel bus to receive the N-bit parallel tail identifier signal. The output of the circuit is an aggregation enable signal. The aggregation processing circuit has a first data input terminal connected to the read data output terminal of the event buffer via a read data bus to obtain the tail event information signal; its second data input terminal is connected to the externally input current event information signal via a parallel bus; and its data output terminal outputs the aggregated event information. The aggregation processing circuit includes a replacement sub-circuit, an accumulation sub-circuit, a superposition sub-circuit, and a data bit-width splicing bus. The input terminals of each of the replacement sub-circuit, the accumulation sub-circuit, and the superposition sub-circuit are connected to the first data input terminal and the second data input terminal, and their respective output terminals are connected to the data bit-width splicing bus, merging multiple channels to generate the aggregated event information. The first multiplexer has a first data input terminal connected to the externally input current event information signal via a parallel bus, a second data input terminal connected to the data output terminal of the aggregation processing circuit via a parallel bus, a selection control terminal connected to the output terminal of the aggregation judgment circuit via a signal line to input the aggregation enable signal, and a data output terminal connected to the write data input terminal of the event buffer via a write data bus.
[0011] As another aspect of this application, a network interface card (NIC) chip is also provided, which integrates at least: A dedicated hardware processing module is used to perform message transmission protocol processing or direct memory access operations and generate event requests. Its output is connected to a receive / transmit pipeline circuit. A microprocessor cluster, consisting of multiple microprocessors, is used to execute microcode programs to process event requests in parallel. As described above, the scheduling aggregation circuit structure has one end connected to the dedicated hardware processing module via a receive / transmit pipeline circuit, and the other end connected to the microprocessor cluster.
[0012] Implementing the embodiments of this application has the following beneficial effects: This application provides a scheduling aggregation circuit structure and network interface card (NIC) chip that uses hard-wired parallel comparison based on a comparator array to release and solidify storage resources. The aggregation judgment circuit, through a cascaded connection of a comparator array, an AND gate array, and an OR gate array, performs a single-cycle parallel level comparison between the current event stream identifier and the N-bit parallel stream identifier signal output from the first register group, and combines this with the tail identifier status output from the second register group to generate an aggregation enable signal. This signal directly controls the selection path of the first multiplexer, ensuring that event information is directed to the aggregation processing circuit or directly written before the write data input, eliminating the need for a hash operation circuit to bind fixed addresses to memory banks, and physically eliminating resource waste caused by overloaded specific memory banks while other memory banks remain idle.
[0013] In this application, hard-wired aggregation logic is used to eliminate the risk of read / write imbalance and overflow. In the aggregation processing circuit, the replacement, accumulation, and superposition sub-circuits are connected in parallel via their respective data buses to the tail event information and the current event information, and are merged and output by a data bit-width splicing bus. When the aggregation enable signal is valid, the current event completes the physical merging of multiple data streams before being written to the event buffer, eliminating the need for blocking read waits on the memory. The chip select terminal of the event buffer is driven by a second multiplexer based on the hard-wired switching between the aggregation write signal and the scheduled read signal. The read / write operation timing is balanced in real-time by combinational logic within the same clock cycle, preventing the address space from being written to without being read until overflow occurs.
[0014] In this application, register levels are hardwired to release the entire array's storage depth. The level states stored in the registers in the first and second register groups are directly hardwired to the comparator and AND gate array. The matching reference for the stream identifier is refreshed by register write operations. The entire address space of the memory bank can be exclusively used by a single stream, without being limited by a fixed queue depth, ensuring the complete availability of hardware storage resources under extreme loads.
[0015] In summary, implementing this application can improve the utilization efficiency of internal hardware resources of the chip and the overall throughput of the data processing path. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, obtaining other drawings based on these drawings without creative effort still falls within the scope of this application.
[0017] Figure 1 This is a schematic diagram of a typical event request and scheduling circuit in the prior art; Figure 2 This application provides a schematic diagram of a scheduling aggregation circuit structure. Figure 3 for Figure 2 Timing diagrams of several key signals; Figure 4 This is a schematic diagram of the structure of one embodiment of a network interface card (NIC) chip provided in this application. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of this application clearer, the application will be described in further detail below with reference to the accompanying drawings.
[0019] like Figure 2The diagram shows a schematic of a scheduling aggregation circuit structure provided in this application. To better understand the connections between the circuit components, the front-end receive / transmit pipeline circuit and the back-end microprocessor cluster are also shown. Figure 3 As shown, in this embodiment, the scheduling aggregation circuit structure includes: An event buffer, which is a static random access memory (SRAM) array, includes at least a chip select terminal, a write data input terminal, and a read data output terminal, and is used to cache event information in hardware; wherein, the event information contains multiple bit fields, including at least a flow identifier (flow_id) field and a data to be processed field (event_in_info). The first register group is a register array consisting of N registers, each register storing a flow identifier (flow_id). The outputs of each bit in the first register group output N-bit parallel flow identifier signals. Figure 2 In the example shown, N equals 256, and the first register group consists of 256 registers, each storing 256 stream identifiers; The second register group is a register array consisting of N registers. Each register stores a tail flag corresponding to a stream identifier. Registers at the same index position in the first and second register groups correspond to the same stream identifier. The output terminals of the second register group output N-bit parallel tail flag signals. Figure 2 In the example shown, the second register group consists of 256 registers, each storing a 256-bit tail flag corresponding to one of the 256 stream identifiers; The aggregation decision circuit includes a cascaded comparator array, an AND gate array, and an OR gate array. One input is connected to the output of the first register group via a parallel bus to receive the N-bit parallel stream identifier signal; another input is connected to the externally input current event stream identifier signal (flow_id_in[23:0]) via a parallel bus; yet another input is connected to the output of the second register group via a parallel bus to receive the N-bit parallel tail identifier signal; and its output outputs an aggregation enable signal (Merge result). The aggregation processing circuit has a first data input terminal connected to the read data output terminal of the event buffer via a read data bus to obtain the tail event information signal (event_tail_info[130:0]), a second data input terminal connected to the externally input current event information signal (event_in_info[130:0]) via a parallel bus, and an output terminal outputting the aggregated event information (event_merge_info[130:0]). The aggregation processing circuit includes a replacement sub-circuit, an accumulation sub-circuit, a superposition sub-circuit, and a data bit-width splicing bus. The input terminals of the replacement sub-circuit, the accumulation sub-circuit, and the superposition sub-circuit are all connected to the first data input terminal and the second data input terminal, and their output terminals are all connected to the data bit-width splicing bus, merging multiple channels to generate the aggregated event information. The first multiplexer U1 has its first data input terminal (0 terminal) connected to the externally input current event information signal via a parallel bus, its second data input terminal (1 terminal) connected to the data output terminal of the aggregation processing circuit via a parallel bus, its selection control terminal connected to the output terminal of the aggregation judgment circuit via a signal line to input the aggregation enable signal (merge result), and its data output terminal connected to the write data input terminal (wdata) of the event buffer via a write data bus. The second multiplexer U2 has its first data input connected to the aggregation write signal line (event_merge_wr), its second data input connected to the output of the aggregation judgment circuit via an inverter INV, its third data input connected to the output of the aggregation judgment circuit, its fourth data input connected to the scheduling read signal line (event_sch_rd), and its output connected to the chip select terminal ce of the event buffer.
[0020] It is understood that the event buffer also has a write address input terminal and a read address input terminal, which are respectively connected to a write address generator and a read address generator. The write address generator is composed of a counter circuit. When the aggregation enable signal is valid, the counter maintains the current count value and increments when it is invalid, so as to realize the hardware holding and incrementing switching of the address. The first register group and the second register group each include a clock terminal, a write enable terminal and a write data terminal. Each register latches the external input stream identifier and the corresponding tail identifier flag bit when the clock rises and the write enable is valid. The output terminals of each register are connected to the corresponding input terminals of the aggregation judgment circuit through hard lines, forming a physical direct connection path for the comparison reference level. The first multiplexer and the second multiplexer are both composed of CMOS transmission gates. Their selection path is determined by the level state of the selection control terminal. The propagation delay from the level change of the selection control terminal to the stable data output terminal is less than one clock cycle.
[0021] More specifically, in the aggregation determination circuit, wherein: The comparator array consists of N comparators. The first input of each comparator is connected to the output of each bit of the first register group. The second input of each comparator is connected to the current event stream identifier signal (flow_id_in[23:0]) via a parallel bus. The output of each comparator outputs an N-bit comparison result signal to the AND gate array via the first parallel bus. Figure 2 In the example shown, the comparator array consists of 256 comparators; The AND gate array consists of N AND gates. The first input of each AND gate is connected to the corresponding bit of the first parallel bus, and the second input of each AND gate is connected to the output of each bit of the second register group. The output of each AND gate outputs an N-bit matching result signal to the OR gate array through the second parallel bus. Figure 2 In the example shown, the AND gate array consists of 256 AND gates; The OR gate array has N input terminals and 1 output terminal. The N input terminals are respectively connected to each bit of the second parallel bus, and the output terminal outputs the aggregation enable signal (merge result). Figure 2 In the example shown, the OR gate array has 256 inputs.
[0022] More specifically, in the aggregation processing circuit, the first parallel data input terminal of the replacement sub-circuit is connected to the read data output terminal of the event buffer via a read data bus to receive a portion of the tail event information signal; the second parallel data input terminal of the replacement sub-circuit is connected to a portion of the signal lines of the current event information signal via a parallel bus; the replacement sub-circuit is composed of bit substitution logic gates, which replace the corresponding bit field of the tail event information signal with a specified bit field of the current event information signal, wherein the specified bit field is at least one subfield in the data field to be processed of the event information; the output terminal of the replacement sub-circuit outputs the replaced event information signal to the data bit-width splicing bus via a third parallel data bus; exist Figure 2In the specific example shown, the replacement sub-circuit includes a ninth selector U9, one input of which is connected to the 0-63 bit signal lines of the current event information signal (event_in_info[63:0]); the other input is connected to the 0-63 bit signal lines of the tail event information signal (event_tail_info[63:0]); its chip select is connected to the 128 bit signal lines of the current event information signal (event_in_info
[128] ); and its output is connected to the data width splicing bus. The effect of the replacement sub-circuit is to replace the corresponding bit segment in the tail event information with the specified bit segment of the current event information (here, [63:0]), while the remaining bit segments remain unchanged.
[0023] The first parallel data input terminal of the accumulator sub-circuit is connected to the read data output terminal of the event buffer via a read data bus to receive a portion of the tail event information signal. The second parallel data input terminal of the accumulator sub-circuit is connected to a portion of the signal lines of the current event information signal via a parallel bus. The accumulator sub-circuit is composed of an adder circuit, which performs an addition operation on a specified bit field segment of the tail event information signal and the corresponding bit field segment of the current event information signal. The specified bit field segment is the count value sub-field in the data field to be processed of the event information. The output terminal of the accumulator sub-circuit outputs the sum value to the data width splicing bus via a sixth parallel data bus. exist Figure 2 In the specific example shown, the accumulator sub-circuit includes an eighth selector U8, an adder U7, and a sixth AND gate U6; wherein, for the sixth AND gate U6, one of its input terminals is the 129-bit signal line of the current event information signal (event_in_info
[129] ); its other input terminal is connected to the 129-bit signal line of the tail event information signal (event_tail_info
[129] ); and its output terminal is connected to the chip select terminal of the eighth selector U8.
[0024] For adder U7, one of its inputs is connected to the 64th to 95th bit signal lines of the current event information signal (event_in_info[95:64]), and its other input is connected to the 64th to 95th bit signal lines of the tail event information signal (event_tail_info[95:64]). Its output is connected to one input of the eighth selector U8. For the eighth selector U8, its other input is connected to the 64th to 95th bit signal lines (event_tail_info[95:64]) of the tail event information signal, and its output is connected to the data width splicing bus. The effect of the accumulator sub-circuit is to add the count value of the current event to the count value of the tail event, and use the result as the new count value.
[0025] The first parallel data input terminal of the superposition sub-circuit is connected to the read data output terminal of the event buffer via a read data bus to receive a portion of the tail event information signal. The second parallel data input terminal of the superposition sub-circuit is connected to a portion of the signal lines of the current event information signal via a parallel bus. The superposition sub-circuit is composed of bit-joining logic gates, which perform bit-joining and merging of different bit fields of the tail event information signal and the current event information signal, wherein the different bit fields include at least two subfields in the data field to be processed. The output terminal of the superposition sub-circuit outputs the superimposed event information signal to the data bit-width joining bus via a ninth parallel data bus. exist Figure 2 In the specific example shown, the superposition sub-circuit includes a disable gate U4 and a fifth selector U5. Specifically, the data input terminal of the disable gate U4 is connected to the 130-bit signal line of the current event information signal (event_in_info
[130] ), its disable terminal is connected to the 130-bit signal line of the tail event information signal (event_tail_info
[130] ), and its output terminal is connected to the chip select terminal of the fifth selector U5.
[0026] For the fifth selector U5, one of its inputs is connected to the 96th to 127th bit signal lines of the current event information signal (event_in_info[127:96]); its other input is connected to the 96th to 127th bit signal lines of the tail event information signal (event_tail_info[127:96]); and its output is connected to the data width splicing bus.
[0027] Furthermore, it also includes a third OR gate, one input of which is connected to the 128th to 130th bit signal lines of the current event information signal (event_in_info[130:128]); its other input is connected to the 128th to 130th bit signal lines of the tail event information signal (event_tail_info[130:128]); and its output is connected to the data width splicing bus. The effect achieved by the superposition sub-circuit is to logically splice the different flag bit fields of the current event and the tail event, while retaining the different information carried by the two events.
[0028] Furthermore, the bus that receives the current event stream identifier signal (flow_id_in[23:0]) and the externally input current event information signal (event_in_info[130:0]) is connected to a receive / transmit pipeline circuit; The read data output terminal rdata of the event buffer is connected to a microprocessor cluster via a parallel bus.
[0029] The following is a brief explanation of the working principle of the scheduling aggregation circuit structure provided in this application.
[0030] like Figure 2 and combined Figure 3 As shown, the entire circuit operates driven by the rising edge of the same clock signal (clk). An event signal, including event_in_info and flow_id_in, is input upstream, along with a valid indicator signal event_in_vld. When event_in_vld is valid, the current event information and flow identifier are synchronously sent to the aggregation judgment circuit and the first multiplexer.
[0031] First, in the aggregation judgment circuit, the flow_id_in signal is compared in parallel with the flow_id 0~255 currently recorded in the first register group through a comparator array. Then, the comparison result is ANDed with the tail flag 0~255 currently recorded in the second register group through an AND gate array to obtain a 256-bit result. Finally, these results are ORed through an OR gate array to obtain the final aggregation enable signal (merge result), which indicates that there is a linked list tail node with the same flow_id as flow_id_in.
[0032] If `merge result` = 1, the aggregation timing branch is entered. On the next rising clock edge after `event_in_vld` becomes valid, the read enable signal (`event_merge_rd`) is set, triggering the event buffer to read the corresponding linked list tail node information to obtain `event_tail_info`. In the aggregation processing circuit, `event_tail_info` and `event_in_info` are processed in parallel through replacement sub-circuits, accumulation sub-circuits, and superposition sub-circuits, and then combined into the `event_merge_info` signal by the data bit-width splicing bus. After several clock cycles of delay generated by the combinational logic gate level, the aggregation write enable signal (`event_merge_wr`) is set, and on the subsequent rising clock edge, `event_merge_info` is written to the original tail node address, completing the aggregation operation. Under this branch, `event_in_wr` remains invalid.
[0033] If merge result = 0, then the non-aggregation timing branch is entered. Within the current clock cycle after event_in_vld becomes valid, the write enable signal (event_in_wr) is directly set, a new address pointer is generated by the write address counter, and the current event_in_info is written to the free memory location of the event buffer without performing an aggregation operation. In this branch, event_merge_rd and event_merge_wr remain invalid.
[0034] The temporal relationships of the main signals in a complete event signal aggregation process can be found in [reference needed]. Figure 3 As shown.
[0035] like Figure 4 The diagram shows a schematic representation of a network interface card (NIC) chip provided in this application. In this embodiment, the NIC chip integrates at least: A dedicated hardware processing module is used to perform message transmission protocol processing or direct memory access operations and generate event requests. Its output is connected to a receive / transmit pipeline circuit. A microprocessor cluster, consisting of multiple microprocessors, is used to execute microcode programs to process event requests in parallel. like Figures 2 to 3 The described scheduling aggregation circuit structure has one end connected to the dedicated hardware processing module via a receive / transmit pipeline circuit, and the other end connected to the microprocessor cluster.
[0036] As is understandable, network interface card (NIC) chips also contain other circuit modules, which will not be elaborated upon here. For more details on the scheduling aggregation circuit structure, please refer to and combine with the aforementioned... Figures 2 to 3 The description of that will not be repeated here.
[0037] In one specific example, the microprocessor cluster has eight microprocessor cores, each with an independent parallel input for event requests and a parallel output for event responses.
[0038] Implementing the embodiments of this application has the following beneficial effects: This application provides a scheduling aggregation circuit structure and network interface card (NIC) chip that uses hard-wired parallel comparison based on a comparator array to release and solidify storage resources. The aggregation judgment circuit, through a cascaded connection of a comparator array, an AND gate array, and an OR gate array, performs a single-cycle parallel level comparison between the current event stream identifier and the N-bit parallel stream identifier signal output from the first register group, and combines this with the tail identifier status output from the second register group to generate an aggregation enable signal. This signal directly controls the selection path of the first multiplexer, ensuring that event information is directed to the aggregation processing circuit or directly written before the write data input, eliminating the need for a hash operation circuit to bind fixed addresses to memory banks, and physically eliminating resource waste caused by overloaded specific memory banks while other memory banks remain idle.
[0039] In this application, hard-wired aggregation logic is used to eliminate the risk of read / write imbalance and overflow. In the aggregation processing circuit, the replacement, accumulation, and superposition sub-circuits are connected in parallel via their respective data buses to the tail event information and the current event information, and are merged and output by a data bit-width splicing bus. When the aggregation enable signal is valid, the current event completes the physical merging of multiple data streams before being written to the event buffer, eliminating the need for blocking read waits on the memory. The chip select terminal of the event buffer is driven by a second multiplexer based on the hard-wired switching between the aggregation write signal and the scheduled read signal. The read / write operation timing is balanced in real-time by combinational logic within the same clock cycle, preventing the address space from being written to without being read until overflow occurs.
[0040] In this application, register levels are hardwired to release the entire array's storage depth. The level states stored in the registers in the first and second register groups are directly hardwired to the comparator and AND gate array. The matching reference for the stream identifier is refreshed by register write operations. The entire address space of the memory bank can be exclusively used by a single stream, without being limited by a fixed queue depth, ensuring the complete availability of hardware storage resources under extreme loads.
[0041] In summary, implementing this application can improve the utilization efficiency of internal hardware resources of the chip and the overall throughput of the data processing path.
[0042] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.
Claims
1. A scheduling aggregation circuit structure, characterized in that, include: An event buffer, which is a static random access memory array, includes at least a chip select terminal, a write data input terminal, and a read data output terminal, and is used to cache event information in hardware; wherein, the event information contains multiple bit fields, including at least a stream identifier field and a data field to be processed; The first register group is a register array consisting of N registers, each register storing a stream identifier. The output terminals of each bit of the first register group output N-bit parallel stream identifier signals. The second register group is a register array consisting of N registers. Each register stores the tail flag corresponding to each stream identifier. Registers with the same index position in the first register group and the second register group correspond to the same stream identifier. The output terminals of each bit of the second register group output N-bit parallel tail flag signals. The aggregation decision circuit includes a cascaded comparator array, an AND gate array, and an OR gate array. One input is connected to the output of the first register group via a parallel bus to receive the N-bit parallel stream identifier signal. Another input is connected to an externally input current event stream identifier signal via a parallel bus. A third input is connected to the output of the second register group via a parallel bus to receive the N-bit parallel tail identifier signal. The output of the circuit is an aggregation enable signal. The aggregation processing circuit has a first data input terminal connected to the read data output terminal of the event buffer via a read data bus to obtain the tail event information signal; its second data input terminal is connected to the externally input current event information signal via a parallel bus; and its data output terminal outputs the aggregated event information. The aggregation processing circuit includes a replacement sub-circuit, an accumulation sub-circuit, a superposition sub-circuit, and a data bit-width splicing bus. The input terminals of each of the replacement sub-circuit, the accumulation sub-circuit, and the superposition sub-circuit are connected to the first data input terminal and the second data input terminal, and their respective output terminals are connected to the data bit-width splicing bus, merging multiple channels to generate the aggregated event information. The first multiplexer has a first data input terminal connected to the externally input current event information signal via a parallel bus, a second data input terminal connected to the data output terminal of the aggregation processing circuit via a parallel bus, a selection control terminal connected to the output terminal of the aggregation judgment circuit via a signal line to input the aggregation enable signal, and a data output terminal connected to the write data input terminal of the event buffer via a write data bus.
2. The circuit structure according to claim 1, characterized in that, In the aggregation determination circuit, wherein: The comparator array consists of N comparators. The first input of each comparator is connected to the output of each bit of the first register group. The second input of each comparator is connected to the current event stream identifier signal through a parallel bus. The output of each comparator outputs an N-bit comparison result signal to the AND gate array through the first parallel bus. The AND gate array consists of N AND gates. The first input of each AND gate is connected to the corresponding bit of the first parallel bus, the second input of each AND gate is connected to the output of each bit of the second register group, and the output of each AND gate outputs an N-bit matching result signal to the OR gate array through the second parallel bus. The OR gate array has N input terminals and 1 output terminal. The N input terminals are respectively connected to each bit of the second parallel bus, and the output terminal outputs the aggregation enable signal.
3. The circuit structure according to claim 2, characterized in that, In the aggregation processing circuit: The first parallel data input terminal of the replacement sub-circuit is connected to the read data output terminal of the event buffer via a read data bus to receive a portion of the tail event information signal; the second parallel data input terminal of the replacement sub-circuit is connected to a portion of the signal lines of the current event information signal via a parallel bus; the replacement sub-circuit is composed of bit substitution logic gates, which replace the corresponding bit field of the tail event information signal with a specified bit field of the current event information signal, wherein the specified bit field is at least one subfield in the data field to be processed of the event information; the output terminal of the replacement sub-circuit outputs the replaced event information signal to the data bit-width splicing bus via a third parallel data bus; The first parallel data input terminal of the accumulator sub-circuit is connected to the read data output terminal of the event buffer via a read data bus to receive a portion of the tail event information signal. The second parallel data input terminal of the accumulator sub-circuit is connected to a portion of the signal lines of the current event information signal via a parallel bus. The accumulator sub-circuit is composed of an adder circuit, which performs an addition operation on a specified bit field segment of the tail event information signal and the corresponding bit field segment of the current event information signal. The specified bit field segment is the count value sub-field in the data field to be processed of the event information. The output terminal of the accumulator sub-circuit outputs the sum value to the data width splicing bus via a sixth parallel data bus. The first parallel data input terminal of the superposition sub-circuit is connected to the read data output terminal of the event buffer via a read data bus to receive a portion of the tail event information signal. The second parallel data input terminal of the superposition sub-circuit is connected to a portion of the signal lines of the current event information signal via a parallel bus. The superposition sub-circuit is composed of bit-joining logic gates, which perform bit-joining and merging of different bit fields of the tail event information signal and the current event information signal, wherein the different bit fields include at least two subfields in the data field to be processed. The output terminal of the superposition sub-circuit outputs the superimposed event information signal to the data bit-width joining bus via a ninth parallel data bus.
4. The circuit structure according to claim 3, characterized in that, Further includes: The second multiplexer has a first data input connected to the aggregation write signal line, a second data input connected to the output of the aggregation judgment circuit via an inverter, a third data input connected to the output of the aggregation judgment circuit, a fourth data input connected to the scheduling read signal line, and its output connected to the chip select terminal of the event buffer.
5. The circuit structure according to claim 4, characterized in that, in: The N is equal to 256, and the first register group consists of 256 registers, each storing 256 stream identifiers; The second register group consists of 256 registers, each storing a 256-bit tail flag corresponding to one of the 256 stream identifiers; The comparator array consists of 256 comparators, the AND gate array consists of 256 AND gates, and the OR gate array has 256 inputs.
6. The circuit structure according to any one of claims 1 to 5, characterized in that, in: The bus that receives the current event stream identifier signal and the externally input current event information signal is connected to a receive / transmit pipeline circuit. The read data output terminal of the event buffer is connected to a microprocessor cluster via a parallel bus.
7. A network interface card (NIC) chip, characterized in that, At least the following are integrated: A dedicated hardware processing module is used to perform message transmission protocol processing or direct memory access operations and generate event requests. Its output is connected to a receive / transmit pipeline circuit. A microprocessor cluster contains multiple microprocessors that execute microcode programs to process event requests in parallel. The scheduling aggregation circuit structure as described in any one of claims 1 to 6 has one end connected to the dedicated hardware processing module via a receive / transmit pipeline circuit, and the other end connected to the microprocessor cluster.
8. The network interface card chip according to claim 7, characterized in that, The microprocessor cluster contains eight microprocessor cores, each with an independent parallel input for event requests and a parallel output for event responses.