Semiconductor package structure

Abstract

The application provides a semiconductor package structure, which comprises: a redistribution layer; a dielectric layer arranged above the redistribution layer, and a plurality of terminals arranged on the dielectric layer; a cavity arranged above the dielectric layer and exposing a plurality of first terminals, the plurality of first terminals being part of the plurality of terminals; and an embedded element arranged between the redistribution layer and the dielectric layer and overlapping with a projection of the plurality of first terminals in a vertical direction. By embedding the embedded element between the redistribution layer and the dielectric layer, the embedded element can support the cavity and the redistribution layer below the cavity, so that the redistribution layer below the cavity can be prevented from warping or deforming, thereby improving product yield. In addition, the embedded element can also provide a bridging line function to improve product electrical performance.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and specifically to a semiconductor packaging structure. Background Technology

[0002] The current structural feature of fan-out multi-chip module (FOMCM) is to integrate dynamic random access memory (DRAM) with system-on-a-chip (SoC die) in a single package to improve integration and performance.

[0003] refer to Figure 1 , Figure 1 This is a schematic diagram of the longitudinal cross-section of a current-technical FOMCM structure. (Example) Figure 1 As shown, the FOMCM structure includes a redistribution layer (RDL) 03, a system-on-a-chip (SoC) 02 and a DRAM 01 arranged side-by-side on the redistribution layer 03, an underfill adhesive 04 filling the spaces between the three, and a molding compound 05 encapsulating the SoC 02, DRAM 01, and underfill adhesive 04. This FOMCM structure integrates the SoC 02 and DRAM 01 into a single molded package.

[0004] However, during the manufacturing process, if any component or circuitry within the FOMCM structure is damaged, DRAM01 will also be lost. This is because, in the integrated molded structure, DRAM01 is encapsulated within the molding material 05 and soldered to the redistribution layer 03. Later in the manufacturing process, it becomes impossible to remove DRAM01 from the structure for reuse. Since DRAM01 is expensive, significantly more so than other components or materials such as the system-on-a-chip 02, this results in material waste, significantly increasing the risk of loss and manufacturing costs.

[0005] To address the aforementioned issues, the applicant proposed in the previous case to first perform molding, and then create a cavity in the molding material 05 using laser drilling or chemical etching methods. Figure 1 (Not shown in the image), and finally, the DRAM 01 is placed into the cavity. This avoids the risk of damage to the DRAM 01, reduces material waste, improves the availability of the DRAM, and lowers the risk of structural failure and manufacturing costs. In practice, the product is shipped as a finished product after the cavity is cut out, and the user is responsible for placing the DRAM 01 inside the cavity.

[0006] The applicant discovered that the above solution has the following defects: during the manufacturing or transportation process, the cavity and the redistribution layer 03 below it are prone to deformation or warping due to lack of support, which leads to a decrease in product reliability and a reduction in product yield. Utility Model Content

[0007] The main objective of this application is to provide a semiconductor packaging structure that improves the reliability and stability of products, thereby increasing product yield.

[0008] This application discloses a semiconductor packaging structure, comprising: a redistribution layer; a dielectric layer disposed above the redistribution layer and having a plurality of terminals disposed thereon; a cavity disposed above the dielectric layer and exposing a plurality of first terminals, wherein the plurality of first terminals are a portion of the plurality of terminals; and an embedded element disposed between the redistribution layer and the dielectric layer, overlapping the projection of the plurality of first terminals in the vertical direction.

[0009] In some alternative embodiments, the semiconductor package structure further includes: an underfill adhesive layer disposed above the dielectric layer; a rigid member disposed above the dielectric layer and surrounding the plurality of first terminals; wherein the rigid member defines the cavity, the plurality of first terminals are located within the cavity, and the underfill adhesive layer is isolated outside the cavity by the rigid member.

[0010] In some alternative implementations, the rigid member consists of multiple metal blocks.

[0011] In some alternative implementations, the embedded element supports the cavity and the redistribution layer located below the cavity.

[0012] In some alternative embodiments, the embedded element is divided into a first region that overlaps with the bottom filling adhesive layer and a second region that overlaps with the cavity, according to its projection in the vertical direction.

[0013] In some alternative implementations, the area of ​​the first region is smaller than the area of ​​the second region.

[0014] In some alternative embodiments, the rigid member is disposed on the dielectric layer by means of an adhesive material.

[0015] In some alternative embodiments, a surrounding metal pad is provided on the dielectric layer, and the rigid member is bonded to the metal pad by solder.

[0016] In some alternative embodiments, the semiconductor package structure further includes: a first conductive pillar, arranged horizontally with the embedded element and overlapping the cavity vertically, for electrically connecting the first terminal and the redistribution layer.

[0017] In some alternative implementations, when viewed from above, the center of the first conductive post and the center of the first terminal are offset.

[0018] In some alternative embodiments, the semiconductor package structure further includes: a molding interposer layer disposed between the redistribution layer and the dielectric layer, covering the embedded component.

[0019] In some alternative implementations, the embedded element and the redistribution layer are hybrid-bonded.

[0020] In some alternative embodiments, the upper surface of the embedded element has a connecting pad that is electrically connected to the terminal.

[0021] In some alternative embodiments, the semiconductor package structure further includes: a first chip disposed on the dielectric layer; and an underfill adhesive layer connecting the first chip, the rigid member, and the dielectric layer.

[0022] In some alternative embodiments, the semiconductor package structure further includes: a molding layer covering the first chip, the rigid member, and the underfill adhesive.

[0023] In some alternative implementations, the upper surfaces of the molding layer, the first chip, and the rigid member are substantially flush.

[0024] In some alternative embodiments, the semiconductor package structure further includes: a second chip disposed within the cavity and electrically connected to the plurality of first terminals.

[0025] In some alternative embodiments, the rigid member is a square frame structure formed by integrally connecting the plurality of metal blocks.

[0026] In some alternative embodiments, the plurality of terminals further include a plurality of second terminals that overlap the bottom filler layer in the vertical direction, and the first chip is electrically connected to the plurality of second terminals.

[0027] In some alternative embodiments, the semiconductor package structure further includes: a second conductive post disposed between the redistribution layer and the dielectric layer, overlapping the bottom filler layer in the vertical direction, and electrically connecting the second terminal to the redistribution layer.

[0028] As described above, to address the technical problem that the cavity and the redistribution layer beneath the FOMCM structure are prone to deformation or warping due to lack of support, affecting product reliability and yield, this application proposes a semiconductor packaging structure. This structure involves placing a dielectric layer above the redistribution layer, creating a cavity above the dielectric layer, and placing multiple first terminals exposed from the cavity on the dielectric layer. Furthermore, embedded components are placed between the redistribution layer and the dielectric layer, with the embedded components overlapping the multiple first terminals in the vertical direction. This allows the embedded components to support the cavity and the redistribution layer beneath it, preventing deformation or warping, thereby improving product reliability and stability, and ultimately increasing product yield. In addition, the embedded components can also provide bridging circuit functionality, thereby improving the product's electrical performance.

[0029] In some alternative implementations, a rigid member can be attached to the dielectric layer and surround multiple first terminals. After the molding layer is formed, grinding is performed to define the cavity defined by the rigid member, exposing the multiple first terminals within the cavity. This allows the DRAM to be subsequently placed into the cavity. This supports placing the DRAM after molding is completed and the post-molding structure is confirmed to be in good condition. This avoids the risk of DRAM damage due to the loss of other components or materials, reduces material waste, improves DRAM availability, allows for better fan-out of the DRAM, simultaneously enhances overall package stability, and reduces the risk of structural failure and manufacturing costs. Attached Figure Description

[0030] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0031] Figure 1 This is a schematic diagram of the longitudinal cross-section of a current-technical FOMCM structure;

[0032] Figure 2 This is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor packaging structure 2a according to an embodiment of this application;

[0033] Figure 3 yes Figure 2 A partially enlarged schematic diagram of the semiconductor package structure 2a shown;

[0034] Figure 4 This is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor packaging structure 4a according to an embodiment of this application;

[0035] Figure 5 This is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor packaging structure 5a according to an embodiment of this application;

[0036] Figures 6 to 7 This is a schematic diagram of the manufacturing steps of a semiconductor packaging structure according to an embodiment of this application.

[0037] Explanation of reference numerals / symbols in the attached diagram:

[0038] 01: DRAM; 02: System-on-a-Chip (SoC die); 03: Redistribution layer; 04: Underfill adhesive; 05: Molding material; 11: Redistribution layer; 12: Dielectric layer; 13: Terminal; 131: First terminal; 132: Second terminal; 14: Underfill adhesive layer; 15: Embedded component; 151: First region; 152: Second region; 153: Connecting pad; 154: Through-silicon via (TSV); 16: Rigid component; 161: Top cover; 17: Cavity; 18: Adhesive material; 19: Metal pad; 20: Solder; 21: First conductive post; 22: Molding interlayer; 23: First chip; 24: Molding layer; 25: Second chip; 26: Filler layer; 27: Second conductive post; 28: Electrical connector; 29: Bump; 30: Carrier. Detailed Implementation

[0039] The specific embodiments of this application will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this application and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and are not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0040] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this application should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.

[0041] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0042] As used herein, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A single layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0043] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers. Further alternatively, the substrate may have semiconductor devices or circuits formed therein.

[0044] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading of the contents described in the specification. They are not intended to limit the scope of this application and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives of this application, should still fall within the scope of the technical content disclosed in this application. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.

[0045] It should also be noted that the longitudinal section corresponding to the embodiment of this application can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0046] Furthermore, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0047] refer to Figure 2 and Figure 3 , Figure 2 This is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor packaging structure 2a according to an embodiment of this application. Figure 3 yes Figure 2 The diagram shows a partially enlarged view of the semiconductor package structure 2a. Figure 2 and Figure 3 As shown, the semiconductor package structure 2a of this application includes:

[0048] Rewire layer 11;

[0049] A dielectric layer 12 is disposed above the redistribution layer 11, and a plurality of terminals 13 are disposed thereon;

[0050] A cavity 17 is disposed above the dielectric layer 12 and exposes a plurality of first terminals 131, wherein the plurality of first terminals 131 are a portion of the plurality of terminals 13;

[0051] An embedded element 15 is disposed between the redistribution layer 11 and the dielectric layer 12, and overlaps with the projection of the plurality of first terminals 131 in the vertical direction.

[0052] Here, the redistribution layer 11 can be composed of conductive and dielectric materials. It should be noted that the fabrication process can employ currently known or future-developed redistribution layer formation technologies; this application does not specifically limit this. For example, it can be formed using methods including, but not limited to, photolithography, electroplating, and electroless plating. Here, the dielectric material can include organic and / or inorganic materials. Organic materials can be, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, also known as prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while inorganic materials can be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material can include a seed layer and a metal layer. Here, the seed layer can be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., while the metal layer can be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or their alloys.

[0053] Here, the dielectric layer 12 can be formed of a dielectric material. The dielectric material can include organic and / or inorganic materials, wherein organic materials can be, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, also known as prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while inorganic materials can be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc.

[0054] Here, terminal 13 can be a conductive pad formed on dielectric layer 12, such as a copper pad, configured to connect to a chip, such as DRAM.

[0055] Here, cavity 17 is a hollow cavity defined by the material in semiconductor package structure 2a, located above the dielectric layer, exposing a plurality of first terminals 131. Cavity 17 is configured to accommodate a chip, such as DRAM.

[0056] Here, the embedded element 15 can be a chip, such as a chip formed on a silicon substrate. Further, the embedded element 15 may include, for example, bridging lines to provide wiring connectivity. Exemplarily, the embedded element 15 can be a functional chip such as a capacitor die, a deep trench capacitor (DTC), etc., to increase functionality.

[0057] Here, the embedded element 15 can be used to support the cavity 17 and the redistribution layer 11 located below the cavity 17 to enhance the structural strength of the area where the cavity 17 is located (i.e., the projection area of ​​the cavity 17 in the vertical direction).

[0058] In some optional embodiments, the semiconductor package structure 2a of this application further includes:

[0059] A bottom filler layer 14 is disposed above the dielectric layer 12;

[0060] A rigid member 16 is disposed above the dielectric layer 12 and surrounds a plurality of first terminals 131;

[0061] The rigid member 16 defines the cavity 17 described above, and a plurality of first terminals 131 are located inside the cavity 17. The bottom filling adhesive layer 14 is isolated outside the cavity 17 by the rigid member 16.

[0062] Here, the underfill layer 14 can be any type of underfill material (UF), such as capillary underfill (CUF), molded underfill (MUF), or non-conductive paste (NCP).

[0063] Here, rigid component 16 is a structural component formed of a rigid material, including but not limited to metallic materials such as copper and aluminum, or non-metallic materials such as ceramics, preferably materials with better heat dissipation performance. For example, commonly used heat sink materials can be used to make rigid component 16.

[0064] In some optional embodiments, the semiconductor package structure 2a of this application further includes: a first chip 23 disposed on the dielectric layer 12 in a manner arranged side-by-side with the rigid member 16; and a bottom filler layer 14 connecting the first chip 23, the rigid member 16, and the dielectric layer 12. Here, the first chip may be, for example, a system-on-a-chip (SoC die). In a fan-out multi-chip module (FOMCM), the system-on-a-chip may be a core unit integrating core computing and control functions, specifically including bare chips such as CPU (central processing unit) and GPU (graphics processing unit).

[0065] In some optional embodiments, the semiconductor packaging structure 2a of this application further includes: a molding layer 24 covering the first chip 23, the rigid member 16, and the bottom filler layer 14. Here, the molding layer 24 can be formed of various molding compounds. Exemplarily, molding compounds may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc. Exemplarily, the molding layer 24 may specifically be an epoxy molding compound (EMC).

[0066] As described above, the semiconductor package structure 2a of this application includes a redistribution layer 11, a dielectric layer 12, embedded components 15, a bottom filler layer 14, a first chip 23, and a rigid member 16. These components can collectively form a fan-out multi-chip module (FOMCM). However, unlike existing FOMCMs, dynamic random access memory (DRAM) is not yet assembled. Instead, a cavity 17 is defined using the rigid member 16, which is configured as a placement area for the DRAM. Unlike existing FOMCMs that bond the system-on-a-chip and DRAM together onto the RDL in the early stages of the manufacturing process, this application can confirm the structural functionality through electrical testing before placing the DRAM into the cavity 17. This avoids the risk of DRAM damage due to the loss of other components or materials, reduces material waste, improves DRAM availability, allows for better fan-out of the DRAM, improves product yield, enhances overall package stability, and reduces structural failure risk and manufacturing costs.

[0067] Furthermore, this application embeds an internal component 15 between the redistribution layer 11 and the dielectric layer 12, and the internal component 15 overlaps with the plurality of first terminals 131 in the vertical direction. Thus, the internal component 15 is located below the cavity 17, and the cavity 17 and the redistribution layer 11 below it are supported by the internal component 15, thereby preventing warping or deformation in this area, improving product reliability and stability, and increasing product yield. In addition, the internal component 15 can also provide bridging circuit functionality, thereby helping to improve the electrical performance of the product.

[0068] The detailed features of the semiconductor packaging structure 2a of this application will be described below.

[0069] In some alternative embodiments, the upper surfaces of the molding layer 24, the first chip 23, and the rigid member 16 are substantially flush. In terms of manufacturing process, the first chip 23 and the rigid member 16 can be exposed by grinding after the molding process, making their upper surfaces flush. Here, the upper surface (i.e., the back side) of the first chip 23 is exposed to the molding layer 24, which helps the first chip 23 dissipate heat and improves heat dissipation performance. It should be noted that "substantially flush" refers to a coplanar state within manufacturing tolerances.

[0070] In some alternative embodiments, the rigid member 16 may be composed of multiple metal blocks. Further, the rigid member 16 may be a square frame structure integrally connected from multiple metal blocks, with its four sides forming a frame of metal blocks, and a hollow cavity 17 in the center. Here, the cavity 17 is defined by the frame of metal blocks on its four sides, by the dielectric layer 12 at its bottom, and by an exposed opening at its top. A DRAM can then be placed into the cavity 17 through the opening at the top of the cavity 17.

[0071] In some alternative embodiments, the rigid member 16 is disposed on the dielectric layer 12 by an adhesive material 18 and a sealed connection is achieved. Here, the adhesive material 18 can be an organic adhesive, such as epoxy resin, or an inorganic adhesive, which is not limited in this application.

[0072] In some alternative embodiments, the plurality of terminals 13 on the dielectric layer 12 further include a plurality of second terminals 132 that overlap with the underfill adhesive layer 14 in the vertical direction, and the first chip 23 is electrically connected to the plurality of second terminals 132. Here, the first chip 23 may be bonded to the dielectric layer 12 by flip-chip bonding (FCB), that is, with the active surface facing the dielectric layer 12, and electrically connected to the plurality of second terminals 132 via bumps 29. The gap between the first chip 23 and the dielectric layer 12 may be filled by the underfill adhesive layer 14; the plurality of second terminals 132 and the plurality of bumps 29 may be covered by the underfill adhesive layer 14.

[0073] In some optional embodiments, the semiconductor package structure 2a of this application further includes: a molding interposer 22 disposed between the redistribution layer 11 and the dielectric layer 12, covering the embedded component 15. Here, the molding interposer 22, together with the embedded component 15, can support the upper dielectric layer 12 and the lower redistribution layer 11, reducing the risk of damage to the dielectric layer 12 and the redistribution layer 11 during the manufacturing process and transportation. Here, the molding interposer 22 can be formed of various molding compounds, and its specific material can be the same as or different from that of the molding layer 24.

[0074] In some optional embodiments, the embedded element 15 is divided, according to its projection in the vertical direction, into a first region 151 that overlaps with the bottom filling adhesive layer 14 and a second region 152 that overlaps with the cavity 17. The area of ​​the first region 151 may be smaller than the area of ​​the second region 152. That is, most of the embedded element 15 is located below the cavity 17, thereby improving support for the cavity 17 and the redistribution layer 11 below it. It should be understood that this application does not limit the area of ​​the first region 151 to necessarily being smaller than the area of ​​the second region 152; in some other optional embodiments, the area of ​​the first region 151 may also be equal to or greater than the area of ​​the second region 152.

[0075] In some alternative embodiments, in the vertical direction, the embedded element 15 extends from one side of the cavity 17 to the center / centerline of the cavity 17 and extends beyond it to increase the support strength of the cavity 17.

[0076] In some alternative implementations, the embedded element 15 is connected to the redistribution layer 11 using hybrid bonding. Hybrid bonding is an advanced 3D integrated circuit (3DIC) integration technology used to achieve high-density, high-performance chip interconnects. Hybrid bonding achieves chip interconnects by directly bonding the metal (typically copper) and dielectric layer (such as silicon oxide) on two structural components (e.g., chips, wafers, redistribution layers, etc.). Using hybrid bonding can reduce the bonding height of the embedded element 15, thereby helping to reduce the thickness of the molding interposer 22.

[0077] In some alternative embodiments, the upper surface of the embedded element 15 has a connecting pad 153, which is electrically connected to the terminal 13 (first terminal 131 and / or second terminal 132).

[0078] In some alternative embodiments, the embedded element 15 has a through-silicon via 154 to enable a through-hole electrical connection. For example, the through-silicon via 154 can be used to electrically connect the redistribution layer 11 and the connection pad 153.

[0079] In some alternative embodiments, the embedded element 15 has a bridging line (not shown in the figure) inside, which, for example, can electrically connect the first terminal 131 and the second terminal 132. For example, when a DRAM is embedded in the cavity 17, the DRAM can be electrically interconnected with the first chip 23 through the bridging line.

[0080] In some optional embodiments, the semiconductor package structure 2a of this application further includes: a first conductive post 21, arranged horizontally with the embedded element 15 and overlapping the cavity 17 vertically, electrically connecting the first terminal 131 and the redistribution layer 11. Here, the first conductive post 21 is covered by and passes through the molding interposer 22. Here, the first conductive post 21 can be used to transmit power signals. When DRAM is installed in the cavity 17, the DRAM power supply can pass through the first conductive post 21 from the side directly up and down to the redistribution layer 11, thereby shortening the electrical path and improving electrical performance.

[0081] In some alternative embodiments, when viewed from above, the center of the first conductive post 21 and the center of the first terminal 131 may be offset, such as... Figure 3 As shown. In the manufacturing process, the first conductive post 21 and the first terminal 131 can be formed separately, rather than integrally. Therefore, they can be aligned or offset to a certain extent in the vertical direction. The offset does not affect the electrical function.

[0082] In some optional embodiments, the semiconductor package structure 2a of this application further includes: a second conductive post 27 disposed between the redistribution layer 11 and the dielectric layer 12, overlapping the bottom filler layer 14 in the vertical direction, and electrically connecting the second terminal 132 to the redistribution layer 11. Here, the second conductive post 27 is covered by and passes through the molding interposer layer 22. Here, by vertically connecting the first chip 23 and the redistribution layer 11 through the second conductive post 27, the electrical path can be shortened and the electrical performance can be improved.

[0083] In some optional embodiments, the semiconductor package structure 2a of this application embodiment further includes an electrical connector 28 disposed on the side surface of the redistribution layer 11 facing away from the dielectric layer 12. For example, the electrical connector 28 may be a C4 (Controlled Collapsed Chip Connection) bump.

[0084] Next, refer to Figure 4 , Figure 4 This is a longitudinal cross-sectional view of a semiconductor packaging structure 4a according to an embodiment of this application. Figure 4 The semiconductor package structure 4a shown is similar to Figure 2 The semiconductor package structure 2a shown differs in that:

[0085] In the semiconductor package structure 4a, a surrounding metal pad 19 is provided on the dielectric layer 12, and a rigid member 16 is bonded to the metal pad 19 by solder 20. Here, the rigid member 16 is bonded to the dielectric layer 12 by soldering, which results in higher bonding strength and better thermal conductivity and heat dissipation performance compared to bonding by adhesive material 18.

[0086] In some alternative embodiments, the surface of the metal pad 19 may have a silver plating layer to improve its solderability with the rigid member 16.

[0087] Next, refer to Figure 5 , Figure 5 This is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor packaging structure 5a according to an embodiment of this application. Figure 5 The semiconductor package structure 5a shown is similar to Figure 2 The semiconductor package structure 2a shown differs in that:

[0088] The semiconductor package structure 5a further includes a second chip 25. The second chip 25 is disposed within the cavity 17 and electrically connected to a plurality of first terminals 131.

[0089] Here, the second chip 25 can be a dynamic random access memory (DRAM).

[0090] In some optional embodiments, the semiconductor package structure 5a further includes a filler layer 26 covering the second chip 25. Here, the filler layer 26 may be an underfill adhesive or a molding compound, etc., and this application is not limited thereto.

[0091] In some alternative embodiments, the filler layer 26 fills and saturates the cavity 17, thereby protecting the second chip 25.

[0092] In some alternative embodiments, the upper surface of the molding layer 24 and the upper surface of the filler layer 26 are substantially flush, with the first chip 23 exposed above the molding layer 24 and the second chip 25 completely embedded in the filler layer 26. It should be noted that "substantially flush" refers to a coplanar state within manufacturing tolerances.

[0093] Next, refer to Figures 6 to 7 , Figures 6 to 7 This is a schematic diagram illustrating the manufacturing steps of a semiconductor packaging structure according to an embodiment of this application. Figures 6 to 7 As shown, the manufacturing process of the semiconductor packaging structure of this application may include the following steps.

[0094] Step S1: Provide a carrier 30, fabricate a redistribution layer 11 on the carrier 30, and fabricate a plurality of first conductive pillars 21 and a plurality of second conductive pillars 27 in two different regions on the redistribution layer 11.

[0095] Step S2: Provide an embedded element 15 and bond the embedded element 15 to the redistribution layer 11 using a hybrid bonding method. Optionally, the embedded element 15 is closer to the first conductive post 21 relative to the second conductive post 27.

[0096] Step S3: Perform the first molding to form a molding interlayer 22 that covers the embedded component 15, the first conductive post 21, and the second conductive post 27.

[0097] Step S4: By grinding, the molding interlayer 22 is thinned to expose the embedded component 15, the first conductive post 21 and the second conductive post 27.

[0098] Step S5: A dielectric layer 12 is disposed on the molding intermediary layer 22, and multiple terminals 13 are fabricated on the dielectric layer 12. The multiple terminals 13 can be electrically connected to the embedded component 15, the first conductive post 21 and the second conductive post 27 respectively.

[0099] Step S6: Provide a first chip 23 and a rigid component 16. The first chip 23 may be a system-on-a-chip. The rigid component 16 may be a square frame structure with openings at both the top and bottom, and the opening at the top is covered and closed by a top cover 161.

[0100] In this step, the rigid member 16 (including the top cover 161) can be bonded and fixed to the dielectric layer 12 (e.g., on the right side) using adhesive material 18, and the plurality of first terminals 131 of the plurality of terminals 13 can be accommodated in the cavity 17 defined by the rigid member 16. Alternatively, the rigid member 16 (including the top cover 161) can be soldered to the metal pad 19 on the dielectric layer 12 using solder 20.

[0101] In this step, the active surface of the first chip 23 faces the dielectric layer 12 and is mounted on the dielectric layer 12 (e.g., on the left side) using flip-chip bonding (FCB). It is electrically connected to the second terminal in this area via bumps 29. In this step, an underfill adhesive layer 14 may be further provided, connecting the first chip 23, the rigid member 16, and the dielectric layer 12. The underfill adhesive layer 14 is isolated outside the cavity 17 by the rigid member 16.

[0102] Here, since the rigid member 16 is directly bonded or welded to the upper surface of the dielectric layer 12 and seals the covered area, the bottom filler layer 14 is mainly located below and around the first chip 23, or on the side of the rigid member 16 or on top of the rigid member 16, but does not completely surround the rigid member 16.

[0103] Step S7: Perform a second molding process to form a molding layer 24 that covers the first chip 23, the rigid component 16, and the bottom filling adhesive layer 14. During this second molding process, the top cover 161 protects the molding material from being poured into the cavity 17 inside the rigid component 16.

[0104] Optionally, the width of the molding interlayer 22 and the dielectric layer 12 may be smaller than the width of the redistribution layer 11, so that the upper surface portion of the redistribution layer 11 is exposed and covered by the molding layer 24.

[0105] Step S8: Trim the molding layer 24 and remove the carrier 30. At this time, the circuit structure in the structure (including the redistribution layer 11, the molding interposer layer 22, the embedded components 15, and the dielectric layer 12) is supported by the molding layer 24.

[0106] Step S9: An electrical connector 28 is disposed on the surface of the redistribution layer 11 facing away from the molding layer 24. For example, C4 bumps can be disposed as electrical connectors 28 by physical vapor deposition (PVD) technology and C4 bump metallization process.

[0107] Step S10: Another carrier 30 is provided as a support structure on the side of the redistribution layer 11 where the electrical connector 28 is provided. Then, the molding layer 24 is thinned by, for example, panel grinding, so that the first chip 23 is exposed in the molding layer 24. In addition, the top cover 161 on the top of the rigid member 16 is removed, so that the cavity 17 defined by the rigid member 16 is exposed. Thus, a package unit including the redistribution layer 11, the molding interposer layer 22, the embedded component 15, the dielectric layer 12, the first chip 23, and the rigid member 16 is obtained.

[0108] It is worth noting that the above steps S1-S10 can be performed using panel-level processes, and many packaging units will be formed on a single panel.

[0109] Step S8: The monomerization process is completed by cutting, and the carrier 30 is removed to obtain an independent single encapsulation unit. This encapsulation unit is as follows: Figure 2 The semiconductor package structure 2a is shown. The semiconductor package structure 2a can be shipped as a finished product, and the user can then install the required components in the cavity 17.

[0110] refer to Figure 5 Optionally, a second chip 25 (e.g., DRAM) can be further disposed within the cavity 17, and a filler layer 26 can be disposed within the cavity 17 to encapsulate and protect the second chip 25, and to fill the cavity 17 completely. Thus, the following is obtained: Figure 5 The semiconductor packaging structure 5a shown is illustrated.

[0111] Although this application has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not limiting of this application. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this application as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this application and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this application may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this application. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this application. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this application.

Claims

1. A semiconductor packaging structure, characterized in that, include: Rewire layer; A dielectric layer is disposed above the redistribution layer, and multiple terminals are disposed thereon; A cavity is disposed above the dielectric layer and exposes a plurality of first terminals, wherein the plurality of first terminals are a portion of the plurality of terminals; An embedded component is disposed between the redistribution layer and the dielectric layer, overlapping the projection of the plurality of first terminals in the vertical direction.

2. The semiconductor packaging structure according to claim 1, characterized in that, Further includes: A bottom filler layer is disposed above the dielectric layer; A rigid member is disposed above the dielectric layer and surrounds the plurality of first terminals; The rigid member defines the cavity, the plurality of first terminals are located inside the cavity, and the bottom filling adhesive layer is isolated outside the cavity by the rigid member.

3. The semiconductor packaging structure according to claim 2, characterized in that, The rigid component is composed of multiple metal blocks.

4. The semiconductor packaging structure according to claim 2, characterized in that, The embedded element supports the cavity and the redistribution layer located below the cavity.

5. The semiconductor packaging structure according to claim 4, characterized in that, The embedded element is divided into a first region that overlaps with the bottom filling adhesive layer and a second region that overlaps with the cavity, according to its projection in the vertical direction.

6. The semiconductor packaging structure according to claim 5, characterized in that, The area of ​​the first zone is smaller than the area of ​​the second zone.

7. The semiconductor packaging structure according to claim 2, characterized in that, The rigid component is mounted on the dielectric layer using an adhesive material.

8. The semiconductor packaging structure according to claim 3, characterized in that, A surrounding metal pad is disposed on the dielectric layer, and the rigid member is bonded to the metal pad by solder.

9. The semiconductor packaging structure according to claim 2, characterized in that, Further includes: The first conductive post is arranged horizontally with the embedded element and overlaps vertically with the cavity, and is used to electrically connect the first terminal and the redistribution layer.

10. The semiconductor packaging structure according to claim 9, characterized in that, Viewed from above, the center of the first conductive post is offset from the center of the first terminal.

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