Chip package

Abstract

The utility model discloses a kind of chip package, including first soldering pad, the first insulating layer of wrapping first soldering pad, second soldering pad being set on the surface of first insulating layer, chip being set on at least one second soldering pad, plastic package being set on the surface of first insulating layer and wrapping second soldering pad and chip, circuit layer being set on plastic package and with second soldering pad and / or chip conductive connection;First soldering pad thickening setting forms thickening soldering pad, protrudes the surface of first insulating layer.In the utility model, first insulating layer wraps first soldering pad, shorten the distance between first soldering pad and second soldering pad, shorten heat transfer distance, improve heat dissipation efficiency;Second soldering pad is set on the surface of first insulating layer, chip is attached on second soldering pad, without polishing to first insulating layer to expose soldering pad, avoid polishing to produce uneven thickness problem;First soldering pad thickening processing forms thickening soldering pad protruding first insulating layer, improve accurate positioning when external connection, avoid appearing problem of false welding.

Description

Technical Field

[0001] This utility model relates to the field of chip packaging technology, and in particular to a chip package. Background Technology

[0002] Some existing chip packages are fabricated by first raising copper on a carrier to form pads, then pressing a dielectric layer onto one side of the pads, and finally grinding the dielectric layer to expose the pads. The carrier at the bottom is then etched away to expose the bottom surface of the pads before mounting the chip and molding the package. This method has the following problems: exposing the pads by grinding the dielectric layer makes it difficult to control the uniformity of the dielectric layer thickness; after grinding, the pad surface is flush with the dielectric layer surface, which can easily lead to cold solder joints during external soldering, affecting the soldering effect; etching away the carrier can easily result in an uneven bottom surface of the pads, posing a risk of chip tilting and thus affecting product quality. Utility Model Content

[0003] The technical problem to be solved by this utility model is to provide an improved chip package.

[0004] The technical solution adopted by this utility model to solve its technical problem is: to provide a chip package, including a first pad, a first insulating layer covering the first pad, a second pad disposed on a surface of the first insulating layer and electrically connected to the first pad, a chip disposed on at least one of the second pads, a molding compound disposed on a surface of the first insulating layer and covering the second pad and the chip, and a circuit layer disposed on the molding compound and electrically connected to the second pad and / or the chip.

[0005] The first pad is thickened to form a thickened pad, and its surface facing away from the second pad protrudes from the surface of the first insulating layer facing away from the molding compound.

[0006] In one embodiment, a first conductive hole is provided in the first insulating layer, and the second pad is electrically connected to the first pad through the first conductive hole.

[0007] In one embodiment, the first conductive hole is a straight hole.

[0008] In one embodiment, a second conductive hole is provided within the molding compound; the second conductive hole extends onto the chip, and the circuit layer is electrically connected to the chip through the second conductive hole.

[0009] In one embodiment, the second conductive hole is a straight hole or a tapered hole.

[0010] In one embodiment, the molding compound has a third conductive via; the third conductive via extends to the second pad on which no chip is mounted, and the circuit layer is electrically connected to the second pad on which no chip is mounted through the third conductive via.

[0011] In one embodiment, the third conductive hole is a straight hole or a tapered hole.

[0012] In one embodiment, the thickness of the second pad is less than the thickness of the thickened pad.

[0013] In one embodiment, the vertical distance between the second pad and the first pad is less than the thickness of the first insulating layer.

[0014] In one embodiment, the chip package further includes a second insulating layer that covers the molding compound and encapsulates the circuit layer.

[0015] The beneficial effects of this utility model are as follows: The first insulating layer wraps around the first pad, shortening the distance between the first pad and the second pad, thereby shortening the heat transfer distance and improving heat dissipation efficiency; The second pad is set on the surface of the first insulating layer, and the chip is mounted on the second pad without grinding the first insulating layer to expose the pad, avoiding the problem of uneven thickness caused by grinding; The first pad is used for external connection, and by thickening the first pad to form a thickened pad protruding from the first insulating layer, the positioning accuracy during external connection is improved, and the problem of cold solder joints is avoided. Attached Figure Description

[0016] The present invention will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings:

[0017] Figure 1 This is a cross-sectional structural diagram of a chip package according to an embodiment of the present invention. Detailed Implementation

[0018] To provide a clearer understanding of the technical features, objectives, and effects of this utility model, the specific embodiments of this utility model will now be described in detail with reference to the accompanying drawings.

[0019] like Figure 1 As shown, a chip package according to an embodiment of the present invention may include at least one first pad 10, at least one second pad 20, a first insulating layer 11, at least one chip 30, a molding compound 40, and a circuit layer 50.

[0020] In this design, a first insulating layer 11 encapsulates a first pad 10, and a second pad 20 is disposed on the first insulating layer 11 and electrically connected to the first pad 10. A chip 30 is disposed on at least one second pad 20 and electrically connected to the second pad 20. A molding compound 40 is disposed on the first insulating layer 11 and encapsulates the second pad 20 and the chip 30. A circuit layer 50 is disposed on the molding compound 40 and electrically connected to the second pad 20 and / or the chip 30.

[0021] Specifically, the first insulating layer 11 covers one surface and all four sides of the first pad 10, making the first pad 10 embedded in the first insulating layer 11, while the opposite surface of the first pad 10 exposes the first insulating layer 11; the second pad 20 is disposed on one surface of the first insulating layer 11 and is electrically connected to the first pad 10. The two opposing surfaces of the first insulating layer 11 are divided into a first surface and a second surface. The first pad 10 is covered by the first insulating layer 11 and the second surface of the first insulating layer 11 is exposed; the second pad 20 is disposed on the first surface of the first insulating layer 11.

[0022] The exposed surface of the first pad 10 is flush with the second surface of the first insulating layer 11. To avoid cold solder joints, the first pad 10 is thickened by means of electroplating copper expansion, thus forming a thickened pad 100. The thickened pad 100 protrudes from the second surface of the first insulating layer 11, that is, it protrudes from the surface of the first insulating layer 11 facing away from the molding compound 40, which allows for more accurate alignment during external soldering.

[0023] Preferably, there are a plurality of first pads 10, which are spaced apart. The number and position of the second pads 20 correspond to the first pads 10, so that each second pad 20 is directly opposite and electrically connected to a first pad 10.

[0024] The outer perimeter of the second pad 20 can be equivalent to, or smaller than or larger than, the outer perimeter of the first pad 10, to ensure that the second pad 20 has sufficient area to mount the chip.

[0025] The surface of the second pad 20 is flat, which is used for chip mounting and ensures that the chip is mounted vertically, avoiding the risk of chip tilting.

[0026] The first insulating layer 11 has a first conductive hole 21, and each second pad 20 is electrically connected to the corresponding first pad 10 through the corresponding first conductive hole 21. The first conductive hole 21 can be formed at the same time as the second pad 20 is set. For example, the second pad 20 is formed by electroplating and etching on the first insulating layer 11. During electroplating, the blind holes in the first insulating layer 11 are also electroplated to form the first conductive hole 21.

[0027] The first conductive hole 21 can be a straight hole or a tapered hole.

[0028] The depth of the first conductive hole 21 is also the vertical distance between the first pad 10 and the second pad 20. Since the first pad 10 is enclosed in the first insulating layer 11, the vertical distance between the first pad 10 and the second pad 20 is less than the thickness of the first insulating layer 11.

[0029] Of all the second pads 20, at least one second pad 20 has a chip 30 mounted on it, while the remaining second pads 20 are second pads 20 without a chip mounted on them.

[0030] The molding compound 40 covers the first surface of the first insulating layer 11, and encapsulates the chip 30, the second pad 20 where the chip 30 is located, and the second pad 20 where no chip is mounted. The circuit layer 50 can be formed on the surface of the molding compound 40 facing away from the first insulating layer 11 by electroplating or the like.

[0031] The encapsulation body 40 can be formed using common encapsulating adhesives such as epoxy resin and polyester resin.

[0032] To achieve a conductive connection between the circuit layer 50 and the chip 30, a second conductive hole 41 is provided in the molding compound 40. The second conductive hole 41 extends onto the chip 30, and the circuit layer 50 is conductively connected to the chip 30 through the second conductive hole 41.

[0033] The second conductive via 41 is formed by a blind via and a conductive layer disposed therein. When the circuit layer 50 is formed by electroplating on the surface of the molding compound 40, the inner wall of the blind via formed on the molding compound 40 is also electroplated. The electroplated layer on the inner wall of the blind via forms a conductive layer, which, together with the blind via, forms the second conductive via 41. The second conductive via 41 can be a straight via or a tapered via; a tapered via has a larger internal plating area than a straight via.

[0034] To achieve conductive connection between the circuit layer 50 and the second pad 20 without a chip, a third conductive hole 42 is provided in the molding compound 40. The third conductive hole 42 extends to the second pad 20 without a chip, and the circuit layer 50 is conductively connected to the second pad 20 without a chip through the third conductive hole 42.

[0035] The third conductive via 42 is formed by a blind via and a conductive layer disposed therein. When the circuit layer 50 is formed by electroplating on the surface of the molding compound 40, the inner wall of the blind via formed on the molding compound 40 is also electroplated. The electroplated layer on the inner wall of the blind via forms a conductive layer, which, together with the blind via, forms the third conductive via 42. The third conductive via 42 can be a straight via or a tapered via; a tapered via has a larger internal plating area than a straight via.

[0036] Chip 30 and the second pad 20 without a chip are also interconnected via circuit layer 50.

[0037] Furthermore, the chip package may also include a second insulating layer 12, which covers the molding compound 40 and wraps the circuit layer 50.

[0038] The second insulating layer 12 can be formed in the same way and with the same material as the first insulating layer 11, using insulating materials such as polypropylene.

[0039] In the fabrication of the chip package of this invention, firstly, a first pad 10 is formed by electroplating on a carrier. A first insulating layer 11 is then pressed onto the carrier and encapsulates the first pad 10. An electroplated layer is formed on the first insulating layer 11, and the electroplated layer is etched to form a second pad 20, ensuring that the second pad 20 is directly opposite and electrically connected to the first pad 10. A chip 30 is mounted on at least one of the second pads 20. A molding compound 40 is disposed on the first insulating layer 11, encapsulating the chip 30 and all the second pads 20 within it. A circuit layer 50 is disposed on the molding compound 40, electrically connecting the chip 30 and / or the second pads 20 without a chip mounted. Finally, the carrier is removed, exposing the surface of the first pad 10 facing away from the second pads 20. A thickened electroplating layer is then applied to the surface of the first pad 10, forming a thickened pad 100 that protrudes from the first insulating layer 11.

[0040] This also includes providing a second insulating layer 12 on the circuit layer 50, which encloses the circuit layer 50.

[0041] The above description is merely an embodiment of this utility model and does not limit the patent scope of this utility model. Any equivalent structural or procedural transformations made based on the description and drawings of this utility model, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this utility model.

Claims

1. A chip package, characterized in that, It includes a first pad, a first insulating layer covering the first pad, a second pad disposed on a surface of the first insulating layer and electrically connected to the first pad, a chip disposed on at least one of the second pads, a molding compound disposed on a surface of the first insulating layer and covering the second pads and the chip, and a circuit layer disposed on the molding compound and electrically connected to the second pads and / or the chip. The first pad is thickened to form a thickened pad, and its surface facing away from the second pad protrudes from the surface of the first insulating layer facing away from the molding compound.

2. The chip package according to claim 1, characterized in that, The first insulating layer has a first conductive hole, and the second pad is electrically connected to the first pad through the first conductive hole.

3. The chip package according to claim 2, characterized in that, The first conductive hole is a straight hole.

4. The chip package according to claim 1, characterized in that, The molding compound has a second conductive hole; the second conductive hole extends onto the chip, and the circuit layer is electrically connected to the chip through the second conductive hole.

5. The chip package according to claim 4, characterized in that, The second conductive hole is a straight hole or a tapered hole.

6. The chip package according to claim 4, characterized in that, The molding compound has a third conductive hole; the third conductive hole extends to the second pad where no chip is mounted, and the circuit layer is electrically connected to the second pad where no chip is mounted through the third conductive hole.

7. The chip package according to claim 6, characterized in that, The third conductive hole is either a straight hole or a tapered hole.

8. The chip package according to claim 1, characterized in that, The thickness of the second pad is less than the thickness of the thickened pad.

9. The chip package according to claim 1, characterized in that, The vertical distance between the second pad and the first pad is less than the thickness of the first insulating layer.

10. The chip package according to any one of claims 1-9, characterized in that, The chip package further includes a second insulating layer, which covers the molding compound and encapsulates the circuit layer.

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