Power distribution network primary and secondary deep fusion ftu power taking circuit system

Abstract

This utility model proposes a deep integration primary and secondary FTU power harvesting circuit system for power distribution networks, comprising: a voltage divider circuit, a rectifier circuit, and a waveform correction circuit; the voltage divider circuit is electrically connected to the rectifier circuit, and the rectifier circuit is electrically connected to the waveform correction circuit; the deep integration primary and secondary FTU power harvesting circuit system for power distribution networks adopts a combined design of a voltage divider circuit and a waveform correction circuit. The waveform correction circuit ensures that the rectified voltage and current are in phase and the output voltage is stable, making the overall load on the secondary side of the transformer resistive, thereby improving power supply stability and reducing reactive power generation.

Description

Technical Field

[0001] This utility model relates to the field of power distribution network technology, and in particular to a deep integration of primary and secondary FTU power harvesting circuit system for power distribution networks. Background Technology

[0002] With the continuous updating and development of technologies related to the deep integration of primary and secondary FTUs, the requirements are becoming increasingly stringent. Considering that most existing power supply circuits in power distribution networks use rectifier bridges followed by capacitors, which generate a large amount of reactive power, while the impact of a single device on the line is relatively small, the cumulative impact is significant when multiple devices are connected to the line. Therefore, it is necessary to provide a new type of power supply circuit to overcome these shortcomings.

[0003] Therefore, it is necessary to provide a deep integration FTU power harvesting circuit system for primary and secondary distribution networks to solve the above problems. Utility Model Content

[0004] The purpose of this invention is to provide a deep integration of primary and secondary FTU power extraction circuit system for power distribution networks. It adopts a combination design of voltage divider circuit and waveform correction circuit. The waveform correction circuit makes the rectified voltage and current in phase and the output voltage stable, so that the load on the secondary side of the transformer is resistive, thereby improving power supply stability and reducing reactive power generation.

[0005] To achieve the above objectives, the technical solution proposed in this utility model is as follows: a deep integration of primary and secondary FTU energy harvesting circuit system for power distribution networks, characterized in that it includes: a voltage divider circuit, a rectifier circuit, and a waveform correction circuit; the voltage divider circuit is electrically connected to the rectifier circuit, and the rectifier circuit is electrically connected to the waveform correction circuit. The waveform correction circuit includes capacitor C2, inductor L1, resistor R1, resistor R3, capacitor C3, capacitor C5, a waveform correction module, a MOSFET, diode D2, diode D3, and load resistor RL. The first terminal of capacitor C2 is electrically connected to the third terminal of the rectifier circuit, the first terminal of inductor L1, and pin e of the waveform correction module. The second terminal of capacitor C2 is electrically connected to the fourth terminal of the rectifier circuit and pin d of the waveform correction module, and is grounded. The second end of the inductor L1 is electrically connected to the first end of the resistor R1, the first end of the capacitor C3, pin b of the waveform correction module, and the drain of the MOSFET D4. The second end of the resistor R1 is grounded, and the second end of the capacitor C3 is electrically connected to the second end of the resistor R2 and grounded. The first end of resistor R3 is electrically connected to the second end of resistor R1. The second end of resistor R3 is electrically connected to the first end of capacitor C5 and pin a of the waveform correction module. The second end of capacitor C5 is grounded. The gate of MOSFET D4 is electrically connected to pin c of the waveform correction module. The source of MOSFET D4 is electrically connected to pin d of the waveform correction module, the anode of diode D2, the first end of capacitor C6, and the first end of load resistor RL. The cathode of diode D2 is electrically connected to the drain of MOSFET D4 and the anode of diode D3. The cathode of diode D3 is electrically connected to the second end of capacitor C6 and the second end of load resistor RL.

[0006] Preferably, the waveform correction circuit further includes a resistor R2 and a capacitor C4, wherein the first end of the resistor R2 is electrically connected to the second end of the resistor R1, and the second end of the resistor R2 is grounded. The first terminal of capacitor C4 is electrically connected to the second terminal of capacitor C3, and the second terminal of capacitor C4 is electrically connected to the second terminal of resistor R2 and grounded.

[0007] Preferably, the voltage divider circuit includes capacitor C1, transformer TX1, varistor MOV1, varistor MOV2, capacitor C14, capacitor C16, varistor MOV3, inductor L2, inductor L3, common mode inductor L4, resistor R4, and capacitor C11. The first terminal of capacitor C1 is connected to an external power source. The second terminal of capacitor C1 is electrically connected to the first terminal of the primary winding of the transformer. The second terminal of the primary winding of the transformer is connected to an external power source. The first terminal of the secondary winding of the transformer is electrically connected to the first terminals of varistor MOV1, capacitor C14, capacitor C16, varistor MOV3, and inductor L3. The second terminal of varistor MOV1 is electrically connected to the second terminal of capacitor C14 and grounded. The second terminal of the secondary winding of the transformer is electrically connected to the first terminals of varistor MOV2, capacitor C16, varistor MOV3, and inductor L2. The second terminal of the varistor MOV2 is electrically connected to the second terminal of capacitor C16, the first terminal of inductor L2, the second terminal of inductor L3, and the second terminal of inductor L3, and is grounded. The second end of inductor L2 is electrically connected to the first coil of common-mode inductor L4. The second end of inductor L3 is electrically connected to the second coil of common-mode inductor L4. The first coil of common-mode inductor L4 is electrically connected to the first end of capacitor C11, the second end of varistor MOV2, and the second end of rectifier circuit. The second coil of common-mode inductor L4 is electrically connected to the first end of resistor R4 and the first end of rectifier circuit. The second end of resistor R4 is electrically connected to the second end of capacitor C11.

[0008] Preferably, the voltage divider circuit further includes capacitors C15, C7, C8, C9, and C10; the first terminal of capacitor C15 is electrically connected to the second terminal of capacitor C16, and the second terminal of capacitor C15 is electrically connected to the second terminal of varistor MOV2 and grounded. The first terminal of capacitor C7 is electrically connected to the first terminal of inductor L3. The second terminal of capacitor C7 is electrically connected to the first terminal of capacitor C8 and the second terminal of varistor MOV2. The second terminal of capacitor C8 is electrically connected to the first terminal of inductor L2. The first terminal of capacitor C9 is electrically connected to the second terminal of inductor L3. The second terminal of capacitor C9 is electrically connected to the first terminal of capacitor C10 and the second terminal of varistor MOV2. The second terminal of capacitor C10 is electrically connected to the second terminal of inductor L2.

[0009] Preferably, the voltage divider circuit includes capacitor C12 and capacitor C13; the first end of capacitor C12 is electrically connected to the first end of resistor R4, the second end of capacitor C12 is electrically connected to the first end of capacitor C13 and the second end of varistor MOV2, and the second end of capacitor C13 is electrically connected to the first end of capacitor C11.

[0010] Compared with existing technologies, the beneficial effects are that the combined design of voltage divider circuit and waveform correction circuit ensures that the rectified voltage and current are in phase and the output voltage is stable. This makes the load on the secondary side of the transformer resistive, and there is always current in the circuit of waveform correction circuit, so that the current of the rectifier circuit will not be interrupted. This improves the power factor and power supply stability, and achieves the effect of reducing reactive power generation.

[0011] Other features and advantages of this invention will be set forth in the following description, and in part will be apparent from the description, or may be learned by practice of the invention. The features and advantages of this invention may be realized and obtained by means of the elements and combinations specifically pointed out in the appended claims. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. Figure 1 The circuit diagram of the deep integration of primary and secondary FTU power harvesting circuit system for power distribution networks provided by this utility model. Detailed Implementation

[0013] To make the objectives, technical solutions, and beneficial effects of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described in this specification are merely for explaining the present utility model and are not intended to limit the present utility model.

[0014] It should be understood that the terms "upper", "lower", "front", "back", "left", "right", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0015] It should also be noted that, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "joining," "fixing," and "setting" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in this utility model can be understood according to the specific circumstances.

[0016] Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. Additionally, "multiple" and "several" mean two or more, unless otherwise explicitly specified.

[0017] Please see Figure 1 This utility model provides a 10kV distribution network primary and secondary deep integration FTU energy harvesting circuit system, including: voltage divider circuit, rectifier circuit and waveform correction circuit; The voltage divider circuit is electrically connected to the rectifier circuit, and the rectifier circuit is electrically connected to the waveform correction circuit. The waveform correction circuit includes capacitor C2, inductor L1, resistors R1 and R3, capacitor C3 and C5, a waveform correction module, a MOSFET, diodes D2 and D3, and a load resistor RL. The first terminal of capacitor C2 is electrically connected to the third terminal of the rectifier circuit, the first terminal of inductor L1, and pin e of the waveform correction module. The second terminal of capacitor C2 is electrically connected to the fourth terminal of the rectifier circuit and pin d of the waveform correction module, and is grounded. The second end of the inductor L1 is electrically connected to the first end of the resistor R1, the first end of the capacitor C3, pin b of the waveform correction module, and the drain of the MOSFET D4. The second end of the resistor R1 is grounded, and the second end of the capacitor C3 is electrically connected to the second end of the resistor R2 and grounded. The first end of resistor R3 is electrically connected to the second end of resistor R1. The second end of resistor R3 is electrically connected to the first end of capacitor C5 and pin a of the waveform correction module. The second end of capacitor C5 is grounded. The gate of MOSFET D4 is electrically connected to pin c of the waveform correction module. The source of MOSFET D4 is electrically connected to pin d of the waveform correction module, the anode of diode D2, the first end of capacitor C6, and the first end of load resistor RL. The cathode of diode D2 is electrically connected to the drain of MOSFET D4 and the anode of diode D3. The cathode of diode D3 is electrically connected to the second end of capacitor C6 and the second end of load resistor RL. The rectifier circuit is used to convert AC circuit into DC circuit, and the waveform correction module is used to adjust the waveform of the current so that the current and voltage are in phase, thereby making the overall load on the secondary side of the transformer basically stable and resistive.

[0018] It should be noted that the rectifier circuit is a rectifier bridge composed of four diodes, which converts the AC power on the secondary side of the transformer into DC power, and the waveform correction module is a UCC28056 PFC controller.

[0019] When MOSFET D4 is turned on, current flows only through inductor L1. As the current in inductor L1 increases, diode D3 turns on to supply power to the load resistor RL. The load resistor RL draws energy to supply the FTU at the back end. When MOSFET D4 is turned off, the current stored in inductor L1 supplies power to capacitor C6 and load resistor RL through diode D3. The load resistor RL draws energy to supply the FTU at the back end.

[0020] Regardless of whether MOSFET D4 is turned on or off, there is always current in the waveform correction circuit loop, and there will be no interruption of current in the rectifier circuit. This improves the power factor and reduces reactive power generation.

[0021] In a preferred embodiment, the waveform correction circuit further includes a resistor R2 and a capacitor C4, wherein the first end of the resistor R2 is electrically connected to the second end of the resistor R1, and the second end of the resistor R2 is grounded. The first terminal of capacitor C4 is electrically connected to the second terminal of capacitor C3, and the second terminal of capacitor C4 is electrically connected to the second terminal of resistor R2 and grounded.

[0022] In a preferred embodiment, the voltage divider circuit includes capacitor C1, transformer TX1, varistor MOV1, varistor MOV2, capacitor C14, capacitor C16, varistor MOV3, inductor L2, inductor L3, common mode inductor L4, resistor R4, and capacitor C11. The first terminal of capacitor C1 is connected to an external power source. The second terminal of capacitor C1 is electrically connected to the first terminal of the primary winding of the transformer. The second terminal of the primary winding of the transformer is connected to an external power source. The first terminal of the secondary winding of the transformer is electrically connected to the first terminals of varistor MOV1, capacitor C14, capacitor C16, varistor MOV3, and inductor L3. The second terminal of varistor MOV1 is electrically connected to the second terminal of capacitor C14 and grounded. The second terminal of the secondary winding of the transformer is electrically connected to the first terminals of varistor MOV2, capacitor C16, varistor MOV3, and inductor L2. The second terminal of the varistor MOV2 is electrically connected to the second terminal of capacitor C16, the first terminal of inductor L2, the second terminal of inductor L3, and the second terminal of inductor L3, and is grounded. The second end of inductor L2 is electrically connected to the first coil of common-mode inductor L4. The second end of inductor L3 is electrically connected to the second coil of common-mode inductor L4. The first coil of common-mode inductor L4 is electrically connected to the first end of capacitor C11, the second end of varistor MOV2, and the second end of rectifier circuit. The second coil of common-mode inductor L4 is electrically connected to the first end of resistor R4 and the first end of rectifier circuit. The second end of resistor R4 is electrically connected to the second end of capacitor C11.

[0023] In this circuit, the capacitive reactance of capacitor C1 is much greater than the inductive reactance of transformer TX1, resulting in a smaller voltage on the primary side of the transformer. This effectively reduces the voltage on the primary side of the transformer. The voltage divider circuit mainly serves as EMC protection, protecting downstream circuits and preventing lightning surges from damaging downstream devices.

[0024] In a preferred embodiment, the voltage divider circuit further includes capacitors C15, C7, C8, C9, and C10; the first terminal of capacitor C15 is electrically connected to the second terminal of capacitor C16, and the second terminal of capacitor C15 is electrically connected to the second terminal of varistor MOV2 and grounded. The first terminal of capacitor C7 is electrically connected to the first terminal of inductor L3. The second terminal of capacitor C7 is electrically connected to the first terminal of capacitor C8 and the second terminal of varistor MOV2. The second terminal of capacitor C8 is electrically connected to the first terminal of inductor L2. The first terminal of capacitor C9 is electrically connected to the second terminal of inductor L3. The second terminal of capacitor C9 is electrically connected to the first terminal of capacitor C10 and the second terminal of varistor MOV2. The second terminal of capacitor C10 is electrically connected to the second terminal of inductor L2.

[0025] In a preferred embodiment, the voltage divider circuit includes capacitor C12 and capacitor C13; the first terminal of capacitor C12 is electrically connected to the first terminal of resistor R4, the second terminal of capacitor C12 is electrically connected to the first terminal of capacitor C13 and the second terminal of varistor MOV2, and the second terminal of capacitor C13 is electrically connected to the first terminal of capacitor C11.

[0026] Through the above design, multiple capacitors (such as capacitors C7, C8, C9, C10, C11, C12, C13, C14, C15, and C16) can be used to filter out common-mode interference and differential-mode interference.

[0027] The 10kV distribution network primary and secondary deep integration FTU power harvesting circuit system is composed of three parts: voltage divider circuit, rectifier circuit and waveform correction circuit.

[0028] Working principle: The rectifier circuit supplies power to pins b and d of the waveform correction control module. The waveform correction module has pins a and e as voltage tracking circuits. The voltage waveform is tracked and the switching state of MOSFET D4 is adjusted through the circuit at pin c to achieve waveform correction, so that the entire load from the secondary side of the transformer is basically stable and exhibits resistive characteristics.

[0029] The resistors R1 and R2 are used to divide the voltage and track the waveform and voltage value of the voltage tracking circuit. The capacitors C3 and C4 utilize the characteristic that the voltage across the capacitor cannot change abruptly to achieve fast tracking. The resistors R3 and C5 filter abnormal disturbances. The diode D3 is used to suppress reverse current flow, and the diode D2 enables freewheeling and prevents reverse breakdown.

[0030] When MOSFET D4 is turned on, current flows only through inductor L1. As the current in inductor L1 increases, diode D3 turns on to supply power to the load resistor RL. The load resistor RL draws energy to supply the FTU at the back end. When MOSFET D4 is turned off, the current stored in inductor L1 supplies power to capacitor C6 and load resistor RL through diode D3. The load resistor RL draws energy to supply the FTU at the back end.

[0031] Regardless of whether MOSFET D4 is turned on or off, there is always current in the waveform correction circuit loop, and there will be no interruption of current in the rectifier circuit. This improves the power factor and reduces reactive power generation.

[0032] This invention is not limited to the description in the specification and embodiments. Therefore, other advantages and modifications can be readily realized by those skilled in the art. Thus, without departing from the spirit and scope of the general concept as defined by the claims and their equivalents, this invention is not limited to the specific details, representative devices and illustrated examples shown and described herein.

Claims

1. A deep integration of primary and secondary FTU power harvesting circuit system for power distribution networks, characterized in that, include: The circuit includes a voltage divider circuit, a rectifier circuit, and a waveform correction circuit; the voltage divider circuit and the rectifier circuit are electrically connected. The waveform correction circuit includes capacitor C2, inductor L1, resistor R1, resistor R3, capacitor C3, capacitor C5, a waveform correction module, a MOSFET, diode D2, diode D3, and load resistor RL. The first terminal of capacitor C2 is electrically connected to the third terminal of the rectifier circuit, the first terminal of inductor L1, and pin e of the waveform correction module. The second terminal of capacitor C2 is electrically connected to the fourth terminal of the rectifier circuit and pin d of the waveform correction module, and is grounded. The second end of the inductor L1 is electrically connected to the first end of the resistor R1, the first end of the capacitor C3, pin b of the waveform correction module, and the drain of the MOSFET D4. The second end of the resistor R1 is grounded, and the second end of the capacitor C3 is electrically connected to the second end of the resistor R2 and grounded. The first end of resistor R3 is electrically connected to the second end of resistor R1. The second end of resistor R3 is electrically connected to the first end of capacitor C5 and pin a of the waveform correction module. The second end of capacitor C5 is grounded. The gate of MOSFET D4 is electrically connected to pin c of the waveform correction module. The source of MOSFET D4 is electrically connected to pin d of the waveform correction module, the anode of diode D2, the first end of capacitor C6, and the first end of load resistor RL. The cathode of diode D2 is electrically connected to the drain of MOSFET D4 and the anode of diode D3. The cathode of diode D3 is electrically connected to the second end of capacitor C6 and the second end of load resistor RL.

2. The power distribution network primary and secondary deeply integrated FTU power taking circuit system of claim 1, wherein, The waveform correction circuit also includes a resistor R2 and a capacitor C4. The first end of the resistor R2 is electrically connected to the second end of the resistor R1, and the second end of the resistor R2 is grounded. The first terminal of capacitor C4 is electrically connected to the second terminal of capacitor C3, and the second terminal of capacitor C4 is electrically connected to the second terminal of resistor R2 and grounded.

3. The power distribution network primary and secondary deeply integrated FTU power taking circuit system of claim 2, wherein, The voltage divider circuit includes capacitor C1, transformer TX1, varistor MOV1, varistor MOV2, capacitor C14, capacitor C16, varistor MOV3, inductor L2, inductor L3, common mode inductor L4, resistor R4, and capacitor C11. The first terminal of capacitor C1 is connected to an external power source. The second terminal of capacitor C1 is electrically connected to the first terminal of the primary winding of the transformer. The second terminal of the primary winding of the transformer is connected to an external power source. The first terminal of the secondary winding of the transformer is electrically connected to the first terminals of varistor MOV1, capacitor C14, capacitor C16, varistor MOV3, and inductor L3. The second terminal of varistor MOV1 is electrically connected to the second terminal of capacitor C14 and grounded. The second terminal of the secondary winding of the transformer is electrically connected to the first terminals of varistor MOV2, capacitor C16, varistor MOV3, and inductor L2. The second terminal of the varistor MOV2 is electrically connected to the second terminal of capacitor C16, the first terminal of inductor L2, the second terminal of inductor L3, and the second terminal of inductor L3, and is grounded. The second end of inductor L2 is electrically connected to the first coil of common-mode inductor L4. The second end of inductor L3 is electrically connected to the second coil of common-mode inductor L4. The first coil of common-mode inductor L4 is electrically connected to the first end of capacitor C11, the second end of varistor MOV2, and the second end of rectifier circuit. The second coil of common-mode inductor L4 is electrically connected to the first end of resistor R4 and the first end of rectifier circuit. The second end of resistor R4 is electrically connected to the second end of capacitor C11.

4. The power distribution network primary and secondary deeply integrated FTU power taking circuit system of claim 3, wherein, The voltage divider circuit also includes capacitors C15, C7, C8, C9 and C10; the first terminal of capacitor C15 is electrically connected to the second terminal of capacitor C16, and the second terminal of capacitor C15 is electrically connected to the second terminal of varistor MOV2 and grounded. The first terminal of capacitor C7 is electrically connected to the first terminal of inductor L3. The second terminal of capacitor C7 is electrically connected to the first terminal of capacitor C8 and the second terminal of varistor MOV2. The second terminal of capacitor C8 is electrically connected to the first terminal of inductor L2. The first terminal of capacitor C9 is electrically connected to the second terminal of inductor L3. The second terminal of capacitor C9 is electrically connected to the first terminal of capacitor C10 and the second terminal of varistor MOV2. The second terminal of capacitor C10 is electrically connected to the second terminal of inductor L2.

5. The power distribution network primary and secondary deeply integrated FTU power taking circuit system of claim 4, wherein, The voltage divider circuit includes capacitor C12 and capacitor C13; the first end of capacitor C12 is electrically connected to the first end of resistor R4, the second end of capacitor C12 is electrically connected to the first end of capacitor C13 and the second end of varistor MOV2, and the second end of capacitor C13 is electrically connected to the first end of capacitor C11.

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