Package substrate

Abstract

A package substrate includes a dielectric layer having opposite first and second sides; a circuit layer formed on the first and second sides of the dielectric layer; a via frame formed by a plurality of vias penetrating the dielectric layer to enclose at least one area in the dielectric layer; and a conductive post formed in the via frame and electrically connected to the circuit layer on the first and second sides of the dielectric layer. The via frame can increase the effective conductive area of the package substrate, and is suitable for products with high conductive and heat dissipation requirements.

Description

Technical Field

[0001] This utility model relates to a packaging substrate, and more particularly to a packaging substrate with through-hole slots to facilitate electrical conduction. Background Technology

[0002] In electronic applications of large products such as vehicles and aircraft, IC packaging substrates face stringent requirements for high voltage, high current transmission, and high thermal conductivity. To meet these demands, the packaging substrate can improve its electrical and thermal conductivity by increasing the copper thickness of the conductive structure, enlarging the via size, and increasing the via area.

[0003] In current packaging substrate designs, slot via structures are commonly used for electrical connections to meet high current and high heat transfer requirements. Specifically, a slot via consists of at least two independent vias, which are then connected to form a large solder pad through electroplating and other steps. However, this traditional slot via has a limited effective conductive area, and it requires patterned electroplating methods such as modified semi-additive plating (MSAP) to fabricate the slot via. During the formation of the large-area solder pad, there is a risk of open circuits.

[0004] like Figure 1A As shown, in the process of existing packaging substrates, a carrier 9 is used to create multiple through holes 12 in the dielectric layer 10, which is covered with metal layers 11 (such as copper foil) on both sides. Figure 1A An enlarged top view of the dashed frame X is shown below. Figure 1B There is no contact between the vias 12. Therefore, the multiple vias 12 in the existing packaging substrate are electrically connected only through the metal layer 11 and the subsequently formed circuit layer (not shown). The exposed conductive area of ​​the vias 12 on the surface of the dielectric layer 10 is small, resulting in poor efficiency and reliability in product applications with high conductivity and thermal conductivity requirements.

[0005] Therefore, overcoming the various problems of the existing technologies has become an urgent issue to be addressed. Utility Model Content

[0006] In view of the various defects of the prior art, the present invention provides a packaging substrate, comprising: a dielectric layer having opposing first and second sides; a circuit layer formed on the first and second sides of the dielectric layer; a via frame groove composed of a plurality of interconnected vias penetrating the dielectric layer to form at least one closed region around the dielectric layer; and conductive pillars formed in the via frame groove and electrically connected to the circuit layer on the first and second sides of the dielectric layer.

[0007] In one specific embodiment of the aforementioned packaging substrate, the sidewall of the through-hole frame groove is curved.

[0008] In one specific embodiment of the aforementioned packaging substrate, the conductive pillar is flush with the surfaces of the first and second sides of the dielectric layer.

[0009] In one specific embodiment of the aforementioned packaging substrate, the distance between the centers of any two adjacent vias is less than the sum of the radii of the two vias.

[0010] In one specific embodiment of the aforementioned packaging substrate, the projected areas of any two adjacent vias on the first and / or second sides of the dielectric layer partially overlap, and the area of ​​the partial overlap is more than 50% of the projected area of ​​a single via on the corresponding first and / or second sides of the dielectric layer.

[0011] In one specific embodiment of the aforementioned packaging substrate, the exposed area of ​​the via on the first side of the dielectric layer is greater than the exposed area of ​​the via on the second side of the dielectric layer.

[0012] In one specific embodiment of the aforementioned packaging substrate, the conductive post in the through hole is a tapered post.

[0013] In one specific embodiment of the aforementioned packaging substrate, the exposed area of ​​the via on the first side of the dielectric layer is equal to the exposed area of ​​the via on the second side of the dielectric layer.

[0014] In one specific embodiment of the aforementioned packaging substrate, the conductive pillar in the through hole is an upright cylinder or a double-conical pillar.

[0015] In one specific embodiment of the aforementioned packaging substrate, the circuit layer on the first side of the dielectric layer is integrally formed with the conductive pillar.

[0016] In one specific embodiment of the aforementioned packaging substrate, the circuit layers on the first and second sides of the dielectric layer are integrally formed with the conductive pillar.

[0017] As can be seen from the above, the packaging substrate of this utility model forms a through-hole frame groove by means of multiple continuous and partially overlapping through holes, which increases the effective conductive area of ​​the packaging substrate and has excellent reliability and reduces the occurrence of open circuit phenomenon in applications requiring high current load or efficient heat dissipation.

[0018] Furthermore, due to the structure formed by the overlapping of multiple through holes in the through hole frame groove of this utility model, the through hole frame groove of this utility model is a long frame-shaped groove with a curved inner sidewall, which provides a larger surface area for the subsequent formation of conductive pillars.

[0019] Furthermore, the through-hole frame groove of this invention significantly reduces the time required for the drilling process. In the formation of traditional slot structures, each through hole generally requires two drilling operations: one for shaping the through hole and the other for removing burrs. In this invention, each through hole only needs to be formed by one drilling operation. Because the through holes are formed by overlapping, the purpose of deburring is achieved while fine-tuning the through hole shape, allowing for the rapid formation of the required through-hole frame groove. Attached Figure Description

[0020] Figure 1A This is a cross-sectional view of an existing packaging substrate during the manufacturing process.

[0021] Figure 1B for Figure 1A A magnified top view of the dashed box X in the middle.

[0022] Figure 2A This is a cross-sectional view of the packaging substrate of this utility model during the manufacturing process.

[0023] Figure 2B This is a partially enlarged top view of the packaging substrate of this utility model.

[0024] Figure 2C This is a top view of the packaging substrate of this utility model.

[0025] Figure 2D-1 for Figure 2C A cross-sectional view at point A (dashed line).

[0026] Figure 2D-2 for Figure 2C A cross-sectional view at point B (dash line).

[0027] Figure 2E This is a cross-sectional view of the packaging substrate of this utility model during the manufacturing process.

[0028] Figure 2F This is a cross-sectional schematic diagram of the packaging substrate of this utility model.

[0029] Figure 3A This is a partially enlarged top view of another packaging substrate method of this utility model.

[0030] The attached figures are labeled as follows:

[0031] 10,20 dielectric layers

[0032] 11 metal layers

[0033] 12,220 through holes

[0034] 2 Packaging substrate

[0035] 2a Enclosed area

[0036] 20a First side

[0037] 20b Second side

[0038] 21a First metal layer

[0039] 21b Second metal layer

[0040] 22 Through-hole frame groove

[0041] 23 Line Layer

[0042] 24 conductive pillars

[0043] 9. Bearing components

[0044] A, B (dashed lines)

[0045] X dashed outline. Detailed Implementation

[0046] The following specific embodiments illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification.

[0047] It should be understood that the structures, proportions, sizes, etc., shown in the accompanying drawings are only for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the implementation conditions of this utility model. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives achieved by this utility model, should still fall within the scope of the disclosed technical content. Furthermore, the terms such as "upper," "lower," "one," "two," "first," and "second" used in this specification are merely for clarity of description and are not intended to limit the scope of implementation of this utility model. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of implementation of this utility model.

[0048] Figures 2A to 2F This is a schematic diagram of the structure and manufacturing method of the packaging substrate 2 of this utility model.

[0049] like Figure 2A As shown, a carrier 9 is provided, and a dielectric layer 20 is formed on the carrier 9. The dielectric layer 20 has a first side 20a and a second side 20b opposite to each other, and a first metal layer 21a and a second metal layer 21b are provided on both surfaces of the dielectric layer 20.

[0050] In this embodiment, the dielectric layer 20 is an ABF film (Ajinomoto build-up film), polybenzoxazole (PBO), polyimide (PI), photoimageable dielectric (PID), glass fiber prepreg (PP), or other dielectric materials.

[0051] Furthermore, the dielectric layer 20 can be formed on the second metal layer 21b by lamination, coating, or other suitable processes, and then the first metal layer 21a can be formed on the other side of the dielectric layer 20 by chemical precipitation, electroless plating, physical vapor deposition, chemical vapor deposition, sputtering, or other methods. Alternatively, if the first metal layer 21a and the second metal layer 21b are copper foils, the dielectric layer 20 can be formed first, and then the first metal layer 21a and the second metal layer 21b can be laminated to both sides of the dielectric layer 20.

[0052] Furthermore, the carrier 9 is a thermally release tape or a temporarily removable adhesive material, such as a double-sided thermal release film, used to provide support during the fabrication of the encapsulation substrate 2. It should be understood that the carrier 9 is a consumable material; therefore, in other embodiments, carrier plates of other specifications can be selected as the carrier 9 as needed. On the other hand, the carrier 9 of this invention can undergo the same process on both sides. The following description only focuses on the process on one side of the carrier 9, without reiterating the process on the other side.

[0053] like Figure 2B As shown in the partially enlarged top view, a plurality of vias 220 are formed in the dielectric layer 20, wherein each via 220 is interconnected and partially overlaps with the others.

[0054] In this embodiment, a plurality of through holes 220 are formed by drilling through the dielectric layer 20 using techniques such as laser drilling or mechanical drilling. Specifically, each through hole 220 may penetrate the first metal layer 21a, the dielectric layer 20, and the second metal layer 21b, or it may only penetrate the first metal layer 21a and the dielectric layer 20 without penetrating the second metal layer 21b. In this embodiment, the through hole 220 does not penetrate the second metal layer 21b, so the second metal layer 21b is still visible at the bottom of the through hole 220.

[0055] Furthermore, the drilling positions of two adjacent through holes 220 overlap, meaning that the distance between the centers of any two adjacent through holes 220 is less than the sum of the radii of the two through holes 220.

[0056] like Figure 2C As shown, the heads and tails of multiple through holes 220 are interconnected to form a through hole frame groove 22, which defines a closed region 2a in the dielectric layer.

[0057] In this embodiment, the total number of vias 220, the shape, length, and arrangement of the via frame groove 22 can all be adjusted according to the layout of the packaging substrate 2. Specifically, the via frame groove 22 formed by multiple vias 220 can be square, rectangular, trapezoidal, polygonal, etc., but is not limited to these; a closed area 2a can be separated in the dielectric layer. This embodiment takes a large via frame groove 22 in the packaging substrate 2 as an example. However, in other specific embodiments, a single packaging substrate 2 can have multiple via frame grooves 22 of different sizes to enhance electrical connections in densely packed circuit areas.

[0058] In the accompanying drawings of this utility model, the interconnected through holes 220 have the same radius. However, depending on the overall design of the packaging substrate 2, the through hole frame 22 can also be formed by interconnecting through holes 220 of different radii.

[0059] In one specific embodiment, the overlapping area of ​​each via 220 may be the same or different. For example, the overlapping area of ​​two adjacent vias 220 exposed on the surfaces of the first side 20a and the second side 20b of the dielectric layer 20 may be more than 50%, 60%, 70%, 80%, or 90% of the area of ​​a single via 220, but is not limited thereto. In other words, the projected areas of any two adjacent vias 220 on the first side 20a and / or the second side 20b of the dielectric layer 20 partially overlap, and the partially overlapping area is more than 50% of the projected area of ​​a single via 220 on the corresponding first side 20a and / or the second side 20b of the dielectric layer 20. In another specific embodiment, such as Figure 3A As shown, the larger the overlapping area of ​​multiple through holes 220, the more the through hole frame groove 22 formed on the exposed surface or outline of the dielectric layer 20 will be close to an elongated ellipse, making it easier to remove residual glue residue and burrs during the drilling process.

[0060] like Figure 2D-1 As shown, the interconnected design of multiple vias 220 surrounds a closed region 2a. In one specific embodiment, the closed region 2a of the dielectric layer 20 can be used to embed electronic components (not shown), allowing the via slot 22 to separate different circuit structures while simultaneously providing signal conduction.

[0061] like Figure 2D-2As shown, multiple through holes 220 are completely interconnected on the first side 20a and the second side 20b of the dielectric layer 20. No dielectric layer 20 remains at the drilled locations, forming a long strip-shaped through hole frame groove 22.

[0062] like Figure 2E As shown, a patterning process is performed to form a circuit layer 23 on the first side 20a of the dielectric layer 20, and a conductive pillar 24 is formed in the through-hole frame groove 22.

[0063] In this embodiment, the circuit layer 23 on the first side 20a of the dielectric layer 20 and the conductive pillar 24 are integrally formed, such as by electroplating. Specifically, the first metal layer 21a can be used as a seed layer, and a conductive material (such as copper) can be formed on the first side 20a of the dielectric layer 20 by electroplating, chemical precipitation or other methods, while simultaneously forming a conductive pillar 24 flush with the surface of the dielectric layer 20.

[0064] Furthermore, the sidewalls of the through-hole frame groove 22 are curved, which increases the contact area between the conductive post 24 and the sidewalls of the through-hole frame groove 22, thereby improving electrical reliability. In addition, the overall shape of the conductive post 24 corresponds to the through-hole frame groove 22, and can be square, rectangular, trapezoidal, polygonal, etc.

[0065] like Figure 2F As shown, the carrier 9 is removed, and another circuit layer 23 is formed on the second side 20b of the dielectric layer 20 to obtain the package substrate 2.

[0066] In this embodiment, the second metal layer 21b is used as a seed layer, and a conductive material (such as copper) is formed on the second side 20b of the dielectric layer 20 using a similar fabrication method to the circuit layer 23 on the first side 20a of the dielectric layer 20. In another specific embodiment, the carrier 9 can be removed before the patterning process, so that the circuit layer 23 and conductive pillar 24 on both sides of the dielectric layer 20 can be fabricated simultaneously, and the structure of the circuit layer 23 on both sides of the dielectric layer 20 can be the same or different. This utility model does not limit the specifications of the circuit layer 23.

[0067] In the drilling process of this utility model, the areas of each through hole 220 exposed on opposite sides of the dielectric layer 20 may be the same or different. In a specific embodiment, if each through hole 220 is drilled by a single laser, the through hole 220 and the conductive post 24 therein are conical, that is, the area of ​​the through hole 220 exposed on the first side 20a of the dielectric layer 20 is greater than the area on the second side 20b of the dielectric layer 20.

[0068] In another specific embodiment, after removing the carrier 9, drilling can also be performed on the second side 20b of the dielectric layer 20. Specifically, the through-hole 220 formed on the first side 20a of the dielectric layer 20 may not completely penetrate the dielectric layer 20. After drilling on the second side 20b of the dielectric layer 20, the through-holes 220 on both sides of the dielectric layer 20 are connected to form a double-conical through-hole 220 and a conductive post 24. In yet another specific embodiment, each of the through-holes 220 is a conventionally mechanically drilled hole, and the through-hole 220 may be vertical, while the conductive post 24 in the through-hole 220 is cylindrical. In several of the embodiments, the area of ​​the through-hole 220 exposed on the first side 20a of the dielectric layer 20 is the same as the area exposed on the second side 20b of the dielectric layer 20, forming a symmetrical through-hole 220 structure.

[0069] In summary, the packaging substrate of this invention has through-hole slots, which can be adjusted by changing laser or mechanical drilling parameters, the diameter of each through-hole, and the overlap area to meet the required specifications. The area of ​​these through-hole slots exposed on the dielectric layer surface is larger than that of ordinary through-holes, which increases the conductive area of ​​the packaging substrate. This results in superior reliability and reduces the occurrence of open circuits in applications requiring high current loads or efficient heat dissipation.

[0070] Furthermore, due to the overlapping and interconnected structure of multiple through holes in the through hole frame groove of this utility model, the through hole frame groove is a long strip frame-shaped hole, which can increase the metal content in the packaging substrate. Moreover, the inner sidewall of the through hole frame groove is curved, which makes the contact area between the conductive pillar formed therein and the through hole frame groove larger, further improving the electrical transmission capability and stability under high current applications.

[0071] Furthermore, the through-hole frame groove design of this utility model can significantly reduce the time required for the drilling process. Because the through holes in the through-hole frame groove are formed by overlapping, burrs can be removed simultaneously during the through-hole shape trimming process with only one drilling operation, improving drilling efficiency and shortening the overall packaging substrate manufacturing process.

[0072] The above embodiments are illustrative of the principles and effects of this utility model, and are not intended to limit this utility model. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of this utility model. Therefore, the scope of protection of this utility model should be as set forth in the claims.

Claims

1. A package substrate, characterized by, include: A dielectric layer having a first side and a second side opposite to each other; A circuit layer is formed on the first and second sides of the dielectric layer; The via frame is composed of multiple interconnected vias penetrating the dielectric layer, forming at least one closed region around the dielectric layer; as well as Conductive pillars are formed in the through-hole frame groove and electrically connect the circuit layers on the first and second sides of the dielectric layer.

2. The package substrate of claim 1, wherein, The sidewalls of the through-hole frame groove are curved.

3. The package substrate of claim 1, wherein, The conductive post is flush with the surfaces of the first and second sides of the dielectric layer.

4. The package substrate of claim 1, wherein, The distance between the centers of any two adjacent through holes is less than the sum of the radii of the two through holes.

5. The package substrate of claim 1, wherein, The projected areas of any two adjacent vias on the first and / or second sides of the dielectric layer partially overlap, and the area of ​​the partial overlap is more than 50% of the projected area of ​​a single via on the corresponding first and / or second sides of the dielectric layer.

6. The package substrate of claim 1, wherein, The exposed area of ​​the via on the first side of the dielectric layer is greater than the exposed area of ​​the via on the second side of the dielectric layer.

7. The package substrate of claim 6, wherein, The conductive post in the through hole is a conical post.

8. The package substrate of claim 1, wherein, The exposed area of ​​the via on the first side of the dielectric layer is equal to the exposed area of ​​the via on the second side of the dielectric layer.

9. The package substrate of claim 8, wherein, The conductive post in the through hole is an upright cylindrical post or a double-conical post.

10. The package substrate of claim 1, wherein, The circuit layer on the first side of the dielectric layer is integrally formed with the conductive pillar.

11. The package substrate of claim 1, wherein, The circuit layers on the first and second sides of the dielectric layer are integrally formed with the conductive pillar.

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