A phase sequence detection circuit

Abstract

The utility model discloses a kind of phase sequence detection circuit, belong to three-phase electric detection technical field.Phase sequence detection circuit includes: JK flip-flop and three signal shaping modules;Three signal shaping modules are respectively connected in each phase voltage signal in the three-phase electric to be measured;The signal shaping module is for converting the phase voltage signal of access as the square wave signal output of same frequency;The output end of three signal shaping modules is respectively corresponding to the set end of the JK flip-flop, clock end and reset end, one of the main output end and the inverting output end of the JK flip-flop is as the result output end of the phase sequence detection circuit;The level of the result output end is used to indicate the phase sequence of the three-phase electric to be measured.The utility model embodiment can detect the phase sequence of three-phase electric, and it is favorable to guarantee the safety of three-phase system.

Description

Technical Field

[0001] This utility model relates to the field of three-phase electrical detection technology, and in particular to a phase sequence detection circuit. Background Technology

[0002] Three-phase electricity consists of three alternating current signals with the same frequency, equal amplitude, and initial phases differing by 120°. During the installation of three-phase power supplies / three-phase electrical equipment, the correct phase sequence is crucial to the safety of the equipment. For example, when an energy storage converter is installed in an energy storage system, incorrect phase sequence connection may cause equipment failure or safety accidents. Therefore, a phase sequence detection circuit is needed to detect the phase sequence of three-phase electricity to ensure the safety of the three-phase system. Utility Model Content

[0003] This invention provides a phase sequence detection circuit to detect the phase sequence of three-phase electricity, which helps to ensure the safety of the three-phase system.

[0004] This utility model embodiment provides a phase sequence detection circuit, including:

[0005] Three signal shaping modules are respectively connected to the voltage signal of each phase of the three-phase electrical circuit to be tested; the signal shaping module is used to convert the connected phase voltage signal into a square wave signal of the same frequency for output;

[0006] The output terminals of the three signal shaping modules are respectively connected to the set terminal, clock terminal, and reset terminal of the JK flip-flop. One of the main output terminal and the inverting output terminal of the JK flip-flop serves as the result output terminal of the phase sequence detection circuit. The level of the result output terminal is used to indicate the phase sequence of the three-phase power supply under test.

[0007] Optionally, the three-phase power to be tested is provided by a three-phase four-wire system, which includes three phase wires and one neutral wire; the three signal shaping modules are connected one-to-one to the three phase wires, and all three signal shaping modules are connected to the neutral wire;

[0008] The signal shaping module includes:

[0009] A differential amplifier unit is provided, wherein the first input terminal of the differential amplifier unit is connected to the phase line connected to the signal shaping module, and the second input terminal of the differential amplifier unit is connected to the neutral line. The differential amplifier unit is used to differentially amplify the signals connected to the first input terminal and the second input terminal respectively to obtain a sinusoidal sampled voltage signal.

[0010] A square wave shaping unit is provided, wherein the input terminal of the square wave shaping unit is connected to the output terminal of the differential amplifier unit, and the output terminal of the square wave shaping unit is connected to the output terminal of the signal shaping module; the square wave shaping unit is used to convert the sinusoidal sampled voltage signal into a square wave signal of the same frequency for output.

[0011] Optionally, the differential amplifier unit includes: a first operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, and a second capacitor;

[0012] The first resistor is connected between the first input terminal of the differential amplifier unit and the first input terminal of the first operational amplifier; the second resistor is connected between the second input terminal of the differential amplifier unit and the second input terminal of the first operational amplifier; the third resistor and the first capacitor are both connected between the first input terminal and the output terminal of the first operational amplifier; the first terminal of the fourth resistor and the first terminal of the second capacitor are both connected to a reference voltage, and the second terminal of the fourth resistor and the second terminal of the second capacitor are both connected to the second input terminal of the first operational amplifier.

[0013] Optionally, the square wave shaping unit includes: a second operational amplifier, a fifth resistor, a sixth resistor, a seventh resistor, and a third capacitor;

[0014] The first input terminal of the second operational amplifier is connected to the output terminal of the differential amplifier unit, and the output terminal of the second operational amplifier is connected to the output terminal of the square wave shaping unit; the first terminal of the fifth resistor is connected to the power supply voltage, the second terminal of the fifth resistor is connected to the output terminal of the second operational amplifier and the first terminal of the sixth resistor, and the second terminal of the sixth resistor is connected to the second input terminal of the second operational amplifier; the first terminal of the seventh resistor and the first terminal of the third capacitor are both connected to the reference voltage, and the second terminal of the seventh resistor and the second terminal of the third capacitor are both connected to the second input terminal of the second operational amplifier.

[0015] Optionally, the signal shaping module further includes a voltage follower connected between the output of the differential amplifier unit and the input of the square wave shaping unit.

[0016] Optionally, the signal shaping module further includes:

[0017] The eighth resistor is connected between the output terminal of the differential amplifier unit and the input terminal of the square wave shaping unit.

[0018] The fourth capacitor is connected between the input terminal of the square wave shaping unit and ground.

[0019] Optionally, the signal shaping module further includes:

[0020] The fifth capacitor is connected between the output terminal of the signal shaping module and ground;

[0021] The first diode is connected between the output terminal of the signal shaping module and ground.

[0022] Optionally, the phase sequence detection circuit further includes a main control module connected to the result output terminal.

[0023] Optionally, the phase sequence detection circuit further includes:

[0024] The display is connected to the main control module;

[0025] And / or,

[0026] The indicator module is connected to the main control module or the result output terminal.

[0027] Optionally, the phase sequence detection circuit further includes: a pull-up resistor, the first end of which is connected to a fixed level signal, and the second end of which is connected to the other of the main output terminal and the inverting output terminal of the JK flip-flop.

[0028] The phase sequence detection circuit provided in this embodiment of the invention converts the voltage signals of each phase of the three-phase power supply under test into square wave signals of the same frequency through three signal shaping modules, and transmits them to the set, clock, and reset terminals of a JK flip-flop, respectively. Based on the different characteristics of the JK flip-flop when different combinations of voltage levels are applied to its set and reset terminals, the output state of the JK flip-flop differs when the three-phase power supply under test is in positive or reverse sequence. Therefore, the phase sequence of the three-phase power supply under test can be determined based on the voltage level of either the main output terminal or the inverting output terminal of the JK flip-flop. In summary, the phase sequence detection circuit provided in this embodiment of the invention can effectively realize the phase sequence detection of three-phase power supply without requiring a power analyzer or other detection devices. Since the three types of inputs of the JK flip-flop are all provided by the corresponding signal shaping modules, no other clock signal is required. Therefore, this phase sequence detection circuit has low cost, simple structure, and is easy to implement, facilitating the detection of the phase sequence of three-phase power supply and contributing to the safety of the three-phase system.

[0029] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of a phase sequence detection circuit provided in an embodiment of the present invention;

[0032] Figure 2 This is a waveform diagram of a JK trigger connected when the phase sequence of the three-phase electrical circuit under test is positive, provided by an embodiment of this utility model.

[0033] Figure 3 This is a waveform diagram of a JK trigger connected when the phase sequence of the three-phase electrical circuit under test is in reverse order, provided by an embodiment of this utility model.

[0034] Figure 4 This is a schematic diagram of the structure of a signal shaping module provided in an embodiment of this utility model;

[0035] Figure 5 This is a schematic diagram of the structure of a differential amplifier unit provided in an embodiment of this utility model;

[0036] Figure 6 This is a schematic diagram of the structure of a square wave shaping unit provided in an embodiment of the present invention;

[0037] Figure 7 This is a schematic diagram of another signal shaping module provided in an embodiment of the present invention;

[0038] Figure 8 This is a schematic diagram of another phase sequence detection circuit provided in this embodiment of the present invention;

[0039] Figure 9 This is a simulation result diagram of a three-phase electrical circuit under test with a positive phase sequence, provided by an embodiment of this utility model.

[0040] Figure 10 This is a simulation result diagram of a three-phase electrical circuit under test with the phase sequence in reverse order, provided by an embodiment of this utility model;

[0041] Figure 11 This is a schematic diagram of another phase sequence detection circuit provided in this embodiment of the utility model. Detailed Implementation

[0042] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0043] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0044] This utility model embodiment provides a phase sequence detection circuit for detecting the phase sequence of three-phase electricity. Figure 1 This is a schematic diagram of a phase sequence detection circuit provided in an embodiment of this utility model. See also... Figure 1 The phase sequence detection circuit includes three signal shaping modules and a JK flip-flop U0.

[0045] The system comprises three signal shaping modules, each connected to the voltage signal of one phase of the three-phase electrical circuit under test. Each module converts the connected voltage signal into a square wave signal of the same frequency for output. For example, the three signal shaping modules include a first signal shaping module 11, a second signal shaping module 12, and a third signal shaping module 13, which respectively connect to the first phase voltage signal L1_V, the second phase voltage signal L2_V, and the third phase voltage signal L3_V of the three-phase electrical circuit under test, and output the first square wave signal L1_sq, the second square wave signal L2_sq, and the third square wave signal L3_sq after signal shaping. The output terminals of the three signal shaping modules are respectively connected to the set terminal J, the clock terminal CLK, and the reset terminal K of the JK flip-flop U0, as well as the main output terminal Q and the inverting output terminal of the JK flip-flop U0. One of them serves as the output terminal of the phase sequence detection circuit; the level of the output terminal is used to indicate the phase sequence of the three-phase power supply under test. For example, the output terminal of the first signal shaping module 11 is connected to the set terminal J of the JK flip-flop U0, the output terminal of the second signal shaping module 12 is connected to the clock terminal CLK of the JK flip-flop U0, and the output terminal of the third signal shaping module 13 is connected to the reset terminal K of the JK flip-flop U0. Figure 1 The example shows the main output terminal Q of the JK flip-flop U0 as the result output terminal, but this is not intended to limit the present invention. In other embodiments, the inverting output terminal of the JK flip-flop U0 can also be used. As the result output terminal, the level of the result signal SOUT output by the result output terminal is used to indicate whether the phase sequence of the three-phase power supply connected to the phase sequence detection circuit is positive or negative (also known as reverse sequence). For example, the main output terminal Q and the inverting output terminal... The other one can be connected to the relevant subsequent circuit according to actual needs, or, at the main output terminal Q and the inverting output terminal... When the other output is not used for any other purpose, it can be floated and pulled to a fixed level by a pull-up resistor; this applies to the main output terminal Q and the inverting output terminal. The specific connection relationship between the other two is not limited.

[0046] For example, the signal shaping module is used to convert the input sinusoidal voltage signal into a square wave signal with the same frequency as the input signal. Each voltage transition edge of the square wave signal corresponds to a zero-crossing point in the sinusoidal voltage signal; the positive half-cycle of the voltage signal corresponds, for example, to the high level of the square wave signal, and the negative half-cycle corresponds, for example, to the low level of the square wave signal. By converting the three-phase voltage signals of the three-phase power supply under test into three square wave signals through three signal shaping modules, the JK flip-flop U0 can determine its main output Q and inverting output Q based on the levels of the set terminal J and reset terminal K, as well as the voltage transition edge of the clock terminal CLK. The output level. For example, the high and low levels of the square wave signals output by each signal shaping module can be controlled according to the voltage recognition capability of each input terminal of the JK flip-flop U0.

[0047] For example, JK flip-flop U0 is a rising edge triggered device, and the characteristics of JK flip-flop U0 can be found in Table 1.

[0048] Table 1

[0049]

[0050] Table 1 only provides examples of the level of the main output terminal Q; the inverting output terminal... The voltage level is inverted compared to the main output Q, which will not be elaborated further. In Table 1, Q... N This indicates the voltage level of the main output terminal Q before the rising edge occurs. N+1 This indicates the level of the main output terminal Q after the rising edge occurs.

[0051] Based on the characteristics of three-phase AC, a positive-sequence three-phase electrical circuit includes three-phase AC voltage signals A, B, and C with the same frequency, equal amplitude, and initial phases differing by 120° sequentially. For example, the B-phase voltage signal lags the A-phase voltage signal by 120°, and the C-phase voltage signal lags the B-phase voltage signal by 120°. Therefore, when the phase sequence of the three-phase voltage signals (L1_V, L2_V, and L3_V) connected to the first to third signal shaping modules is (A, B, C), (B, C, A), or (C, A, B), it indicates that the three-phase electrical circuit connected to the phase sequence detection circuit is in positive sequence. Conversely, when the phase sequence of L1_V, L2_V, and L3_V is (A, C, B), (B, A, C), or (C, B, A), it indicates that the three-phase electrical circuit connected to the phase sequence detection circuit is in reverse sequence.

[0052] Based on this pattern, and considering the characteristics of JK flip-flop U0 that forces the main output Q to 0 when J=0 and K=1 occurs at the rising edge of the clock terminal CLK, and that forces the main output Q to 1 when J=1 and K=0 occurs at the rising edge of the clock terminal CLK, this embodiment of the invention connects the output terminals of the three signal shaping modules to the set terminal J, the clock terminal CLK, and the reset terminal K of JK flip-flop U0, respectively. This allows the forward and reverse sequence of the three-phase power under test to correspond to the two sets of characteristics mentioned above, thus enabling the determination of the main output Q / inverting output. The voltage level is used to determine whether the three-phase electricity under test is in positive or negative sequence.

[0053] Specifically, when the first phase voltage signal L1_V, the second phase voltage signal L2_V, and the third phase voltage signal L3_V are in positive sequence, the waveform relationship of the first square wave signal L1_sq, the second square wave signal L2_sq, and the third square wave signal L3_sq can be found in [reference needed]. Figure 2 .according to Figure 2 It can be seen that when any rising edge of the second square wave signal L2_sq occurs, see... Figure 2 At the time indicated by the dashed line, the first square wave signal L1_sq is high and the third square wave signal L3_sq is low, corresponding to the rising edge characteristic of the clock terminal CLK when J=1 and K=0. Therefore, when the three-phase power under test is in positive sequence, the main output terminal Q of the JK flip-flop U0 outputs 1 (i.e., high level), and the inverting output terminal... Output 0 (i.e., low level).

[0054] When the first phase voltage signal L1_V, the second phase voltage signal L2_V, and the third phase voltage signal L3_V are in reverse order, the waveform relationship of the first square wave signal L1_sq, the second square wave signal L2_sq, and the third square wave signal L3_sq can be found in [reference needed]. Figure 3 .according to Figure 3 It can be seen that when any rising edge of the second square wave signal L2_sq occurs, see... Figure 3 At the time indicated by the dashed line, the first square wave signal L1_sq is low, and the third square wave signal L3_sq is high, corresponding to the rising edge characteristic of the clock terminal CLK when J=0 and K=1. Therefore, when the three-phase power under test is in reverse order, the main output terminal Q of the JK flip-flop U0 outputs 0 (i.e., low level), and the inverting output terminal... Output 1 (i.e., high level).

[0055] The phase sequence detection circuit provided in this embodiment converts the voltage signals of each phase of the three-phase power supply under test into square wave signals of the same frequency through three signal shaping modules, and transmits them to the set terminal J, clock terminal CLK, and reset terminal K of the JK flip-flop U0, respectively. Based on the different characteristics of the JK flip-flop U0 when different levels are applied to the set terminal J and reset terminal K, the output state of the JK flip-flop U0 differs when the three-phase power supply under test is in positive sequence and reverse sequence. Therefore, according to the main output terminal Q and the inverting output terminal of the JK flip-flop U0... The level of any one of these parameters can determine the phase sequence of the three-phase power supply being tested. In summary, the phase sequence detection circuit provided in this embodiment can effectively detect the phase sequence of three-phase power without requiring a power analyzer or other detection devices. Since the three types of inputs to the JK flip-flop U0 are all provided by the corresponding signal shaping modules, no other clock signal is needed. Therefore, this phase sequence detection circuit has low cost, a simple structure, and is easy to implement, facilitating the detection of the phase sequence of three-phase power and contributing to ensuring the safety of the three-phase system.

[0056] Based on the above embodiments, optionally, the three-phase electricity to be tested is provided by a three-phase four-wire system, which includes three phase lines and one neutral line (also called a neutral wire). The three phase lines are used to transmit the first phase voltage signal L1_V, the second phase voltage signal L2_V, and the third phase voltage signal L3_V, respectively. The voltage on the neutral line is, for example, called the neutral point voltage (denoted as N_V). Three signal shaping modules are connected one-to-one to the three phase lines to respectively access the voltage signal of each phase in the three-phase electricity to be tested; and all three signal shaping modules are connected to the neutral line and connected to the neutral point voltage N_V.

[0057] Figure 4 This is a schematic diagram of the structure of a signal shaping module provided in an embodiment of this utility model. See also... Figure 4The signal shaping module 10 specifically includes a differential amplifier unit 110 and a square wave shaping unit 120. The first input terminal of the differential amplifier unit 110 is connected to the phase line to which the signal shaping module 10 is connected, and receives the phase voltage signal L_V transmitted on that phase line; the second input terminal of the differential amplifier unit 110 is connected to the neutral line, and receives the neutral point voltage N_V. The differential amplifier unit 110 is used to differentially amplify the signals received at the first and second input terminals respectively, obtaining a sinusoidal sampled voltage signal L_samp. The input terminal of the square wave shaping unit 120 is connected to the output terminal of the differential amplifier unit 110, and receives the sinusoidal sampled voltage signal L_samp; the output terminal of the square wave shaping unit 120 is connected to the output terminal of the signal shaping module 10; the square wave shaping unit 120 is used to convert the sinusoidal sampled voltage signal L_samp into a square wave signal L_sq of the same frequency for output. It is understandable that each signal shaping module 10 has the same circuit structure, the only difference being that it connects to different phase voltage signals L_V during application, and connects to different input terminals of the JK flip-flop U0.

[0058] In this embodiment, by setting a differential amplifier unit 110 to sample the phase voltage between the phase line and the neutral line, a sinusoidal sampled voltage signal L_samp with the same frequency as the phase voltage signal L_V is provided, which can effectively suppress common-mode interference and reduce sampling errors. Furthermore, the square wave shaping unit 120 can convert the sinusoidal sampled voltage signal L_samp into a square wave signal L_sq with the same frequency, thereby effectively capturing each zero-crossing point of the phase voltage signal L_V and converting it into each voltage transition edge of the square wave signal L_sq.

[0059] Figure 5 This is a schematic diagram of the structure of a differential amplifier unit provided in an embodiment of this utility model. See also... Figure 5 In one embodiment, the differential amplifier unit 110 optionally includes: a first operational amplifier U1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, and a second capacitor C2. The first resistor R1 is connected between the first input terminal of the differential amplifier unit 110 and the first input terminal of the first operational amplifier U1; the second resistor R2 is connected between the second input terminal of the differential amplifier unit 110 and the second input terminal of the first operational amplifier U1; the third resistor R3 and the first capacitor C1 are both connected between the first input terminal and the output terminal of the first operational amplifier U1; the first terminal of the fourth resistor R4 and the first terminal of the second capacitor C2 are both connected to a reference voltage Vref, and the second terminal of the fourth resistor R4 and the second terminal of the second capacitor C2 are both connected to the second input terminal of the first operational amplifier U1.

[0060] For example, the first input terminal of the first operational amplifier U1 is its non-inverting input terminal, and the second input terminal is its inverting input terminal. That is, the phase voltage signal L_V is transmitted to the non-inverting input terminal of the first operational amplifier U1 after being current-limited by the first resistor R1, and the neutral point voltage N_V is transmitted to the inverting input terminal of the first operational amplifier U1 after being current-limited by the second resistor R2. The differential amplification factor G of the differential amplifier unit 110 is: G = R3 / R1. Therefore, the sinusoidal sampled voltage signal L_samp is: L_samp = G × (L_V - N_V). For example, the reference voltage Vref is a DC voltage with a positive voltage. In this embodiment, based on the reference voltage Vref, a DC bias can be provided to the first operational amplifier U1 to avoid the differential amplifier unit 110 from losing the negative half-cycle waveform of the AC voltage sampling. For example, the reference voltage Vref can be half of the positive power supply voltage connected to the first operational amplifier U1. For instance, if the positive power supply voltage connected to the first operational amplifier U1 is 3.3V, then Vref = 1.65V.

[0061] Figure 6 This is a schematic diagram of the structure of a square wave shaping unit provided in an embodiment of this utility model. See also... Figure 6 Based on the above embodiments, optionally, the square wave shaping unit 120 includes: a second operational amplifier U2, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and a third capacitor C3. The first input terminal of the second operational amplifier U2 is connected to the output terminal of the differential amplifier unit 110 in the signal shaping module 10 where the square wave shaping unit 120 is located, and is connected to a sinusoidal sampling voltage signal L_samp; the output terminal of the second operational amplifier U2 is connected to the output terminal of the square wave shaping unit 120 to output a square wave signal L_sq; the first terminal of the fifth resistor R5 is connected to the power supply voltage VCC, and the second terminal of the fifth resistor R5 is connected to the output terminal of the second operational amplifier U2 and the first terminal of the sixth resistor R6, respectively; the second terminal of the sixth resistor R6 is connected to the second input terminal of the second operational amplifier U2; the first terminal of the seventh resistor R7 and the first terminal of the third capacitor C3 are both connected to the reference voltage Vref, and the second terminals of the seventh resistor R7 and the third capacitor C3 are both connected to the second input terminal of the second operational amplifier U2.

[0062] For example, the first input terminal of the second operational amplifier U2 is its non-inverting input terminal, and the second input terminal is its inverting input terminal. The square wave shaping unit 120 constitutes a comparator circuit structure. The sinusoidal sampled voltage signal L_samp passes through the square wave shaping unit 120 to obtain a power frequency square wave with a positive half-cycle corresponding to (R6+R7) / (R5+R6+R7)×(VCC-Vref) and a negative half-cycle corresponding to R6 / (R6+R7)×Vref. The third capacitor C3 serves as a filter capacitor. The power supply voltage VCC is a positive DC voltage, for example, equal to 3.3V. The first operational amplifier U1 and the second operational amplifier U2 can use the same power supply voltage and reference voltage Vref. It is understood that in practical applications, the resistance values ​​of each resistor in the square wave shaping unit 120 can be set according to the voltage range recognizable by the relevant ports of the JK flip-flop U0. Voltage can be adjusted by resistor division so that the high and low voltages of the square wave signal L_sq are both within the recognizable range of the JK flip-flop U0.

[0063] Figure 7 This is a schematic diagram of another signal shaping module provided in an embodiment of this utility model. See also... Figure 7 Based on the above embodiments, the signal shaping module 10 may optionally further include a voltage follower 130, which is connected between the output terminal of the differential amplifier unit 110 and the input terminal of the square wave shaping unit 120. By adding the voltage follower 130, signal attenuation can be reduced based on impedance matching.

[0064] Specifically, the voltage follower 130 may include a third operational amplifier U3, the non-inverting input of the third operational amplifier U3 is connected to the output of the differential amplifier unit 110, the output of the third operational amplifier U3 is connected to the input of the square wave shaping unit 120, and the inverting input of the third operational amplifier U3 is connected to the output of the third operational amplifier U3.

[0065] See also Figure 7 Optionally, based on the above embodiments, the signal shaping module 10 may further include an eighth resistor R8 and a fourth capacitor C4. The eighth resistor R8 is connected between the output terminal of the differential amplifier unit 110 and the input terminal of the square wave shaping unit 120. If a voltage follower 130 is provided, the eighth resistor R8 can be connected between the output terminal of the third operational amplifier U3 and the input terminal of the square wave shaping unit 120. The fourth capacitor C4 is connected between the input terminal of the square wave shaping unit 120 and ground. Both the eighth resistor R8 and the fourth capacitor C4 are used for filtering, which can improve the reliability of signal transmission.

[0066] See also Figure 7Based on the above embodiments, optionally, the signal shaping module 10 further includes a fifth capacitor C5 and a first diode D1. The fifth capacitor C5 is connected between the output terminal of the signal shaping module 10 and ground; the first diode D1 is connected between the output terminal of the signal shaping module 10 and ground. The fifth capacitor C5 serves as the output filter capacitor of the signal shaping module 10, and the first diode D1 can specifically have its cathode connected to the output terminal of the signal shaping module 10 and its anode grounded, acting as a clamping force to prevent zero-crossing interference.

[0067] Use three Figure 7 The phase sequence detection circuit composed of the signal shaping module 10 shown can be found in [reference]. Figure 8 To verify the detection effect of the phase sequence detection circuit provided in this embodiment of the invention, the applicant conducted... Figure 8 The circuit shown was simulated and verified; the simulation results can be found in [reference needed]. Figure 9 and Figure 10 Specifically, Figure 9 This is a simulation result diagram of the three-phase electrical phase sequence under test provided by an embodiment of this utility model. It can be seen that the waveform relationship of the three square wave signals obtained in the positive sequence is... Figure 2 The theoretical relationship is consistent with that, and when the main output terminal Q is used as the result output terminal, SOUT=1, that is, the result signal SOUT is high level. Figure 10 This is a simulation result diagram of the three-phase electrical phase sequence under test when it is in reverse sequence, provided by an embodiment of this utility model. It can be seen that the waveform relationship of the three square wave signals obtained in reverse sequence is... Figure 3 The theoretical relationship is consistent with that, and when the main output terminal Q is used as the result output terminal, SOUT=0, that is, the result signal SOUT is low. The above results show that the phase sequence detection circuit provided by this utility model embodiment can effectively detect the phase sequence of three-phase electricity.

[0068] Figure 11 This is a schematic diagram of another phase sequence detection circuit provided in this embodiment of the present invention. See also... Figure 11 Based on the above embodiments, the phase sequence detection circuit may optionally include: a pull-up resistor RP, the first end of which is connected to a fixed-level signal V0, and the second end of which is connected to the main output terminal Q and the inverting output terminal of the JK flip-flop U0. The other one. It's understandable that the main output terminal Q and the inverting output terminal... The other end is the one that is not used as the result output. For example, when the main output Q is used as the result output, the inverting output... Connect the second terminal of the pull-up resistor RP; when the output terminal is inverted When used as the output terminal, the main output terminal Q is connected to the second terminal of the pull-up resistor RP.

[0069] In this embodiment, by setting a pull-up resistor RP, the main output terminal Q and the inverting output terminal can be prevented from being connected. The other signal is left floating to prevent accidental triggering by external interference and to avoid the uncertainty of the behavior of the JK flip-flop U0. For example, the fixed-level signal V0 can be a ground signal or a high-level signal, which can be set according to actual needs.

[0070] See also Figure 11 Based on the above embodiments, the phase sequence detection circuit may optionally include a main control module 20, which is connected to the result output terminal. The main control module 20 can confirm the phase sequence and perform subsequent processing based on the level of the result output terminal. For example, the main control module 20 may include a DSP (Digital Signal Processor).

[0071] Furthermore, the phase sequence detection circuit may also include a display 30. The display 30 is connected to the main control module 20. After acquiring the result signal SOUT, the main control module 20 can control the display 30 to display the result. Additionally, the main control module 20 can also acquire the voltage signals of each phase and the square wave signals and control the display 30 to display them.

[0072] Furthermore, the phase sequence detection circuit may also include an indicator module 40, which can be configured as follows: Figure 11 The indicator module 40 can be directly connected to the result output terminal and driven by the result signal SOUT to indicate the result; alternatively, the indicator module 40 can also be connected to the main control module 20 and driven by the main control module 20 to indicate the result. For example, the indicator module 40 may include a light-emitting diode or a buzzer, etc., to indicate the result in the form of sound and light. The specific configuration of the indicator module 40 is not limited here.

[0073] In summary, this utility model embodiment provides a phase sequence detection circuit, mainly composed of a differential amplifier unit, a square wave shaping unit, and a JK flip-flop. It may also include other components to improve circuit reliability. Compared to related technologies that rely on oscilloscopes and power analyzers for three-phase phase sequence detection, the phase sequence detection circuit provided in this utility model embodiment, except for the display, is entirely composed of chips and electronic components. It eliminates the need for expensive testing instruments, resulting in low cost and a simple structure. These chips and electronic components can be integrated onto a circuit board for packaging and, together with the display, form a portable testing device suitable for various application scenarios, enabling convenient and quick three-phase phase sequence detection. For example, this phase sequence detection circuit can be used for phase sequence detection during the installation of energy storage converters, such as detecting the relevant phase sequence on the AC grid side of the energy storage converter (e.g., the phase sequence at the grid-side output). Particularly for industrial and commercial energy storage systems used in grid-connected and off-grid applications, it can effectively improve the safety of energy storage converter installation and enhance system operational safety and reliability.

[0074] The specific embodiments described above do not constitute a limitation on the scope of protection of this utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. A phase sequence detection circuit, characterized in that, include: Three signal shaping modules are respectively connected to the voltage signal of each phase of the three-phase electrical circuit under test; The signal shaping module is used to convert the received single-phase voltage signal into a square wave signal of the same frequency for output. The output terminals of the three signal shaping modules are respectively connected to the set terminal, clock terminal, and reset terminal of the JK flip-flop. One of the main output terminal and the inverting output terminal of the JK flip-flop serves as the result output terminal of the phase sequence detection circuit. The level of the result output terminal is used to indicate the phase sequence of the three-phase power supply under test.

2. The phase sequence detection circuit according to claim 1, characterized in that, The three-phase power to be tested is provided by a three-phase four-wire system, which includes three phase wires and one neutral wire; the three signal shaping modules are connected one-to-one to the three phase wires, and all three signal shaping modules are connected to the neutral wire; The signal shaping module includes: A differential amplifier unit, wherein the first input terminal of the differential amplifier unit is connected to the phase line connected to the signal shaping module, and the second input terminal of the differential amplifier unit is connected to the neutral line, and the differential amplifier unit is used to differentially amplify the signals respectively connected to the first input terminal and the second input terminal to obtain a sinusoidal sampled voltage signal; A square wave shaping unit is provided, wherein the input terminal of the square wave shaping unit is connected to the output terminal of the differential amplifier unit, and the output terminal of the square wave shaping unit is connected to the output terminal of the signal shaping module; the square wave shaping unit is used to convert the sinusoidal sampled voltage signal into a square wave signal of the same frequency for output.

3. The phase sequence detection circuit according to claim 2, characterized in that, The differential amplifier unit includes: a first operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, and a second capacitor; The first resistor is connected between the first input terminal of the differential amplifier unit and the first input terminal of the first operational amplifier; the second resistor is connected between the second input terminal of the differential amplifier unit and the second input terminal of the first operational amplifier; the third resistor and the first capacitor are both connected between the first input terminal and the output terminal of the first operational amplifier; the first terminal of the fourth resistor and the first terminal of the second capacitor are both connected to a reference voltage, and the second terminal of the fourth resistor and the second terminal of the second capacitor are both connected to the second input terminal of the first operational amplifier.

4. The phase sequence detection circuit according to claim 2, characterized in that, The square wave shaping unit includes: a second operational amplifier, a fifth resistor, a sixth resistor, a seventh resistor, and a third capacitor; The first input terminal of the second operational amplifier is connected to the output terminal of the differential amplifier unit, and the output terminal of the second operational amplifier is connected to the output terminal of the square wave shaping unit; the first terminal of the fifth resistor is connected to the power supply voltage, the second terminal of the fifth resistor is connected to the output terminal of the second operational amplifier and the first terminal of the sixth resistor, and the second terminal of the sixth resistor is connected to the second input terminal of the second operational amplifier; the first terminal of the seventh resistor and the first terminal of the third capacitor are both connected to the reference voltage, and the second terminal of the seventh resistor and the second terminal of the third capacitor are both connected to the second input terminal of the second operational amplifier.

5. The phase sequence detection circuit according to claim 2, characterized in that, The signal shaping module further includes a voltage follower connected between the output of the differential amplifier unit and the input of the square wave shaping unit.

6. The phase sequence detection circuit according to claim 2, characterized in that, The signal shaping module further includes: The eighth resistor is connected between the output terminal of the differential amplifier unit and the input terminal of the square wave shaping unit. The fourth capacitor is connected between the input terminal of the square wave shaping unit and ground.

7. The phase sequence detection circuit according to claim 2, characterized in that, The signal shaping module further includes: The fifth capacitor is connected between the output terminal of the signal shaping module and ground; The first diode is connected between the output terminal of the signal shaping module and ground.

8. The phase sequence detection circuit according to claim 1, characterized in that, Also includes: The main control module is connected to the result output terminal.

9. The phase sequence detection circuit according to claim 8, characterized in that, Also includes: The display is connected to the main control module; And / or, The indicator module is connected to the main control module or the result output terminal.

10. The phase sequence detection circuit according to claim 1, characterized in that, Also includes: A pull-up resistor is provided, with its first end connected to a fixed-level signal and its second end connected to either the main output or the inverting output of the JK flip-flop.

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