Chip high and low temperature test system
Patent Information
- Application Number
- CN202521946432.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-10
- Publication Date
- 2026-11-03
- Estimated Expiration
- 2035-09-10
AI Technical Summary
Existing high and low temperature testing systems for LPDDR chips suffer from uneven temperature distribution on the motherboard and slow heating/cooling rates, which negatively impact testing efficiency and effectiveness.
Thermocouple probes are used to acquire the surface temperature of the chip under test in real time. A multi-level TEC module is used for closed-loop control to precisely control the temperature of only the area of the chip under test. Combined with fans and heat sinks, the heating and cooling rates are improved.
It achieves precise temperature control in the chip testing area, improves the heating and cooling rate, reduces energy consumption, and increases testing efficiency.
Smart Images
Figure CN224934111U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of chip testing technology, and in particular relates to a chip high and low temperature testing system. Background Technology
[0002] LPDDR (Low-Power Double Data Rate SDRAM) is a memory technology designed specifically for mobile devices (such as smartphones, tablets, and wearable devices). It is one of the core components of mobile electronic devices, and its reliability is crucial. LPDDR chips have a relatively high rate of discrete failures due to their physical characteristics. During the R&D and production testing phases, rigorous screening tests are required to identify defective products. According to industry research and practice, temperature has a significant effect on the failure triggering of LPDDR chips. Therefore, high and low temperature factors can be incorporated into the LPDDR chip testing process to accelerate the screening of unqualified products.
[0003] The most common high and low temperature testing system for LPDDR chips is to place the LPDDR chip and the motherboard for testing the LPDDR chip together in a high and low temperature chamber or similar equipment for high and low temperature testing. However, because the entire test motherboard must meet the standards of the LPDDR chip under test, such as LPDDR4(x) products, the automotive-grade AEC-Q100 Grade 1 certification requires a test temperature range of -40℃ to +125℃. This means the test motherboard must also maintain normal operation in an environment of -40℃ to +125℃, placing stringent temperature requirements on it. Moreover, the entire chamber usually has a uniform inlet / outlet for cold / hot air, making it difficult to ensure that the LPDDR chips under test in different locations are all within the set target temperature. To improve production efficiency, multiple test motherboards are usually placed in the same high and low temperature chamber. However, due to differences in air resistance, there are temperature differences in different locations, ranging from several degrees to ten degrees. Placing multiple test motherboards in different locations makes it difficult to ensure that the LPDDR chips under test are all within the set target temperature, affecting the test results. In addition, the high and low temperature chamber has a relatively large space and a slow heating and cooling rate, which affects production testing efficiency. Utility Model Content
[0004] The purpose of this invention is to address the aforementioned problems by providing a high and low temperature chip testing system that heats / cools only the space where the chip under test is placed, and obtains the surface temperature of the chip under test in real time through a thermocouple probe for closed-loop control to achieve precise temperature control. Furthermore, due to the significant reduction in the space to be controlled, the heating / cooling rate of the area where the chip under test is placed can be greatly improved, reducing the energy consumption required for heating / cooling and further improving the efficiency of high and low temperature chip testing.
[0005] To achieve the above objectives, the technical solution adopted by this utility model is as follows:
[0006] A chip high and low temperature testing system includes: high and low temperature testing equipment, a host computer, and a SOC system module;
[0007] The high and low temperature testing equipment includes a test motherboard, a temperature control board, and a temperature adjustment mechanism.
[0008] The test motherboard is equipped with several chip test sockets for placing the chips to be tested.
[0009] The temperature regulation mechanism includes thermocouple probes, silicone pads, multi-stage TEC modules, heat sinks, and fans stacked in sequence.
[0010] The thermocouple probe is placed on the surface of the chip under test and connected to the temperature control board.
[0011] The silicone pad is fixed to the multi-level TEC module by a fixing component.
[0012] The silicone pad is a thermally conductive silicone pad;
[0013] The thermally conductive silicone pad is disposed on the bottom surface of the multi-level TEC module and is in close contact with the surface of the chip under test to exchange heat with the chip under test.
[0014] The multi-level TEC module includes several cascaded TEC components, the upper and lower surfaces of which are cold and hot surfaces.
[0015] The heat sink and the fan are positioned above the multi-stage TEC module to dissipate heat from the multi-stage TEC module.
[0016] The temperature control board is equipped with a logic control unit;
[0017] The temperature control board acquires the surface temperature of the chip under test in real time through the thermocouple probe, and regulates the power of the multi-level TEC module through the logic control unit.
[0018] The chip test socket is equipped with pads or probes for data and signal transmission between the chip under test and the test motherboard.
[0019] The test motherboard uses a SOC chipset for testing the chip under test.
[0020] The SOC system module performs algorithm read and write operations on the chip under test and uploads the recorded algorithm test results to the host computer.
[0021] The host computer is used to coordinate the working status of the SOC system module and the high and low temperature testing equipment, and to statistically record the algorithm test results of the chip under test.
[0022] The beneficial effects of this utility model are:
[0023] This application heats / cools only the space where the chip under test is placed, and obtains the surface temperature of the chip under test in real time through a thermocouple probe for closed-loop control; and because the temperature control space is greatly reduced, the heating / cooling rate of the area where the chip under test is placed can be greatly improved, the energy consumption required for heating / cooling can be reduced, and the high and low temperature testing efficiency of the chip can be further improved.
[0024] To make the above and other objects, features and advantages of this utility model more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the specific embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0026] Figure 1 A framework diagram of a chip high and low temperature testing system provided for an embodiment of this utility model.
[0027] Figure 2 An exploded view of the temperature regulation mechanism provided in an embodiment of this utility model. Detailed Implementation
[0028] The foregoing and other technical contents, features, and effects of this utility model will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the scope of this utility model.
[0029] Example:
[0030] like Figure 1As shown, a high and low temperature chip testing system includes: a high and low temperature testing device 1, a host computer 2, and a SOC (System on Chip) system module 3; the test motherboard 11 uses an SOC chipset to test the chip under test, performs algorithm read and write operations on the chip under test, and uploads the recorded algorithm test results to the host computer 2; the host computer 2 coordinates the working status of the high and low temperature testing device 1 and the SOC system module 3, and records the algorithm test results of the chip under test.
[0031] This application uses high and low temperature testing equipment 1 combined with SOC system module 3 to perform algorithm-level read and write operations on the chip under test, which can more realistically reflect the performance of the chip under test under different temperature conditions, and the test results are more valuable for reference.
[0032] The test motherboard 11 uses a SOC chipset solution. The test motherboard has a high degree of integration and can directly realize the complex algorithm reading and writing of the chip under test without the need to build additional discrete test circuits. This simplifies the test link, reduces signal interference, and improves test accuracy. SOC chipsets typically support multiple interface protocols and algorithm logic, which can be adapted to different types and specifications of chips under test. The collaborative control architecture of the host computer 2 also facilitates the subsequent expansion of test items and improves the reusability of the system.
[0033] The host computer 2 coordinates the testing process (such as synchronous temperature adjustment and algorithm testing process), avoiding the lag of manual operation and significantly improving the efficiency of batch testing. This application records test data through SOC system module 3 and uploads it to host computer 2, which facilitates centralized storage, statistical analysis and traceability of test results of the chip under test in the full temperature range. It can quickly locate the performance bottleneck of the chip under test in high and low temperature environments and provide accurate data support for chip optimization.
[0034] The integrated system design of this application reduces compatibility issues between devices, and the high integration of the SOC solution reduces hardware costs; the automated collaborative control of the host computer 2 simplifies the operation process and reduces the requirements for the professional skills of operators.
[0035] Specifically, such as Figure 2 As shown, the high and low temperature testing equipment 1 includes a test motherboard 11, a temperature control board 12, and a temperature adjustment mechanism; the test motherboard 11 is fixed with several chip test sockets 111 for placing the chip under test; the temperature adjustment mechanism includes thermocouple probes 13, silicone pads 14, multi-stage TEC (Thermoelectric Cooler) modules 15, heat sinks 16, and fans 17 stacked in sequence; the thermocouple probes 13 are placed on the surface of the chip under test and connected to the temperature control board 12.
[0036] The multi-level TEC module 15 achieves bidirectional temperature control (cooling / heating) through the Peltier effect. Combined with the thermocouple probe 13 for real-time monitoring of the chip surface temperature, it can accurately control the temperature environment of the chip under test (temperature control accuracy is usually within ±0.5℃). Moreover, the multi-level structure design can generate a larger temperature difference range (usually -40℃ to 125℃ or even wider) compared to single-level TEC components, meeting the testing requirements of chips under extreme temperatures.
[0037] like Figure 2 As shown, the silicone pad 14 and the multi-level TEC module 15 are fixed by the fixing component 18. The silicone pad 14 is a thermally conductive silicone pad, which is set on the bottom surface of the multi-level TEC module 15. After the assembly is pressed together, the thermally conductive silicone pad 14 is in close contact with the surface of the chip under test, serving as a medium for exchanging heat with the chip under test. The silicone pad 14 is tightly attached to the chip under test and the multi-level TEC module 15, and its high elasticity and thermal conductivity fill the gaps in the contact surface, significantly reducing the contact thermal resistance and improving the heat conduction efficiency.
[0038] Thermocouple probe 13 is placed directly on the surface of the chip under test. Compared with indirect temperature measurement methods, it can more accurately reflect the actual operating temperature of the chip and avoid test errors caused by temperature lag.
[0039] like Figure 2 As shown, the multi-stage TEC module 15 is used for cooling / heating and includes several cascaded TEC components, with the upper / lower surfaces of the TEC components being the cold / hot surfaces. The heat sink 16 and fan 17 are positioned above the multi-stage TEC module 15 to dissipate heat. The heat sink 16 and fan 17 form a high-efficiency heat dissipation combination, which can quickly dissipate the heat from the high-temperature end of the multi-stage TEC module 15 (especially in cooling mode), preventing the multi-stage TEC module 15 from overheating and causing performance degradation or damage, and ensuring stable operation of the equipment during long-term testing.
[0040] like Figure 2 As shown, the test motherboard 11 integrates several chip test sockets 111, supporting simultaneous testing of multiple chips and significantly improving test throughput; the standardized test socket design can be adapted to chips under test with different package types (such as adjusting the socket size or pin definition), enhancing the versatility of the equipment.
[0041] In a preferred embodiment of this utility model, the chip test socket 111 is provided with pads or probes for data and signal transmission between the chip under test and the test motherboard 11.
[0042] For chips with fixed package types (such as mass-produced LPDDR chips), the pads in the test socket 111 can adopt a "custom layout" that directly corresponds to the chip pins one by one, without the need for additional adapters, simplifying the test link; at the same time, the plating on the surface of the pads (such as gold plating) can improve wear resistance and extend the service life of the test socket.
[0043] When using adjustable structures such as spring probes, the test socket can be adapted to chips with different pin specifications (such as switching from LPDDR4 to LPDDR5 testing) by replacing the "probe module" or adjusting the probe spacing, without having to replace the entire test socket 111, which greatly reduces equipment procurement and maintenance costs, and is especially suitable for verification testing of multiple chip models in the R&D stage.
[0044] The chip testing in this application needs to be carried out under harsh conditions such as high and low temperature cycling and long-term operation. The structural design of the pads or probes can ensure connection stability and is compatible with automated loading and unloading equipment (such as robotic arms). It eliminates the need for manual alignment of pins, further improving operational efficiency and reducing problems such as accidental touches and misalignments caused by manual operation. The spring probes continuously apply contact pressure through their own elasticity, which can prevent contact loosening caused by thermal expansion and contraction of materials even in high and low temperature environments (such as -40℃ to 125℃). The pads increase the contact area through "surface contact" and reduce the probability of single-point contact failure. During the test (such as fan cooling and slight equipment vibration), the connection between the pads / probes and the pins of the chip under test is not easy to fall off or become misaligned, reducing test interruptions caused by abnormal connections and ensuring the stability of long-term continuous testing.
[0045] In a preferred embodiment of this utility model, the temperature control board 12 is provided with a logic control unit; the temperature control board 12 obtains the surface temperature of the chip under test in real time through the thermocouple probe 13, and regulates the power of the multi-level TEC module 15 through the logic control unit.
[0046] Specifically, the temperature control board 12 includes a logic control unit, such as an MCU (Microcontroller Unit), a PLC (Programmable Logic Controller), a CPLD (Complex Programmable Logic Device), an FPGA (Field-Programmable Gate Array), or a CPU (Central Processing Unit). The temperature control board 12 acquires the real-time temperature of the surface of the chip under test (LPDDR chip) through a thermocouple probe 13. Based on the difference between the real-time surface temperature of the chip under test (LPDDR chip) and the set value, the duty cycle of the PWM (Pulse Width Modulation) signal controlling the power of the multi-level TEC module is adjusted in real time using a PID (Proportional-Integral-Derivative) algorithm, thereby achieving precise closed-loop control of the temperature of the chip under test (LPDDR chip).
[0047] Specifically, the low-temperature testing process for the chip under test is as follows:
[0048] After the system starts up, the temperature control board 12 controls the operation of the multi-stage TEC module 15. The lower surface of the TEC component is the cold surface and the upper surface is the hot surface. With multiple (usually two or three) TEC components cascaded, the lower surface of the bottommost TEC component can obtain a lower temperature, thereby absorbing heat from the chip under test through the thermal pad 14 to cool the chip under test. In addition, the cooling power of the multi-stage TEC module 15 is adjusted in real time by the temperature feedback from the thermocouple probe 13 placed on the surface of the chip under test, so that the chip under test is stabilized within the set temperature range.
[0049] During this process, the heat generated by the multi-stage TEC module 15 is continuously carried away by the heat sink 16 placed above it and the fan 17. After the chip under test stabilizes within the set temperature range, the SOC system module 3 begins to perform algorithm read and write operations on the chip under test, records the algorithm test results, and uploads them to the host computer 2. The host computer 2 coordinates the working status of the SOC system module 3 and the high and low temperature test equipment 1, and statistically records the test results of the chip under test.
[0050] Specifically, the high-temperature testing process for the chip under test is as follows:
[0051] After the system starts up, the temperature control board 12 reverses the positive and negative terminals of the power supply to the multi-stage TEC module 15, making the upper surface of the TEC component a cold surface and the lower surface a hot surface. With multiple (usually two or three) TEC components cascaded, the lower surface of the bottommost TEC component can obtain a higher temperature, thereby heating the chip under test through the thermal pad 14 and raising the temperature of the chip under test. Furthermore, the cooling power of the multi-stage TEC module 15 is adjusted in real time based on the temperature feedback from the thermocouple probe 13 placed on the surface of the chip under test, so that the chip under test is stabilized within the set temperature range.
[0052] After the chip under test stabilizes within the set temperature range, the SOC system module 3 begins to perform algorithm read and write operations on the chip under test, records the algorithm test results, and uploads them to the host computer 2. The host computer 2 coordinates the working status of the SOC system module 3 and the high and low temperature test equipment 1, and statistically records the test results of the chip under test.
[0053] This application enables LPDDR4X chips to be heated from 25°C to 125°C in less than 80 seconds, while common aging chamber equipment takes 15 minutes to 1 hour to heat up from 25°C to 125°C, depending on the heat output, chamber volume, load, etc.
[0054] This application enables LPDDR4X chips to be cooled from 25°C to -40°C in approximately 210 seconds, while common aging chamber equipment takes anywhere from 40 minutes to 2 hours to cool from 25°C to -40°C, depending on factors such as thermal power, chamber volume, and load.
[0055] Based on the data comparison above, this application can significantly improve the heating / cooling rate of the area where the chip under test is placed, reduce the energy consumption required for heating / cooling, and further improve the high and low temperature testing efficiency of the chip.
[0056] In summary, this application provides a chip high and low temperature testing system that heats / cools only the space where the chip under test is placed, and obtains the surface temperature of the chip under test in real time through a thermocouple probe for closed-loop control to achieve precise temperature control. Furthermore, due to the significant reduction in the space to be controlled, the heating / cooling rate of the area where the chip under test is placed can be greatly improved, the energy consumption required for heating / cooling can be reduced, and the efficiency of high and low temperature testing of the chip can be further improved.
[0057] Although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
[0058] The detailed descriptions listed above are merely specific descriptions of feasible implementation methods of this utility model, and are not intended to limit the scope of protection of this utility model. All equivalent implementation methods or modifications made without departing from the spirit of this utility model should be included within the scope of protection of this utility model.
Claims
1. A chip high and low temperature testing system, characterized in that, include: High and low temperature testing equipment (1), host computer (2), and SOC system module (3); The high and low temperature testing equipment (1) includes a test main board (11), a temperature control board (12), and a temperature adjustment mechanism; The test motherboard (11) is fixed with several chip test sockets (111) for placing the chip to be tested; The temperature regulation mechanism includes a thermocouple probe (13), a silicone pad (14), a multi-stage TEC module (15), a heat sink (16), and a fan (17) stacked in sequence; The thermocouple probe (13) is placed on the surface of the chip under test and connected to the temperature control board (12).
2. The chip high and low temperature testing system according to claim 1, characterized in that, The silicone pad (14) and the multi-level TEC module (15) are fixed together by a fixing component (18).
3. The chip high and low temperature testing system according to claim 2, characterized in that, The silicone pad (14) is a thermally conductive silicone pad; The thermally conductive silicone pad (14) is disposed on the bottom surface of the multi-level TEC module (15) and is in close contact with the surface of the chip under test to exchange heat with the chip under test.
4. The chip high and low temperature testing system according to claim 1, characterized in that, The multi-level TEC module (15) includes several cascaded TEC components, the upper / lower surfaces of which are cold / hot surfaces.
5. The chip high and low temperature testing system according to claim 1, characterized in that, The heat sink (16) and the fan (17) are disposed above the multi-level TEC module (15) to dissipate heat from the multi-level TEC module (15).
6. The chip high and low temperature testing system according to claim 1, characterized in that, The temperature control board (12) is equipped with a logic control unit; The temperature control board (12) acquires the surface temperature of the chip under test in real time through the thermocouple probe (13), and regulates the power of the multi-level TEC module (15) through the logic control unit.
7. The chip high and low temperature testing system according to claim 1, characterized in that, The chip test socket (111) is provided with pads or probes for data and signal transmission between the chip under test and the test motherboard (11).
8. A chip high and low temperature testing system according to claim 7, characterized in that, The test motherboard (11) uses an SOC chipset to test the chip under test.
9. A chip high and low temperature testing system according to claim 8, characterized in that, The SOC system module (3) performs algorithm read and write operations on the chip under test and uploads the recorded algorithm test results to the host computer (2).
10. A chip high and low temperature testing system according to claim 9, characterized in that, The host computer (2) is used to coordinate the working status of the high and low temperature test equipment (1) and the SOC system module (3), and to statistically record the algorithm test results of the chip under test.