Packaging structure

Abstract

Some embodiments of the present application provide a package structure, comprising: a substrate; a processor disposed on the substrate; a molding compound encapsulating the processor; a memory disposed above the processor; and a pillar structure connected to the memory, wherein the pillar structure extends through the molding compound and is in direct contact with the molding compound, wherein the processor and the memory are at different levels and do not overlap in a vertical direction. The present application makes the package structure free from warpage matching risk by making the processor and the memory not overlap in the vertical direction, making the process relatively easy and improving the heat dissipation performance of the package structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor structure technology, and more specifically, to a packaging structure. Background Technology

[0002] Currently, memory packaging utilizes PoP (Polypture on Packaging) technology. For details, see... Figure 1A and Figure 1B In the existing package structure 10, the memory 11 is stacked on top of the processor 12 on a printed circuit board (PCB) 13. This makes heat dissipation difficult during processor 12 operation, and the warpage of both the processor 12 and the memory 11 makes bonding difficult. Therefore, this package structure 10 has disadvantages such as poor heat dissipation, difficulty in warpage matching, and difficulty in packaging, as detailed below:

[0003] (1) Poor heat dissipation: Because the memory 11 is stacked on top of the processor 12, the heat dissipation of the processor 12 is hindered;

[0004] (2) Warp matching difficulty: Due to the different structures of memory 11 and processor 12, their respective warps interfere with each other, making assembly difficult; and

[0005] (3) Cost-effectiveness: The current packaging method is OSAT (Outsourced Semiconductor Packaging and Testing), which stacks the memory 11 on top of the processor 12. This will affect the yield of the corresponding packaging structure and thus affect the packaging cost.

[0006] Therefore, a new packaging structure is needed to solve the above problems. Utility Model Content

[0007] To address the aforementioned issues, this application employs a side-by-side (misaligned) approach for the processor and memory. Processor attachment operations are performed first, followed by memory attachment operations in later stages of manufacturing. This eliminates the need to consider memory warpage during processor manufacturing. In this application, the later memory operations are considered later stages, thus improving packaging cost-effectiveness. Furthermore, a heatsink can be added above the processor, allowing heat to be dissipated and improving heat dissipation.

[0008] Some embodiments of this application provide a packaging structure including: a substrate; a processor disposed on the substrate; a molding compound molding the processor; a memory disposed above the processor; and a pillar structure connected to the memory, wherein the pillar structure extends through the molding compound and is in direct contact with the molding compound, wherein the processor and the memory are located at different levels and do not overlap in the vertical direction.

[0009] In some embodiments, the package structure further includes a heat sink disposed above the processor and surrounding the memory, wherein the memory is disposed within a cavity of the heat sink.

[0010] In some embodiments, the packaging structure further includes a thermal interface material disposed between the molding compound and the heat sink, wherein the thermal interface material is in direct contact with the processor, the heat sink and the pillar structure.

[0011] In some embodiments, the memory is surrounded on three sides by the heat sink when viewed from above.

[0012] In some embodiments, when viewed from above, the heat sink forms an open area and exposes a portion of the thermal interface material.

[0013] In some embodiments, the memory is spaced apart from the sidewall of the non-enclosed region of the heat sink.

[0014] In some embodiments, the pillar structure is disposed around the processor and directly below the memory.

[0015] In some embodiments, the top surface of the column structure is flush with the top surface of the processor.

[0016] In some embodiments, the bottom surface of the memory is higher than the top surface of the processor.

[0017] In some embodiments, the processor includes an application-specific integrated circuit (ASIC).

[0018] In some embodiments, when viewed from above, the exposed portion of the thermal interface material surrounds the memory.

[0019] In some embodiments, the processor is coupled to the substrate via a first conductive connector.

[0020] In some embodiments, the substrate includes a printed circuit board.

[0021] In some embodiments, the thermal interface material is further in direct contact with the molding compound and spaced apart from the memory.

[0022] In some embodiments, the memory is coupled to the pillar structure via a second conductive connector, wherein the second conductive connector extends through the thermal interface material.

[0023] In some embodiments, the packaging structure further includes: a bottom filler that seals the first conductive connector and is disposed between the processor and the substrate.

[0024] In some embodiments, the package structure further includes an external connector disposed on the side of the substrate opposite to the processor.

[0025] Other embodiments of this application provide a packaging structure including: a substrate; a processor disposed on the substrate; a molding compound molding the processor; a pillar structure disposed around the processor and extending through the molding compound; and a memory coupled to the pillar structure, wherein the pillar structure is disposed directly below the memory and at the same level as the processor, and wherein the top surface of the pillar structure is flush with the top surface of the processor.

[0026] In some embodiments, the bottom surface of the memory is higher than the top surface of the processor.

[0027] In some embodiments, the packaging structure further includes: a heat sink disposed above the processor and surrounding the memory; and a thermal interface material disposed between the molding compound and the heat sink, wherein the memory is disposed within a cavity of the heat sink, and wherein the thermal interface material is in direct contact with the processor, the heat sink and the pillar structure.

[0028] This application arranges the processor and memory side-by-side, ensuring they do not overlap vertically. This eliminates the risk of warpage in the package structure and simplifies the manufacturing process. Furthermore, a heatsink is placed above the processor, improving the heat dissipation performance of the package structure. Attached Figure Description

[0029] The various aspects of this utility model can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0030] Figure 1A and Figure 1B The packaging structure in the prior art is shown.

[0031] Figure 2 and Figure 3 The packaging structure according to some embodiments of this application is shown.

[0032] Figures 4 to 13 The process flow of the packaging structure according to some embodiments of this application is shown. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art are within the scope of protection of this application. In addition, when using terms such as "approximately," "about," "substantial," or "basically" to describe numerical values ​​or numerical ranges, unless otherwise stated, the term is intended to cover values ​​within ±10% of the described value. For example, the term "about 5nm" covers a size range from 4.5nm to 5.5nm.

[0034] The packaging structure of this application attaches the processor and memory in a side-by-side (misaligned) manner. In the corresponding manufacturing process, the attachment operations such as the processor are performed first, and the attachment operations such as the memory are performed in subsequent processes, so that the processor manufacturing process does not need to take into account the warpage behavior of the memory. In this application, the subsequent memory operation is a later-stage operation, thus improving packaging cost-effectiveness. In addition, a heat sink can be installed on top of the processor, allowing the heat source to be transferred away through the heat sink, thereby improving the heat dissipation effect.

[0035] Specifically, see Figure 2 , Figure 2 A packaging structure 100 according to some embodiments of this application is shown. From Figure 2 As can be seen from the image, the packaging structure 100 includes: a substrate 101, a processor 102 disposed on the substrate 101, a molding compound 104 encapsulating the processor 102, and a memory 103 disposed above the processor 102. Figure 2 As can be seen, the processor 102 and the memory 103 are located at different levels and do not overlap in the vertical direction D. The package structure 100 also includes pillar structures 105, which are connected to the memory 103, further... Figure 2 As can be seen, the pillar structure 105 extends through the molding compound 104 and is in direct contact with the molding compound 104. In this application, the pillar structure 105 is in direct contact with the molding compound 104, which reduces the variety of materials used in the subsequent polishing process and lowers the risk of delamination of the corresponding encapsulation structure 100.

[0036] In some embodiments, the pillar structure 105 is disposed around the processor 102 and directly below the memory 103. Figure 2In the illustrated embodiment, the top surface 105t of the pillar structure 105 is flush with the top surface 102t of the processor 102, and the bottom surface 103d of the memory 103 is higher than the top surface 102t of the processor 102. Therefore, in this application, the pillar structure 105 and the processor 102 are at the same level, while the memory 103 is at a level above the pillar structure 105 and the processor 102, and is located directly above the pillar structure 105. In this application, the processor 102 and the memory 103 are arranged (attached) side-by-side (misaligned), thereby improving the yield and heat dissipation performance of the corresponding package structure 100. In some embodiments, the processor 102 includes, but is not limited to, an application-specific integrated circuit (ASIC). In some embodiments, the substrate 101 is or includes a printed circuit board (PCB). In some embodiments, the molding compound 104 may include molding compounds, epoxy composites, etc. In some embodiments, the pillar structure 105 may be, but is not limited to, metals or metal alloys such as copper, gold, and silver.

[0037] also, Figure 2 The illustrated package structure 100 also includes a heat sink 106 disposed above the processor 102 and surrounding the memory 103, wherein the memory 103 is disposed within the cavity R of the heat sink 106. In a further embodiment, the package structure 100 further includes a thermal interface material 107 disposed between the molding compound 104 and the heat sink 106, such as... Figure 2 As shown, the thermal interface material 107 is in direct contact with the processor 102, the heat sink 106, and the pillar structure 105. Furthermore, the thermal interface material 107 is in direct contact with the molding compound 104 and is spaced apart from the memory 103. Figure 2 As shown, the memory 103 is bonded to the pillar structure 105 via a second conductive connector 111 extending through the thermal interface material 107. In some embodiments, the second conductive connector 111 may include a copper pillar 111A and microbumps 111B located on the copper pillar 111A; in some embodiments, the microbumps 111B are made of solder. In some embodiments, the heat sink 106 may include, but is not limited to, a metal or metal alloy such as copper. In some embodiments, the thermal interface material 107 is a material with high thermal conductivity and may include, but is not limited to, a material such as thermally conductive adhesive.

[0038] Figure 3 A top view of the package structure 100 is shown, and Figure 2 It is along Figure 3 The cross-sectional view of line AA. (See diagram below.) Figure 3 As shown, in a top view, the memory 103 is surrounded on three sides by a heat sink 106; that is, the cavity R of the heat sink 106 is defined on three sides by the heat sink 106. In a further embodiment, from Figure 3As can be seen from above, the heat sink 106 forms a non-enclosed region (formed through cavity R) and exposes a portion of the thermal interface material 107, and the exposed portion of the thermal interface material 107 surrounds the memory 103. Furthermore, the memory 103 is spaced apart from the sidewalls 106s of the non-enclosed region of the heat sink 106.

[0039] Return to reference Figure 2 The processor 102 is bonded to the substrate 101 via a first conductive connector 108, specifically, connected to a pad 101P1 on the substrate 101. In some embodiments, the first conductive connector 108 may include a copper pillar 108A and microbumps 108B located on the copper pillar 108A; in some embodiments, the microbumps 108B are made of solder. Further, an underfill 109 seals the first conductive connector 108 and is disposed between the processor 102 and the substrate 101. In some embodiments, the underfill 109 includes, but is not limited to, materials such as epoxy composites and molding compounds. Further, the package structure 100 also includes an external connector 110 disposed on the side of the substrate 101 opposite to the processor 102 and connected to the pad 101P2 of the substrate 101. In a further embodiment, the substrate 101 has a dielectric layer 101D and metal lines 101L disposed in the dielectric layer 101D and vias 101V connecting the metal lines 101L for electrical connection. In some embodiments, the external connector 110 may include solder or the like. In some embodiments, the dielectric layer 104 is formed of a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. In other embodiments, the dielectric layer 104 is formed of a nitride, such as silicon nitride; an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. In some embodiments, the metal line 101L and the via 101V may include a metal such as copper. In some embodiments, the pads 101P1 and 101P2 may include a metal such as copper.

[0040] Reference Figure 2Other embodiments of this application provide a package structure 100, including: a substrate 101; a processor 102 disposed on the substrate 101; a molding compound 104 molding the processor 102; a pillar structure 105 disposed around the processor 102 and extending through the molding compound 104; and a memory 103 coupled to the pillar structure 105, wherein the pillar structure 105 is disposed directly below the memory 103 and at the same level as the processor 102, and wherein the top surface 105t of the pillar structure 105 is flush with the top surface 102t of the processor 102. In some embodiments, the bottom surface 103d of the memory 103 is higher than the top surface 102t of the processor 102. In some embodiments, the package structure 100 further includes: a heat sink 106 disposed above the processor 102 and surrounding the memory 103; and a thermal interface material 107 disposed between the molding compound 104 and the heat sink 106, wherein the memory 103 is disposed within the cavity R of the heat sink 106, and wherein the thermal interface material 107 is in direct contact with the processor 102, the heat sink 106 and the pillar structure 105.

[0041] In summary, the packaging structure 100 provided in this application has the following advantages:

[0042] (1) Excellent heat dissipation effect, because a heat sink 106 is installed above the processor 102 (processor), so that the heat source is transferred out through the heat sink 106.

[0043] (2) No warpage matching risk, because the processor 102 and memory 103 are arranged side by side, so the manufacturing process of the processor 102 does not need to take into account the warpage behavior of the memory 103; and

[0044] (3) The process packaging is relatively easy because the processor 102 and the memory 103 are set up side by side. Therefore, the attachment operation of the processor 102 can be performed first, and the attachment operation of the memory 103 can be performed in the later process, which can improve the cost-effectiveness of packaging.

[0045] The following reference Figures 4 to 13 Let me introduce Figure 2 The forming process of the package structure 100 shown.

[0046] First, see Figure 4 A carrier 1001 is provided, which can be any suitable carrier, such as a glass carrier, a silicon carrier, etc. In this embodiment, a glass carrier can be used. See also Figure 5A release membrane 1002 is coated onto the carrier 1001. The release membrane 1002 may be formed of a polymer-based material and can be removed from the above structure along with the carrier 1001 in a subsequent step. In some embodiments, the release membrane 1002 may be a UV adhesive that loses its adhesiveness when exposed to UV light. The release membrane 1002 may be dispensed in liquid form and cured, and may be a laminated film or the like laminated onto the carrier 1001.

[0047] See Figure 6 A substrate 101 is formed on a carrier 1001 and a release mold 1002. Specifically, a dielectric layer 101D is formed on the carrier 1001 and the release mold 1002, the bottom surface of which may contact the top surface of the release mold 1002. In some embodiments, the dielectric layer 101D is formed of a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. In other embodiments, the dielectric layer 104 is formed of nitrides such as silicon nitride; oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. The dielectric layer 101D can be formed by any acceptable deposition process such as spin coating, chemical vapor deposition (CVD), lamination, or combinations thereof.

[0048] A via 101V is formed in the dielectric layer 101D, and a metal line 101L is formed on the dielectric layer 101D. Specifically, the dielectric layer 101D can be patterned using processes commonly used in the art to form an opening through the dielectric layer 101D. A conductive material is formed in the opening and on the dielectric layer 101D. The conductive material can be formed by plating, such as electroplating or chemical plating. The conductive material can include metals such as copper, titanium, tungsten, and aluminum, thereby forming the metal line 101L and the via 101V. The steps of forming the dielectric layer 101D, the metal line 101L, and the via 101V are then repeated until a substrate 101 of the desired thickness is formed. After forming the substrate 101, pillar structures 105, such as copper pillars, are formed on portions of the substrate 101 by plating processes such as electroplating or chemical plating.

[0049] Next, see Figure 7 The processor 102 is attached to the pad 101P1 of the substrate 101 via the first conductive connector 108. In this embodiment, the first conductive connector 108 includes a copper pillar 108A and microbumps 108B located on the copper pillar 108A.

[0050] See Figure 8After attaching the processor 102, an underfill 109 can be formed between the processor 102 and the substrate 101 and around the first conductive connector 108. The underfill 109 can reduce stress. In some embodiments, the underfill 109 can be formed by a capillary flow process.

[0051] See Figure 9 The molding compound 104 is formed by a molding process, such as using molding compound. After the molding compound 104 is formed, the molding compound 104 is ground by a grinding process to expose the top surface 102t of the processor 102 and the top surface 105t of the pillar structure 105, and the top surface 102t of the processor 102 is flush with the top surface 105t of the pillar structure 105.

[0052] See Figure 10 The heat sink 106 is attached to the molding compound 104, the processor 102, and the pillar structure 105 via the thermal interface material 107. Figure 10 As can be seen, the heat sink 106 may have a cavity R directly above the pillar structure 105 for attaching the memory 103.

[0053] See Figure 11 Carrier debonding is performed to separate carrier 1001 from substrate 101 (debonding). See also Figure 12 A pad 101P2 is formed on the side of the substrate 101 opposite to the processor 102, and an external connector 110 is formed on the pad 101P2 using a ball mounting process. In some embodiments, the external connector 110 may be a solder ball. In some embodiments, the external connector 110 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof. In some embodiments, the external connector 110 may be formed by first forming a solder layer using common methods such as evaporation, electroplating, printing, solder transfer, ball mounting, etc. Once the solder layer has been formed on the structure, reflow may be performed to shape the material into the desired bump shape.

[0054] After the external connector 110 is formed, see Figure 13 Through sawing process Figure 12 The resulting structure is cut to form individual structures. Finally, the memory 103 is attached to the pillar structure 105 through the cavity R of the heat sink 106, thereby obtaining... Figure 2 The packaging structure 100 shown is shown.

[0055] In summary, this application employs a side-by-side (misaligned) arrangement of the processor 102 and memory 103. The attachment operation of the processor 102 (such as a processor) is performed first, followed by the attachment operation of the memory 103 (such as a memory) in a later-stage process. This eliminates the need to consider the warpage behavior of the memory 103 during the processor 102 manufacturing process. In this application, the memory 103 is a later-stage process, thus improving the cost-effectiveness of the package structure 100. Furthermore, a heat sink 106 can be added above the processor 102, allowing heat to be transferred away, thereby improving the heat dissipation effect of the package structure 100.

[0056] Furthermore, this design utilizes the side-by-side chips of the substrate 101 with a fan-out and then distribution structure to reduce the process risk of stacked package (POP) structures, and therefore can also be applied to processes such as passive component SiP (silicon phosphide) packaging.

[0057] The features of several embodiments have been summarized above to enable those skilled in the art to better understand aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present invention.

Claims

1. A packaging structure, characterized in that, include: substrate; A processor is disposed on the substrate; Molded compound, used to mold the processor; The memory is located above the processor; as well as A pillar structure, connected to the memory, wherein the pillar structure extends through the molding compound and is in direct contact with the molding compound. The processor and the memory are located at different levels and do not overlap in the vertical direction.

2. The packaging structure according to claim 1, characterized in that, Also includes: A heat sink is disposed above the processor and surrounding the memory. The memory is disposed inside the cavity of the heat sink.

3. The packaging structure according to claim 2, characterized in that, Also includes: A thermal interface material is disposed between the molding compound and the heat sink. The thermal interface material is in direct contact with the processor, the heat sink, and the column structure.

4. The packaging structure according to claim 3, characterized in that, When viewed from above, the radiator forms an open area and exposes a portion of the thermal interface material.

5. The packaging structure according to claim 4, characterized in that, The memory is spaced apart from the sidewall of the non-enclosed area of ​​the heat sink.

6. The packaging structure according to claim 1, characterized in that, The top surface of the column structure is flush with the top surface of the processor.

7. The packaging structure according to claim 1, characterized in that, The bottom surface of the memory is higher than the top surface of the processor.

8. The packaging structure according to claim 4, characterized in that, When viewed from above, the exposed portion of the thermal interface material surrounds the memory.

9. The packaging structure according to claim 3, characterized in that, The thermal interface material is further in direct contact with the molding compound and spaced apart from the memory.

10. The packaging structure according to claim 3, characterized in that, The memory is connected to the pillar structure via a second conductive connector. The second conductive connector extends through the thermal interface material.

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