Packaging assembly and electronic device

Abstract

The application relates to the technical field of semiconductors, and provides a packaging assembly and electronic equipment. The packaging assembly comprises a base layer, a first heat-conducting member, a heat-dissipating member, a plurality of second heat-conducting members and a heat buffer. The first heat-conducting member is connected with a bearing part of the base layer, heat generated by a chip after operation can be conducted to the first heat-conducting member, the heat generated by the chip can be conducted to the heat buffer through the first heat-conducting member, and the heat can be dispersed to each part of the heat buffer. The heat generated by the chip can also be conducted to the plurality of second heat-conducting members through the heat buffer, the plurality of second heat-conducting members can efficiently conduct the heat generated by the chip to the heat-dissipating member, so that the heat can be dissipated. The heat generated by the chip is conducted to the plurality of second heat-conducting members, the heat can be dispersed in the plurality of second heat-conducting members, thereby preventing the heat from being concentrated in a certain area in the base layer, and further preventing the temperature of a local area of the packaging assembly from being too high.

Description

Technical Field

[0001] This application relates to a packaging component and an electronic device, belonging to the field of semiconductor technology. Background Technology

[0002] As electronic equipment systems such as optoelectronic co-packaging, high-bandwidth memory, silicon photonics interconnect, high-speed optical communication, and RF power amplifiers continue to develop towards high performance, miniaturization, and high integration, the heat flux generated by chips in the packaging structure has increased significantly, and thermal management has become one of the core bottlenecks affecting system stability and reliability.

[0003] Currently, heat dissipation in electronic device packaging structures mainly uses copper pillars, but this heat dissipation method has low heat diffusion efficiency, which leads to heat concentration and thus low heat dissipation efficiency. Utility Model Content

[0004] This application provides a packaging component and an electronic device to solve the problem of low heat dissipation efficiency in packaging structures in the related art.

[0005] To achieve the above objectives, this application adopts the following technical solution:

[0006] In a first aspect, this application provides a packaging component, including:

[0007] The base layer has a support portion for supporting the chip on one side surface in the thickness direction;

[0008] A first heat-conducting element is inserted into the base layer along the thickness direction of the base layer, and one end of the first heat-conducting element is connected to the bearing part;

[0009] The heat dissipation component is stacked on the side of the base layer facing away from the supporting part;

[0010] Multiple second heat-conducting elements are provided, each of which extends through the base layer along its thickness direction. One end of each second heat-conducting element is connected to the heat dissipation element, and the multiple second heat-conducting elements are spaced apart.

[0011] A thermal buffer is disposed within the base layer. The thermal buffer has a first side and a second side opposite to each other in the thickness direction. The end of the first thermal conductive member opposite to the bearing portion is connected to the first side, and the end of the second thermal conductive member opposite to the heat dissipation member is connected to the second side.

[0012] In some embodiments, there are also multiple first heat-conducting elements, and the multiple first heat-conducting elements are arranged at intervals, and the number of first heat-conducting elements is less than the number of second heat-conducting elements.

[0013] In some embodiments, a plurality of the first heat-conducting elements are spaced apart along a first direction; and / or,

[0014] Multiple second heat-conducting elements are spaced apart along the first direction;

[0015] The first direction is perpendicular to the thickness direction of the base layer.

[0016] In some embodiments, a plurality of the first heat-conducting elements are further spaced apart along a second direction; and / or,

[0017] Multiple second heat-conducting elements are also spaced apart along the second direction;

[0018] The first direction, the second direction, and the thickness direction of the base layer are perpendicular to each other.

[0019] In some embodiments, the spacing between at least partially adjacent first heat-conducting elements differs along the first direction and the second direction; and / or,

[0020] Along the first direction and the second direction, the spacing between at least some of the adjacent second heat-conducting elements is different.

[0021] In some embodiments, along the first direction, the distance between the two outermost first heat-conducting elements is a first distance, and the distance between the two outermost second heat-conducting elements is a second distance, wherein the first distance is smaller than the second distance; and / or,

[0022] Along the second direction, the distance between the two outermost first heat-conducting elements is the third distance, and the distance between the two outermost second heat-conducting elements is the fourth distance, wherein the third distance is smaller than the fourth distance.

[0023] In some embodiments, a plurality of the first heat-conducting elements are arranged at circumferential intervals along a predetermined circumference; and / or,

[0024] Multiple second heat-conducting elements are arranged at circumferential intervals along the preset circumference.

[0025] In some embodiments, a plurality of the first heat-conducting elements are further arranged radially at intervals along the predetermined circumference; and / or,

[0026] The plurality of second heat-conducting elements are also arranged radially at intervals along the preset circumference.

[0027] In some embodiments, the packaging assembly further includes a solder layer disposed on the carrier portion, the side of the solder layer facing away from the carrier portion being used for connection with the chip.

[0028] In some embodiments, the packaging assembly further includes a wiring layer that extends through the substrate along its thickness direction, the wiring layer being used for electrical connection to the chip.

[0029] In some embodiments, the surface of the wiring layer facing away from the substrate and the surface of the solder layer facing away from the substrate are on the same plane.

[0030] In some embodiments, the wiring layer and the soldering layer are an integral structure.

[0031] In some embodiments, the weld layer includes a plurality of weld sublayers, and the plurality of weld sublayers are arrayed on one side surface of the base layer in the thickness direction.

[0032] In some embodiments, the welding layer and the wiring layer are made of copper or copper alloy, and the first heat-conducting element and the second heat-conducting element are both made of copper.

[0033] In some embodiments, the thermal buffer is made of graphite, aluminum nitride, or copper.

[0034] In some embodiments, the base layer includes a first layer and a second layer, the first heat-conducting element is inserted through the first layer, the second heat-conducting element is inserted through the second layer, the second layer has a mounting groove, the heat buffer is disposed in the mounting groove, the first layer is stacked on the second layer, and the first layer seals the opening of the mounting groove.

[0035] In some embodiments, the encapsulation assembly further includes a dielectric layer stacked on the side of the solder layer facing away from the base layer.

[0036] Secondly, based on the packaging components described above, this application also provides an electronic device, including a chip and the packaging components described above, wherein the chip is disposed on the carrier portion.

[0037] In the packaging assembly provided in this application, the carrier portion of the base layer can be used to mount the chip. A first thermal conductive element is connected to the carrier portion, and the heat generated by the chip during operation can be conducted to the first thermal conductive element. The heat generated by the chip can be conducted to a thermal buffer through the first thermal conductive element, and the heat can be distributed to various parts of the thermal buffer. The heat generated by the chip can also be conducted to multiple second thermal conductive elements through the thermal buffer, and the multiple second thermal conductive elements can efficiently conduct the heat generated by the chip to a heat sink so that the heat can be dissipated. The conduction of the heat generated by the chip to multiple second thermal conductive elements can disperse the heat among the multiple second thermal conductive elements, thereby preventing heat from concentrating in a local area within the base layer, and thus preventing the local temperature of the packaging assembly from becoming too high.

[0038] The electronic device provided in this application, including the aforementioned packaging components, enables the electronic device to operate at a lower temperature and to operate more safely and stably. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 A schematic diagram of the encapsulation components provided in the embodiments of this application;

[0041] Figure 2 A schematic diagram of the first thermal conductive element of the encapsulation assembly provided in the embodiments of this application. Figure 1 ;

[0042] Figure 3 Schematic diagram of the second thermal conductive element of the encapsulation assembly provided in the embodiments of this application. Figure 1 ;

[0043] Figure 4 A schematic diagram of the first thermal conductive element of the encapsulation assembly provided in the embodiments of this application. Figure 2 ;

[0044] Figure 5 Schematic diagram of the second thermal conductive element of the encapsulation assembly provided in the embodiments of this application. Figure 2 ;

[0045] Figure 6 A schematic diagram of the first thermal conductive element of the encapsulation assembly provided in the embodiments of this application. Figure 3 ;

[0046] Figure 7 Schematic diagram of the second thermal conductive element of the encapsulation assembly provided in the embodiments of this application. Figure 3 ;

[0047] Figure 8 This is a schematic diagram of the solder layer of the encapsulation component provided in the embodiments of this application;

[0048] Figure 9 This is a schematic diagram of the dielectric layer of the encapsulation component provided in the embodiments of this application;

[0049] Figure 10 This is a schematic diagram of the first layer of the encapsulation component provided in an embodiment of this application;

[0050] Figure 11 This is a schematic diagram of the second layer of the encapsulation component provided in an embodiment of this application.

[0051] Explanation of reference numerals in the attached figures:

[0052] 100 - Base layer; 110 - First layer; 111 - Bearing component; 112 - First opening; 120 - Second layer; 121 - Mounting groove; 122 - Second opening;

[0053] 200 - First heat-conducting component;

[0054] 300 - Second heat-conducting component;

[0055] 400 - Heat sink;

[0056] 500 - Thermal buffer; 510 - First side; 520 - Second side;

[0057] 600 - Weld layer; 610 - Weld sublayer; 620 - Dielectric layer;

[0058] 700 - Wiring layer;

[0059] 800-chip. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0061] As electronic equipment systems such as optoelectronic co-packaging, high-bandwidth memory, silicon photonics interconnect, high-speed optical communication, and RF power amplifiers continue to develop towards high performance, miniaturization, and high integration, the heat flux generated by chips in the packaging structure has increased significantly, and thermal management has become one of the core bottlenecks affecting system stability and reliability.

[0062] Currently, heat dissipation in electronic device packaging structures mainly uses copper pillars, but this heat dissipation method has low heat diffusion efficiency, which leads to heat concentration and thus low heat dissipation efficiency.

[0063] In the packaging assembly proposed in this application, the support portion of the base layer can be used to mount the chip. A first thermal conductive element is connected to the support portion, and the heat generated by the chip during operation can be conducted to the first thermal conductive element. The heat generated by the chip can be conducted to a thermal buffer through the first thermal conductive element, and the heat can be distributed to various parts of the thermal buffer. The heat generated by the chip can also be conducted to multiple second thermal conductive elements through the thermal buffer, and the multiple second thermal conductive elements can efficiently conduct the heat generated by the chip to a heat sink so that the heat can be dissipated. The conduction of the heat generated by the chip to multiple second thermal conductive elements can disperse the heat among the multiple second thermal conductive elements, thereby preventing heat from concentrating in a local area within the base layer, and thus preventing the local temperature of the packaging assembly from becoming too high.

[0064] The electronic device proposed in this application, including the aforementioned packaging components, enables the electronic device to operate at a lower temperature and to operate more safely and stably.

[0065] The contents of this application will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can have a clearer and more detailed understanding of the contents of this application.

[0066] This application proposes an encapsulated component, with reference to... Figure 1 As shown, it includes a base layer 100, a first thermal conductive element 200, a heat sink 400, a thermal buffer 500, and multiple second thermal conductive elements 300. This encapsulation assembly can be used in electronic devices.

[0067] The base layer 100 serves as the fundamental component of the encapsulation assembly of this application. The base layer 100 provides a mounting base for at least some other components of the encapsulation assembly and protects those components. The base layer 100 may be made of glass, which possesses excellent electrical insulation, dielectric stability, and mechanical and thermal stability. The glass base layer 100 also offers higher dimensional accuracy and optical translucency, resulting in superior durability and reliability.

[0068] The base layer 100 has a bearing portion 111, which is located on one side of the base layer 100 in the thickness direction. The bearing portion 111 is used to mount the chip 800. The thickness direction of the base layer 100 is... Figure 1 The chip 800 is fixed to the support portion 111, thereby fixing the chip 800 to the support portion 111. The first heat-conducting element 200 penetrates the base layer 100 along the thickness direction of the base layer 100, and one end of the first heat-conducting element 200 is connected to the support portion 111. For details, refer to... Figure 10The base layer 100 has a first opening 112 through which the first heat-conducting element 200 passes. The inner diameter of the first opening 112 matches the outer diameter of the first heat-conducting element 200, so that the sidewall of the first heat-conducting element 200 can fit against the inner wall of the first opening 112, thereby fixing the first heat-conducting element 200 within the first opening 112. Since the first heat-conducting element 200 is connected to the supporting portion 111, the chip 800 disposed on the supporting portion 111 can also directly or indirectly contact the first heat-conducting element 200. The heat generated by the chip 800 during operation can be conducted to the first heat-conducting element 200.

[0069] A thermal buffer 500 is disposed within the base layer 100. The thermal buffer 500 has a first side 510 and a second side 520 opposite to each other in the thickness direction. The end of the first thermal conductive member 200 opposite to the bearing portion 111 is connected to the first side 510. In this way, the heat generated by the chip 800 can be conducted to the thermal buffer 500 through the first thermal conductive member 200.

[0070] refer to Figure 11 As shown, the base layer 100 also has a second opening 122. Multiple second heat-conducting elements 300 are disposed through the second opening 122 along the thickness direction of the base layer 100, thus penetrating the base layer 100. The multiple second heat-conducting elements 300 are spaced apart. One end of each of the multiple second heat-conducting elements 300 is connected to the second side 520 of the heat buffer 500. Heat generated by the chip 800 is conducted to the heat buffer 500 through the first heat-conducting element 200, and can then be conducted to the multiple second heat-conducting elements 300 through the heat buffer 500.

[0071] The heat sink 400 is disposed on the side of the base layer 100 facing away from the bearing portion 111, so that the heat sink 400 is located on the surface of the base layer 100 and can be exposed to the air. The second heat-conducting element 300 is connected to the heat sink 400 on the side facing away from the heat buffer 500. Heat conducted to the second heat-conducting element 300 can also be conducted to the heat sink 400 and dissipated into the air through the heat sink 400.

[0072] The multiple second heat-conducting elements 300 are spaced apart within the base layer 100 in a direction perpendicular to the thickness direction of the base layer 100. This allows the heat generated by the chip 800 to be distributed among the multiple second heat-conducting elements 300, enabling the heat to be conducted to the heat sink 400 more efficiently. This allows the heat generated by the chip 800 to be conducted to the heat sink 400 more efficiently, and then dissipated into the air more efficiently through the heat sink 400.

[0073] Furthermore, multiple second heat-conducting components 300 are distributed in various areas within the base layer 100. After the heat generated by the chip 800 is conducted to these components, it can also be distributed throughout the base layer 100. This ensures that the heat generated by the chip 800 is distributed across the base layer 100, preventing heat concentration in any single area and resulting in a more balanced temperature across the packaged component. This prevents damage from excessively high temperatures in any single area of ​​the packaged component.

[0074] In some embodiments, to further improve the heat dissipation efficiency of the packaging assembly of this application, the number of first thermal conductive elements 200 can also be set to multiple. Multiple first thermal conductive elements 200 are also spaced apart and pass through the base layer 100. One side of each of the multiple first thermal conductive elements 200 is connected to the bearing portion 111 of the base layer 100, and the other side of each of the multiple first thermal conductive elements 200 is connected to the thermal buffer 500. The heat generated by the chip 800 can be conducted to the multiple first thermal conductive elements 200, allowing the heat generated by the chip 800 to be efficiently conducted through the multiple first thermal conductive elements 200. The heat can also be efficiently conducted through the multiple first thermal conductive elements 200 to the thermal buffer 500, and then to the multiple second thermal conductive elements 300.

[0075] The total number of multiple first heat-conducting elements 200 is less than the total number of multiple second heat-conducting elements 300, so that the heat generated by the chip 800 can be diffused from the multiple first heat-conducting elements 200 to the multiple second heat-conducting elements 300, thereby making the heat generated by the chip 800 more evenly distributed.

[0076] In some implementations, reference Figure 2 As shown, the plurality of first heat-conducting elements 200 of this application can be spaced apart along a first direction, wherein the first direction is perpendicular to the thickness direction of the base layer 100. Figure 2 In the Y direction. In this way, multiple first heat-conducting elements 200 can be distributed in an orderly manner within the base layer 100, and a certain distance can be maintained between the multiple first heat-conducting elements 200.

[0077] refer to Figure 3 As shown, the plurality of second heat-conducting elements 300 of this application can be arranged at intervals along the first direction. In this way, the plurality of second heat-conducting elements 300 can be distributed in an orderly manner within the base layer 100, and a certain distance can be maintained between the plurality of second heat-conducting elements 300.

[0078] In some implementations, reference Figure 2 As shown, the plurality of first heat-conducting elements 200 of this application may also be spaced apart along a second direction, wherein the first direction and the second direction are perpendicular to each other with respect to the thickness direction of the base layer 100, and the second direction is... Figure 2In the Z direction. In this way, multiple first heat-conducting elements 200 can be distributed in an orderly manner within the base layer 100, and a certain distance can be maintained between the multiple first heat-conducting elements 200.

[0079] The multiple second heat-conducting elements 300 of this application can also be arranged at intervals along the second direction. In this way, the multiple second heat-conducting elements 300 can be distributed in an orderly manner within the base layer 100, and a certain distance can be maintained between the multiple second heat-conducting elements 300.

[0080] In some implementations, reference Figure 4 As shown, the spacing between the plurality of first heat-conducting elements 200 in this application can be set differently along the first or second direction, thus allowing for a wider distribution range of the plurality of first heat-conducting elements. Specifically, among the plurality of first heat-conducting elements 200, those corresponding to areas of the chip 800 with high heat generation can be arranged relatively centrally, and the spacing between these first heat-conducting elements 200 can be set relatively small, thereby allowing areas of the chip 800 with high heat generation to be connected to a larger number of first heat-conducting elements 200. In this way, the heat from areas of the chip 800 with high heat generation can be conducted to the first heat-conducting elements 200 more efficiently.

[0081] Correspondingly, among the multiple first heat-conducting elements 200, the multiple first heat-conducting elements 200 corresponding to the area of ​​low heat generation of chip 800 can be relatively dispersed. The spacing between these first heat-conducting elements 200 can be set relatively large, thereby reducing the number of first heat-conducting elements 200 and reducing the cost of the packaging components of this application.

[0082] refer to Figure 5 As shown, the spacing between the plurality of second heat-conducting elements 300 in this application can be set differently along the first or second direction, thus allowing for a wider distribution range of the plurality of second heat-conducting elements. Specifically, among the plurality of second heat-conducting elements 300, those corresponding to areas of the chip 800 with high heat generation can be arranged relatively centrally, and the spacing between these second heat-conducting elements 300 can be set relatively small, allowing areas of the chip 800 with high heat generation to be closer to a greater number of second heat-conducting elements 300. In this way, the heat from areas of the chip 800 with high heat generation can be conducted to the second heat-conducting elements 300 more efficiently.

[0083] Correspondingly, among the multiple second heat-conducting elements 300, the multiple second heat-conducting elements 300 corresponding to the areas of the chip 800 with low heat generation can be relatively dispersed. The spacing between these second heat-conducting elements 300 can be set to be relatively large, thereby reducing the number of second heat-conducting elements 300 and reducing the cost of the packaging components of this application.

[0084] In some implementations, reference Figure 2As shown, the spacing between the multiple first heat-conducting elements 200 can also be set to be consistent along the first direction and the second direction, so that the multiple first heat-conducting elements 200 can be evenly distributed in the base layer 100, so that the heat generated in each area of ​​the chip 800 can be efficiently conducted through the first heat-conducting elements 200.

[0085] Along the first and second directions, refer to Figure 3 As shown, the spacing between the multiple second heat-conducting elements 300 can also be set to be consistent, so that the multiple second heat-conducting elements 300 can be evenly distributed in the base layer 100, so that the heat generated in each area of ​​the chip 800 can be efficiently conducted through the second heat-conducting elements 300.

[0086] In some implementations, reference Figure 1 As shown, along the first direction, the distance between the two outermost first heat-conducting elements 200 is the first distance, and the distance between the two outermost second heat-conducting elements 300 is the second distance, with the first distance being smaller than the second distance. Thus, along the first direction, the distribution range of the multiple second heat-conducting elements 300 is wider than the distribution range of the multiple first heat-conducting elements 200, allowing the multiple second heat-conducting elements 300 to effectively disperse the heat generated by the chip 800, further preventing the heat generated by the chip 800 from concentrating in a portion of the base layer 100.

[0087] Along the second direction, refer to Figure 1 As shown, the distance between the two outermost first heat-conducting elements 200 in the second direction is the third distance, and the distance between the two outermost second heat-conducting elements 300 in the second direction is the fourth distance, with the third distance being smaller than the fourth distance. Thus, along the second direction, the distribution range of the multiple second heat-conducting elements 300 is wider than the distribution range of the multiple first heat-conducting elements 200, allowing the multiple second heat-conducting elements 300 to effectively disperse the heat generated by the chip 800, further preventing the heat generated by the chip 800 from concentrating in a portion of the base layer 100.

[0088] In some implementations, reference Figure 6 As shown, the plurality of first heat-conducting elements 200 of this application can also be arranged at intervals along a preset circumferential direction, so that the plurality of first heat-conducting elements 200 are distributed in various areas within the base layer 100. Specifically, the spacing between multiple groups of adjacent first heat-conducting elements 200 can be set to be the same, or the spacing between multiple groups of adjacent first heat-conducting elements 200 can be set to be different. In addition, it is also possible to set the spacing between some adjacent first heat-conducting elements 200 to be the same, and the spacing between some adjacent first heat-conducting elements 200 to be different.

[0089] refer to Figure 7As shown, the plurality of second heat-conducting elements 300 of this application can also be spaced apart along a preset circumferential direction, so that the plurality of second heat-conducting elements 300 are distributed in various areas within the base layer 100. Specifically, the spacing between multiple groups of adjacent second heat-conducting elements 300 can be set to be the same, or the spacing between multiple groups of adjacent second heat-conducting elements 300 can be set to be different. In addition, it is also possible to set some adjacent second heat-conducting elements 300 to have the same spacing, and some adjacent second heat-conducting elements 300 to have different spacing.

[0090] In some implementations, reference Figure 6 As shown, the plurality of first heat-conducting elements 200 can also be arranged radially at intervals along a preset circumference, so that the plurality of first heat-conducting elements 200 are further distributed in various areas within the base layer 100. Specifically, the spacing between multiple groups of adjacent first heat-conducting elements 200 along the preset circumference can be set to be the same, or the spacing between multiple groups of adjacent first heat-conducting elements 200 can be set to be different. In addition, it is also possible to set some adjacent first heat-conducting elements 200 to have the same spacing, and some adjacent first heat-conducting elements 200 to have different spacing.

[0091] refer to Figure 7 As shown, the multiple second heat-conducting elements 300 can also be arranged radially at intervals along a preset circumference, so that the multiple second heat-conducting elements 300 are further distributed in various areas within the base layer 100. Specifically, the spacing between multiple groups of adjacent second heat-conducting elements 300 along the preset circumference can be set to be the same, or the spacing between multiple groups of adjacent second heat-conducting elements 300 can be set to be different. In addition, it is also possible to set some adjacent second heat-conducting elements 300 to have the same spacing, and some adjacent second heat-conducting elements 300 to have different spacing.

[0092] In some implementations, reference Figure 1 As shown, to better fix the chip 800 to the support portion 111 of the base layer 100, the packaging assembly of this application may further include a solder layer 600. The solder layer 600 is disposed on the support portion 111, and the chip 800 can be soldered to the solder layer 600, thereby allowing the chip 800 to be positioned opposite the support portion 111 of the base layer 100. The soldering of the chip 800 to the solder layer 600 ensures a stable and reliable connection between the chip 800 and the solder layer 600, thus making the chip 800 relatively stable with respect to the base layer 100.

[0093] Specifically, the side of the first heat-conducting component 200 away from the heat buffer component 500 can be connected to the solder layer 600. The solder layer 600 can completely cover the surface of the chip 800 facing the base layer 100, or the solder layer 600 can cover the main heat-generating parts of the chip 800 facing the base layer 100. The heat generated by the chip 800 can be conducted to the solder layer 600 first and then to the first heat-conducting component 200.

[0094] In some implementations, reference Figure 1 As shown, the packaging assembly of this application may further include a wiring layer 700, which extends through the base layer 100 along its thickness direction and is used for electrical connection with the chip 800. Specifically, one end of the wiring layer 700 may extend through the base layer 100 toward the support portion 111, so that one end of the wiring layer 700 can be electrically connected to the chip 800 disposed on the support portion 111, and the other end of the wiring layer 700 may extend through the other side of the base layer 100 in the thickness direction to be electrically connected to other components, so that the chip 800 can be powered and transmit electrical signals.

[0095] In some implementations, reference Figure 1 As shown, the surface of the wiring layer 700 facing away from the substrate 100 and the surface of the solder layer 600 facing away from the substrate 100 are on the same plane. Specifically, on the top side of the substrate 100, the wiring layer 700 and the solder layer 600 are at the same height, so that the wiring layer 700 and the solder layer 600 can be flush. The chip 800 can be disposed on top of the solder layer 600 and the wiring layer 700. The portion of the surface of the chip 800 facing the substrate 100 is opposite to the solder layer 600, and the portion of the surface of the chip 800 facing the substrate 100 can also be opposite to the wiring layer 700, thereby allowing the chip 800 to be easily connected to both the solder layer 600 and the wiring layer 700.

[0096] In addition, in other embodiments, the height of the solder layer 600 may be higher than that of the wiring layer 700, or the height of the wiring layer 700 may be higher than that of the solder layer 600, which can be determined according to the packaging process of the packaging component of this application.

[0097] In some embodiments, the solder layer 600 and the wiring layer 700 of this application can be configured as an integral structure to reduce the difficulty of the fabrication process of the solder layer 600 and the wiring layer 700, thereby reducing the fabrication cost of the packaging component of this application.

[0098] Both the solder layer 600 and the wiring layer 700 can be fabricated using standard wiring processes, and both can be made of copper. Specifically, the mounting areas for the solder layer 600 and the wiring layer 700 can be formed on the surface of the substrate 100 through an etching process, and then the solder layer 600 and the wiring layer 700 are formed by electroplating copper. This allows the solder layer 600 and the wiring layer 700 to be formed in a single process flow, reducing the number of fabrication steps in the packaging component of this application and lowering the manufacturing cost.

[0099] In some implementations, reference Figure 8As shown, the soldering groove of this application may include multiple soldering sub-layers 610, which are spaced apart along a first direction and a second direction. Specifically, the position and number of the multiple soldering sub-layers 610 can be determined according to the number and position of the heat-generating parts of the chip 800, so that the multiple soldering sub-layers 610 can be respectively opposite to the multiple heat-generating parts of the chip 800. In this way, the heat generated by the multiple heat-generating parts of the chip 800 can be conducted to the multiple soldering sub-layers 610 respectively, so that the heat generated by the multiple heat-generating parts of the chip 800 can be efficiently conducted to the first heat-conducting element 200.

[0100] Furthermore, multiple first heat-conducting elements 200 can be connected to multiple solder sublayers 610 respectively, so that the heat generated by the chip 800 can be conducted to the multiple first heat-conducting elements 200 through the multiple solder sublayers 610 respectively. Of course, some of the multiple first heat-conducting elements 200 can also be connected to multiple solder sublayers 610, or multiple first heat-conducting elements 200 can be connected to the same solder sublayer 610. In both cases, the heat generated by the chip 800 can be efficiently conducted to the first heat-conducting elements 200.

[0101] In some embodiments, the first heat-conducting element 200 and the second heat-conducting element 300 of this application may be made of copper. Specifically, a first opening 112 and a second opening 122 can be formed on the base layer 100 by an etching process. The number of first openings 112 corresponds to the number of first heat-conducting elements 200, and the number of second openings 122 corresponds to the number of second heat-conducting elements 300. Then, the first heat-conducting element 200 is formed in the first opening 112 by an electroplating copper process, and the second heat-conducting element 300 is formed in the second opening 122 by an electroplating copper process.

[0102] In some embodiments, the heat buffer 500 of this application can be made of graphite, aluminum nitride, or copper. This gives the heat buffer 500 strong heat resistance and thermal conductivity, making the structure of the heat buffer 500 stable and reliable.

[0103] In some implementations, reference Figure 10 and Figure 11 As shown, the base layer 100 of this application may include a first layer 110 and a second layer 120. A first heat-conducting element 200 passes through the first layer 110, and a second heat-conducting element 300 passes through the second layer 120. The second layer 120 has a mounting groove 121, and a heat buffer 500 is disposed within the mounting groove 121. The first layer 110 is stacked on top of the second layer 120, and the first layer 110 seals the opening of the mounting groove 121. In this way, the heat buffer 500 can be sandwiched between the first layer 110 and the second layer 120, so that the heat buffer 500 is enclosed within the base layer 100.

[0104] Specifically, the first layer 110 and the second layer 120 can be manufactured separately, with a first opening 112 formed in the first layer 110 and a second opening 122 formed in the second layer 120. The first opening 112 penetrates the first layer 110, and the second opening 122 penetrates the second layer 120. After the second layer 120 has a mounting groove 121, one end of the second opening 122 is located on the bottom wall of the mounting groove 121, so that the second opening 122 communicates with the mounting groove 121. The heat buffer 500 is fixed in the mounting groove 121, and then the first layer 110 is stacked on the second layer 120, so that the heat buffer 500 is sealed in the mounting groove 121. A first heat-conducting element 200 is formed in the first opening 112 and a second heat-conducting element 300 is formed in the second opening 122 by electroplating copper. Finally, the first layer 110 is stacked on the second layer 120, and the first layer 110 and the second layer 120 are bonded together to form the base layer 100.

[0105] In some implementations, reference Figure 9 As shown, the packaging component of this application may further include a dielectric layer 620, which is stacked on the side of the bonding layer 600 facing away from the base layer 100. Specifically, the dielectric layer 620 is located between the bonding layer 600 and the chip 800. When the heat-generating part of the chip 800 facing the base layer 100 is made of a semiconductor material, such as silicon dioxide, the dielectric layer 620 can also be made of silicon dioxide. The dielectric layer 620 is connected to the bottom side of the chip 800 facing the base layer 100, so that the dielectric layer 620 and the chip 800 can be stably and reliably bonded, thereby allowing the chip 800 to maintain structural stability.

[0106] When the heat-generating part of the chip 800 facing the bottom of the substrate 100 is made of metal, such as copper, the dielectric layer 620 is not required, allowing the chip 800 to be directly connected to the solder layer 600. This allows the heat generated by the chip 800 to be conducted to the solder layer 600 more efficiently.

[0107] In preparing the packaging structure of this application, a blank structure of the first layer 110 is selected, and a first opening 112 is formed in the blank structure of the first layer 110 by laser-induced modification combined with wet etching, thereby forming the first layer 110. Subsequently, a first heat-conducting element 200 is formed in the first opening 112 by electroplating copper, and the first heat-conducting element 200 is CMP polished to make the two ends of the first heat-conducting element 200 flat with the two side surfaces of the first layer 110 in the thickness direction.

[0108] A blank structure for the second layer 120 is selected. An etching process is used to form a mounting groove 121 on the blank structure of the second layer 120, and a second opening 122 communicating with the mounting groove 121 is formed, thus forming the second layer 120. Subsequently, a second heat-conducting element 300 is formed within the second opening 122 using an electroplating copper process, and the second heat-conducting element 300 is then CMP-polished to make its two ends flush with the surface structures of the two sides of the second layer 120 in the thickness direction. A heat buffer 500 is deposited and formed within the mounting groove 121 of the second layer 120.

[0109] Based on the packaging components described above, this application also proposes an electronic device that includes the packaging components described above.

[0110] It should be noted that the terms "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," etc., mentioned in the specification indicate that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.

[0111] Generally speaking, terms should be understood at least in part by their use in context. For example, at least in part by context, the term "one or more" as used in the text can be used to describe any feature, structure, or characteristic of the singular meaning, or a combination of features, structures, or characteristics of the plural meaning. Similarly, at least in part by context, terms such as "a" or "the" can also be understood to convey either singular or plural usage.

[0112] Furthermore, for ease of explanation, spatially relative terms such as "below," "below," "under," "above," and "above" may be used to describe the relationship of one element or feature relative to other elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation other than those shown in the figures. The device may have other orientations (rotated 90° or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0113] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A packaging component, characterized in that, include: The base layer (100) has a support portion (111) on one side surface in the thickness direction for supporting the chip (800). A first heat-conducting element (200) is inserted through the base layer (100) along the thickness direction of the base layer (100), and one end of the first heat-conducting element (200) is connected to the bearing part (111); A heat sink (400) is stacked on the side of the base layer (100) facing away from the bearing portion (111); Multiple second heat-conducting elements (300) are provided, each of which is inserted through the base layer (100) along the thickness direction of the base layer (100). One end of each second heat-conducting element (300) is connected to the heat dissipation element (400). The multiple second heat-conducting elements (300) are spaced apart. A thermal buffer (500) is disposed within the base layer (100). The thermal buffer (500) has a first side (510) and a second side (520) opposite to each other in the thickness direction. The end of the first thermal conductive member (200) away from the bearing portion (111) is connected to the first side (510), and the end of the second thermal conductive member (300) away from the heat dissipation member (400) is connected to the second side (520).

2. The packaging component according to claim 1, characterized in that, The number of the first heat-conducting element (200) is also multiple, and the number of the first heat-conducting element (200) is less than the number of the second heat-conducting element (300); A plurality of the first heat-conducting elements (200) are spaced apart along a first direction and a second direction; and / or, A plurality of the second heat-conducting elements (300) are spaced apart along the first direction and the second direction; The first direction, the second direction, and the thickness direction of the base layer (100) are perpendicular to each other.

3. The packaging component according to claim 2, characterized in that, Along the first direction and the second direction, the spacing between at least some adjacent first heat-conducting elements (200) is different; and / or, Along the first direction and the second direction, the spacing between at least some of the adjacent second heat-conducting elements (300) is different.

4. The packaging component according to claim 3, characterized in that, Along the first direction, the distance between the two outermost first heat-conducting elements (200) is the first distance, and the distance between the two outermost second heat-conducting elements (300) is the second distance, and the first distance is smaller than the second distance; And / or, Along the second direction, the distance between the two outermost first heat-conducting elements (200) is the third distance, and the distance between the two outermost second heat-conducting elements (300) is the fourth distance, wherein the third distance is smaller than the fourth distance.

5. The packaging component according to claim 2, characterized in that, A plurality of the first heat-conducting elements (200) are arranged at circumferential and radial intervals along a predetermined circumference; and / or, Multiple second heat-conducting elements (300) are arranged at circumferential and radial intervals along the preset circumference.

6. The packaging component according to any one of claims 1-5, characterized in that, The packaging assembly further includes a solder layer (600) disposed on the support portion (111), and the side of the solder layer (600) facing away from the support portion (111) is used to connect with the chip (800).

7. The packaging component according to claim 6, characterized in that, The packaging assembly further includes a wiring layer (700) that extends through the base layer (100) along its thickness direction and is used for electrical connection with the chip (800). The surface of the wiring layer (700) facing away from the base layer (100) and the surface of the solder layer (600) facing away from the base layer (100) are on the same plane, and the wiring layer (700) and the solder layer (600) are an integral structure.

8. The packaging component according to any one of claims 1-5, characterized in that, The material of the heat buffer (500) is graphite, aluminum nitride or copper.

9. The packaging component according to any one of claims 1-5, characterized in that, The base layer (100) includes a first layer (110) and a second layer (120). The first heat-conducting element (200) passes through the first layer (110), and the second heat-conducting element (300) passes through the second layer (120). The second layer (120) has a mounting groove (121). The heat buffer (500) is disposed in the mounting groove (121). The first layer (110) is stacked on the second layer (120), and the first layer (110) seals the opening of the mounting groove (121).

10. An electronic device, characterized in that, It includes a chip (800) and a packaging assembly as described in any one of claims 1-9, wherein the chip (800) is disposed on the carrier portion (111).

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