Semiconductor module and packaging structure

Abstract

A semiconductor module includes an interposer, a plurality of semiconductor dies, and a backside capacitor. The plurality of semiconductor dies are located on the interposer, with each of the semiconductor dies having a front side surface facing the interposer and a backside surface opposite the interposer. The backside capacitor is located on the backside surface of at least one of the semiconductor dies and electrically coupled to the interposer. Related packaging structures are also provided.

Description

Technical Field

[0001] This utility model relates to a semiconductor module and packaging structure, and more particularly to a semiconductor module and packaging structure having a back-side capacitor electrically coupled to an interposer layer. Background Technology

[0002] The semiconductor industry continues to develop due to the increasing integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). These various electronic components can include integrated passive devices (IPDs), such as capacitors.

[0003] In addition to smaller electronic components, improvements have been made to component packaging to provide smaller packages that occupy less area than previous packages. Exemplary approaches include quad flat packs (QFP), pin grid arrays (PGA), ball grid arrays (BGA), flip chips (FC), three-dimensional integrated circuits (3DIC), wafer-level packages (WLP), packages on packages (PoP), systems on chips (SoC), or systems on integrated circuits (SoIC) devices. Some of these 3D devices are fabricated by placing chips on top of each other. These 3D devices offer higher integration density and other advantages due to the reduced interconnect length between stacked chips. However, many challenges remain associated with 3D devices. Utility Model Content

[0004] This invention provides a semiconductor module including an interposer, a plurality of semiconductor dies, and a back-side capacitor. The plurality of semiconductor dies are located on the interposer, wherein each semiconductor die has a front surface facing the interposer and a back surface relative to the interposer. The back-side capacitor is located on the back surface of at least one of the semiconductor dies and is electrically coupled to the interposer.

[0005] In some embodiments, the semiconductor module further includes an upper molding layer surrounding the plurality of semiconductor grains, wherein the back-side capacitor is located on the upper molding layer.

[0006] In some embodiments, the back-side capacitor includes: a passivation film located on an upper surface of the upper molded layer; and a pair of parallel metal films located within the passivation film and separated by the passivation film.

[0007] In some embodiments, the passivation film includes a plurality of passivation layers, the plurality of passivation layers including: a first passivation layer located on the upper surface of the upper forming layer, wherein a first metal film of the pair of parallel metal films is located on the first passivation layer; a second passivation layer located on the first passivation layer, wherein a second metal film of the pair of parallel metal films is located on the second passivation layer; and a third passivation layer located on the second passivation layer and the second metal film.

[0008] In some embodiments, the second passivation layer separates the first metal film from the second metal film and includes a charge separation layer containing an electric field in the back-side capacitor.

[0009] In some embodiments, the semiconductor module further includes: a connection structure configured to electrically couple the pair of parallel metal films to an interposer, wherein the interposer includes a distribution structure including a plurality of distribution lines, and the connection structure is configured to electrically couple the pair of parallel metal films to the plurality of distribution lines.

[0010] In some embodiments, the connection structure includes: a pair of lower connecting portions located within the intermediary layer and connected to the plurality of distribution lines of the distribution structure; a pair of shaped through holes located in the upper shaped layer and connected to the pair of lower connecting portions; and a pair of upper through holes located in the passivation film and connected to the pair of shaped through holes and the pair of parallel metal films.

[0011] In some embodiments, the pair of shaped vias are located in the upper shaped layer outside the plurality of semiconductor grains, the pair of parallel metal films are located above one of the plurality of semiconductor grains, each of the pair of parallel metal films includes a hanging portion extending beyond one side of the semiconductor grain, and one of the pair of upper vias is connected to the hanging portion.

[0012] In some embodiments, the area of ​​the back-side capacitor is 10% to 100% of the area of ​​the semiconductor module.

[0013] This utility model provides a method for manufacturing a semiconductor module, including forming an interposer layer; connecting a plurality of semiconductor dies to the interposer layer, wherein each semiconductor die has a front surface facing the interposer layer and a back surface relative to the interposer layer; forming an upper molding layer around the semiconductor dies; and forming a back capacitor on the back surface of at least one of the semiconductor dies and on the upper molding layer, such that the back capacitor is electrically coupled to the interposer layer through the upper molding layer.

[0014] This utility model provides a packaging structure including a packaging substrate and a semiconductor module located on the packaging substrate. The semiconductor module includes: an interposer, a plurality of semiconductor dies located on the interposer, and a back-side capacitor located on the semiconductor dies and electrically coupled to the interposer, wherein the back-side capacitor includes a passivation film and a pair of parallel metal films located within the passivation film. The packaging structure includes a thermal interface material located on the back-side capacitor and in contact with the passivation film, wherein the pair of parallel metal films are located between the semiconductor dies and the thermal interface material. The packaging structure includes a package cap located on the thermal interface material and connected to the packaging substrate. Attached Figure Description

[0015] The concept of the embodiments of this utility model will be better understood by referring to the following detailed description and accompanying drawings. It should be noted that, according to standard industry practice, the various features in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity. Similar features are designated with similar reference numerals throughout the specification and drawings.

[0016] Figure 1A It is a vertical sectional view (front view) of a semiconductor module according to one or more embodiments.

[0017] Figure 1B It is a detailed vertical sectional view (front view) of a semiconductor module according to one or more embodiments.

[0018] Figure 1C This is a detailed vertical sectional view (front view) of the back-side capacitor in a semiconductor module according to one or more embodiments.

[0019] Figure 1D It is a vertical sectional view (side view) of a semiconductor module according to one or more embodiments.

[0020] Figure 1E It is a plan view (e.g., top view) of a package structure (with the back capacitor omitted) according to one or more embodiments.

[0021] Figure 1F It is a plan view (e.g., a top view) of a package structure (including the position of the parallel metal film in the back capacitor) according to one or more embodiments.

[0022] Figure 2A This is a vertical cross-sectional view of an intermediate structure including an intermediary layer (e.g., an organic intermediary layer) formed on a carrier substrate (e.g., a carrier wafer) according to an embodiment of the present invention.

[0023] Figure 2B It is a vertical cross-sectional view of an intermediate structure including a first semiconductor die and a second semiconductor die according to one or more embodiments.

[0024] Figure 2C It is a vertical cross-sectional view of an intermediate structure including a bottom filling layer of a semiconductor module according to one or more embodiments.

[0025] Figure 2D A vertical cross-sectional view of an intermediate structure including an upper molding layer is shown according to one or more embodiments.

[0026] Figure 2E A vertical cross-sectional view is shown of an intermediate structure including a first through molding via (TMV) and a second TMV, according to one or more embodiments.

[0027] Figure 2F A vertical cross-sectional view of an intermediate structure following a planarization process according to one or more embodiments is shown.

[0028] Figure 2G A vertical cross-sectional view of an intermediate structure including a back-side capacitor is shown according to one or more embodiments.

[0029] Figure 2H A vertical cross-sectional view is shown of an intermediate structure including a plurality of controlled collapse chip connection (C4) bumps according to one or more embodiments.

[0030] Figure 3 A flowchart illustrating a method for manufacturing a semiconductor module according to one or more embodiments is shown.

[0031] Figure 4A It is a vertical sectional view (front view) of the package structure according to one or more embodiments.

[0032] Figure 4B It is a vertical sectional view (side view) of the packaging structure according to one or more embodiments.

[0033] Figure 5A It is a vertical cross-sectional view of an intermediate structure of a package substrate including an upper bonding pad and a lower bonding pad according to one or more embodiments.

[0034] Figure 5B A vertical cross-sectional view of the intermediate structure of a semiconductor module that can be mounted on a package substrate according to one or more embodiments is illustrated.

[0035] Figure 5C A vertical cross-sectional view is shown of an intermediate structure in which an underfill layer for a package can be formed on a package substrate according to one or more embodiments.

[0036] Figure 5DA vertical cross-sectional view is shown of an intermediate structure of a thermal interface material (TIM) layer that can be attached to (e.g., formed on) a back-side capacitor according to one or more embodiments.

[0037] Figure 5E A vertical cross-sectional view of an intermediate structure of an adhesive layer that can be applied to a packaging substrate according to one or more embodiments is illustrated.

[0038] Figure 5F A vertical cross-sectional view is shown of an intermediate structure of a package cover that can be attached (e.g., mounted) to a package substrate according to one or more embodiments.

[0039] Figure 5G A vertical cross-sectional view is shown of an intermediate structure of a ball grid array (BGA) comprising a plurality of solder balls that can be formed on a package substrate according to one or more embodiments.

[0040] Figure 6 A flowchart illustrating a method for manufacturing a package structure according to one or more embodiments is provided.

[0041] Figure 7A It is a vertical cross-sectional view of a semiconductor module having a first alternative configuration according to one or more embodiments.

[0042] Figure 7B It is a top view of a semiconductor module having a first alternative configuration according to one or more embodiments.

[0043] Figure 8A It is a vertical cross-sectional view of a semiconductor module having a second alternative configuration according to one or more embodiments.

[0044] Figure 8B It is a top view of a semiconductor module having a second alternative configuration according to one or more embodiments.

[0045] List of reference numerals

[0046] 1: Carrier substrate

[0047] 10: Intermediary layer

[0048] 12: Polymer layer

[0049] 12a: Redistribution layer

[0050] 13: Upper passivation layer

[0051] 13a: Upper joint pad

[0052] 13a1: First upper mating pad

[0053] 13a2: Second upper bonding pad

[0054] 14: Lower passivation layer

[0055] 14a: Lower joint pad

[0056] 100: Package structure

[0057] 110: Packaging substrate

[0058] 110a: Passivation layer (top solder mask) on the package substrate

[0059] 110b: Under-package passivation layer (under solder mask)

[0060] 112: Core

[0061] 112a: Through hole

[0062] 114: Dielectric layer on the packaging substrate

[0063] 114a: Bonding pad on the package substrate

[0064] 114b: Metal interconnect structure

[0065] 116: Under-package dielectric layer

[0066] 116a: Under-substrate bonding pad

[0067] 116b: Metal interconnect structure

[0068] 119: Encapsulation bottom filler layer

[0069] 120: Semiconductor Module

[0070] 121: Controlled Collapse Chip Connector Bump (C4 Bump)

[0071] 127: Upper molding layer

[0072] 127a: First side

[0073] 127b: Second side

[0074] 127c: Third side

[0075] 127d: Fourth side

[0076] 128: Microbumps

[0077] 129: Bottom filler layer of semiconductor module

[0078] 130: Encapsulation cap

[0079] 130a: Package cover pin portion

[0080] 130p: Package cover portion

[0081] 140: Semiconductor die

[0082] 140a: Top surface of semiconductor die (top surface)

[0083] 141: First semiconductor die

[0084] 142: Second semiconductor die

[0085] 145: Active Zone

[0086] 160: Adhesive layer

[0087] 170: Thermal interface materials

[0088] 180: Ball Grid Array (BGA)

[0089] 181: Welding ball

[0090] 200: Charge storage structure

[0091] 201: Passivation film

[0092] 201L1: First passivation layer

[0093] 201L2: Second passivation layer

[0094] 201L3: Third passivation layer

[0095] 210: Backside capacitor

[0096] 210A: First capacitor

[0097] 210B: Second capacitor

[0098] 211: First Metallic Film

[0099] 211o: Overhanging part

[0100] 211V: First top through hole

[0101] 212: Second metal film

[0102] 212o: Overhanging part

[0103] 212V: Second upper through hole

[0104] 215: First Metallic Film

[0105] 215°: Overhanging section

[0106] 215V: First top through hole

[0107] 216: Second metal film

[0108] 216o: Overhanging section

[0109] 216V: Second upper through hole

[0110] 220: Distribution Structure

[0111] 221: First distribution line

[0112] 221V: First bottom through hole

[0113] 222: Second distribution line

[0114] 222V: Second lower through hole

[0115] 230: Connection Structure

[0116] 231: First formed through hole

[0117] 232: Second forming through hole

[0118] 310, 320, 330, 340: Steps

[0119] 610, 620, 630, 640: Steps

[0120] A-A', B-B', C-C': Lines

[0121] D1, D2, D3, D4: Distance

[0122] Dt: Diameter

[0123] OD1, OD2, OD5, OD6: Overhang distance

[0124] O110a, O110b: Opening

[0125] Tc, Td: Thickness

[0126] Tp1: First thickness

[0127] Tp2: Second thickness

[0128] Tp3: Third thickness Detailed Implementation

[0129] The following disclosure provides numerous different embodiments or examples to implement various features of the present invention. Reference numerals and / or letters may be repeated in the various examples described herein. These repetitions are for brevity and clarity and do not in themselves imply any relationship between the various disclosed embodiments and / or configurations. Furthermore, specific examples of components and configurations are described below to simplify the description of the embodiments of the present invention. Of course, these specific examples are merely illustrative and not intended to limit the embodiments of the present invention. For example, in the following description, reference to a first feature being formed on or above a second feature indicates that it may include embodiments where the first and second features are in direct contact, or embodiments where additional features are formed between the first and second features, so that the first and second features may not be in direct contact.

[0130] In addition, spatially related terms may be used herein. For example, terms such as “below,” “under,” “lower,” “above,” “higher,” and similar terms are used to describe the relationship between one element or feature shown in the diagram and another element(s). These spatially related terms are intended to include different orientations of the device in use or operation, in addition to the orientation shown in the diagram. The device may be rotated to different orientations (90 degrees or other orientations), and the spatially related terms used herein may be interpreted accordingly. Unless otherwise expressly stated, it is presumed that each element with the same designation has the same material composition and a thickness within the same thickness range.

[0131] Capacitors can be included in semiconductor modules (e.g., chip-on-wafer (CoW) structures). Semiconductor modules can be used in applications such as high-performance computing (HPC), radio frequency (RF) and microwave circuits, automotive electronics, and mobile devices. Capacitors can be included within integrated passive devices (IPDs) attached to the semiconductor module. IPDs can be located beneath the semiconductor module, for example, beneath an interposer layer within the semiconductor module. Capacitors can also be included within embedded deep trench capacitors (eDTCs). Integrating capacitors into semiconductor modules can improve performance, size, and / or efficiency.

[0132] Capacitors can be used, for example, as decoupling capacitors to filter noise and stabilize the power supply voltage of semiconductor modules. Decoupling capacitors provide local charge storage, which helps eliminate voltage fluctuations, thereby ensuring a stable power supply to circuits (such as integrated circuits) within the semiconductor module. Capacitors can also be used to reduce noise. By being physically located near the active circuitry within the semiconductor module, these capacitors can reduce the effects of electromagnetic interference (EMI) and crosstalk, thereby improving signal integrity and overall device performance.

[0133] Capacitors can also be used to maintain power integrity in semiconductor modules. Specifically, capacitors help ensure that voltage levels within a semiconductor module remain stable, especially during periods of rapid power consumption changes in different parts of the circuitry. Capacitors also help eliminate rapid current changes, thereby preventing voltage drops (known as droop) that could lead to circuit failure or performance degradation.

[0134] Capacitors can also be used to maintain signal integrity in semiconductor modules. Specifically, semiconductor modules can be used to filter out high-frequency noise from signals, thereby ensuring that only the desired signal frequency passes through. Furthermore, in radio frequency (RF) and high-speed digital circuits, capacitors can be used to match impedance, minimize signal reflections and losses, and thus improve signal transmission quality.

[0135] Furthermore, by including capacitors within the semiconductor module, the need for discrete components (such as those on a printed circuit board (PCB)) can be eliminated, thereby reducing the overall device footprint. Positioning capacitors closer to the active circuitry further minimizes parasitic inductance and resistance, resulting in better performance (especially in high-frequency applications). Capacitors also help dissipate heat from critical areas, aiding in heat management within the semiconductor module and improving its reliability and lifespan.

[0136] At least one embodiment of this invention may include a CoW (or wafer-on-a-substrate) back-side capacitor (e.g., a back-side film structure). At least one embodiment may implement a back-side capacitor having a backside metal (BSM) and a passivation film on the back side of the CoW. Advantages of at least one embodiment may include bringing more capacitors (e.g., with larger capacitance values) closer to the wafer. Specifically, at least one or more embodiments may enable film capacitors on the back side of the CoW while simultaneously providing low CoW warpage (e.g., a warpage adjustment film) and low thermal resistance.

[0137] At least one embodiment may include a silicon-based wafer (System-on-a-Chip (SoC), High-bandwidth Memory (HBM), etc.), an interposer, an encapsulating material layer (upper molding layer), one or more interconnects (e.g., C4 bumps), a package substrate, a back-side thin-film capacitor, and one or more molded vias (TMVs).

[0138] A TMV can connect a back-side capacitor (back-side film capacitor) to one or more metal layers (e.g., a redistribution layer (RDL) structure) in a semiconductor module (e.g., in the interposer of the semiconductor module). The TMV can be formed of metal or other suitable conductive materials. The back-side capacitor can be formed on the back side of the semiconductor module and can be formed of multiple metal films and one or more passivation films.

[0139] In at least one embodiment, the area of ​​the back-side capacitor can range from 10% to 100% of the back-side area of ​​the semiconductor module. The thickness of the back-side capacitor can range from 0.1 μm to 10000 μm.

[0140] Figure 1A It is a vertical sectional view (front view) of a semiconductor module 120 according to one or more embodiments. Figure 1B It is a detailed vertical sectional view (front view) of a semiconductor module 120 according to one or more embodiments. Figure 1C This is a detailed vertical sectional view (front view) of the back-side capacitor 210 in a semiconductor module 120 according to one or more embodiments. Figure 1D It is a vertical cross-sectional view (side view) of a semiconductor module 120 according to one or more embodiments. Figure 1E It is a plan view (e.g., top-down view) of a package structure 100 (back-side capacitor 210 omitted) according to one or more embodiments. Figure 1F It is a plan view (e.g., top view) of a package structure 100 (including the position of the parallel metal film in the back capacitor 210) according to one or more embodiments. Figure 1A The vertical section view (front view) along Figure 1E and Figure 1F Line A-A' in the middle. Figure 1D The vertical sectional view (side view) along Figure 1E and Figure 1F Line B-B' in the middle.

[0141] like Figure 1AAs shown, semiconductor module 120 may include an interposer 10, one or more semiconductor dies 140 located on the interposer 10, and a back-side capacitor 210 located above and adjacent to the one or more semiconductor dies 140. The back-side capacitor 210 may be electrically coupled to the interposer 10. Semiconductor module 120 is not limited to any particular configuration. Semiconductor module 120 may include, for example, a wafer-on-wafer (CoW) design, an integrated fan-out design, etc. In at least one embodiment, the interposer 10 may be replaced by one or more substrates in semiconductor module 120.

[0142] Interposer 10 is not necessarily limited to any particular material or configuration. Interposer 10 may include, for example, organic materials (e.g., dielectric polymers), inorganic materials (e.g., silicon), glass substrates, etc. In at least one embodiment, interposer 10 may include a plurality of alternately stacked polymer layers 12 (i.e., dielectric layers) and a plurality of redistribution layers 12a. The number of polymer layers 12 and / or the number of redistribution layers 12a in interposer 10 are not limited by the scope of this invention.

[0143] In at least one embodiment, the polymer layer 12 may include, for example, polyimide (PI), epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer-based dielectric material. In some embodiments, the redistribution layer 12a may include a conductive material. The conductive material may include a metal, such as copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals.

[0144] The redistribution layer 12a may include a metallic interconnect structure, i.e., a metallic structure providing electrical connections between nodes in the structure. The redistribution layer 12a may include a metal seed layer (not shown) and a metallic filler material (not shown) situated on the metal seed layer. The metal seed layer may include, for example, a stack of titanium barrier layers and copper seed layers. The thickness of the titanium barrier layer may range from 50 nm to 500 nm, while the thickness of the copper seed layer may range from 50 nm to 500 nm. The metallic filler material of the redistribution layer 12a may include copper, nickel, or both copper and nickel. Other suitable metallic filler materials are also within the scope of this invention. The thickness of the metallic filler material deposited on each redistribution layer 12a may range from 2 micrometers to 40 micrometers, for example, from 4 micrometers to 10 micrometers, but smaller or larger thicknesses may also be used.

[0145] In at least one embodiment, the redistribution layer 12a may include a plurality of metal traces (lines) and a plurality of metal vias connecting the plurality of metal traces to each other. The metal traces may be located on the polymer layer 12 respectively and may extend along the x-direction (first horizontal direction) and the y-direction (second horizontal direction) on the upper surface of the polymer layer 12. The metal vias may extend along the z-direction between the polymer layers 12.

[0146] An upper passivation layer 13 may be formed on the wafer-side surface of the interposer 10. The upper passivation layer 13 may include silicon oxide, silicon nitride, a low-k dielectric material (e.g., a carbon-doped oxide), an extremely low-k dielectric material (e.g., silicon dioxide doped with porous carbon), a combination thereof, or other suitable materials.

[0147] One or more upper bonding pads 13a may be formed in the upper passivation layer 13 on the wafer-side surface of the interposer 10. The upper passivation layer 13 may at least partially cover the upper bonding pads 13a. That is, the upper bonding pads 13a may at least partially expose the wafer-side surface of the interposer 10. The upper bonding pads 13a may be electrically coupled to the redistribution layer 12a. The upper bonding pads 13a may include, for example, one or more layers, and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metallic materials are also within the scope of this invention.

[0148] A lower passivation layer 14 may be formed on the side surface of the interposer layer 10. The lower passivation layer 14 may also include silicon oxide, silicon nitride, a low dielectric constant dielectric material (e.g., carbon-doped oxide), an extremely low dielectric constant dielectric material (e.g., porous carbon-doped silicon dioxide), a combination of the foregoing, or other suitable materials. A lower bonding pad 14a may be electrically coupled to the redistribution layer 12a. The lower bonding pad 14a may be located within the lower passivation layer 14. The lower passivation layer 14 may at least partially cover the lower bonding pad 14a. That is, the lower bonding pad 14a may at least partially expose the side surface of the interposer layer 10. The lower bonding pad 14a may also include, for example, one or more layers, and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metallic materials are also within the scope of this invention.

[0149] Semiconductor module 120 may further include controlled collapse chip connection (C4) bumps 121 (e.g., collapseable SnAg solder bumps) on the board-side surface of the interposer 10. Semiconductor module 120 can be bonded and electrically coupled to a package substrate (not shown) via the C4 bumps 121. The C4 bumps 121 may be formed on lower bonding pads 14a on the board-side surface of the interposer 10. The C4 bumps 121 can be bonded to the package substrate using solder reflow, compression bonding, thermoforming, or other methods. In at least one embodiment, the C4 bumps 121 may include an underbump metallurgy (UBM) layer (not shown) on the lower bonding pads 14a. In at least one embodiment, the C4 bumps 121 may include contact pads (e.g., copper / nickel contact pads) on the UBM layer and a SnAg solder layer on the contact pads.

[0150] Semiconductor dies (collectively referred to as semiconductor dies 140) may be attached to the upper surface of the interposer 10. A plurality of semiconductor dies 140 may include a first semiconductor die 141 and a second semiconductor die 142. Although the semiconductor module 120 is illustrated as including a specific number and a specific size of semiconductor dies 140 having a specific configuration, the number, size, and configuration of the semiconductor dies 140 are not limited to any specific number, size, and configuration. Specifically, the semiconductor module 120 may include any number, size, and configuration of semiconductor dies 140.

[0151] Semiconductor die 140 may include an active region 145, which includes an active device (e.g., a transistor). Semiconductor die 140 may also include a bulk silicon region located on the active region 145. Typically, each semiconductor die 140 may have a substantially uniform thickness in the z-direction. Therefore, the upper surfaces (e.g., back surfaces) of each of the first semiconductor die 141 and the second semiconductor die 142 may be substantially coplanar (e.g., formed in the same xy plane) and are collectively referred to as semiconductor die upper surface 140a. Each of the first semiconductor die 141 and the second semiconductor die 142 may include a lower surface (e.g., a front surface) opposite the upper surface and facing the interposer 10.

[0152] Semiconductor die 140 can be attached (e.g., bonded) to upper bonding pad 13a on the wafer side surface of interposer 10 via microbumps 128. Microbumps 128 can electrically couple active regions 145 of semiconductor die 140 to the upper bonding pad 13a of interposer. Each microbump 128 may include a copper pillar and solder bumps located on the copper pillar. Other suitable interconnect structures can be used instead of microbumps 128.

[0153] A bottom fill layer 129 of the semiconductor module may be formed (e.g., individually or collectively) below and around each semiconductor die 140. In at least one embodiment, the height of the upper surface of the bottom fill layer 129 of the semiconductor module may be substantially coplanar with the height of the upper surface 140a of the semiconductor die 140. In at least one embodiment, the height of the upper surface of the bottom fill layer 129 of the semiconductor module may be lower than the height of the upper surface 140a of the semiconductor die 140.

[0154] A semiconductor module underfill layer 129 may also be formed around the microbumps 128. The semiconductor module underfill layer 129 may be formed on and bonded to the upper surface of the interposer 10 (e.g., the upper surface of the upper passivation layer 13). In this way, the semiconductor module underfill layer 129 can secure each semiconductor die 140 to the interposer 10. The semiconductor module underfill layer 129 may be formed of an epoxy resin-based polymer material. Other suitable materials may be used for the semiconductor module underfill layer 129.

[0155] Each semiconductor die 140 may include, for example, a single semiconductor die structure, a system-on-a-chip (SoC) die, or an integrated system-on-a-chip (SoIC) die, and may be implemented using three-dimensional integrated packaging technology (e.g., fan-out technology).Specifically, each semiconductor die 140 may include, for example, semiconductor wafers or wafers, logic wafers (e.g., mobile application processors, microcontrollers, etc.) or memory wafers (e.g., high-bandwidth memory (HBM) wafers, hybrid memory cubes (HMC), dynamic random access memory (DRAM) wafers, wide input / output (I / O) wafers, magnetoresistive random access memory (M-RAM) wafers, resistive random-access memory (R-RAM) wafers, NAND flash memory (NAND) wafers, static random access memory (SRAM), etc.), central processing unit (CPU) wafers, graphics processing unit (GPU) wafers, field-programmable gate arrays (FPGAs), etc., for high-performance computing (HPC) applications, artificial intelligence (AI) applications, and 5G mobile network applications. Array (FPGA) chips, network chips, application-specific integrated circuit (ASIC) chips, artificial intelligence / deep neural network (AI / DNN) accelerator chips, auxiliary processors, accelerators, on-chip memory buffers, high data rate transceiver chips, I / O interface chips, IPD chips, power management chips (e.g., power management integrated circuit (PMIC) chips), radio frequency (RF) chips, sensor chips, micro-electro-mechanical system (MEMS) chips, signal processing chips (e.g., digital signal processing (DSP) chips), front-end chips (e.g., analog front-end (AFE) chips), monolithic 3D heterogeneous chip stacking chips, etc. Other chips are also within the scope of this invention.In at least one embodiment, the first semiconductor die 141 may include a master die (e.g., a SOC die), and the second semiconductor die 142 may include an auxiliary die (e.g., an HBM die).

[0156] The semiconductor module 120 may also include an upper molding layer 127 formed around the semiconductor die 140. The outer sidewalls of the upper molding layer 127 may be substantially aligned with the outer sidewalls of the interposer layer 10. The upper molding layer 127 may also have a substantially uniform (e.g., flat) upper surface and be substantially coplanar with the upper surface 140a of the semiconductor die 140.

[0157] The upper molding layer 127 can also be formed on and around the bottom fill layer 129 of the semiconductor module. Although Figure 1A Not shown in the diagram, but when the height of the upper surface of the bottom fill layer 129 of the semiconductor module is lower than the height of the upper surface 140a of the semiconductor die 140, the upper molding layer 127 can be formed on and bonded to the inner and / or outer sidewalls of the semiconductor die 140. Specifically, the upper molding layer 127 can be formed in the die gaps between semiconductor dies 140 and bonded to the inner sidewalls of the semiconductor die 140. The upper molding layer 127 can also be formed on the bottom fill layer 129 of the semiconductor module in the die gaps. The upper molding layer 127 can also be bonded to the wafer side surface of the interposer layer 10 (e.g., the upper surface of the upper passivation layer 13) and the bottom fill layer 129 of the semiconductor module.

[0158] In at least one embodiment, the upper molding layer 127 may be formed of a curable material that can be cured to form a rigid solid structure. The upper molding layer 127 may include, for example, an epoxy molding compound (EMC). In at least one embodiment, the upper molding layer 127 may include a material substantially similar to the package underfill layer 119 and the semiconductor module underfill layer 129. In at least one embodiment, the upper molding layer 127 may include a polymeric material, particularly an epoxy-based polymeric material. Other suitable molding materials may also be used.

[0159] In at least one embodiment, the coefficient of thermal expansion (CTE) of the upper molding layer 127 may be substantially similar to that of the intermediate layer 10. In at least one embodiment, the upper molding layer 127 may include additive materials (e.g., fillers added to the polymer material) to improve the properties of the upper molding layer 127 (e.g., thermal conductivity, CTE, etc.). Additive materials may include, for example, non-conductive powders, such as oxide powders. Other fillers in the upper molding layer 127 are also within the scope of this invention.

[0160] like Figure 1AAs shown, the back-side capacitor 210 may include a passivation film 201 and one or more capacitors located within the passivation film 201. The passivation film 201 may contact the entire upper surface of the upper molding layer 127 and the upper surface 140a of the semiconductor die 140. The passivation film 201 may also contact the upper surface of the semiconductor module bottom fill layer 129 between the semiconductor dies 140. In at least one embodiment, the sidewalls of the passivation film 201 may be substantially aligned with the sidewalls of the upper molding layer 127.

[0161] Capacitor 210 may include, for example, a first capacitor 210A located above a first semiconductor die 141 and a second capacitor 210B located above a second semiconductor die 142 (e.g., the outermost semiconductor die). The first capacitor 210A may include a plurality of parallel metal films in the passivation film 201, including a first metal film 211 and a second metal film 212. In at least one embodiment, the second metal film 212 may extend beyond the first metal film 211 in at least one direction (e.g., the x-direction) to allow the second metal film 212 to be connected from below to the interposer 10. The second capacitor 210B may include a plurality of parallel metal films located in the passivation film 201, including a first metal film 215 and a second metal film 216. Although... Figure 1A Not shown, but the second metal film 216 may extend beyond the first metal film 215 in at least one direction (e.g., the y direction) to allow the second metal film 216 to be connected to the interposer layer 10 from below.

[0162] Although Figure 1A Only one back-side capacitor 210 is shown, but additional back-side capacitors 210 can be stacked on top of the back-side capacitor 210 shown in semiconductor module 120. Furthermore, although... Figure 1A Only two capacitors are shown in the back-side capacitor 210, but the back-side capacitor 210 may include any number of capacitors. Furthermore, the size and position of the first capacitor 210A and the second capacitor 210B are not necessarily limited to [specific dimensions]. Figure 1A The size and position within the capacitor. That is, the first capacitor 210A and the second capacitor 210B can have any size and be located anywhere within the back capacitor 210.

[0163] Semiconductor module 120 may also include a distribution structure 220 located in the interposer 10. In at least one embodiment, the distribution structure 220 may include a plurality of metal traces (e.g., a redistribution layer (RDL) structure) in the redistribution layer 12a. The distribution structure 220 may include, for example, a first distribution line 221 of a first metal film 215 electrically coupled to a second capacitor 210B in the back-side capacitor 210. The distribution structure 220 may also include a second distribution line 222 of a second metal film 216 electrically coupled to a second capacitor 210B in the back-side capacitor 210. Although Figure 1ANot shown, but the distribution structure 220 may include additional distribution lines (e.g., redistribution layer 12a) of the first metal film 211 electrically coupled to the first capacitor 210A and additional distribution lines of the second metal film 212 electrically coupled to the first capacitor 210A.

[0164] The semiconductor module 120 may also include a connection structure 230 that electrically couples the back-side capacitor 210 to a distribution structure 220 in the interposer 10. The connection structure 230 may include a plurality of molded vias (TMVs), including a first molded via 231 that electrically couples a first metal film 215 in the second capacitor 210B to a first distribution line 221 in the distribution structure 220. The plurality of TMVs in the connection structure 230 may also include a second molded via 232 that electrically couples a second metal film 216 in the second capacitor 210B to a second distribution line 222 in the distribution structure 220. Although... Figure 1A Not shown, but connection structure 230 may include additional TMV for connecting the first metal layer 211 and the second metal layer 212 of the first capacitor 210A to the distribution structure 220. Connection structure 230 may also include additional elements in the interposer 10 and passivation film 201, which will be described in more detail below.

[0165] The semiconductor module 120 with a back-side capacitor 210 can have several advantages over comparable semiconductor modules. Specifically, the back-side capacitor 210 allows more capacitors (e.g., with larger capacitance values) to be placed close to the semiconductor die 140 in the semiconductor module 120. In at least one embodiment, the back-side capacitor 210 can provide a capacitance greater than 10 nF / mm². 2 The capacitance density is high. In at least one embodiment, the back-side capacitor 210 can be positioned closer to the active region 145 of the semiconductor die 140 (from a distance of 50µm to 775µm, depending on the thickness of the semiconductor die 140) compared to a conventional semiconductor module 120. This can help reduce the resistance between the capacitor and the active region 145. The semiconductor module 120 including the back-side capacitor 210 is particularly useful in high-power ICs, including, for example, logic / power ICs, memory, wafers, I / O wafers, 3D ICs, etc.

[0166] Furthermore, the back-side capacitor 210 can help reduce warpage of the semiconductor module 120. In at least one embodiment, the back-side capacitor 210 can serve as a CoW warpage adjustment film. The reduction in warpage can be attributed to multiple pairs of parallel metal films in the passivation film 201 and the back-side capacitor 210. In addition, the back-side capacitor 210 can help reduce thermal resistance, making it easier for heat to dissipate from the semiconductor module 120.

[0167] Refer again Figure 1BThe back-side capacitor 210 may be included in the semiconductor module 120 and as part of the charge storage structure 200. The charge storage structure may also include a distribution structure 220 and a connection structure 230. Various portions of the charge storage structure 200 may be composed of conductive materials, such as metallic materials (e.g., copper).

[0168] In the back-side capacitor 210, each of the first metal film 215 and the second metal film 216 of the second capacitor 210B (and each of the first metal film 211 and the second metal film 212 of the first capacitor 210A) may be composed of a conductive material. In at least one embodiment, each of the first metal film 215 and the second metal film 216 of the second capacitor 210B (and each of the first metal film 211 and the second metal film 212 of the first capacitor 210A) may be composed of one or more metal layers, said metal layers including metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). In at least one embodiment, the thickness Tc of the first metal film 215 and the second metal film 216 of the second capacitor 210B (and the first metal film 211 and the second metal film 212 of the first capacitor 210A) may be in the range of 0.1 μm to 100 μm. The metal films of the first capacitor 210A and the second capacitor 210B may be substantially parallel. The metal films of the first capacitor 210A and the second capacitor 210B may have the same or different thicknesses and may be composed of the same or different materials.

[0169] In the distribution structure 220, each of the first distribution line 221 and the second distribution line 222 may be composed of the same material as the other redistribution layers 12a in the intermediate layer 10. In at least one embodiment, each of the first distribution line 221 and the second distribution line 222 may be composed of one or more metal layers, including metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). In at least one embodiment, the thickness Td of each of the first distribution line 221 and the second distribution line 222 may be in the range of 0.01 μm to 100 μm. The first distribution line 221 and the second distribution line 222 may have the same or different thicknesses and may be composed of the same or different materials.

[0170] In the connection structure 230, the height of each of the first formed through-hole 231 and the second formed through-hole 232 may be approximately the same as the thickness of the upper formed layer 127. Furthermore, each of the first formed through-hole 231 and the second formed through-hole 232 may consist of one or more metal layers, including metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). The diameter Dt (e.g., width) of each of the first formed through-hole 231 and the second formed through-hole 232 may be in the range of 10 μm to 1000 μm.

[0171] In addition to the first formed through-hole 231 and the second formed through-hole 232, the connection structure 230 may include a first upper through-hole 211V in the passivation film 201 of the back-side capacitor 210. The first upper through-hole 211V (upper connection portion) can connect the first metal film 215 of the second capacitor 210B to the first formed through-hole 231 in the upper formed layer 127. The connection structure 230 may include a second upper through-hole 212V (upper connection portion) in the passivation film 201. The second upper through-hole 212V can connect the second metal film 216 of the second capacitor 210B to the second formed through-hole 232 in the upper formed layer 127. Each of the first upper through-hole 211V and the second upper through-hole 212V may consist of one or more metal layers, including metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.).

[0172] The connecting structure 230 may also include a first upper bonding pad 13a1 in the interposer layer 10 and one or more first lower through holes 221V. The first upper bonding pad 13a1 and the first lower through holes 221V (collectively referred to as the lower connecting portion) can connect the first distribution line 221 of the distribution structure 220 to the first molding through hole 231 in the upper molding layer 127. The connecting structure 230 may also include a second upper bonding pad 13a2 in the interposer layer 10 and one or more second lower through holes 222V (collectively referred to as the lower connecting portion). The second upper bonding pad 13a2 and the second lower through hole 222V can connect the second distribution line 222 of the distribution structure 220 to the second molding through hole 232 in the upper molding layer 127.

[0173] The first upper bonding pad 13a1 and the second upper bonding pad 13a2 may have substantially the same size and shape as the other upper bonding pads 13a in the interposer layer 10. The first upper bonding pad 13a1 and the second upper bonding pad 13a2 may also be made of substantially the same material as the other upper bonding pads 13a in the interposer layer 10. The first lower via 221V and the second lower via 222V may have substantially the same size and shape as the other metal vias in the redistribution layer 12a in the interposer layer 10. The first lower via 221V and the second lower via 222V may also be made of substantially the same material as the other metal vias in the redistribution layer 12a in the interposer layer 10.

[0174] The passivation film 201 may include one or more layers of passivation material. In at least one embodiment, the passivation film 201 may include one or more layers of dielectric material. In at least one embodiment, the material in the passivation film 201 above and / or below the parallel metal films (first metal film 211 and second metal film 212) of the first capacitor 210A and above and / or below the parallel metal films (first metal film 215 and second metal film 216) of the second capacitor 210B may be different from the material in the passivation film 201 between the parallel metal films of the first capacitor 210A and the parallel metal films of the second capacitor 210B. In at least one embodiment, the passivation film 201 may include SiN. x SiO x Polybenzoxazole (PBO), polyimide (PI), Ajinomoto build-up film (ABF), and bismaleimide triazine (BT) are among the materials that can be used in the passivation film 201.

[0175] In at least one embodiment, the passivation film 201 may have a first thickness Tp1 between the semiconductor die 140 and the first metal plate 215 of the second capacitor (and between the semiconductor die 140 and the first metal plate 211 of the first capacitor 210A). The passivation film 201 may also include a second thickness Tp2 between the parallel metal plates of the second capacitor 210B (and between the parallel metal plates of the first capacitor 210A). The passivation film 201 may also include a third thickness Tp3 above the parallel metal plates of the second capacitor 210B (and above the parallel metal plates of the first capacitor 210A).

[0176] In at least one embodiment, the second thickness Tp2 may be less than the third thickness Tp3. In at least one embodiment, the third thickness Tp3 may be at least twice the second thickness Tp2. In at least one embodiment, the second thickness Tp2 may be substantially the same as the first thickness Tp1. In at least one embodiment, the first thickness Tp1 may be less than the second thickness Tp2. In at least one embodiment, each of the first thickness Tp1 and the second thickness Tp2 may be in the range of 0.01 μm to 100 μm. In at least one embodiment, the third thickness Tp3 may be in the range of 0.1 μm to 100 μm. In at least one embodiment, the total thickness of the passivation film (e.g., Tp1 + Tp2 + Tp3) may be in the range of 0.1 μm to 10000 μm.

[0177] Refer again Figure 1C and Figure 1D The passivation film 201 may include multiple layers of passivation material (dielectric material). Specifically, the passivation film 201 may include a first passivation layer 201L1 located on the upper surface 140a of the semiconductor die 140, the upper surface of the upper molding layer 127, and the upper surface of the bottom filling layer 129 of the semiconductor module. The first metal film 215 of the second capacitor 210B (and the first metal film 211 of the first capacitor 210A) may be formed on the upper surface of the first passivation layer 201L1. A first upper via 211V may be formed in the first passivation layer 201L1.

[0178] The passivation film 201 may also include a second passivation layer 201L2 formed on the upper surface of the first passivation layer 201L1 and on the first metal film 215 of the second capacitor 210B (and the first metal film 211 of the first capacitor 210A). The second metal film 216 of the second capacitor 210B (and the second metal film 212 of the first capacitor 210A) may be formed on the upper surface of the second passivation layer 202L1. The second passivation layer 201L2 may separate the first metal film 215 from the second metal film 216 (and the first metal film 211 from the second metal film 212) and may serve as a charge separation layer, containing the electric field in the back-side capacitor 210. A second upper via 212V may be formed in the second passivation layer 201L2 and the first passivation layer 201L1. The passivation film 201 may also include a third passivation layer 201L3 formed on the second passivation layer 201L2 and the second metal film 216 of the second capacitor 210B (and the second metal film 212 of the first capacitor 210A).

[0179] Refer again Figure 1EThe upper molding layer 127 may be formed around the entire semiconductor die 140 and the bottom fill layer 129 of the semiconductor module. The semiconductor module 120 may have a generally rectangular shape in a top view. The length of the semiconductor module 120 in the x-direction may be greater than its length in the y-direction. The length of the first semiconductor die 141 in the x-direction may be less than its length in the y-direction. The length of the second semiconductor die 142 in the x-direction may be less than its length in the y-direction.

[0180] like Figure 1E As shown, the position of the semiconductor die 140 may be substantially offset from the center of the upper molding layer 127 (e.g., offset from the center of the semiconductor module 120). This allows the upper molding layer 127 to accommodate one or more TMVs (e.g., first molded via 231, second molded via 232, etc.) in the connection structure 230 of the charge storage structure 200.

[0181] The upper molding layer 127 may have a first side 127a and a second side 127b opposite to the first side 127a. The upper molding layer 127 may also have a third side 127c and a fourth side 127d opposite to the third side 127c. The distance D1 in the y-direction between one side of the first semiconductor die 141 and the first side 127a of the upper molding layer 127 may be greater than the distance D2 in the y-direction between the opposite side of the first semiconductor die 141 and the second side 127b of the upper molding layer 127. The distance D3 in the x-direction between one side of the second semiconductor die 142 and the third side 127c of the upper molding layer 127 may be greater than the distance D4 in the x-direction between the opposite side of the outermost first semiconductor die 141 and the fourth side 127d of the upper molding layer 127.

[0182] Refer again Figure 1F For ease of understanding, the passivation film 201 of the back-side capacitor 210 is omitted. However, the outer periphery of the passivation film 201 can be approximately coextensive with the outer periphery of the upper molded layer 127. The position of the outer periphery of the passivation film is determined by... Figure 1F The dashed line in the middle represents...

[0183] like Figure 1F As shown, the back-side capacitor 210 may include a total of three capacitors. The back-side capacitor 210 may include a first capacitor 210A located on a first semiconductor die 141 closer to the center. The back-side capacitor 210 may also include two second capacitors 210B located on two second semiconductor dies 142 respectively.

[0184] The first capacitor 210A may cover substantially the entirety of the first semiconductor die 141 located closer to the center. The outer periphery of the first capacitor 210A may be substantially co-linear with the outer periphery of the first semiconductor die 141 located closer to the center. However, the first metal film 211 may include a hanging portion 211o that extends beyond the edge of the first semiconductor die 141 toward the first side 127a of the upper molding layer 127 by a hanging distance OD1. A first upper via 211V may be connected to the bottom side of the hanging portion 211o of the first metal film 211. The second metal film 212 may include a hanging portion 212o that extends beyond the edge of the first metal film 211 toward the first side 127a of the upper molding layer 127 by a hanging distance OD2. A second upper via 212V may be connected to the bottom side of the hanging portion 212o of the second metal film 212. In at least one embodiment, the hanging distance OD1 may be substantially the same as the hanging distance OD2. In at least one embodiment, the overhang distance OD1 may be at least 10% larger than the diameter of the first upper through hole 211V. In at least one embodiment, the overhang distance OD2 may be at least 10% larger than the diameter of the second upper through hole 212V.

[0185] Each second capacitor 210B may cover substantially the entirety of the corresponding second semiconductor die 142. The outer periphery of the second capacitor 210B may be substantially co-extended with the outer periphery of the second semiconductor die 142. However, the first metal film 215 may include a dangling portion 215o that extends beyond the edge of the second semiconductor die 142 toward the third side 127c of the upper molding layer 127 by a dangling distance OD5. A first upper via 215V may be connected to the bottom side of the dangling portion 215o of the first metal film 215. The second metal film 216 may include a dangling portion 216o that extends beyond the edge of the first metal film 215 toward the third side 127c of the upper molding layer 127 by a dangling distance OD6. A second upper via 216V may be connected to the bottom side of the dangling portion 216o of the second metal film 216. In at least one embodiment, the dangling distance OD5 may be substantially the same as the dangling distance OD6. In at least one embodiment, the overhang distance OD5 may be at least 10% larger than the diameter of the first upper through hole 215V. In at least one embodiment, the overhang distance OD6 may be at least 10% larger than the diameter of the second upper through hole 216V.

[0186] In at least one embodiment, each of the pair of parallel metal films in each of the three capacitors (first capacitor 210A and two second capacitors 210B) may be substantially aligned with its corresponding semiconductor die. The area of ​​each of the pair of parallel metal films in each of the three capacitors may be the same as the area of ​​the upper surface of its corresponding semiconductor die. However, the size and position of the capacitors in the back-side capacitor 210 are not necessarily limited to the size and position of the semiconductor die. In at least one embodiment, the total area of ​​the back-side capacitors (e.g., the total area of ​​the first capacitor 210A and the two second capacitors 210B) is in the range of 10% to 100% of the area of ​​the semiconductor module.

[0187] Figures 2A to 2F Various intermediate structures in a method of manufacturing package module 120 according to one or more embodiments are illustrated. Figure 2A This is a vertical cross-sectional view of an intermediate structure according to an embodiment of the present invention, which includes an interposer 10 (e.g., an organic interposer) formed on a carrier substrate 1 (e.g., a carrier wafer). The carrier substrate 1 may be a circular wafer or a rectangular wafer. The lateral dimension of the carrier substrate 1 (e.g., the diameter of a circular wafer or one side of a rectangular wafer) may be in the range of 100 mm to 500 mm, for example, 200 mm to 400 mm, but smaller or larger lateral dimensions may also be used. The carrier substrate 1 may include a semiconductor substrate, an insulating substrate, or a conductive substrate. The carrier substrate 1 may be transparent or opaque. The thickness of the carrier substrate 1 is sufficient to provide mechanical support for the interposer array formed on it. For example, the thickness of the carrier substrate 1 may be in the range of 60 micrometers to 1 millimeter, but smaller or larger thicknesses may also be used.

[0188] An adhesive layer (not shown) can be applied to the top surface of a carrier substrate 1. In one embodiment, the carrier substrate 1 may include an optically transparent material, such as glass or sapphire. In this embodiment, the adhesive layer may include a light-to-heat conversion (LTHC) layer. An LTHC layer is a solvent-based coating applied using a spin-coating method. The LTHC layer can form a layer that converts ultraviolet light into heat, causing the LTHC layer to lose its adhesiveness. Alternatively, the adhesive layer may include a thermally degradable adhesive material. For example, the adhesive layer may include an acrylic pressure-sensitive adhesive that decomposes at high temperatures. The debonding temperature of the thermally degradable adhesive material may be in the range of 150°C to 400°C. Other suitable thermally degradable adhesive materials that decompose at other temperatures are also within the scope of this invention.

[0189] The lower bonding pad 14a can be formed on the adhesive layer. The lower bonding pad 14a can comprise any metallic material that can be bonded to solder material. The lower bonding pad 14a can be formed by depositing one or more metal layers (e.g., by chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition techniques), said metal layers comprising metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). The metal layers can then be patterned using a lithography process to form the lower bonding pad 14a. The lithography process can include forming a patterned photoresist mask (not shown) on the metallic material and etching (e.g., wet etching, dry etching, etc.) through openings in the photoresist mask to expose the upper surface of the metallic material. The photoresist mask can then be removed by ashing, dissolving the photoresist mask, or consuming the photoresist mask during the etching process.

[0190] In at least one embodiment, the lower bonding pad 14a may comprise a bump under-metal (UBM) layer stack deposited over the adhesive layer. The material layer order within the UBM layer stack can be selected such that solder material portions can subsequently bond to the bottom portion of the UBM layer stack. Layer stacks that can be used for the UBM layer stack include, but are not limited to, stacks of Cr / Cr-Cu / Cu / Au, Cr / Cr-Cu / Cu, TiW / Cr / Cu, Ti / Ni / Au, and Cr / Cu / Au. Other suitable materials are also within the scope contemplated by this invention. The thickness of the UBM layer stack can be in the range of 5 micrometers to 60 micrometers, for example, 10 micrometers to 30 micrometers, but smaller or larger thicknesses may also be used. A photoresist layer may be applied over the UBM layer stack and may be photolithographically patterned to form an array of discretely patterned photoresist material portions. An etching process may be performed to remove unmasked portions of the UBM layer stack. The etching process may be an isotropic etching process or an anisotropic etching process. The remaining portion of the UBM layer stack may form the lower bonding pad 14a. In at least one embodiment, the lower bonding pad 14a may be configured as a two-dimensional array, which may be a two-dimensional periodic array, such as a rectangular periodic array. In at least one embodiment, the lower bonding pad 14a may be formed as a base for supporting a controlled collapse wafer interconnect (C4) bump structure.

[0191] Next, a lower passivation layer 14 can be formed on the side surface of the interposer 10 and over the lower bonding pad 14a. The lower passivation layer 14 can be formed by depositing one or more layers of passivation material (e.g., by CVD, PVD, or other suitable deposition techniques). Passivation materials include silicon oxide, silicon nitride, low dielectric constant dielectric materials (e.g., carbon-doped oxides), very low dielectric constant dielectric materials (e.g., porous carbon-doped silicon dioxide), combinations thereof, or other suitable materials. The passivation material can then be planarized (e.g., by wet etching, dry etching, etc.) to form the lower passivation layer 14.

[0192] Next, multiple dielectric layers 12 and multiple redistribution layers 12a can be alternately formed on the lower passivation layer 14 and the lower bonding pad 14a. It should be noted that, although... Figure 2A The illustration shows five dielectric layers 12 and four redistribution layers 12a. More or fewer dielectric layers 12 and redistribution layers 12a are also within the scope of this invention.

[0193] Each dielectric layer 12 can be formed, for example, by depositing (e.g., by CVD, PVD, or other suitable deposition techniques) a layer of dielectric polymer material (e.g., polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO)). Other suitable materials are also within the scope of this invention. The thickness of the dielectric polymer material layer can range from 4 micrometers to 60 micrometers, but smaller or larger thicknesses can also be used. Next, the dielectric layer 12 can be patterned by a lithography process to form vias in the dielectric layer 12. The lithography process may include forming a patterned photoresist mask (not shown) on the dielectric material layer and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the dielectric material through openings in the photoresist mask. The photoresist mask can then be removed by ashing, dissolving the photoresist mask, or consuming the photoresist mask during the etching process.

[0194] Next, a redistribution layer 12a (e.g., metal traces and metal vias) can be formed on the dielectric layer 12. For example, the redistribution layer 12a can be formed by depositing (e.g., by CVD, PVD, or other suitable deposition techniques) one or more layers of metal material (e.g., copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals) on the dielectric layer 12 and in the vias formed by the patterned dielectric layer 12. Next, the redistribution layer 12a can be patterned using a lithography process. The lithography process may include forming a patterned photoresist mask (not shown) on the metal material layer and etching (e.g., wet etching, dry etching, etc.) through openings in the photoresist mask to expose the upper surface of the metal material. Subsequently, the photoresist mask can be removed by ashing, dissolving the photoresist mask, or consuming the photoresist mask during the etching process.

[0195] like Figure 2AAs shown, the first distribution line 221 and the second distribution line 222 of the distribution structure 220 can be formed in the dielectric layer 12 along with the formation of the redistribution layer 12a. Furthermore, the first lower via 221V and the second lower via 222V of the connection structure 230 can also be formed in the dielectric layer 12 along with the formation of the redistribution layer 12a. That is, the same process steps used to form the redistribution layer 12a can be used to form the first distribution line 221, the second distribution line 222, the first lower via 221V, and the second lower via 222V. In at least one embodiment, the first distribution line 221, the second distribution line 222, the first lower via 221V, and the second lower via 222V are part of the redistribution layer 12 (e.g., an RDL structure) included in the interposer layer 10.

[0196] like Figure 2A As further shown, an upper bonding pad 13a can then be formed on the uppermost dielectric layer 12. The upper bonding pad 13a can be formed by a process similar to that described above for the lower bonding pad 14a. Furthermore, the first upper bonding pad 13a1 and the second upper bonding pad 13a2 can also be formed on the uppermost dielectric layer 12 together with the other upper bonding pads 13a of the interposer layer 10. That is, the same process steps used to form the upper bonding pad 13a can be used to form the first upper bonding pad 13a1 and the second upper bonding pad 13a2 of the connection structure 230.

[0197] Next, an upper passivation layer 13 can be formed on the uppermost dielectric layer 12 and the upper bonding pad 13a. The upper passivation layer 13 can also be formed on the first upper bonding pad 13a1 and the second upper bonding pad 13a2 of the connection structure 230. The upper passivation layer 13 can be formed by a process similar to that of the lower passivation layer 14 described above.

[0198] Figure 2B This is a vertical cross-sectional view of an intermediate structure including a first semiconductor die 141 and a second semiconductor die 142 according to one or more embodiments. The first semiconductor die 141 and the second semiconductor die 142 may be placed on the interposer module 10, for example, by using an electromechanical pick-and-place (PNP) machine.

[0199] Each of the first semiconductor die 141 and the second semiconductor die 142 may be bonded to a corresponding subset of the upper bonding pad 13a. The first semiconductor die 141 and the second semiconductor die 142 may be electrically coupled to each other via one or more redistribution layers 12a in the interposer 10. In at least one embodiment, the first distribution line 221 and the second distribution line 222 of the distribution structure 220 may be electrically isolated from the redistribution layers 12a in the interposer 10, and therefore electrically isolated from the semiconductor die 140. In at least one embodiment, the first distribution line 221 and the second distribution line 222 of the distribution structure 220 may be electrically coupled to at least a portion of the redistribution layers 12a in the interposer 10, and therefore electrically coupled to the semiconductor die 140.

[0200] Each of the first semiconductor die 141 and the second semiconductor die 142 may be bonded to the interposer layer 10 via one or more microbumps 128. In at least one embodiment, the microbumps 128 may comprise a two-dimensional array of microbumps 128, and each of the first semiconductor die 141 and the second semiconductor die 142 may be attached to the upper bonding pad 13a via C2 bonding (e.g., solder bonding). After the bump structure of the semiconductor wafer (e.g., the first semiconductor die 141 and the second semiconductor die 142) is disposed above the upper bonding pad 13a, a C2 bonding process that reflows the solder portions of the microbumps 128 may be performed.

[0201] Figure 2C This is a vertical cross-sectional view of an intermediate structure including a semiconductor module underfill layer 129 according to one or more embodiments. The semiconductor module underfill layer 129 can be applied by depositing and / or injecting an epoxy resin-based polymer material onto the interposer layer 10. The epoxy resin-based polymer material can be applied onto the interposer layer 10, thereby forming below and around the microbumps 128. Subsequently, the semiconductor module underfill layer 129 can be cured, for example, in an oven at about 150°C for about 90 minutes, to give the semiconductor module underfill layer 129 sufficient rigidity and mechanical strength.

[0202] Figure 2D A vertical cross-sectional view of an intermediate structure including an upper molding layer 127 according to one or more embodiments is illustrated. The upper molding layer 127 can be dispensed with liquid molding material (e.g., epoxy molding material) using a suitable dispensing tool. Figure 2E The upper molding layer 127 is formed on the intermediate structure. The upper molding layer 127 can be distributed on the intermediate structure so that its height is greater than the height of the upper surface 140a of the semiconductor die 140 (first semiconductor die 141 and second semiconductor die 142).

[0203] In at least one embodiment, the dispensing of molding material can be automated. Specifically, various aspects of the dispensing process can be computer-controlled by a control system (e.g., an electronic control system, a central processing unit (CPU)). In at least one embodiment, the initiation of molding material dispensing, the flow rate of molding material dispensing, and the cessation of molding material dispensing can be controlled by the control system. The control system can be programmed to dispense a predetermined amount of molding material, for example, based on various input parameters. Input parameters may include, for example, the volume of the space surrounding the interposer 10, the size of the interposer 10, the size of the first semiconductor die 141, the size of the second semiconductor die 142, etc.

[0204] In at least one embodiment, the molding material of the upper molding layer 127 may include a capillary material (e.g., a capillary bottom-filling material). The molding material may have low viscosity. Specifically, the viscosity at 10 rpm may be less than about 5000 cP. In at least one embodiment, the molding material may include a low-viscosity suspension of a thermally conductive but non-conductive material (e.g., an oxide filler) in a prepolymer. Low viscosity can help facilitate the flow of the molding material around the first semiconductor die 141 and the second semiconductor die 142. Low viscosity can also help prevent the formation of voids in the upper molding layer 127. In at least one embodiment, the upper molding layer 127 may be substantially void-free.

[0205] Figure 2E A vertical cross-sectional view of an intermediate structure including a first molded through-hole 231 and a second molded through-hole 232 according to one or more embodiments is illustrated. After the upper molding layer 127 has fully cured, the first molded through-hole 231 and the second molded through-hole 232 of the connecting structure 230 can be formed in the upper molding layer 127. First, the openings of the first molded through-hole 231 and the second molded through-hole 232 can be formed in the upper molding layer 127.

[0206] In at least one embodiment, openings can be formed via a laser drilling process. In this process, a suitable laser (e.g., a CO2 layer or an ultraviolet (UV) laser) can be positioned above the intermediate structure. The laser focus can be directed to the desired locations of the first formed via 231 and the second formed via 232. The laser can then be activated to drill openings in the upper formed layer 127, the size and depth of which correspond to the size and depth of the first and second formed vias 231 and 232. The laser spot size, pulse duration, and energy density can be carefully controlled to achieve the desired depth and diameter of the openings without damaging the surrounding material. The laser can be pulsed onto the upper formed layer 127, rapidly heating and evaporating the material in the target area. The laser can be programmed to drill to a specific depth (e.g., the thickness of the formed material) to ensure that the openings reach the first upper bonding pad 13a1 and the second upper bonding pad 13a2.

[0207] After forming the openings of the first shaped through-hole 231 and the second shaped through-hole 232, the first shaped through-hole 231 and the second shaped through-hole 232 can be formed within the openings. In at least one embodiment, the first shaped through-hole 231 and the second shaped through-hole 232 can be formed by an electroplating process, wherein the first shaped through-hole 231 and the second shaped through-hole 232 grow within the openings. In the electroplating process, the first upper bonding pad 13a1 and the second upper bonding pad 13a2 serve as seed layers for initiating the growth of the first shaped through-hole 231 and the second shaped through-hole 232 through the electroplating process.

[0208] According to one or more embodiments, Figure 2F A vertical cross-sectional view of the intermediate structure after the planarization process is shown. After forming the first molded via 231 and the second molded via 232 (e.g., through an electroplating process), the upper molded layer 127, the first molded via 231, and the second molded via 232 can be planarized using a planarization process. The planarization process can be used such that each of the upper surface of the upper molded layer 127, the upper surface of the first molded via 231, and the upper surface of the second molded via 232 is substantially coplanar with the upper surfaces of the first semiconductor die 141 and the second semiconductor die 142. The upper molded layer 127, the first molded via 231, and the second molded via 232 can be planarized, for example, by grinding, chemical mechanical polishing (CMP), or other suitable planarization techniques.

[0209] Figure 2GA vertical cross-sectional view of an intermediate structure including a back-side capacitor 210 according to one or more embodiments is illustrated. The back-side capacitor 210 may be manufactured in a manner similar to, for example, the manner in which the dielectric layer 12 and the redistribution layer 12a of the interposer 10 are manufactured. Specifically, a first passivation layer 201L1 may be formed on the upper surface of the upper forming layer 127 and the upper surface 140a of the semiconductor die 140 by a suitable deposition process (e.g., by CVD, PVD or other suitable deposition techniques). The first passivation layer 201L1 may be formed, for example, by depositing a layer of dielectric polymer material (e.g., SiN). x SiO x The dielectric polymer material can be formed using materials such as polybenzoxazole (PBO), polyimide (PI), ajinomoto bleached film (ABF), bismaleimide triazine (BT), or benzocyclobutene (BCB). Other suitable materials are also within the scope of this invention. Next, the dielectric polymer material can be patterned using a photolithography process to form a via for the first upper via 211V in the first passivation layer 201L1. The photolithography process may include forming a patterned photoresist mask (not shown) on the dielectric polymer material layer and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the dielectric polymer material through openings in the photoresist mask. The photoresist mask can then be removed by ashing, dissolving the photoresist mask, or consuming the photoresist mask during the etching process.

[0210] Next, a first metal film 211 and a first metal film 215 can be formed on the first passivation layer 201L1. For example, the first metal film 211 and the first metal film 215 can be formed by depositing (e.g., by CVD, PVD or other suitable deposition techniques) one or more layers of metal material (e.g., copper, aluminum, nickel, titanium, a combination of the foregoing or other suitable metals) on the first passivation layer 201L1 and in the vias formed by patterning the first passivation layer 201L1. Subsequently, the metal material can be patterned by a lithography process to form the first upper via 211V, the first metal film 211, and the first metal film 215. The lithography process may include forming a patterned photoresist mask (not shown) on the metal material layer and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the metal material through openings in the photoresist mask. Subsequently, the photoresist mask can be removed by ashing, dissolving the photoresist mask, or consuming the photoresist mask during the etching process.

[0211] A similar process can be performed to complete the formation of the back-side capacitor 210. Specifically, the second passivation layer 201L2 can be formed by performing a suitable deposition process on the first passivation layer 201L1, the first metal film 211, and the first metal film 215. An opening for the second upper via 212V can be formed in the second passivation layer 201L2 and the first passivation layer 201L1 (e.g., by photolithography). Metal material can be deposited on the second passivation layer 201L2 and patterned (e.g., by photolithography) to form the second upper via 212V, the second metal film 212, and the second metal film 216. Then, a third passivation layer 201L3 can be formed on the second passivation layer 201L2, the second metal film 212, and the second metal film 216 (e.g., by a suitable deposition process).

[0212] Figure 2H A vertical cross-sectional view of an intermediate structure including a plurality of C4 bumps 121 according to one or more embodiments is illustrated. After the back-side capacitor 210 is formed, the carrier substrate 1 can be separated from the interposer 10. The carrier substrate 1 can be separated from the interposer 10, for example by disabling the adhesive layer (not shown) to which the carrier substrate is attached to the interposer 10. The adhesive layer can be disabled, for example, by thermal annealing at high temperature (e.g., for heat-failed adhesive materials), or by exposing the adhesive layer to ultraviolet light (e.g., for ultraviolet-failed adhesive materials).

[0213] Next, a plurality of C4 bumps 121 may be formed on the intermediate structure. The C4 bumps 121 may include, for example, solder balls formed on the lower bonding pad 14a by an electroplating process. The plurality of C4 bumps 121 may contact the lower bonding pad 14a through openings in the lower passivation layer 14. In at least one embodiment, one or more under-bump metallization (UBM) layers (not shown) may be formed on the lower bonding pad 14a. Next, a plurality of C4 bumps 121 may be formed to contact the lower bonding pad 14a through the UBM layer.

[0214] Multiple semiconductor modules 120 can be simultaneously formed on the interposer 10 (e.g., an interposer wafer) in a wafer-level process. After forming the C4 bumps 121, a monolithic process can be performed to monolithize the semiconductor modules 120. For example, the monolithic process can be performed by cutting the interposer 10 (and the molding material 127 and passivation film 201 formed on the back-side capacitor 210 above it) along a cutting line located outside the first capacitor 210A and the second capacitor 210B using a cutting saw. Specifically, the cutting line can be located at a position sufficiently far from the first capacitor 210A and the second capacitor 210B (e.g., greater than 0.8 mm).

[0215] Figure 3A flowchart illustrating a method for manufacturing a semiconductor module according to one or more embodiments is provided. Step 310 includes forming an interposer layer. Step 320 includes attaching a plurality of semiconductor dies to the interposer layer. Step 330 includes forming an upper molding layer around the plurality of semiconductor dies. Step 340 includes forming a back-side capacitor on the plurality of semiconductor dies and the upper molding layer, such that the back-side capacitor is electrically coupled to the interposer layer through the upper molding layer.

[0216] Figure 4A and Figure 4B It is a vertical cross-sectional view of a package structure 100 including a semiconductor module 120 according to one or more embodiments. Figure 4A It is a vertical sectional view (front view) of the package structure 100 according to one or more embodiments. Figure 4B It is a vertical sectional view (side view) of the encapsulation structure 100 according to one or more embodiments.

[0217] like Figure 4A As shown, the package structure 100 may include a package substrate 110, a semiconductor module 120 including a back-side capacitor 210 located on the package substrate 110, and a package cover 130 located on the semiconductor module 120. The package cover 130 may include a package cover portion 130p located above the semiconductor module 120 and a package cover pin portion 130a attached to the package substrate 110.

[0218] The packaging substrate 110 may include a core substrate or a coreless substrate. In at least one embodiment, the packaging substrate 110 may include, for example, a core 112, an upper packaging substrate dielectric layer 114 formed on the core 112 (e.g., a first side or wafer side of the packaging substrate 110), and an under packaging substrate dielectric layer 116 formed on the core 112 (e.g., a second side or board side of the packaging substrate 110). Specifically, the packaging substrate 110 may include a layering film substrate such as an Ajinomoto layering film (ABF) substrate. That is, in at least one embodiment, each of the upper packaging substrate dielectric layer 114 and the under packaging substrate dielectric layer 116 may be described as an ABF layer.

[0219] Core 112 can help provide rigidity to the encapsulation substrate 110. Core 112 may include, for example, epoxy resin, such as bismaleimide triazine epoxy resin (BT epoxy resin) and / or glass fiber laminate. Core 112 may alternatively or additionally include organic materials, such as polymeric materials. Specifically, core 112 may include dielectric polymeric materials, such as polyimide (PI), benzocyclobutene (BCB) polymer, or polybenzoxazole (PBO). Other suitable dielectric materials are also contemplated within the scope of this invention.

[0220] The core 112 may include one or more vias 112a. The vias 112a may extend from the lower surface of the core 112 to the upper surface of the core 112. The vias 112a may allow electrical connection between the upper dielectric layer 114 and the lower dielectric layer 116 of the package substrate. The vias 112a may include, for example, one or more layers, and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metallic materials are also within the scope of this invention.

[0221] A dielectric layer 114 on the package substrate may be formed on the upper surface of the core 112. The dielectric layer 114 on the package substrate may include multiple layers, and in particular may include a build-up film (e.g., ABF). The dielectric layer 114 on the package substrate may also include organic materials, such as polymeric materials. Specifically, the dielectric layer 114 on the package substrate may include dielectric polymeric materials, such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). Other suitable dielectric materials are also within the scope of this invention.

[0222] The dielectric layer 114 on the package substrate may include one or more on-package substrate bonding pads 114a located on the wafer-side surface of the dielectric layer 114 on the package substrate. The on-package substrate bonding pads 114a may be exposed on the wafer-side surface of the dielectric layer 114 on the package substrate. The dielectric layer 114 on the package substrate may also include one or more metal interconnect structures 114b. The metal interconnect structures 114b may be connected to the on-package substrate bonding pads 114a and vias 112a in the core 112. The metal interconnect structures 114b may include metal layers (e.g., copper traces) and metal vias connecting the metal layers. The on-package substrate bonding pads 114a and the metal interconnect structures 114b may include, for example, one or more layers, and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metallic materials are also within the scope of this invention.

[0223] A passivation layer 110a on the package substrate may be formed on the wafer-side surface of the dielectric layer 114 on the package substrate. The passivation layer 110a on the package substrate may partially cover the bonding pad 114a on the package substrate. The passivation layer 110a may include silicon oxide, silicon nitride, a low dielectric constant dielectric material (e.g., carbon-doped oxide), an extremely low dielectric constant dielectric material (e.g., porous carbon-doped silicon dioxide), a combination of the foregoing, or other suitable materials.

[0224] A sub-dielectric layer 116 may be formed on the lower surface of the core 112. The sub-dielectric layer 116 may also comprise multiple layers, and particularly may comprise a build-up film (e.g., ABF). The sub-dielectric layer 116 may also comprise organic materials, such as polymeric materials. Specifically, the sub-dielectric layer 116 may comprise dielectric polymeric materials, such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). Other suitable dielectric materials are also within the scope of this invention.

[0225] The under-package dielectric layer 116 may include one or more under-package bonding pads 116a located on the board-side surface of the under-package dielectric layer 116. Specifically, the under-package bonding pads 116a may be exposed on the board-side surface of the under-package dielectric layer 116. The under-package dielectric layer 116 may also include one or more metal interconnect structures 116b. The metal interconnect structures 116b may be connected to the under-package bonding pads 116a and the vias 112a in the core 112. The metal interconnect structures 116b may include metal layers (e.g., copper traces) and metal vias connecting the metal layers. The under-package bonding pads 116a and the metal interconnect structures 116b may include, for example, one or more layers, and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metallic materials are also within the scope of this invention.

[0226] A passivation layer 110b under the package substrate may be formed on the board-side surface of the dielectric layer 116 under the package substrate. The passivation layer 110b under the package substrate may partially cover the bonding pad 116a under the package substrate. The passivation layer 110b under the package substrate may include silicon oxide, silicon nitride, a low dielectric constant dielectric material (e.g., carbon-doped oxide), an extremely low dielectric constant dielectric material (e.g., porous carbon-doped silicon dioxide), a combination of the foregoing, or other suitable materials.

[0227] A ball grid array (BGA) 180 comprising a plurality of solder balls 181 may be formed on the board-side surface of the dielectric layer 116 beneath the package substrate. The solder balls 181 allow the package structure 100 to be securely mounted on a substrate (e.g., a printed circuit board (PCB)) and electrically coupled to the PCB substrate. The solder balls 181 may contact the bonding pads 116a beneath the package substrate. Therefore, the solder balls 181 may be electrically connected to the bonding pads 114a on the package substrate via the metal interconnect structure 116b, the via 112a, and the metal interconnect structure 114b.

[0228] Semiconductor module 120 can be mounted on package substrate 110. Specifically, C4 bump 121 of semiconductor module 120 can be attached to bonding pad 114a on package substrate 110. Figure 4AAs shown, the length of the packaging substrate 110 in the x-direction can be greater than the length of the semiconductor module 120 in the x-direction. The width of the packaging substrate 110 in the y-direction can also be greater than the width of the semiconductor module 120 in the y-direction.

[0229] An underfill layer 119 may be formed on the package substrate 110 and located below and around the semiconductor module 120. The underfill layer 119 may also be formed around the C4 bump 121. The underfill layer 119 thereby securely attaches the semiconductor module 120 to the package substrate 110. The underfill layer 119 may be formed of a material similar to the material of the underfill layer 129 of the semiconductor module. In at least one embodiment, the underfill layer 119 may be formed of an epoxy-based polymer material.

[0230] The package structure 100 may further include a thermal interface material (TIM) layer 170 on the semiconductor module 120. The TIM layer 170 may be located on the upper surface of the back-side capacitor 210. The TIM layer 170 may include, for example, grease-type TIM, paste-type TIM, thin-film TIM, gel-type TIM, graphite thin-film TIM, liquid metal TIM (e.g., gallium-rich TIM), phase change material (PCM) type TIM, etc. In at least one embodiment, the TIM layer 170 may include a low-melting-temperature (LMT) metal TIM. The PCM type TIM may include, for example, a polymer-based phase change material TIM. PCM type TIM can improve porosity and delamination issues, enhance thermal contact resistance, and improve thermal efficiency in the package structure 100. In at least one embodiment, the PCM type TIM can change from a solid state to a high-viscosity semi-liquid state at approximately 60°C. In at least one embodiment, the TIM layer 170 may include materials based on gallium, indium, silver, solder, etc. Other types of TIMs in TIM layer 170 are also within the scope of this invention.

[0231] A TIM layer 170 may be formed on the back-side capacitor 210 to dissipate heat generated during operation of the semiconductor module 120 (e.g., operation of the semiconductor die 140). The TIM layer 170 may be attached to the back-side capacitor 210, for example, via a thermally conductive adhesive. The TIM layer 170 may have low overall thermal resistance and high thermal conductivity. The bond-line thickness (BLT) (e.g., the distance between the package cover 130 and the back-side capacitor 210) may be less than about 100 μm, but larger or smaller distances may also be used.

[0232] The package cover 130 may be located above the semiconductor module 120 and connected to the package substrate 110. The package cover 130 may include a package cover portion 130p formed on a TIM layer 170 above the semiconductor module 120. The TIM layer 170 may be compressed between the underside of the package cover portion 130p and the back capacitor 210. The package cover 130 may also include a package cover lead portion 130a located around the outer periphery of the package cover portion 130p. The package cover lead portion 130a may be secured to the package substrate 110 by an adhesive layer 160.

[0233] The package cover 130 can be formed of, for example, a metal, ceramic, or polymer material. In at least one embodiment, the material of the package cover 130 may include copper with a nickel-coated surface. The thickness of the nickel-coated surface may be in the range of 1 μm to 10 μm. The package cover portion 130p may be plate-shaped (e.g., planar) and generally parallel to the upper surface of the package substrate 110. The package cover portion 130p may, for example, be in... Figure 4A The package cover portion 130p extends in the xy-plane. It may include an outer sidewall substantially aligned with the outer sidewall of the package cover pin portion 130a. The center of the package cover portion 130p in the xy-plane may be substantially aligned in the z-direction with the center of the semiconductor module 120 in the xy-plane. The upper surface of the package cover portion 130p may be substantially parallel to the lower side of the package cover portion 130p.

[0234] An adhesive layer 160 may be formed on the package substrate 110 near the sidewall of the semiconductor module 120. The adhesive layer 160 may bond the package cover pin portion 130a to the package substrate 110. The thickness of the adhesive layer 160 may be in the range of 50 μm to 200 μm. The adhesive layer 160 may include, for example, a silicone adhesive (e.g., containing alumina, zinc oxide, resin, etc.) or an epoxy adhesive. Other suitable adhesives may also be used. The adhesive layer 160 may contact the recessed upper surface of the back metal layer or the upper molding layer 127.

[0235] Figures 5A to 5G Various intermediate structures in a method of manufacturing a package structure 100 according to one or more embodiments are illustrated. Figure 5A This is a vertical cross-sectional view of an intermediate structure of a package substrate 110 including an upper package substrate bonding pad 114a and a lower package substrate bonding pad 116a, according to one or more embodiments. A package substrate 110 including a core 112, an upper package substrate dielectric layer 114, and a lower package substrate dielectric layer 116 can be provided.

[0236] The bonding pad 114a on the package substrate may, for example, be formed on the uppermost dielectric layer of the dielectric layer 114 on the package substrate. The bonding pad 114a on the package substrate may be formed as a contact metal interconnect structure 114b. The bonding pad 114a on the package substrate may be formed by depositing a metal layer (e.g., copper, aluminum, or other suitable conductive material) on the upper surface of the dielectric layer 114 on the package substrate. Subsequently, the metal layer may be patterned by etching (e.g., by wet etching, dry etching, etc.) to form the bonding pad 114a on the package substrate. Other suitable metal layer materials and etching processes are also within the scope of this invention.

[0237] The under-package bonding pad 116a may be formed on, for example, the bottom dielectric layer of the under-package dielectric layer 116. The under-package bonding pad 116a may be formed as a contact metal interconnect structure 116b. The under-package bonding pad 116a may be formed in a manner similar to that used to form the bonding pad 114a on the package substrate (e.g., by depositing a metal layer, patterning a metal layer by etching, etc.).

[0238] After forming the upper bonding pad 114a and the lower bonding pad 116a of the package substrate, a surface roughening treatment (e.g., copper roughening (CZ) treatment) can be selectively performed. In the surface roughening treatment, the surfaces of the upper bonding pad 114a (e.g., copper surface) and the lower bonding pad 116a (e.g., copper surface) can be etched using an organic acid-based micro-etching solution to form an ultra-roughened surface (e.g., copper surface). The unique roughened copper surface morphology of the upper bonding pad 114a and the lower bonding pad 116a can contribute to achieving higher copper-resin adhesion.

[0239] Next, a passivation layer 110a on the upper bonding pad 114a and a passivation layer 110b on the lower bonding pad 116a of the package substrate can be formed, respectively. In at least one embodiment, the passivation layer 110a on the upper bonding pad 114a of the package substrate may include a solder resist layer (e.g., a polymer material), also referred to as a solder mask layer. The passivation layer 110a on the upper bonding pad 110a may also be referred to as the upper solder resist layer 110a, and the passivation layer 110b on the lower bonding pad 110b may also be referred to as the lower solder resist layer 110b.

[0240] A passivation layer 110a on the package substrate and a passivation layer 110b under the package substrate can be applied simultaneously. The passivation layers 110a and 110b can be applied, for example, as liquid photosensitive films. The liquid photosensitive film can be applied, for example, by screen printing or spraying onto the surface of the package substrate 110. The liquid photosensitive film can be applied onto the bonding pads 114a and 116a under the package substrate. Alternatively, the passivation layers 110a and 110b can be applied as dry film photosensitive films, which can be vacuum-laminated onto the surface of the package substrate 110 and onto the bonding pads 114a and 116a, respectively. The passivation layer 110a on the packaging substrate and the passivation layer 110b under the packaging substrate may be formed alternatively or additionally by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, lamination or other suitable deposition techniques.

[0241] The passivation layer 110a on the package substrate and the passivation layer 110b under the package substrate may be applied such that their thicknesses are slightly greater than the thicknesses of the bonding pad 114a on the package substrate and the bonding pad 116a under the package substrate, respectively. Alternatively, the passivation layer 110a on the package substrate and the passivation layer 110b under the package substrate may be applied such that their upper surfaces are substantially coplanar with the upper surfaces of the bonding pad 114a on the package substrate and the bonding pad 116a under the package substrate, respectively.

[0242] Next, an opening O can be formed in the passivation layer 110a on the packaging substrate. 110a This exposes the upper surface of the bonding pad 114a on the package substrate. An opening O can be formed in the passivation layer 110b under the package substrate. 110b This exposes the upper surface of the bonding pad 116a beneath the package substrate. Opening O 110a and opening O 110b It can be formed, for example, using a photolithography process. In at least one embodiment, the opening O... 110a and opening O 110b It can be formed in a separate lithography process.

[0243] Used to form an opening O 110a The lithography process (e.g., multiple processes) may include forming a patterned photoresist mask (not shown) on a passivation layer 110a on a package substrate, and etching (e.g., wet etching, dry etching, etc.) through openings in the photoresist mask to expose the upper surface of the passivation layer 110a on the package substrate. The photoresist mask may then be removed by ashing, dissolving the photoresist mask, or consuming the photoresist mask during the etching process.

[0244] Used to form an opening O 110bThe lithography process (e.g., multiple processes) may include forming a patterned photoresist mask (not shown) on a passivation layer 110b under the package substrate, and etching (e.g., wet etching, dry etching, etc.) through openings in the photoresist mask to expose the upper surface of the passivation layer 110b under the package substrate. The photoresist mask may then be removed by ashing, dissolving the photoresist mask, or consuming the photoresist mask during the etching process.

[0245] An opening O is formed in the passivation layer 110a on the packaging substrate. 110a An opening O is formed in the passivation layer 110b under the packaging substrate. 110b Subsequently, the passivation layer 110a (upper solder mask) on the package substrate and the passivation layer 110b (lower solder mask) on the package substrate can be cured by, for example, thermal curing or ultraviolet (UV) curing.

[0246] Figure 5B A vertical cross-sectional view of an intermediate structure according to one or more embodiments is illustrated, wherein a semiconductor module 120 may be mounted on a package substrate 110. The semiconductor module 120 may be mounted on the package substrate 110, for example, via a flip-chip bonding (FCB) process. The semiconductor die module 121 may be positioned above the package substrate 110, for example, via an electromechanical pick-and-place (PNP) machine. Next, a C4 bump 121 on the semiconductor die module 121 may be lowered onto a package substrate bonding pad 114a of the package substrate 110 and heated to cause the C4 bump 121 to collapse and bond to the package substrate bonding pad 114a.

[0247] Figure 5C This illustration shows a vertical cross-sectional view of an intermediate structure in which an underfill layer 119 may be formed on an encapsulation substrate 110 according to one or more embodiments. The underfill layer 119 may be formed of an epoxy-based polymer material. Figure 5C As shown, the package underfill layer 119 may be formed (e.g., implanted) into the package substrate 110 below and around the semiconductor module 120 and the C4 bump 121. The package underfill layer 119 may then be cured, for example, in an oven (for 60 to 120 minutes at a temperature of 120°C to 180°C) to give the package underfill layer 119 sufficient rigidity and mechanical strength.

[0248] Figure 5DThe illustration depicts a vertical cross-sectional view of a TIM layer 170 that may be attached (e.g., formed on) an intermediate structure of a back-side capacitor 210, according to one or more embodiments. Depending on the type of TIM layer 170 used, a thermally conductive adhesive may be applied to the upper surface of the back-side capacitor 210, or no thermally conductive adhesive may be applied. The material of the TIM layer 170 may be in the form of grease, gel, paste, etc., in which case the material may be dispensed onto a thermally conductive adhesive (if present) or onto the upper surface of the encapsulation module. If the TIM layer 170 is solid, the TIM layer 170 may be pressed onto the back-side capacitor 210 or onto an adhesive (if present).

[0249] Figure 5E A vertical cross-sectional view is illustrated of an intermediate structure according to one or more embodiments in which an adhesive layer 160 can be applied to a package substrate 110. The adhesive layer 160 can be applied to the package substrate 110 using a dispensing tool (e.g., an automated dispensing tool). The dispensing tool can distribute the adhesive layer 160 in a frame shape around the semiconductor module 120. Upon application, the adhesive layer 160 can be sufficiently rigid to form semi-solid beads on the surface of the package substrate 110. In at least one embodiment, the viscosity of each adhesive layer 160 upon application can be greater than 50,000 centipoise (cp). The shape of the semi-solid beads can remain substantially unchanged between the time of application by the dispensing tool and the time of subsequent attachment of the package cap 130. The position of the frame shape of the adhesive layer 160 can correspond to the position of the package cap pin 130a of the package cap 130. Pressing the package cap 130 onto the adhesive layer 160 can deform the adhesive layer 160.

[0250] Figure 5F A vertical cross-sectional view is illustrated of an intermediate structure according to one or more embodiments in which a package cover 130 may be attached to (e.g., mounted on) a package substrate 110. In at least one embodiment, a package substrate 110 having a semiconductor module 120 may be placed on a surface. The package cover 130 may then be positioned above the package substrate 110, for example, by an electromechanical pick-and-place (PNP) machine. Next, the package cover 130 may be lowered above the semiconductor module 120 and placed onto the package substrate 110. The package cover pins 130a of the package cover 130 may then be aligned with an adhesive layer 160 formed on the package substrate 110. The package cover 130 may then be pressed down onto the TIM layer 170 by applying pressure, such that the package cover pins 130a of the package cover 130 are attached to the package substrate 110 via the adhesive layer 160.

[0251] Next, the package cap 130 can be clamped onto the package substrate 110 for a period of time to allow the adhesive layer 160 to cure and form a strong bond between the package substrate 110 and the package cap 130. For example, the package cap 130 can be clamped onto the package substrate 110 using a thermal clamping module. The thermal clamping module can apply a uniform force to the upper surface of the package cap 130. In one or more embodiments, the thermal clamping module can apply pressure to the package cap 130.

[0252] Figure 5G A vertical cross-sectional view is illustrated of an intermediate structure of a BGA 180, comprising a plurality of solder balls 181, which may be formed on a package substrate 110 according to one or more embodiments. The plurality of solder balls 181 may be formed through an opening O in the passivation layer 110b beneath the package substrate. 110b Solder balls 181 are formed on bonding pads 116a under the package substrate. Solder balls 181 can be formed, for example, by an electroplating process. Solder balls 181 can be formed, for example, located below the package cover pins 130a and below the semiconductor module 120, and between the two. A plurality of solder balls 181 can constitute a BGA 180, which allows the package structure 100 to be securely mounted (e.g., via surface mount technology (SMT)) on a substrate, such as a printed circuit board, and electrically coupled to the substrate. The formation of solder balls 181 completes the fabrication of the package structure 100.

[0253] Figure 6 A flowchart illustrating a method for manufacturing a package structure 100 according to one or more embodiments is provided. Step 610 includes forming a semiconductor module including a back-side capacitor. Step 620 includes attaching the semiconductor module to a package substrate. Step 630 includes placing a thermal interface material (TIM) layer on the back-side capacitor. Step 640 includes attaching a package cap to the package substrate above the semiconductor module. Figure 6 The method shown is not intended to limit this method to a specific sequence of steps.

[0254] Figure 7A and Figure 7B This is a schematic diagram of a semiconductor module 120 having a first alternative configuration according to one or more embodiments. Figure 7A This is a vertical cross-sectional view of a semiconductor module 120 having a first alternative configuration according to one or more embodiments. Figure 7A As shown, the semiconductor module 120 with the first alternative configuration can be coupled with... Figures 1A to 1FThe semiconductor module 120 is generally similar to the first alternative configuration. However, in the first alternative configuration, the semiconductor module 120 may include a second semiconductor die 142 (e.g., an HBM die) on the opposite side of the first semiconductor die 141. The back-side capacitor 210 may also include a second capacitor 210B located on the opposite side of the semiconductor module 120 (e.g., in the x-direction). The semiconductor module 120 may also include a connection structure 230 and a distribution structure 220 located on the opposite side of the semiconductor module 120 (e.g., in the x-direction). With this configuration, the total capacitance of the back-side capacitor 210 may be greater than [a certain value]. Figures 1A to 1F The capacitance value in the back-side capacitor 210.

[0255] Figure 7B It is a top view of a semiconductor module 120 having a first alternative configuration according to one or more embodiments. Figure 7A The vertical section view in the middle is along Figure 7B As shown by line C-C' in the diagram. Figure 7B As shown, the semiconductor module 120 with the first alternative configuration may have a total of five capacitors, including one first capacitor 210A located above the first semiconductor die 141 and four second capacitors 210B located above the second semiconductor die 142. Figure 7B As further shown, the second capacitors 210B located on opposite sides of the first semiconductor die 141 can be configured as mirror images of each other. Furthermore, in the semiconductor module 120 with the first alternative configuration, each of the five capacitors can have a dedicated connection structure 230 and a distribution structure 220.

[0256] Figure 8A and Figure 8B This is a schematic diagram of a semiconductor module 120 having a second alternative configuration according to one or more embodiments. Figure 8A This is a vertical cross-sectional view of a semiconductor module 120 having a second alternative configuration according to one or more embodiments. Figure 8A As shown, the semiconductor module 120 with the second alternative configuration can be used with... Figure 7A and Figure 7B The semiconductor module 120 with the first alternative configuration is substantially similar.

[0257] However, in the second alternative configuration, the second capacitor 210B can be omitted from the back-side capacitor 210. The back-side capacitor 210 in the second alternative configuration may include a first capacitor 210A, which covers substantially the entirety of the semiconductor module 120. Figure 7A and Figure 7BSimilar to the first alternative configuration, the semiconductor module 120 with the second alternative configuration may also have a connection structure 230 and a distribution structure 220 on opposite sides of the semiconductor module 120 (e.g., in the x-direction). With this configuration, the total capacitance of the back-side capacitor 210 can be greater than [a certain value]. Figures 1A to 1F The back-side capacitor 210 and Figure 7A and Figure 7B The capacitance value in the back-side capacitor 210 of the first alternative configuration.

[0258] Figure 8B It is a top view of a semiconductor module 120 having a second alternative configuration according to one or more embodiments. Figure 8A The vertical cross-section view in the middle is along Figure 8B As shown by line D-D' in the diagram. Figure 8B As shown, the semiconductor module 120 with the second alternative structure may have four sets of first upper vias 211V and second upper vias 212V, located at the four corners of the first capacitor 210A. Furthermore, in the semiconductor module 120 with the second alternative structure, each set of first upper vias 211V and second upper vias 212V has a dedicated connection structure 230 and a distribution structure 220.

[0259] It should be noted that the semiconductor module 120 with the second alternative structure does not necessarily include four sets of first upper vias 211V and second upper vias 212V, but may include more or fewer sets of first upper vias 211V and second upper vias 212V. In at least one embodiment, the semiconductor module 120 with the second alternative configuration may include one or more sets of first upper vias 211V and second upper vias 212V. Furthermore, the size and location of the multiple sets of first upper vias 211V and second upper vias 212V may be different from those of the other sets. Figure 8B The dimensions and positions shown are different.

[0260] Reference Figures 1A to 8B The semiconductor module 120 may include an interposer 10, a plurality of semiconductor dies 140 located on the interposer 10, wherein each of the plurality of semiconductor dies 140 has a front surface facing the interposer 10 and a back surface 140a relative to the interposer 10, and a back capacitor 210 located on the back surface 140a of at least one of the plurality of semiconductor dies 140 and electrically coupled to the interposer 10.

[0261] In some embodiments, the semiconductor module 120 may further include an upper molding layer 127 surrounding a plurality of semiconductor dies 140, wherein a back-side capacitor 210 may be located on the upper molding layer 127.

[0262] In some embodiments, the back-side capacitor 210 may include a passivation film 201 located on the upper surface of the upper molding layer 127, and a pair of parallel metal films 211 / 212, 215 / 216 located in and separated by the passivation film 201.

[0263] In some embodiments, the passivation film 201 may include a plurality of passivation layers 201L1, 201L2, and 201L3, including a first passivation layer 201L1 located on the surface of the upper molding layer 127, wherein the first metal films 211 and 215 of the pair of parallel metal films 211 / 212 and 215 / 216 may be located on the first passivation layer 201L1, the second passivation layer 201L2 is located on the first passivation layer 201L1, wherein the second metal films 212 and 216 of the pair of parallel metal films 211 / 212 and 215 / 216 may be located on the second passivation layer 201L2, and the third passivation layer 201L3 is located on the second passivation layer 201L2 and the second metal films 212 and 216.

[0264] In some embodiments, the second passivation layer 201L2 may separate the first metal films 211, 215 from the second metal films 212, 216, and may include a charge separation layer, which may contain the electric field in the back-side capacitor 210.

[0265] In some embodiments, the semiconductor module 120 may further include a connection structure 230 configured to electrically couple the pair of parallel metal films 211 / 212, 215 / 216 and the interposer 10.

[0266] In some embodiments, the interposer 10 may include a distribution structure 220, which includes a plurality of distribution lines 221, 222, and a connection structure 230 may be configured to electrically connect the pair of parallel metal films 211 / 212, 215 / 216 to the plurality of distribution lines 221, 222.

[0267] In some embodiments, the connection structure 230 may include a pair of lower connection portions 221V / 13a1, 222V / 13a2 located in the interposer layer 10, which are connected to a plurality of distribution lines 221, 222 of the distribution structure 220; a pair of shaped through-holes (TMVs) 231, 232 located in the upper shaped layer 127, which are connected to the pair of lower connection portions 221V / 13a1, 222V / 13a2; and a pair of upper through-holes 211V / 212V, 215V / 216V located in the passivation film 201, which are connected to the pair of shaped through-holes 231, 232 and the pair of parallel metal films 211 / 212, 215 / 216.

[0268] In some embodiments, the pair of shaped vias 231, 232 may be located in the upper shaped layer 127 outside the plurality of semiconductor grains 140.

[0269] In some embodiments, the pair of parallel metal films 211 / 212, 215 / 216 may be located above one of the plurality of semiconductor grains 140.

[0270] In some embodiments, each of the pair of parallel metal films 211 / 212, 215 / 216 may include overhanging portions OD1 / OD2, OD5 / OD6 extending beyond one side of one of the plurality of semiconductor grains 140, and one of the upper vias 211V / 212V, 215V / 216V may be connected to the overhanging portions OD1 / OD2, OD5 / OD6.

[0271] In some embodiments, the area of ​​the back-side capacitor 210 may be 10% to 100% of the area of ​​the semiconductor module 120.

[0272] In some embodiments, the thickness of the back-side capacitor 210 may be between 0.1 μm and 10,000 μm.

[0273] Refer again Figures 1A to 8B The method of manufacturing semiconductor module 120 may include forming an interposer 10; attaching a plurality of semiconductor dies 140 to the interposer 10, wherein each of the plurality of semiconductor dies 140 has a front surface facing the interposer 10 and a back surface 140a relative to the interposer 10; forming an upper molding layer 127 around the plurality of semiconductor dies 140; and forming a back capacitor 210 on the back surface 140a of at least one of the plurality of semiconductor dies 140 and the upper molding layer 127, such that the back capacitor 210 can be electrically coupled to the interposer 10 through the upper molding layer 127.

[0274] In some embodiments, forming the back-side capacitor 210 may include forming a passivation film 201 on the upper surface of the upper molding layer 127, and forming a pair of parallel metal films 211 / 212, 215 / 216 in the passivation film 201, the pair of parallel metal films 211 / 212, 215 / 216 being separated by the passivation film 201.

[0275] In some embodiments, forming a passivation film 201 may include forming a first passivation layer 201L1 on the upper surface of the upper forming layer 127, wherein forming the pair of parallel metal films 211 / 212, 215 / 216 may include forming the first metal films 211 and 215 of the pair of parallel metal films 211 / 212, 215 / 216 on the first passivation layer 201L1, forming a second passivation layer 201L2 on the first passivation layer 201L1, wherein forming the pair of parallel metal films 211 / 212, 215 / 216 may include forming the second metal films 212 and 216 of the pair of parallel metal films 211 / 212, 215 / 216 on the second passivation layer 201L2, and forming a third passivation layer 201L3 on the second passivation layer 201L2 and the second metal films 212 and 216.

[0276] In some embodiments, the method may further include forming a connection structure 230 configured to electrically couple the pair of parallel metal films 211 / 212, 215 / 216 to the interposer 10.

[0277] In some embodiments, forming the interposer 10 may include forming a distribution structure 220 including multiple distribution lines 221, 222, and forming the connection structure 230 may include forming the connection structure 230 to electrically couple the pair of parallel metal films 211 / 212, 215 / 216 and the interposer 10. The pair of parallel metal films 211 / 212, 215 / 216 are coupled to the multiple distribution lines 221, 222 of the distribution structure 220.

[0278] In some embodiments, forming the connection structure 230 may include forming a pair of lower connection portions 221V / 13a1, 222V / 13a2 in the intermediate layer 10 and connecting them to a plurality of distribution lines 221, 222; forming a pair of shaped through-holes (TMVs) 231, 232 in the upper shaped layer 127 and connecting them to the pair of lower connection portions 221V / 13a1, 222V / 13a2; and forming a pair of upper through-holes 211V / 212V, 215V / 216V in the passivation film 201 and connecting them to the pair of shaped through-holes 231, 232 and the pair of parallel metal films 211 / 212, 215 / 216.

[0279] Refer again Figures 1A to 8BThe package structure 100 may include a package substrate 110; a semiconductor module 120 located on the package substrate 110, the semiconductor module 120 including an interposer 10, a plurality of semiconductor dies 140 located on the interposer 10, and a back capacitor 210 located on the plurality of semiconductor dies 140 and electrically connected to the interposer 10, wherein the back capacitor 210 may include a passivation film 201 and a pair of parallel metal films 211 / 212, 215 / 216 located in the passivation film 201; a thermal interface material 170 located on the back capacitor 210 and in contact with the passivation film 201, wherein the pair of parallel metal films 211 / 212, 215 / 216 may be located between the plurality of semiconductor dies 140 and the thermal interface material 170; and a package cap located on the thermal interface material 170 and attached to the package substrate 110.

[0280] The foregoing outlines the features of numerous embodiments, enabling those skilled in the art to better understand the various embodiments of this invention. Those skilled in the art will understand that other processes and structures can be easily designed or modified based on the embodiments of this invention to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the spirit and scope of this invention. Various changes, substitutions, and modifications can be made to the embodiments of this invention without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor module, characterized in that, include: One intermediary layer; Multiple semiconductor grains are located on the interposer layer, wherein each of the multiple semiconductor grains has a front surface facing the interposer layer and a back surface opposite the interposer layer. as well as A back-side capacitor is located on the back-side surface of at least one of the plurality of semiconductor chips and is electrically coupled to the interposer layer.

2. The semiconductor module as described in claim 1, characterized in that, It also includes an upper molding layer surrounding the plurality of semiconductor grains, wherein the back-side capacitor is located on the upper molding layer.

3. The semiconductor module as described in claim 2, characterized in that, The back-side capacitor includes: A passivation film is located on an upper surface of the upper molded layer; and A pair of parallel metal films are located within and separated by the passivation film.

4. The semiconductor module as described in claim 3, characterized in that, The passivation film includes multiple passivation layers, which include: A first passivation layer is located on the upper surface of the upper forming layer, wherein one of the pair of parallel metal films is located on the first passivation layer; A second passivation layer is located on the first passivation layer, wherein a second metal film of the pair of parallel metal films is located on the second passivation layer; and A third passivation layer is located on the second passivation layer and the second metal film.

5. The semiconductor module as described in claim 4, characterized in that, The second passivation layer separates the first metal film from the second metal film and includes a charge separation layer containing an electric field in the back capacitor.

6. The semiconductor module as described in claim 3, characterized in that, Also includes: A connection structure configured to electrically couple the pair of parallel metal films to an interposer, wherein the interposer includes a distribution structure comprising a plurality of distribution lines, and the connection structure is configured to electrically couple the pair of parallel metal films to the plurality of distribution lines.

7. The semiconductor module as described in claim 6, characterized in that, The connection structure includes: A pair of lower connecting portions, located within the intermediate layer and connected to the plurality of distribution lines of the distribution structure; A pair of molded through holes, located in the upper molded layer and connected to the pair of lower connecting portions; and A pair of through-holes are located in the passivation film and connected to the pair of shaped through-holes and the pair of parallel metal films.

8. The semiconductor module as described in claim 7, characterized in that, The pair of shaped vias are located in the upper shaped layer outside the plurality of semiconductor grains. The pair of parallel metal films are located above one of the plurality of semiconductor grains. Each of the pair of parallel metal films includes a hanging portion that extends beyond one side of the semiconductor grain. One of the pair of upper vias is connected to the hanging portion.

9. The semiconductor module as described in claim 2, characterized in that, The area of ​​the back-side capacitor is 10% to 100% of the area of ​​the semiconductor module.

10. A packaging structure, characterized in that, include: One packaging substrate; A semiconductor module, located on the package substrate, and comprising: One intermediary layer; Multiple semiconductor chips are located on the interposer layer; and A back-side capacitor is located on the plurality of semiconductor chips and electrically coupled to the interposer layer, wherein the back-side capacitor includes a passivation film and a pair of parallel metal films located in the passivation film. A thermal interface material is located on the back-side capacitor and in contact with the passivation film, wherein the pair of parallel metal films are located between the plurality of semiconductor grains and the thermal interface material; and A cover is located on the thermal interface material and connected to the encapsulation substrate.

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