Semiconductor package

Abstract

The present disclosure provides semiconductor packages. A semiconductor package includes a leadframe, a first chip, a second chip, a first clip, a second clip, a first wire, and a second wire. The leadframe includes a first die pad, a second die pad, a first lead, a second lead, and a third lead. The second die pad is electrically isolated from the first die pad. The first lead, the second lead, and the third lead are electrically isolated from the first die pad and the second die pad, wherein the second die pad and the plurality of leads surround the first die pad. The first chip is attached to the first die pad. The second chip is attached to the second die pad. The first clip connects a first electrode of the first chip and the second die pad. The second clip connects a first electrode of the second chip and the first lead. The first wire connects a second electrode of the first chip to the second lead. The second wire connects a second electrode of the second chip to the third lead.

Description

Technical Field

[0001] This utility model relates to semiconductor packaging, and more specifically, to power semiconductor packaging with a half-bridge circuit structure. Background Technology

[0002] A half-bridge circuit is a common power conversion circuit used for voltage conversion, motor drives, and more. It typically consists of two switches (usually MOSFETs or IGBTs) connected in series with a DC power supply. In this architecture, increasing the switching frequency of the control transistors improves the integrity of the power output signal, reduces losses during the conversion process, and provides better dynamic response for controlling the output voltage / current.

[0003] As the frequency of control signals increases, traditional half-bridge circuit modules encounter the following problems, including: longer gate drive loops are prone to significant parasitic effects (such as parasitic capacitance and parasitic inductance); longer high-frequency power supply loops cause the input capacitors to be placed far from the input voltage terminal and the ground terminal, reducing overall efficiency; if multiple individually packaged components are combined into a power module, it will occupy a large area on the circuit board, making the utilization efficiency of the circuit board area worse; and high current signals (such as power signals) and high-frequency control signals are prone to signal interference, making the gate drive signal unstable.

[0004] Therefore, existing power semiconductor packages with half-bridge circuit structures need further improvement to achieve more ideal high power and low loss, so as to be suitable for fast switching applications. Utility Model Content

[0005] Embodiments of this disclosure relate to a semiconductor package. The semiconductor package includes: a lead frame, a first chip, a second chip, a first clamp, a second clamp, a first bonding wire, and a second bonding wire. The lead frame includes: a first chip substrate, a second chip substrate, a first lead, a second lead, and a third lead. The second chip substrate is electrically isolated from the first chip substrate. The first lead, the second lead, and the third lead are electrically isolated from the first chip substrate and the second chip substrate, wherein the second chip substrate and the plurality of leads surround the first chip substrate. The first chip is attached to the first chip substrate. The second chip is attached to the second chip substrate. The first clamp connects a first electrode of the first chip to the second chip substrate. The second clamp connects the first electrode of the second chip to the first lead. The first bonding wire connects a second electrode of the first chip to the second lead. The second bonding wire connects a second electrode of the second chip to the third lead.

[0006] Embodiments of this disclosure relate to a semiconductor package. The semiconductor package includes: a lead frame, a first chip, a second chip, a first clamp, a second clamp, a first bonding wire, a second bonding wire, and a molded package. The lead frame includes: a first chip substrate, a second chip substrate, a first lead, a second lead, and a third lead. The second chip substrate is electrically isolated from the first chip substrate. The first lead is electrically isolated from both the first chip substrate and the second chip substrate. The second lead and the third lead are both electrically isolated from the first chip substrate, the second chip substrate, and the first lead. The first chip is attached to the first chip substrate, and a first electrode of the first chip is connected to the first chip substrate. The second chip is attached to the second chip substrate, and a first electrode of the second chip is connected to the second chip substrate. The first clamp connects the second electrode of the first chip to the second chip substrate. The second clamp connects the second electrode of the second chip to the first lead. The first bonding wire connects the third electrode of the first chip to the second lead. The second bonding wire connects the third electrode of the second chip to the third lead. The molding package encapsulates the first chip, the second chip, the first clamp, the second clamp, and the lead frame.

[0007] Embodiments of this disclosure relate to a semiconductor package. The semiconductor package includes: a lead frame, a first chip, a second chip, a first clamp, a second clamp, a first bonding wire, a second bonding wire, and a molded package. The lead frame includes: a chip substrate, a first lead, a second lead, a third lead, and a fourth lead. The first lead, the second lead, the third lead, and the fourth lead surround the chip substrate, and the chip substrate, the first lead, the second lead, the third lead, and the fourth lead are electrically isolated from each other. The first chip is attached to the chip substrate, wherein the source of the first chip is connected to the chip substrate. The second chip is attached to the chip substrate, wherein the drain of the second chip is connected to the chip substrate. The first clamp connects the drain of the first chip and the first lead. The second clamp connects the source of the second chip and the second lead. The first bonding wire connects the gate of the first chip to the third lead. The second bonding wire connects the gate of the second chip to the fourth lead. The molding package encapsulates the first chip, the second chip, the first clamp, the second clamp, and the lead frame. Attached Figure Description

[0008] The various embodiments of this disclosure can be best understood when read in conjunction with the accompanying drawings and the following detailed description. It should be noted that the structures are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various structures may be arbitrarily enlarged or reduced.

[0009] Figure 1 The diagram shown is a circuit diagram of a half-bridge circuit according to certain embodiments of this case;

[0010] Figure 2 The image shown is a perspective view of a semiconductor package according to a first embodiment of this invention;

[0011] Figure 3 The image shown is a top view of a semiconductor package according to a first embodiment of this invention;

[0012] Figure 4 The image shown is a bottom view of a semiconductor package according to the first embodiment of this invention;

[0013] Figure 5 The image shown is a top view of a semiconductor package according to a second embodiment of this invention;

[0014] Figure 6 The image shown is a bottom view of a semiconductor package according to a second embodiment of this invention;

[0015] Figure 7 The image shown is a top view of a semiconductor package according to a third embodiment of this invention;

[0016] Figure 8 The image shown is a bottom view of a semiconductor package according to a third embodiment of this invention;

[0017] Identical or similar components are designated using the same reference numerals in the drawings and detailed description. Several embodiments of this disclosure will be readily understood from the following detailed description in conjunction with the accompanying drawings. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below. Of course, these are merely examples and are not intended to be limiting. In this disclosure, references to forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Embodiments of this disclosure are discussed in detail below. However, it should be understood that this disclosure provides many applicable concepts that can be embodied in a wide variety of specific environments. The specific embodiments discussed are merely illustrative and do not limit the scope of this disclosure.

[0020] This disclosure provides a semiconductor package. In this semiconductor package, by arranging two chip substrates and internal leads in a surrounding manner and forming a half-bridge circuit structure with appropriate electrical connections, the semiconductor package of this disclosure has a shorter gate drive loop and a shorter power supply loop. Furthermore, this disclosure separates the power supply loop and the control signal loop to avoid mutual interference, thus making it suitable for high-frequency control signals. In addition, the integrated semiconductor package of this disclosure can save board space compared to traditional circuit modules composed of discrete components on a circuit board.

[0021] Figure 1 The diagram shown is a circuit diagram of a half-bridge circuit 90 according to certain embodiments of this invention. Specifically, the half-bridge circuit 90 may include a first transistor 91, a second transistor 92, an input capacitor 93, an output capacitor 94, and an inductor 95. The first transistor 91 includes a drain 911, a gate 912, and a source 913. The second transistor 92 includes a drain 921, a gate 922, and a source 923. In some embodiments, the first transistor 91 and the second transistor 92 may be power transistors, such as power MOSFETs. In some embodiments, the first transistor 91 and the second transistor 92 may have the same doping type, such as an N-type transistor or a P-type transistor.

[0022] First transistor 91 and second transistor 92 are connected in series. In some embodiments, the source 913 of the first transistor 91 may be electrically connected to the drain 921 of the second transistor 92. The connection point between the source 913 of the first transistor 91 and the drain 921 of the second transistor 92 may be referred to as node N1 (switching node). In some embodiments, the drain 911 of the first transistor 91 is electrically connected to the positive input terminal 901 of the half-bridge circuit 90, and the source 913 of the first transistor 91 is electrically connected to the positive output terminal 903 of the half-bridge circuit 90 through node N1. The drain 921 of the second transistor 92 is electrically connected to the positive output terminal 903 of the half-bridge circuit 90 through node N1, and the source 923 of the second transistor 92 is electrically connected to the negative input terminal 902 and the negative output terminal 904 of the half-bridge circuit 90. In some embodiments, the negative input terminal 902 and the negative output terminal 904 are configured to be grounded.

[0023] In some embodiments, an input capacitor 93 is disposed between the positive input terminal 901 and the negative input terminal 902. The voltage across the input capacitor 93 corresponds to the input voltage Vin between the positive input terminal 901 and the negative input terminal 902. In some embodiments, an output capacitor 94 is disposed between the positive output terminal 903 and the negative output terminal 904. One end of the output capacitor 94 is electrically connected to the positive output terminal 903 through node N2. The voltage across the output capacitor 94 corresponds to the output voltage Vo between the positive output terminal 903 and the negative output terminal 904. In some embodiments, an inductor 95 is disposed between node N1 and the positive output terminal 903. In some embodiments, the inductor 95 is disposed between node N1 and node N2. The inductor 95 can be a load component.

[0024] In some embodiments, the first transistor 91 is referred to as the high-side transistor or high-side switch, and the second transistor 92 is referred to as the low-side transistor or low-side switch. Different power supply loops can be formed by controlling the on / off states of the first transistor 91 and the second transistor 92. The on / off state of the first transistor 91 is determined by a drive signal supplied to the gate 912, and the on / off state of the second transistor 92 is determined by a drive signal supplied to the gate 922. In this embodiment, a power supply loop refers to a loop formed by current flowing through the source and drain of a transistor. For example, when the first transistor 91 is turned on and the second transistor 92 is turned off, the current can flow along the first power supply circuit through the input capacitor 93, the first transistor 91, node N1, inductor 95, and output capacitor 94; when the first transistor 91 is turned off and the second transistor 92 is turned on, the current can flow along the second power supply circuit through the second transistor 92, node N1, inductor 95, and output capacitor 94; when the first transistor 91 is turned on and the second transistor 92 is turned on, the current can flow along the third power supply circuit through the input capacitor 93, the first transistor 91, node N1, and second transistor 92.

[0025] Figures 2 to 4 This application is based on Figure 1 The first embodiment of the single semiconductor package solution provided by the half-bridge circuit 90. Figure 2 The image shown is a 3D view of semiconductor package 10. Figure 3 The image shown is a top view of the semiconductor package 10. Figure 4The diagram shows a bottom view of a semiconductor package 10. In a first embodiment, the semiconductor package 10 may include a lead frame 200. The lead frame 200 forms a support structure and an electrical connection structure for the semiconductor package 10. In some embodiments, the lead frame 200 includes a first chip substrate 210, a second chip substrate 220, a first lead 230, a second lead 240, and a third lead 250. The first chip substrate 210 is used to mount a first chip 310. The second chip substrate 220 is used to mount a second chip 320. The first chip substrate 210 and the second chip substrate 220 are electrically isolated. In some embodiments, any two of the first lead 230, the second lead 240, the third lead 250, the first chip substrate 210, and the second chip substrate 220 are electrically isolated from each other. In some embodiments, the first chip substrate 210, the second chip substrate 220, the first lead 230, the second lead 240, and the third lead 250 may extend to the side of the semiconductor package 10 and form a plurality of pins for receiving external electrical signals. In some embodiments, the first chip substrate 210, the second chip substrate 220, the first lead 230, the second lead 240, and the third lead 250 may be made of copper or other metals.

[0026] In some embodiments, the second chip base 220, the first lead 230, the second lead 240, and the third lead 250 are configured to surround the first chip base 210. In other words, one or more sides of the second chip base 220 may be surrounded by the second chip base 220, the first lead 230, the second lead 240, and the third lead 250. In some embodiments, the semiconductor package 10 includes a first chip 310, a second chip 320, a first clamp 410, a second clamp 420, a first bonding wire 440, and a second bonding wire 450. The first chip 310 is attached to the first chip base 210. The second chip 320 is attached to the second chip base 220.

[0027] In some embodiments, the first clamp 410 and the second clamp 420 are metal strips, such as copper strips. Specifically, the first clamp 410 may include a pair of spaced-apart first support portions 412A and 412B and a first raised portion 414 connecting the pair of first support portions 412A and 412B. One of the first support portions 412A contacts a first electrode of the first chip 310, and the first support portion 412B contacts a second chip base 220. In some embodiments, the second clamp 420 includes a pair of spaced-apart second support portions 422A and 422B and a second raised portion 424 connecting the second support portions 422A and 422B. The second support portion 422B contacts a first electrode of the second chip 320, and the second support portion 422A contacts a first lead 230. In some embodiments, the first bonding wire 440 and the second bonding wire 450 are metal wires, such as copper wires. In some embodiments, the first clamp 410 or the second clamp 420 may be replaced by the bonding wires. In some embodiments, the first bonding line 440 or the second bonding line 450 may be replaced by the metal clamp.

[0028] The first chip 310 in this embodiment can correspond to Figure 1 The second transistor 92, and the second chip 320 can correspond to Figure 1 The first transistor 91. In some embodiments, the first clamp 410 connects the first electrode of the first chip 310 and the second chip base 220, wherein the first electrode of the first chip 310 may be the drain electrode. That is, the first electrode of the first chip 310 may correspond to Figure 1 The drain electrode 921 of the second transistor 92. In some embodiments, the second clamp 420 connects the first electrode of the second chip 320 and the first lead 230, wherein the first electrode of the second chip 320 may be the drain electrode. That is, the first electrode of the second chip 320 may correspond to the drain electrode. Figure 1 The drain electrode 911 of the first transistor 91. In some embodiments, the first bonding line 440 connects the second electrode of the first chip 310 to the second lead 240, wherein the second electrode of the first chip 310 may be the gate electrode. That is, the second electrode of the first chip 310 may correspond to the drain electrode 911 of the first transistor 91. Figure 1 The gate electrode 922 of the second transistor 92. In some embodiments, the second bonding line 450 connects the second electrode of the second chip 320 to the third lead 250, wherein the second electrode of the second chip 320 may be the gate electrode. That is, the second electrode of the second chip 320 may correspond to Figure 1 The gate electrode 912 of the first transistor 91.

[0029] In some embodiments, the semiconductor package 10 further includes a third clamp 430A and a fourth clamp 430B. In some embodiments, the third clamp 430A and the fourth clamp 430B have substantially the same structure and function as the first clamp 410 or the second clamp 420. The third clamp 430A connects the third electrode of the first chip 310 to the first chip base 210, wherein the third electrode of the first chip 310 may be a source electrode. That is, the third electrode of the first chip 310 may correspond to... Figure 1 The source electrode 923 of the second transistor 92. The fourth clamp 430B connects the third electrode of the second chip 320 to the second chip base 220, wherein the third electrode of the second chip 320 can be the source electrode. That is, the third electrode of the second chip 320 can correspond to Figure 1 The source electrode 913 of the first transistor 91.

[0030] In some embodiments, the semiconductor package 10 further includes a first capacitor 330. The first capacitor 330 connects the first chip substrate 210 to a lead connected to the second clamp 420. That is, the first capacitor 330 connects the first chip substrate 210 and the first lead 230. In some embodiments, the first capacitor 330 may serve as an input capacitor. The first capacitor 330 may correspond to Figure 1 The input capacitor 93. The first chip base 210 may extend and connect to the positive input pin of the semiconductor package 10, the pin corresponding to... Figure 1 The positive input terminal 901. The first pin 230 can extend and connect to the negative input pin of the semiconductor package 10, which can correspond to... Figure 1 The negative input terminal is 902.

[0031] The second chip base 210 can extend and connect to the positive output pin of the semiconductor package 10, the positive output pin corresponding to... Figure 1 The positive output terminal 903. The first pin 230 can extend and connect to the negative output pin of the semiconductor package 10, the negative output terminal corresponding to... Figure 1 The negative output terminal 904. In some embodiments, the semiconductor package 10 further includes a molding package 500. For example, the molding package 500 may be a thermosetting epoxy molding compound used to protect the components in the semiconductor package 10 from moisture penetration into the semiconductor package 10, and has good thermal stability. In some embodiments, the molding package 500 encapsulates a first chip 310, a second chip 320, a first clamp 410, a second clamp 420, and a lead frame 200.

[0032] Based on the above description, by designing the lead frame 200 of the semiconductor package 10 to have a first chip base 210, a second chip base 220, and the plurality of leads 230, 240, and 250, and by using appropriate electrical connection structures (e.g., first clamp 410, second clamp 420, third clamps 430A and 430B, first bonding wire 440, second bonding wire 450, etc.), the lead frame 200 of the semiconductor package 10 can be used to connect leads such as leads 210, second chip base 220, and the plurality of leads 230, 240, and 250. Figure 1 The half-bridge circuit 90 shown is implemented as a semiconductor package 10.

[0033] Furthermore, in some embodiments, the first chip substrate 210 has a first side S1, a second side S2, and a third side S3, wherein the first side S1 and the third side S3 are opposite each other, and both the first side S1 and the third side S3 are adjacent to the second side S2. In some embodiments, the second chip substrate 220 surrounds at least the first side S1 and the second side S2 of the first chip substrate 210. In some embodiments, the first lead 230 is located on the first side S1 of the first chip substrate 210. In some embodiments, the second lead 240 is located on the third side S3 of the first chip substrate 210. In some embodiments, the third lead 250 is located on the second side S2 of the first chip substrate 210.

[0034] In some embodiments, the first side S1 of the first chip base 210 faces the second chip base 220, the second chip 320, and the first lead 230. In some embodiments, the second side S2 of the first chip base 210 faces the third lead 250. In some embodiments, the third side S3 of the first chip base 210 faces the second lead 240.

[0035] In some embodiments, the semiconductor package 10 further includes a fourth lead 260. The fourth lead 260 is a Kelvin source lead and is adjacent to the third side S3 of the first chip substrate 210, and is electrically connected to the first chip substrate 210 via a third bonding wire 460. In some embodiments, one side 232 of the first lead 230 is substantially aligned with one side 216 of the first chip substrate 210 and one side 262 of the fourth lead 260.

[0036] In some embodiments, when viewed from a top view (e.g.) Figure 3As shown, the semiconductor package 10 has a rectangular outer contour. In some embodiments, the second chip substrate 220 includes a second body 222, a terminal portion 226, and a connection portion 224 connecting the second body 222 and the terminal portion 226. In some embodiments, the connection portion 224 and the terminal portion 226 of the second chip substrate 220 are located between the first chip substrate 210 and the third lead 250. In some embodiments, the first chip substrate 210, the second chip substrate 220, and the first lead 230 are arranged in a ring. Specifically, the first chip substrate 210, the second chip substrate 220, and the first lead 230 may be arranged in a ring in a clockwise direction. In this embodiment, the gate drive circuit refers to the circuit formed by the gate driver outside the semiconductor package 10 providing gate drive signals to the gates of transistors 310 and 320 through leads 250 and 240 inside the semiconductor package 10. The control signal circuit refers to the circuit formed by a microcontroller unit outside the semiconductor package 10 providing control signals to the gate driver outside the semiconductor package 10. In other words, the entire control signal circuit is located outside the semiconductor package 10, thus better avoiding mutual interference between the power supply circuit and the control signal circuit. Specifically, the chips 310 and 320 of the semiconductor package 10 in this embodiment have a lateral structure, that is, the source, drain, and gate of chips 310 and 320 are all located on the upper surface of chips 310 and 320. Furthermore, the second chip base 220 and multiple leads 230, 240, and 250 in the lead frame 200 surround the first chip base 210 in the lead frame 200, thereby minimizing the power supply circuit and the gate drive circuit, and achieving the effect of reducing parasitic capacitance in the circuit. Furthermore, this ring arrangement effectively reduces mutual interference between the current signal and the gate drive signal because it reduces the overlap area between them. Additionally, the aforementioned semiconductor package integrates multiple components into a single package, increasing signal density while minimizing signal interference.

[0037] refer to Figure 2 and Figure 4 In some embodiments, such as Figures 2 to 4 As shown, the bottom surface of the first chip substrate 210 can be flush with the bottom surface of the semiconductor package 10 and exposed from the bottom side of the semiconductor package 10. In some embodiments, the bottom surface of the first chip substrate 210 is substantially flush with the bottom surface of the molded package 500.

[0038] In some embodiments, the thickness T3 of the connecting portion 224 of the second chip substrate 220 is less than the thickness T2 of the second body 222 of the second chip substrate 220, and less than the thickness T4 of the terminal portion 226 of the second chip substrate 220. In some embodiments, the thickness T1 of the first chip substrate 210 is substantially the same as the thickness T2 of the second body 222 of the second chip substrate 220. Figures 2 to 4As shown, the bottom surface of the second body 222 of the second chip base 220 can be flush with the bottom surface of the semiconductor package 10 and exposed from the bottom side of the semiconductor package 10. In contrast, the bottom surface of the connector 224 can be disposed on the molded package 500 and is not exposed from the bottom side of the semiconductor package 10. In some embodiments, the top surfaces of the second body 222, the terminal portion 226, and the connector 224 are substantially flush, the bottom surfaces of the second body 222, the terminal portion 226, and the molded package 500 are substantially flush, and the molded package 500 covers the bottom surface of the connector 224. In some embodiments, the thickness of the connector 224 is half the thickness of the second body 222 and the terminal portion 226.

[0039] In some embodiments, the bottom surface of the first lead 230 and a portion of its body is substantially flush with the bottom surface of the molded package 500. The bottom surface of the second lead 240 and a portion of its body is substantially flush with the bottom surface of the molded package 500. The bottom surface of the third lead 250's pin portion is substantially flush with the bottom surface of the molded package 500. The bottom surface of the fourth lead 260's pin and a portion of its body is substantially flush with the bottom surface of the molded package 500. By exposing a portion of the leads to the bottom surface of the semiconductor package, the overall heat dissipation area can be increased.

[0040] In some embodiments, the first chip 310 may have a length direction LD1, and the second chip 320 may have a length direction LD2. In some embodiments, the first chip 310 on the first chip base 210 is configured such that the length direction LD1 is approximately along a first direction (Y direction), and the second chip 320 on the second chip base 220 is configured such that the length direction is approximately along a second direction (X direction), wherein the first direction (Y direction) and the second direction (X direction) are approximately perpendicular to each other. That is, the length direction LD1 of the first chip 310 is approximately perpendicular to the length direction LD2 of the second chip 320.

[0041] Figures 5 to 6 This application is based on Figure 1 The second embodiment of the single semiconductor package solution provided by the half-bridge circuit 90. Figure 5 The image shown is a top view of semiconductor package 10A; Figure 6The image shown is a bottom view of semiconductor package 10B. In a second embodiment, semiconductor package 10A includes a lead frame 200A, a first chip 310, a second chip 320, a first clamp 410, a second clamp 420, a first bonding wire 440, a second bonding wire 450, and a molded package 500. Lead frame 200A includes a first chip substrate 210, a second chip substrate 220, a first lead 230, a second lead 240, and a third lead 250. The second chip substrate 220 is electrically isolated from the first chip substrate 210. The first lead 230 is electrically isolated from the first chip substrate 210 and the second chip substrate 220. The second lead 240 and the third lead 250 are both electrically isolated from the first chip substrate 210, the second chip substrate 220, and the first lead 230. The first chip 310 is attached to the first chip substrate 210, and a first electrode of the first chip 310 is connected to the first chip substrate 210. A second chip 320 is attached to a second chip base 220, and a first electrode of the second chip 320 is connected to the second chip base 220. A first clamp 410 connects the second electrode of the first chip 310 to the second chip base 220. A second clamp 420 connects the second electrode of the second chip 320 to a first lead 230. A first bonding wire 440 connects the third electrode of the first chip 310 to the second lead 240. A second bonding wire 450 connects the third electrode of the second chip 320 to the third lead 250. A molded package 500 encapsulates the first chip 310, the second chip 320, the first clamp 410, the second clamp 420, and the lead frame 200A.

[0042] In some embodiments, the first electrode of the first chip 310 may be a source electrode. That is, the first electrode of the first chip 310 may correspond to... Figure 1 The source electrode 923 of the second transistor 92. The second electrode of the first chip 310 can be the drain electrode. That is, the second electrode of the first chip 310 can correspond to the source electrode 923 of the second transistor 92. Figure 1 The drain electrode 921 of the second transistor 92. The third electrode of the first chip 310 may be the gate electrode. That is, the third electrode of the first chip 310 may correspond to... Figure 1 The gate electrode 922 of the second transistor 92. In some embodiments, the first electrode of the second chip 320 may be the drain electrode. That is, the first electrode of the second chip 320 may correspond to the gate electrode 922 of the second transistor 92. Figure 1 The source electrode 913 of the first transistor 91. The second electrode of the second chip 320 can be the drain electrode. That is, the second electrode of the second chip 320 can correspond to the source electrode 913 of the first transistor 91. Figure 1 The drain electrode 911 of the first transistor 91. The third electrode of the second chip 320 may be the gate electrode. That is, the third electrode of the second chip 320 may correspond to... Figure 1The gate electrode 912 of the first transistor 91. The second lead 240 and the third lead 250 are electrically connected to the gate electrodes of the first chip 310 and the second chip 320, respectively. The pins connected to the second lead 240 and the third lead 250 can be called gate pins.

[0043] In some embodiments, the first chip substrate 210 has a first side S1 and a second side S2 adjacent to the first side S1, and the second chip substrate 220 and the first lead 230 are placed along the first side S1 of the first chip substrate 210. In some embodiments, the second lead 240 and the third lead 250 are placed on the second side S2 of the first chip substrate 210. In some embodiments, when viewed from a top view (e.g.) Figure 5 The semiconductor package 10A has a rectangular outer contour, and the first side S1 and the second side S2 of the first chip base 210 are substantially perpendicular to each other. In some embodiments, the first side S1 of the first chip base 210 faces the first lead 230 and the second chip base 220, and the second side S2 of the first chip base 210 faces the second lead 240 and the third lead 250.

[0044] In some embodiments, the first clamp 410 includes a pair of spaced-apart first support portions 412A and 412B and a first raised portion 414 connecting the first support portions 412A and 412B. The first support portion 412A contacts the second electrode of the first chip 310, and the first support portion 412B contacts the second chip base 220. In some embodiments, the second clamp 420 includes a pair of spaced-apart second support portions 422A and 422B and a second raised portion 424 connecting the second support portions 422A and 422B. The first support portion 422A contacts the second electrode of the second chip 320, and the first support portion 422B contacts the first lead 230. The structure of the support portions and raised portions of the first clamp 410 and the second clamp 420 in this embodiment is basically the same as that in the first embodiment. The detailed three-dimensional structure is as follows: Figure 2 As shown, repeated illustrations and descriptions are omitted here.

[0045] In some embodiments, the semiconductor package 10A further includes a capacitor 330. The capacitor 330 connects the first chip substrate 210 to the first lead 230. The capacitor 330 can serve as an input capacitor for the semiconductor package 10A, capable of filtering input signals. The capacitor 330 in this embodiment may correspond to... Figure 1 The input capacitor 93 is shown. Additionally... Figure 1 The output capacitor 94 shown is optional; in this embodiment, the semiconductor package 10A does not include an additional output capacitor.

[0046] In some embodiments, the first chip 310 may have a length direction LD1, and the second chip 320 may have a length direction LD2. In some embodiments, the first chip 310 on the first chip base 210 is configured such that the length direction LD1 is approximately along a first direction (Y direction), and the second chip 320 on the second chip base 220 is configured such that the length direction is approximately along a second direction (X direction), wherein the first direction (Y direction) and the second direction (X direction) are approximately perpendicular to each other. That is, the length direction LD1 of the first chip 310 is approximately perpendicular to the length direction LD2 of the second chip 320.

[0047] like Figure 6 As shown, the bottom surfaces of the first chip base 210, the second chip base 220, and the first lead 230 can be substantially flush with the bottom surface of the molded package 500. In some embodiments, the bottom surfaces of the pin portions of the second lead 240 and the third lead 250 can be substantially flush with the bottom surface of the molded package 500, and the main body portions of the second lead 240 and the third lead 250 can be disposed in the molded package 500. In some embodiments, the thickness of the pin portions of the second lead 240 and the third lead 250 is greater than the thickness of the main body portions. In particular, the chips 310 and 320 of the semiconductor package 10A of this embodiment have a vertical structure, that is, the source of the chips 310 and 320 is located on one side of the chip, and the drain is located on the other side of the chip, so that current passes through the chip in a vertical direction. Furthermore, the first chip base 210, the second chip base 220, and the multiple leads 230, 240, and 250 in the lead frame 200 are arranged in a ring shape to minimize the power supply loop and the gate drive loop, thereby reducing parasitic capacitance in the circuit. Additionally, this ring arrangement effectively reduces mutual interference between the current signal and the gate drive signal because the overlap area between them is reduced.

[0048] Figure 7 The image shown is a top view of a semiconductor package according to a third embodiment of this invention; Figure 8The diagram shows a bottom view of a semiconductor package according to a third embodiment of this invention. In the third embodiment, the semiconductor package 10B includes: a lead frame 200B, a first chip 310, a second chip 320, a first clamp 420, a second clamp 410, a first bonding wire 440, a second bonding wire 450, and a molded package 500. The lead frame 200A includes a chip base 210', a first lead 230', a second lead 220', a third lead 240', and a fourth lead 250'. The first lead 230', the second lead 220', the third lead 240', and the fourth lead 250' surround the chip base 210', and the chip base 210', the first lead 230', the second lead 220', the third lead 240', and the fourth lead 250' are electrically isolated from each other. A first chip 310 is attached to a chip base 210', with the source of the first chip 310 connected to the chip base 210'. A second chip 320 is attached to the chip base 210', with the drain of the second chip 320 connected to the chip base 210'. A first clamp 420 connects the drain of the first chip 310 to a first lead 230'. A second clamp 410 connects the source of the second chip 320 to a second lead 220'. A first bonding wire 440 connects the gate of the first chip 310 to a third lead 240'. A second bonding wire 450 connects the gate of the second chip 320 to a fourth lead 250'. A molded package 500 encapsulates the first chip 310, the second chip 320, the first clamp 420, the second clamp 410, and the lead frame 200B.

[0049] In some embodiments, the chip substrate 210' has a first side S1, a second side S2, and a third side S3, wherein the first side S1 and the third side S3 are opposite each other and both the first side S1 and the third side S3 are adjacent to the second side S2. In some embodiments, a first lead 230' is located on the first side S1 of the chip substrate 210', a second lead 220' is located on the second side S2 of the chip substrate 210', a third lead 240' is located on the second side S2 of the chip substrate 210', and a fourth lead 250' is located on the third side S3 of the chip substrate 210'. In some embodiments, the first side S1 of the chip substrate 210' faces the first lead 230', the second side S2 of the chip substrate 210' faces the second lead 220' and the third lead 240', and the third side S3 of the chip substrate 210' faces the fourth lead 250'. That is, the three sides S1, S2 and S3 of the chip base 210' are surrounded by the first lead 230', the second lead 220', the third lead 240' and the fourth lead 250'.

[0050] In some embodiments, when viewed from a top view, the chip substrate 210', the first lead 230', the second lead 220', and the third lead 240' are arranged to form a rectangular outer contour. In some embodiments, when viewed from a top view, the chip substrate 210', the first lead 230', the second lead 220', the third lead 240', and the fourth lead 250' are arranged to form a rectangular outer contour. According to the above configuration, when viewed from a top view, the semiconductor package 10B has a rectangular outer contour. In some embodiments, the length of the fourth lead 250' in the first direction (X direction) is greater than the lengths of the chip substrate 210' and the third lead 240' in the first direction (X direction). For example, one side of the fourth lead 250' is approximately aligned with the outer side of the chip substrate 210', and the other side of the fourth lead 250' is approximately aligned with the outer side of the third lead 240'.

[0051] In some embodiments, the first clamp 420 includes a pair of spaced-apart first support portions 422A and 422B and a first raised portion 424 connecting the first support portions 422A and 422B. The first support portion 422A contacts the drain of the first chip 310, and the first support portion 422B contacts the first lead 230'. In some embodiments, the second clamp 410 includes a pair of spaced-apart second support portions 412A and 412B and a second raised portion 414 connecting the second support portions 412A and 412B. The second support portion 412A contacts the source of the second chip 320, and the second support portion 412B contacts the second lead 220'. The structure of the support portions and raised portions of the first clamp 420 and the second clamp 410 in this embodiment is basically the same as that in the first embodiment. The detailed three-dimensional structure is as follows: Figure 2 As shown, repeated illustrations and descriptions are omitted here.

[0052] In some embodiments, the semiconductor package 10B further includes a capacitor 330, wherein the capacitor 330 connects the second lead 220' to the first lead 230'. In some embodiments, the first chip 310 may have a length direction LD1, and the second chip 320 may have a length direction LD2. In some embodiments, the first chip 310 on the first chip base 210' is configured such that the length direction LD1 is generally along a first direction (Y direction), and the second chip 320 on the second chip base 220' is configured such that the length direction is generally along a second direction (X direction), wherein the first direction (Y direction) and the second direction (X direction) are generally perpendicular to each other. That is, the length direction LD1 of the first chip 310 is generally perpendicular to the length direction LD2 of the second chip 320.

[0053] like Figure 8As shown, the bottom surface of the first chip base 210', the bottom surface of the first lead 230', and the bottom surface of the second lead 220' can be substantially flush with the bottom surface of the molded package 500. In some embodiments, the bottom surface of the pin portions of the third lead 240' and the fourth lead 250' can be substantially flush with the bottom surface of the molded package 500, and the main body portions of the second lead 240' and the third lead 250' can be disposed in the molded package 500. In some embodiments, the thickness of the pin portions of the second lead 240' and the third lead 250' is greater than the thickness of the main body portions. In particular, the semiconductor package 10B of this embodiment is a half-bridge switch formed by placing two chips on the same chip base 210' in the lead frame. The chips 310 and 320 have a vertical structure, that is, the source of the chips 310 and 320 is located on one side of the chip, and the drain is located on the other side of the chip, so that the current passes through the chip in a vertical direction. Furthermore, multiple leads 230', 220', 240', and 250' in the lead frame 200B surround the chip base 210' in the lead frame 200B, thereby minimizing the power supply loop and gate drive loop and reducing parasitic capacitance in the circuit. Additionally, this ring arrangement effectively reduces mutual interference between the current signal and the gate drive signal due to the reduced overlap area between them.

[0054] In this document, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “left,” and “right” may be used for ease of description to describe the relationship between one component or feature as shown in the accompanying drawings and one or more other components or features. In addition to the orientation depicted in the accompanying drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly. It should be understood that when a component is referred to as “connected to” or “coupled to” another component, it may be directly connected to or coupled to the other component, or there may be an intermediate component present.

[0055] As used herein, the terms “approximately,” “substantially,” “essentially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation occurs precisely or instances where the event or situation is close to occurring. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. A range may be expressed herein as a distance from one endpoint to another or between two endpoints. All ranges disclosed herein include endpoints unless otherwise specified. The term “substantially coplanar” may mean that the positional difference between two surfaces located along the same plane is within a few micrometers (μm), such as within 10 μm, 5 μm, 1 μm, or 0.5 μm. When a numerical value or characteristic is referred to as “substantially” the same, the term may refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of said values.

[0056] The foregoing has summarized the features of several embodiments and detailed aspects of this disclosure. The embodiments described in this disclosure can readily serve as the basis for designing or modifying other processes and structures to achieve the same or similar purposes and / or realize the same or similar advantages of the embodiments described herein. Such equivalent constructions do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor package, characterized in that, include: The lead frame includes: First chip base; The second chip base is electrically isolated from the first chip base; and The first lead, the second lead, and the third lead are electrically isolated from the first chip substrate and the second chip substrate, wherein the second chip substrate and the plurality of leads surround the first chip substrate; The first chip is attached to the first chip base; The second chip is attached to the second chip base; The first clamp connects the first electrode of the first chip and the second chip base; The second clamp connects the first electrode of the second chip and the first lead; A first bonding line connects the second electrode of the first chip to the second lead; and The second bonding line connects the second electrode of the second chip to the third lead.

2. The semiconductor package according to claim 1, characterized in that, It also includes molded packaging, which encapsulates the first chip, the second chip, the first clamp, the second clamp, and the lead frame.

3. The semiconductor package according to claim 2, characterized in that: The first chip base has a first side, a second side, and a third side, wherein the first side is opposite to the third side and both are adjacent to the second side. The second chip base surrounds at least the first side and the second side of the first chip base. The first lead is located on the first side of the first chip base. The second lead is located on the third side of the first chip base, and The third lead is located on the second side of the first chip base.

4. The semiconductor package according to claim 3, characterized in that, It also includes a fourth lead, which is a Kelvin source lead and is adjacent to the third side of the first chip base, and is electrically connected to the first chip base through a third bonding wire.

5. The semiconductor package according to claim 4, characterized in that, One side of the first lead is generally aligned with one side of the first chip base and one side of the fourth lead.

6. The semiconductor package according to claim 5, characterized in that, The bottom surface of the first chip base is substantially flush with the bottom surface of the molded package.

7. The semiconductor package according to claim 6, characterized in that, The thickness of the first chip base is basically the same as the thickness of the second body of the second chip base.

8. The semiconductor package according to claim 2, characterized in that: The second chip base includes a second body, a terminal portion, and a connecting portion connecting the second body and the terminal portion. The thickness of the connecting portion is less than the thickness of the second body and less than the thickness of the terminal portion. The top surfaces of the second body, the terminal portion, and the connecting portion are substantially flush. The bottom surfaces of the second body, the terminal portion, and the molded package are substantially flush. The molded package covers the bottom surface of the connecting portion.

9. The semiconductor package according to claim 1, characterized in that, When viewed from above, the semiconductor package has a rectangular outer contour.

10. The semiconductor package according to claim 1, characterized in that, The first chip base, the second chip base, and the first lead are arranged in a ring.

11. The semiconductor package according to any one of claims 1 to 10, characterized in that... Also includes: The third clamp connects the third electrode of the first chip to the first chip base; and The fourth clamp connects the third electrode of the second chip to the base of the second chip.

12. The semiconductor package according to any one of claims 1 to 10, characterized in that: The first clamp includes a pair of first support portions spaced apart and a first raised portion connecting the pair of first support portions. One of the pair of first support portions contacts the first electrode of the first chip, and the other of the pair of first support portions contacts the base of the second chip. The second clamp includes a pair of second support portions spaced apart and a second raised portion connecting the pair of second support portions. One of the pair of second support portions contacts the first electrode of the second chip, and the other of the pair of second support portions contacts the first lead.

13. The semiconductor package according to any one of claims 1 to 10, characterized in that, It also includes a first capacitor, which connects the first chip base to the first lead.

14. The semiconductor package according to any one of claims 1 to 10, characterized in that, The length direction of the first chip is approximately perpendicular to the length direction of the second chip.

15. A semiconductor package, characterized in that, include: The lead frame includes: First chip base; The second chip base is electrically isolated from the first chip base; The first lead is electrically isolated from the first chip base and the second chip base; The second lead and the third lead are both electrically isolated from the first chip base, the second chip base and the first lead; A first chip is attached to a first chip base, and the first electrode of the first chip is connected to the first chip base; The second chip is attached to the second chip base, and the first electrode of the second chip is connected to the second chip base; The first clamp connects the second electrode of the first chip and the base of the second chip. The second clamp connects the second electrode of the second chip to the first lead; The first bonding line connects the third electrode of the first chip to the second lead; The second bonding wire connects the third electrode of the second chip to the third lead; and Molded packaging encapsulates the first chip, the second chip, the first clamp, the second clamp, and the lead frame.

16. The semiconductor package according to claim 15, characterized in that, The first chip base has a first side and a second side adjacent to the first side, the second chip base and the first lead are placed along the first side of the first chip base, and the second lead and the third lead are placed on the second side of the first chip base.

17. The semiconductor package according to claim 15, characterized in that, When viewed from above, the semiconductor package has a rectangular outer contour.

18. The semiconductor package according to claim 15, characterized in that: The first clamp includes a pair of first support portions spaced apart and a first raised portion connecting the pair of first support portions. One of the pair of first support portions contacts the second electrode of the first chip, and the other of the pair of first support portions contacts the base of the second chip. The second clamp includes a pair of second support portions spaced apart and a second raised portion connecting the pair of second support portions. One of the pair of first support portions contacts the second electrode of the second chip, and the other of the pair of first support portions contacts the first lead.

19. The semiconductor package according to any one of claims 15 to 18, characterized in that, It also includes a capacitor that connects the first chip base to the first lead.

20. The semiconductor package according to any one of claims 15 to 18, characterized in that, The length direction of the first chip is approximately perpendicular to the length direction of the second chip.

21. A semiconductor package, characterized in that, include: The lead frame includes: Chip base; First lead; Second lead; The third lead; and A fourth lead, wherein the first lead, the second lead, the third lead and the fourth lead surround the chip substrate, and the chip substrate, the first lead, the second lead, the third lead and the fourth lead are electrically isolated from each other; A first chip is attached to the chip base, wherein the source of the first chip is connected to the chip base; A second chip is attached to the chip base, wherein the drain of the second chip is connected to the chip base; The first clamp connects the drain of the first chip and the first lead; The second clamp connects the source of the second chip to the second lead; The first bonding line connects the gate of the first chip to the third lead; The second bonding wire connects the gate of the second chip to the fourth lead; and Molded packaging encapsulates the first chip, the second chip, the first clamp, the second clamp, and the lead frame.

22. The semiconductor package according to claim 21, characterized in that: The chip base has a first side, a second side, and a third side, wherein the first side and the third side are opposite to each other and both are adjacent to the second side. The first lead is located on the first side of the chip base. The second lead is located on the second side of the chip base. The third lead is located on the second side of the chip base, and The fourth lead is located on the third side of the chip base.

23. The semiconductor package according to claim 21, characterized in that, When viewed from above, the chip base, the first lead, the second lead, and the third lead are arranged to form a rectangular outer contour.

24. The semiconductor package according to claim 21, characterized in that, When viewed from above, the semiconductor package has a rectangular outer contour.

25. The semiconductor package according to claim 21, characterized in that, The length of the fourth lead in the first direction is greater than the length of the chip substrate in the first direction and the length of the third lead in the first direction.

26. The semiconductor package according to any one of claims 21 to 25, characterized in that: The first clamp includes a pair of first support portions spaced apart and a first raised portion connecting the pair of first support portions. One of the pair of first support portions contacts the drain of the first chip, and the other of the pair of first support portions contacts the first lead. The second clamp includes a pair of second support portions spaced apart and a second raised portion connecting the pair of second support portions. One of the pair of second support portions contacts the source electrode of the second chip, and the other of the pair of second support portions contacts the second lead.

27. The semiconductor package according to any one of claims 21 to 25, characterized in that, It also includes a capacitor that connects the second lead to the first lead.

28. The semiconductor package according to any one of claims 21 to 25, characterized in that, The length direction of the first chip is approximately perpendicular to the length direction of the second chip.

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