SiC semiconductor device and method for its manufacture

Abstract

Semiconductor device comprising a SiC semiconductor layer (2), a well region (4) selectively formed on a surface of the SiC semiconductor layer (2), and a doping implantation region (3) selectively formed on a surface of the well region (4), wherein the doping implantation area (3) has a depression which is formed in a section of it on a surface of the doping implantation area (3) and the section having the depression does not extend to an end of the doping implantation area (3), wherein a section up to the end of the doping implantation area (3) has a hook-shaped shape curved upwards towards a cover surface of the semiconductor layer (2), wherein at least one side surface of the recess has a gate oxide layer, and wherein the section with the hook-shaped shape bent upwards towards the top surface of the semiconductor layer (2) is arranged below a poly-Si gate electrode (8) of the semiconductor device, the poly-Si gate electrode (8) extending over the section having the recess.

Description

[0001] Regarding German patent DE 10 2011 003 843, the 2nd Senate (Voidance Senate) of the Federal Patent Court, based on the oral proceedings of February 29, 2024, has ruled as follows: recognized as rightful: I. Claim 1 and claim 2 of German patent DE 10 2011 003 843 are partially declared invalid by replacing claim 1 and claim 2 of this patent with the following wording:

[0002] The present invention relates to a semiconductor device with a target area and a source area, and in particular to a SiC semiconductor device using silicon carbide, and to methods for its manufacture.

[0003] The electrical breakdown field strength and band gap of silicon carbide are approximately ten and three times greater, respectively, than those of silicon. Accordingly, a power device using silicon carbide can operate at a higher temperature with lower resistance compared to a power device using silicon, as currently employed. In particular, a MOSFET and an IGBT using silicon carbide are quite promising because, in normal operating mode and at the time of switching, they exhibit lower losses compared to a MOSFET and an IGBT of the same breakdown voltage using silicon. Therefore, various methods for fabricating a MOSFET and an IGBT using silicon carbide have been proposed (see e.g., JP 2000-164525 A).

[0004] In the MOSFET that uses silicon carbide, a channel resistance contributes half to the ON resistance, which is part of a loss that occurs when current flows. The channel resistance is determined by a channel length Lch, which depends on a positional relationship between a p-well region and a source region, as described in Fig. Figure 1 shows that if the channel length Lch changes due to a mask misalignment occurring in a step of forming the p-well and source regions, a chip can fail due to local current concentration in a chip area. Therefore, precisely controlling the channel length Lch is a significant problem.

[0005] In a known method for fabricating a MOSFET using silicon carbide, a marker region is formed at the beginning of a wafer process. This marker region serves as a reference for mask alignment in a photomechanical process. Based on this marker region, mask alignment is then performed to form a p-shaped well region. Mask alignment is also performed, again using the marker region as a reference, to form an n-shaped source region. A well contact region is then formed in the center of the source region. Finally, mask alignment is performed in the same manner, based on the marker region, to form an electrode structure.

[0006] JP 2006-128 191 A describes a procedure in which the tub implantation is first performed using an initial mask, and then an additional mask is applied without removing the first one to implant the source region. JP H11-274 173 A alternatively discusses an approach in which the same mask is used for implanting the source region and, after modification, also for tub implantation.

[0007] The object of the present invention is to provide a structure for a semiconductor device that suppresses a fluctuation in channel length, as well as a method for its manufacture.

[0008] The problem is solved by a semiconductor device according to claim 1.

[0009] The SiC semiconductor device comprises: a SiC semiconductor layer, a well region selectively formed on a surface of the SiC semiconductor layer, and a doping implantation region selectively formed on a surface of the well region. The doping implantation region has a depression formed in a portion of it on a surface of the doping implantation region, except in a portion near an end section, and the portion near the end section has a hook-shaped form curved upwards towards a top surface of the semiconductor layer.

[0010] Since the area near the end section of the doping implantation area has a shape that curves upwards towards a top surface of the semiconductor layer, an inversion layer can be formed uniformly on a wafer surface.

[0011] The problem is also solved by a method for manufacturing a SiC semiconductor device according to claim 3.

[0012] The method comprises the steps of: (a) etching areas of a SiC semiconductor layer serving as the doping implantation area and the mark area using a single mask, (b) performing ion implantation in the wells of the areas serving as the doping implantation area and the mark area using the single mask at least from one direction oblique to a surface of the SiC semiconductor layer, and (c) positioning another mask based on the well of the area serving as the doping implantation area or the mark area, and performing well implantation in an area containing the doping implantation area.

[0013] Since etching for the doping implantation area and the marker area is performed using a single mask, the doping implantation area can be formed without misalignment relative to the marker area, thus suppressing channel length variations. Furthermore, by performing ion implantation from an oblique angle, the doping implantation area can be formed close to the side face of the well. Therefore, an inversion layer can be formed uniformly on a wafer surface.

[0014] The problem is also solved by a method for manufacturing a SiC semiconductor device according to claim 4.

[0015] The procedure comprises the steps of: (a) performing ion implantation in regions of a SiC semiconductor layer serving as the doping implantation region and the marker region, using a single mask at least from one direction oblique to a surface of the SiC semiconductor layer; (b) performing etching to partially remove ion-implanted portions of the regions serving as the doping implantation region and marker region to form wells; and (c) positioning another mask based on the well of the region serving as the doping implantation region or marker region, and performing well implantation in a region containing the doping implantation region.

[0016] Since etching for the doping implantation area and the marker area is performed using a single mask, the doping implantation area can be formed without misalignment relative to the marker area, thus suppressing channel length variation. Furthermore, by performing ion implantation from an oblique angle, the doping implantation area can be formed close to the side surface of the well. Therefore, an inversion layer can be formed uniformly on a wafer surface. Because etching is performed after ion implantation has been carried out during the formation of the doping implantation area, the doping implantation area is not affected by the etching process and can be formed without variation.

[0017] The problem is also solved by a method for manufacturing a SiC semiconductor device according to claim 5.

[0018] The process comprises the following steps: (a) etching areas of a SiC semiconductor layer that serve as the doping implantation area and the marker area, using a single mask that has low selectivity with respect to the SiC semiconductor layer, to form wells; (b) performing ion implantation in the wells of the areas serving as the doping implantation area and the marker area, using the single mask; and (c) positioning another mask based on the well of the area serving as the doping implantation area or the marker area, and performing well implantation in an area containing the doping implantation area.

[0019] Since the etching is performed using a mask that has low selectivity towards the SiC semiconductor layer, the mask opening is formed in a tapered shape. Therefore, the mask thickness is small in the region near the edge of the opening. Ions are implanted through the mask and also into a section of the SiC semiconductor layer immediately beneath this section. This allows the doping implantation area to be stably formed near a side face of the well, enabling the uniform formation of an inversion layer on the wafer surface. Furthermore, the end section of the doping implantation area is tapered, eliminating any sharp angles. This prevents breakdown caused by an electric field concentration.

[0020] The problem is also solved by a method for manufacturing a SiC semiconductor device according to claim 7.

[0021] The procedure comprises the steps of: (a) performing ion implantation in areas of a SiC semiconductor layer serving as the doping implantation area and the mark area, using a single mask with a tapered opening; (b) performing etching using the single mask to partially remove ion-implanted areas of the regions serving as the doping implantation area and the mark area, to form wells; and (c) positioning another mask based on the well of the region serving as the doping implantation area or the mark area, and performing well implantation in a region containing the doping implantation area.

[0022] Since the mask opening has a tapered shape, the mask thickness is small in the area near the edge of the opening. Ions are implanted through the mask into a section of the SiC semiconductor layer immediately below this area. Therefore, the doping implantation region can be formed stably near a side face of the well, allowing for the uniform formation of an inversion layer on the wafer surface. Furthermore, the end section of the doping implantation region is tapered, and thus there is no sharp-angled section. This prevents breakthrough caused by an electric field concentration. Since etching is performed after ion implantation during the formation of the doping implantation region, the doping implantation region is also unaffected by the etching process and can be formed without fluctuations.

[0023] Further developments of the invention are specified in the dependent claims.

[0024] Further features and advantages of the invention will become apparent from the description of exemplary embodiments with reference to the accompanying drawings. Fig. Figure 1 is a sectional view showing the structure of a SiC semiconductor device. Fig. Figure 2 is a sectional view showing a process for manufacturing the SiC semiconductor device according to a known technique. Fig. Figure 3 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the known technique. Fig. Figure 4 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the known technique. Fig. Figure 5 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the known technique. Fig. Figure 6 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the known technique. Fig. Figure 7 is a sectional view showing a process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 8 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 9 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 10 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 11 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 12 is a sectional view showing a process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 13 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 14 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 15 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 16 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 17 is a sectional view showing a process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 19 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 20 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 21 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 22 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 23 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 23 is a sectional view showing a process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 24 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 25 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 26 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 27 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 28 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 29 is a sectional view showing a process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 30 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 31 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 32 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 33 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 34 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 35 is a sectional view showing a process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 36 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 37 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 38 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 39 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention. Fig. Figure 40 is a sectional view showing the process for manufacturing the SiC semiconductor device according to the present invention.

[0025] The technical background of the present invention is a process for producing a Fig. 1 MOSFET shown in the course of the in Fig. The steps shown in 2-6 are described.

[0026] First, a wafer is prepared using a mask 20, in which an epitaxial n - -SiC layer 2 (n-SiC epi-layer) on an n + -SiC substrate 1 (n+SiC substrate) is formed, etched to form a mark area ( Fig. 2) Then a mask 21 is formed based on the brand area, and Al is implanted to form a p-tub area 4 ( Fig. 3) Additionally, a mask 22 is formed based on the brand area, and N ions are implanted to form an n-source area 3 ( Fig. 4) In the same way, a mask 23 is formed based on the mark area, and Al ions are implanted to form a trough contact area 5 in the center of the source area 3. Subsequently, a mask alignment based on the mark area is performed in the same way to create an electrode setup ( Fig. 6) to form. In the electrode structure, reference numeral 6 denotes a Ni layer, reference numeral 7 a gate oxide layer, reference numeral 8 a polysilicon (Poly-Si), reference numeral 9 an intermediate insulating layer, reference numeral 10 an Al layer and reference numeral 11 a drain electrode.

[0027] If the mask alignments are performed based on the etched section of the mark area, while the source area 3 and the p-tub area 4 are formed as described above, a mask misalignment will be repeated in each step, causing a large variation in a channel length Lch (see above). Fig. 1).

[0028] Therefore, in a process for fabricating a MOSFET, which is a SiC semiconductor device according to the present invention, a marker region and a source region 3 are etched using a single mask, and subsequent mask alignments are performed based on an etched portion of the marker region or the source region 3 (since the magnitude of the mask misalignment between the marker region and the source region 3 is zero, the marker region or the source region 3 can serve as a reference). In this way, a variation in the channel length Lch is suppressed.

[0029] According to one embodiment of the present invention, the marker area and the source area 3 are formed simultaneously by performing etching and ion implantation using a single mask, and therefore an etched section of the source area 3 is formed without misalignment relative to the reference marker area. If mask alignment is performed in subsequent source formation steps using the etched section of the marker area or the source area 3, a variation in the channel length Lch can be suppressed because the source area 3 is formed without misalignment relative to the marker area.

[0030] During the course of the Fig. The procedure shown in Figures 7-11 describes an example of a process for fabricating a MOSET in which etching and ion implantation are performed simultaneously to form the mark region and the source region. First, using a single mask 30, etching is performed for the source region 3 and the mark region on a SiC semiconductor layer containing an n+SiC substrate 1 and an n-SiC epi-layer 2 formed on the n+SiC substrate 1, thereby forming pits with a depth of 0.2 µm ( Fig. 7) Mask 30 and masks 31 and 32, which are described later, are formed from a resist mask or a hard mask such as an oxide layer or a nitride layer.

[0031] Then, reusing the same single mask, 30 N (nitrogen) or P (phosphorus) are injected vertically with an implantation rate of 3×10 19 cm -3ion-implanted to form an n-source region 3 with a depth of 0.4 µm ( Fig. 8).

[0032] Then Al (aluminium) or B (boron) ions are implanted using a p-well implantation mask 31, which is aligned based on the indentation of the mark area or the source area 3 to form a p-well area 4 having a depth of 1.0 µm ( Fig. 9) The depression is formed in the source region 3, and therefore a portion of the p-trough region 4, which is formed directly below the source region 3, corresponds to the magnitude of the level difference caused by the depression. Since the p-trough region 4 thus has an umbilical structure, the penetration strength can be improved.

[0033] Subsequently, using a basin contact implantation mask 32 aligned based on the depression of the mark area or the source area 3, Al or B ions are implanted to form a basin contact area 5 in the center of the source area 3 ( Fig. 10) The Al or the B are implanted at a higher concentration than in p-pan implantation or source implantation. This is the first time the complete source region 3 is formed.

[0034] Subsequently, although a detailed description is omitted, a high-temperature activation heat treatment is carried out, and the gate oxide layer 7, the poly-Si gate electrode 8, the intermediate insulating layer 9, the source electrodes 6 and 10, the drain electrode 11, and the like are successively formed, so that a Fig. The MOSFET shown in section 11 is completed. The drain electrode 11 can be made of Ni, for example, or alternatively of a multilayer metal.

[0035] By etching the areas where the mark area and source area 3 are to be formed simultaneously, the number of steps can be reduced and the manufacturing process simplified compared to forming the mark area and source area 3 separately. Consequently, working time can be shortened and costs reduced. Furthermore, by forming the mark area and source area 3 simultaneously, mask misalignment of the source area 3 relative to a mark reference does not need to be considered, and the positional accuracy of the source area 3 relative to the well area 4 is significantly improved. This can suppress fluctuations in the channel length Lch to a minimum, and the quality of a chip can be improved because it prevents the chip from failing due to current concentration caused by fluctuations in the ON resistance.

[0036] At the in Fig. In the manufacturing process shown in 7-11, etching is first carried out for the mark area and the source area 3 ( Fig. 7) and then the ion implantation is performed ( Fig. 8) However, there is a possibility that the shape of a resist pattern may change due to etching, causing source region 3 to change in the subsequent ion implantation step. To prevent this problem, it is desirable to perform the etching after the ion implantation has been carried out, as described in Fig. 12-16 is shown.

[0037] First, in a semiconductor layer containing the n+SiC substrate 1 and an n-SiC epi-layer 2 formed on the n+SiC substrate 1, N or P is vertically ion-implanted in regions where the source region 3 and the marker region are to be formed using the single mask 30 ( Fig. 12). Additionally, using the same mask 30 again, etching is carried out to create a depression ( Fig. 13). Then, similarly to the above, with reference to Fig. 7-11 described process of the p-tub area 4 ( Fig. 14) and the tub contact area 5 ( Fig. 15) formed based on the deepening of the mark area or the source area 3. In addition, high-temperature actuation heat treatment is carried out, and the gate oxide layer 7, the poly-Si gate electrode 8, the intermediate insulating layer 9, the source electrode 6, the drain electrode 11 and the like are formed successively. Thus, a Fig. 16 MOSFETs shown are completed.

[0038] In this manufacturing process, etching for source region 3 is performed after ion implantation. This prevents source region 3 from changing due to alterations in the resist pattern caused by etching. However, the ion implantation step requires prior deep implantation, taking into account the etching depth.

[0039] When a MOSFET using SiC as the material is passed through the Fig. The process shown in 7-11 or the one in Fig. In the process shown in 12-16, the following problem arises: in SiC, an implanted element diffuses hardly in any lateral direction, unlike in Si. Therefore, the source region 3 spreads in the Fig. 8 and Fig. In the ion implantation step shown in Figure 12, the process is not carried out laterally from an opening in the mask 30, but directly downwards. Since the source region 3 is formed simultaneously with the marker region, a wafer surface is etched, and a top surface of the source region 3 forms a depression. Therefore, in the subsequent step, the gate oxide layer is formed not only on the wafer surface but also on a side surface of the depression (in a cross-sectional direction of the wafer), as shown in Figure 12. Fig. 11 and Fig. 16 is shown.

[0040] SiC has a hexagonal crystal structure. The oxidation rate in one direction of a wafer surface ((0001) face) and in a cross-sectional direction are different. For example, if the wafer cross-sectional direction is an (11-20) face, the gate oxide layer 7 is several times thicker in the cross-sectional direction than in the surface direction (even if Fig. 11 and Fig. Figure 16 shows that the gate oxide layer 7 is approximately twice as thick in the cross-sectional direction as in the surface direction (in reality, it is even thicker). The channel is formed along the hook-shaped gate oxide layer 7. A problem arises here: the channel resistance is unstable because the thickness of the gate oxide layer 7 changes as described above.

[0041] Furthermore, the gate oxide layer 7 is affected in the cross-sectional direction by the accuracy of the well etching process, and the layer thickness changes due to this accuracy. If the gate oxide layer 7 is thick, an inversion layer is hardly formed. Consequently, the formation of the inversion layer varies or fluctuates between the wafer surface (a surface of the well region 4) and the side face of the well (in the cross-sectional direction of the wafer).

[0042] To solve these problems, it is necessary to also form the source region 3 in a section of the SiC epilayer 2 on the side surface of the depression, in order to stably form the inversion layer only on the wafer surface. An example of such a manufacturing process is shown in Fig. Shown 17-22. Fig. Figures 17-22 show a manufacturing process in which implantation occurs during the ion implantation step of the Fig. The manufacturing process shown in 7-11 is carried out at an angle.

[0043] First, similar to the one in Fig. The process shown in Figure 7-11, using the single mask 30 in which a marker section aperture and a source section aperture are formed, is performed on a semiconductor layer containing an n+SiC substrate and an n-SiC epi-layer 2 formed on the n+SiC substrate 1, thereby forming depressions with a depth of 0.2 µm of the marker area and the source area 3 ( Fig. 17) In this process, an area defined by a combination of the entire source area 3 and the trough contact area 5 formed in the source area 3 is formed such that it has a depression shape. The mask 30, as well as the masks 31 and 32, which are described later, consist of a resist mark or a hard mask such as an oxide layer or a nitride layer.

[0044] Then, using the same mask, 30 N or P is vertically ion-implanted with an implantation quantity of 3×10 19 cm -3 , in order to form an n-source region 3 with a depth of 0.4 µm ( Fig. 18). The same ion implantation is then performed with a rotation of the wafer or obliquely at an angle of approximately 5-30° relative to the direction perpendicular to the wafer ( Fig. 19). This allows the source region 3 to also be formed in a region of the n-SiC epi-layer 2 near the side surface of the depression. The in Fig. Step 18 shown can be omitted, and ion implantation can be performed obliquely or with rotation of the wafer from the beginning.

[0045] Then Al or B ions are implanted using a p-well implantation mask 31, which is aligned based on the indentation of the mark area or the source area 3 to form a p-well area 4 with a depth of 1.0 µm ( Fig. 20). In a subsequent step, similar to the one described in Fig. In step 10, the tub contact area 5 is formed using a tub contact implantation mask 32, which is aligned based on the indentation of the mark area or the source area 3 ( Fig. 21). A high-temperature activation heat treatment is then carried out, and the gate oxide layer 7, the poly-Si gate electrode 8, the intermediate insulating layer 9, the source electrode 6, the drain electrode 11, and the like are successively formed. Thus, the in Fig. 22 MOSFETs shown are completed.

[0046] Source region 3 has a depression formed in a section of it, except for a section near its end at the surface of source region 3. This section near the end has a hook-like shape, curved upwards towards a top surface of the semiconductor layer. This allows the inversion layer to form stably on the wafer surface.

[0047] In this way, the process for manufacturing the semiconductor device of this embodiment comprises the steps: (a) forming wells by etching areas of the SiC semiconductor layer that serve as source area 3 (doping implantation area) and as marker area using the single mask, (b) performing ion implantation in the wells that serve as source area 3 and marker area using the same mask as in step (a) at least from one direction oblique to the surface of the SiC semiconductor layer, and (c) aligning a further mask based on at least the well that serves as doping implantation area, and performing well implantation in an area that contains the doping implantation area.

[0048] By performing the etching for source region 3 and the marker region using the single mask, source region 3 can be formed without misalignment relative to the marker region, thus suppressing channel length variations. Furthermore, by performing ion implantation from an oblique direction, source region 3 can also be etched close to the side surface of the well, preventing oxide layer formation on the well surface. Therefore, the inversion layer can be formed uniformly on the wafer surface.

[0049] The semiconductor device of this embodiment thus formed comprises the n+SiC substrate 1, the n-SiC epi-layer 2 (SiC semiconductor layer), the p-well regions 4, which are selectively formed on the surface of the SiC semiconductor layer, and the source regions 3 (doping implantation regions), which are selectively formed on the surface of the p-well regions 4. The source region 3 has a depression formed in a portion of its surface, except in a portion near the end, and the portion near the end has a hook-shaped form that curves upwards towards the top surface of the semiconductor layer. This enables the inversion layer to form uniformly on the wafer surface.

[0050] Even in the Fig. The same effects can be achieved by performing an oblique implantation in the ion implantation step, as shown in the manufacturing process 12-16. Fig. Figures 23-28 show a manufacturing process in which the oblique implantation occurs during the ion implantation step in the Fig. The manufacturing process shown in 12-16 is carried out.

[0051] First, similar to the one in Fig. 12-16 process into a semiconductor layer containing the n+SiC substrate 1 and an n-SiC epi-layer 2 formed on the n+SiC substrate 1, N or P is vertically implanted into regions where the source region 3 and the mark region are to be formed using the single mask 30. Fig. 23). The same ion implantation is then performed with rotation of the wafer or obliquely at an angle of approximately 5-30° relative to the direction perpendicular to the wafer ( Fig. 24).

[0052] Then, using the same mask, 30 etching steps are performed to create a depression ( Fig. 25). Subsequently, similar to those relating to Fig. 14 and Fig. 15 described steps of the p-tub area 4 ( Fig. 26) and the tub contact area 5 ( Fig. 27) formed based on the deepening of the mark area or the source area 3. In addition, a high-temperature activation heat treatment is carried out, and the gate oxide layer 7, the poly-Si gate electrode 8, the intermediate insulating layer 9, the source electrode 6, the drain electrode 11 and the like are formed successively. Thus, a Fig. 28 MOSFETs shown are completed.

[0053] The process for manufacturing the semiconductor device of this embodiment comprises the steps of: (a) performing ion implantation in regions of the SiC semiconductor layer serving as source region 3 (doping implantation region) and as marker region, at least from one direction oblique to the surface of the SiC semiconductor layer; (b) performing etching using the same mask as in step (a) to partially remove ion-implanted portions of the regions serving as source region 3 and as marker region in order to form depressions; and (c) positioning another mask based on the depression of the region serving as source region 3 or as marker region, and performing trough implantation in a region containing source region 3.

[0054] By performing the etching for both source region 3 and the mark region using a single mask, source region 3 can be formed without misalignment relative to the mark region, thus suppressing channel length variations. Furthermore, by performing ion implantation from an oblique angle, source region 3 is formed beyond the mask opening. When the depression is formed during the etching step, source region 3 is also formed close to the side surface of the depression. Therefore, the inversion layer can be formed uniformly across the wafer surface. Because the etching is performed after ion implantation in source region 3, the source region is not affected by the etching process and is formed without variations.

[0055] Fig. 29-34 show a process for manufacturing a MOSFET, in which in the Fig. In the etching step shown in Figure 17, a mask with low selectivity relative to the SiC semiconductor layer (epi-layer 2) is used. When etching for the mark region and the source region 3 on the SiC semiconductor layer is performed using a mask 70 with low selectivity, one opening of the mask 70 has a tapered shape. The etch rate is set such that its ratio (mask / SiC semiconductor layer) ≥ 1.

[0056] Then, using the same mask 70, an ion implantation is performed in the direction perpendicular to the wafer ( Fig. 30). Since the mask 70 was formed in the previous step in the tapered shape, a section of the mask 70 near a boundary between the mask 70 and the opening has a small thickness. Ions are implanted through the mask 70 into a section of the epi-layer 2 that lies immediately below this section of the mask 70. Consequently, without performing the oblique implantation, the source region 3 is formed stably near the side surface of the well, so that an end section of the source region 3 has a tapered shape. This makes it possible to form an inversion layer stably on the wafer surface.

[0057] However, an oblique implantation can also be performed to form the source region 3 near the side surface of the well. In this case, the ion implantation is performed with a rotation of the wafer or obliquely at an angle of approximately 50–30° relative to the direction perpendicular to the wafer ( Fig. 31).

[0058] The following steps are the same as those in Fig. 7-11 shown, and the p-tub area 4 and the tub contact area 5 are formed ( Fig. 32 and Fig. 33). In addition, a high-temperature activation heat treatment is carried out, and the gate oxide layer 7, the poly-Si gate electrode 8, the intermediate insulating layer 9, the source electrode 6, the drain electrode 11, and the like are successively formed. Thus, a Fig. 34 MOSFETs shown are completed.

[0059] Fig. Figures 35-40 show a manufacturing process in which a mask with a tapered shape is used in the ion implantation step of Fig. 23 is used, which is in the Fig. Figures 23-28 show the manufacturing process for a MOSFET, in which etching is performed after source implantation. Fig. Figure 35 shows a step of performing ion implantation using a mask 70, which has tapered openings due to post-annealing. When N ions are implanted in the direction perpendicular to the wafer, the ion implantation through the mask 70 also takes place in a region located immediately around the opening in a thinned section of the mask 70. Consequently, the source region 3 is formed without oblique implantation beyond the opening of the mask 70, and an end section of the source region has a tapered shape.

[0060] However, an oblique implantation can also be performed to create the source area 3 beyond the opening of mask 70. In this case, the ion implantation is performed with rotation of the wafer or obliquely at an angle of approximately 5-30° relative to the direction perpendicular to the wafer ( Fig. 36). Then etching is performed for source area 3 using the same mask 70 ( Fig. 37). Thus, a depression is formed in source area 3. Since source area 3 is formed beyond an area corresponding to the opening of mask 70, source area 3 is also formed near the side surface of the depression.

[0061] The following steps are the same as in Fig. 26-28 shown, and the p-tub area 4 and the tub contact area 5 are formed ( Fig. 38 and Fig. 39). In addition, a high-temperature activation heat treatment is carried out, and the gate oxide layer 7, the poly-Si gate electrode 8, the intermediate insulating layer 9, the source electrode 6, the drain electrode 11, and the like are successively formed. Thus, a Fig. 40 MOSFETs shown are completed.

[0062] Source region 3 has a depression formed on its surface in a section of it, except for a section near the end. This area near the end has a hook-like shape that curves upwards towards the top surface of the semiconductor layer. This allows the inversion layer to form stably on the wafer surface.

[0063] Although a MOSFET was described above, an IGBT differs from a MOSFET only in its structure on one back surface of the substrate (the drain side in the case of a MOSFET) and has the same structure on one front surface as a MOSFET. Therefore, the manufacturing process described above is also applicable to an IGBT and results in improved controllability of the channel length.

[0064] The semiconductor device of this embodiment has the following effects: the semiconductor device thus formed of this embodiment contains the n+SiC substrate 1, the n-SiC epi-layer 2 (SiC semiconductor layer), the p-well regions 4, which are selectively formed on the surface of the SiC semiconductor layer 2, and the source regions 3 (doping implantation regions), which are selectively formed on the surface of the p-well regions 4. The doping implantation region has a depression formed in a portion of it on the surface of the doping implantation region 3, except in a portion near the end, and the portion near the end has a hook-shaped form that curves upwards towards the top surface of the semiconductor layer. This enables the inversion layer to be formed uniformly on the wafer surface.

[0065] Preferably, the end section of the doping implantation area has a tapered shape. This design also makes it possible to form the inversion layer uniformly on the wafer surface.

[0066] The first method for manufacturing the semiconductor device of this embodiment has the following effects: the first method for manufacturing the semiconductor device of this embodiment comprises the steps of: (a) forming wells by etching areas of the SiC semiconductor layer that serve as source area 3 (doping implantation area) and as marker area, using a single mask; (b) performing ion implantation in the wells of the areas that serve as source area 3 and as marker area, using the same mask as in step (a), at least from one direction oblique to the surface of the SiC semiconductor layer; and (c) aligning a further mask based on the well of the area that serves as source area 3 or marker area, and performing well implantation in an area that contains the doping implantation area 3.

[0067] By performing etching for source region 3 and the marker region using the single mask, source region 3 can be formed without misalignment relative to the marker region, thus suppressing channel length variation. Furthermore, by performing ion implantation from an oblique direction, source region 3 can also be formed on the side faces of the well. Therefore, the inversion layer can be formed uniformly across the wafer surface.

[0068] The second method for fabricating the semiconductor device of this embodiment comprises the steps of: (a) performing ion implantation in regions of the SiC semiconductor layer serving as source region 3 (doping implantation region) and as marker region, using a single mask at least from one direction oblique to the surface of the SiC semiconductor layer; (b) performing etching to partially remove the ion-implanted portions of the regions serving as source region 3 and as marker region, using the same mask as in step (a) to form wells; and (c) positioning another mask based on the well of the region serving as source region 3 or marker region, and performing well implantation in a region containing source region 3.

[0069] By performing the etching for both the source region 3 and the marker region using the single mask, the source region 3 can be formed without misalignment relative to the marker region, thus suppressing any variation in channel length. Furthermore, by performing the ion implantation from an oblique angle, the source region 3 can also be formed on the side face of the well, allowing the inversion layer to be formed uniformly across the wafer surface. Since the etching is performed after the ion implantation has been carried out during the formation of the source region 3, the source region 3 is not affected by the etching process and is formed without any variation.

[0070] The third method for fabricating the semiconductor device of this embodiment comprises the steps: (a) forming wells by etching areas of the SiC semiconductor layer that serve as the doping implantation area (source area 3) and as the marker area, using a single mask that has low selectivity with respect to the SiC semiconductor layer, (b) performing ion implantation in the wells that serve as the source area 3 and marker area, using the same mask as in step (a), and (c) aligning another mask based on the well of the area that serves as the source area 3 or marker area, and performing well implantation in an area that contains the source area 3.

[0071] Since the etching is performed using the mask, which has low selectivity towards the SiC semiconductor layer, the opening of the mask 70 is formed in a tapered shape. Therefore, the thickness of the mask 70 is small in a section near the edge of the opening. Ions are also implanted through the mask 70 into a section of the SiC semiconductor layer immediately below this section. Therefore, the source region 3 can be formed stably near the side face of the well, allowing the inversion layer to form uniformly on the wafer surface. Furthermore, the end section of the source region 3 is formed in a tapered shape, and therefore there is no steep-angle section. Thus, breakdown caused by an electric field concentration can be prevented.

[0072] Preferably, the ion implantation in step (b) is carried out from at least one direction oblique to the surface of the SiC semiconductor layer. This allows the source region 3 to form stably near the side face of the depression, so that the inversion layer can be formed uniformly on the wafer surface.

[0073] The fourth method for fabricating the semiconductor device according to this invention comprises the steps of: (a) performing ion implantation in regions of the SiC semiconductor layer serving as the doping implantation region (source region 3) and as the marker region, using a single mask with tapered openings; (b) performing etching using the same mask as in step (a) to partially remove ion-implanted portions of the regions serving as source region 3 and as marker region to form wells; and (c) positioning another mask based on the well of the region serving as source region 3 or marker region and performing well implantation in a region containing the doping implantation region 3.

[0074] Since the opening of mask 70 is formed in a tapered shape, the thickness of mask 70 is small in a section near the edge of the opening. Ions are implanted through mask 70 into a section of the SiC semiconductor layer located directly beneath this section. Therefore, the source region can be formed stably near the side face of the well, enabling the inversion layer to form uniformly on the wafer surface. Furthermore, the end section of source region 3 is formed in a tapered shape, and therefore there is no section with a steep angle. Thus, breakthrough caused by an electric field concentration can be prevented. In addition, since etching is performed after ion implantation during the formation of source region 3, the source region 3 is not affected by the etching and forms without any variation.

[0075] Preferably, the ion implantation in step (a) is carried out from at least one direction oblique to the surface of the SiC semiconductor layer. This allows the source region 3 to be formed stably near the side face of the well, so that the inversion layer can be formed uniformly on the wafer surface.

Claims

[1] Semiconductor device comprising a SiC semiconductor layer (2), a well region (4) selectively formed on a surface of the SiC semiconductor layer (2), and a doping implantation region (3) selectively formed on a surface of the well region (4), wherein the doping implantation area (3) has a depression which is formed in a section of it on a surface of the doping implantation area (3) and the section having the depression does not extend to an end of the doping implantation area (3), wherein a section up to the end of the doping implantation area (3) has a hook-shaped shape curved upwards towards a cover surface of the semiconductor layer (2), wherein at least one side surface of the recess has a gate oxide layer, and wherein the section with the hook-shaped shape bent upwards towards the top surface of the semiconductor layer (2) is arranged below a poly-Si gate electrode (8) of the semiconductor device, the poly-Si gate electrode (8) extending over the section having the recess. [2] Semiconductor device according to claim 1, wherein an end surface of the doping implantation area (3) has a tapered shape. [3] Method for manufacturing a SiC semiconductor device comprising the following steps in the sequence below: (a) Etching areas of a SiC semiconductor layer (2) serving as a doping implantation area (3) and as a marker area, using a single mask (30) to form pits, (b) Performing ion implantation using the single mask (30) in the recesses of the areas serving as the doping implantation area (3) and as the marker area, at least from one direction oblique to a surface of the SiC semiconductor layer (2) and (c) Positioning a further mask (31) based on the depression of the area serving as the doping implantation area (3) or as the marker area, and performing a tub implantation in an area containing the doping implantation area (3). [4] Method for manufacturing a SiC semiconductor device by the steps carried out in the following sequence: (a) Performing ion implantation in regions of a SiC semiconductor layer (2) serving as a doping implantation region (3) and as a marker region, using a single mask (30) at least from one direction oblique to a surface of the SiC semiconductor layer (2), (b) Performing etching using the single mask (30) to partially remove ion-implanted sections of the areas serving as the doping implantation area (3) and as the mark area, to form depressions and (c) Positioning a further mask (31) based on the depression of the area serving as the doping implantation area (3) or as the marker area, and performing a tub implantation in an area containing the doping implantation area (3). [5] Method for manufacturing a SiC semiconductor device comprising the steps: (a) Etching areas of a SiC semiconductor layer (2) serving as a doping implantation area (3) and as a marker area, using a single mask (70) having low selectivity towards the SiC semiconductor layer (2), to form depressions, (b) Performing ion implantation using the single mask (70) in the recesses of the areas serving as the doping implantation area (3) and as the marking area, and (c) Positioning a further mask (71) based on the depression of the area serving as the doping implantation area (3) or as the marker area, and performing a tub implantation in an area containing the doping implantation area (3). [6] Method for producing a SiC semiconductor device according to claim 5, wherein step (b) includes a step of performing ion implantation at least from one direction oblique to a surface of the SiC semiconductor layer (2). [7] Method for manufacturing a SiC semiconductor device comprising the steps: (a) Performing ion implantation in areas of a SiC semiconductor layer (2) serving as a doping implantation area (3) and as a tag area, using a single mask (70) with a tapered opening, (b) Performing etching using the single mask (70) to partially remove ion-implanted sections of the areas serving as the doping implantation area (3) and as the mark area, to form depressions and (c) Positioning a further mask (71) based on the depression of the area serving as the doping implantation area (3) or as the marker area, and performing a tub implantation in an area containing the doping implantation area (3). [8] Method for producing a SiC semiconductor device according to claim 7, wherein step (a) includes a step of performing ion implantation at least from one direction oblique to a surface of the SiC semiconductor layer (2).

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