Storage array with hierarchical bitline structure

Abstract

Storage array (10), comprising: - a multitude of word lines (WL) extending along a first direction; - a plurality of memory cells (MC) coupled to a first sub-bit line (SBL) extending along a second direction that is essentially orthogonal to the first direction; and - characterized by: - a first selector region (20) located essentially in the middle of the first SBL, thereby dividing the plurality of memory cells (MC) into two subgroups, the first selector region (20) comprising at least one selector transistor (ST) coupled to the first SBL; and - a main bit line (MBL) extending along the second direction and coupled to the selector transistor (ST); - wherein the MBL is bent obliquely in the selector region (20) in order to overlap the selector transistor (ST), wherein a reactive capacitance structure (60a) is provided on the MBL at the intersection point; and - where the selector transistor (ST) is a vertical channel selector transistor (40).

Description

[0001] A hierarchical bitline architecture is used to enable high-speed operations. For example, US Patent No. 6,456,521 (Hsu et al.) discloses a hierarchical bitline system DRAM architecture which has a DRAM array containing master and local bitlines, with each master bitline coupled to two local bitlines.

[0002] US Patent No. 6,084,416 discloses a memory cell array divided into an odd number of sub-arrays. US Patent No. 6,084,816 further discloses word lines comprising a portion of a low-resistance upper word line arranged in parallel to a portion of a lower word line forming the gate of the cell transistor.

[0003] US 2002 / 085405 A1 describes a bitline architecture with electrically controllable bitline lengths. The bitlines are equipped with a switch that selectively couples or decouples local bitline segments depending on whether memory access is required. Controllable bitline lengths can lead to a reduction in power consumption without the need for additional read amplifiers or an additional metal layer.

[0004] Reference is also made to the publications US 5 610 871 A, US 6 707 700 B2, US 6 839 267 B1, CMOS Processors and Memories, Ed. Krzysztof Iniewski, Springer, Aug.2010, pp. 308-309 and US 2010 / 0 142 257 A1.

[0005] In hierarchical digital line (DL) design, sub-digital lines are divided into segments and connected by main digital lines. A selector is used to choose the sub-DL. Due to the high resistance of digital lines, the ends of the sub-digital lines are the weakest point in terms of signal margin. To address this issue, metal or high-dose silicon are used. However, metal is difficult to integrate into sub-digital lines due to process limitations, while high-dose silicon arrangements pose a high risk of leakage.

[0006] Therefore, the present invention aims to provide a memory cell array with a novel hierarchical bit line (BL) arrangement to reduce BL resistance and thus avoid a poorer signal reserve.

[0007] This is achieved by a storage array according to claim 1. The dependent claims relate to associated further developments and improvements.

[0008] As will be evident from the following detailed description, the claimed invention provides: a memory array comprising a plurality of word lines extending along a first direction; a plurality of memory cells coupled to a first sub-bit line (SBL) extending along a second direction oriented substantially orthogonal to the first direction; a first selector region arranged substantially in the middle of the first SBL, thereby dividing the plurality of memory cells into two sub-groups, the first selector region comprising at least one selector transistor coupled to the first SBL; and a main bit line (MBL) extending along the second direction and coupled to the selector transistor.The MBL is bent at an angle in the selector region to overlap the selector transistor, with a reactive capacitance structure provided on the MBL at the intersection point. The selector transistor is a vertical channel selector transistor.

[0009] The invention is further illustrated below by way of example, with reference to the accompanying drawing figures. Fig. Figure 1 is a schematic partial top view of a storage array according to an embodiment of the present invention; Fig. 2A and Fig. 2B are schematic sectioned views along lines II' and II-II' in Fig. 1; Fig. Figures 3A-3C are schematic diagrams showing the layouts of the MBL, SBL and selector area according to exemplary embodiments of the invention; Fig. Figure 4 shows an alternative layout for the SBL section and the selector areas according to another embodiment; Fig. Figure 5 shows a layout for the SBL sections and the selector regions with yet another embodiment; and Fig. Figure 6 shows another embodiment of a storage array according to this invention.

[0010] It should be noted that all figures are to be understood schematically. The relative dimensions and proportions of parts of the drawings are exaggerated or reduced in size to make the drawings easier to understand. The same reference symbols are generally used to refer to corresponding or similar features in modified or different embodiments.

[0011] The following detailed description refers to the accompanying drawings, which form part thereof and illustrate selected examples according to which the embodiments can be implemented. These embodiments are described in sufficient detail to enable a person skilled in the art to carry them out, and it is noted that other embodiments may be used and structural, logical, and electrical modifications may be made without deviating from the described embodiments. The following detailed description is therefore not to be interpreted in a limiting sense, and the embodiments contained herein are defined by the accompanying claims.

[0012] With regard to the fabrication of transistors and integrated circuits, the term "main surface" refers to the semiconductor layer area in and along which a large number of transistors are fabricated. In the following, the term "vertical" is understood to mean essentially orthogonal to the main surface. Typically, the main surface extends along a <100> -Layer of a monocrystalline silicon layer on which the field-effect transistor units are manufactured.

[0013] Fig. Figure 1 shows the layout of a portion of the memory array 10 in a memory chip according to an exemplary embodiment. The memory array 10 comprises a plurality of word lines, which generally extend parallel along a first direction, e.g., the reference y-axis. For simplicity, only some of the word lines (e.g., WL) are shown. L1 , WL S1 , WL S2 , WL R1 , WL R2 , WLR3 and WL R4 ) of the memory array 10 in Fig. Figure 1 shows that the word lines can be divided into two subgroups by a selector region 20. At least one selector transistor is provided in the selector region 20. It should be understood that although two selector transistors (e.g., ST) L and ST R As shown in the diagram, it is possible to use a single selector transistor or more than two selector transistors in selector region 20. Fig. 1 are word lines (e.g. WL) R1 , WL R2 , WL R3 and WL R4 ) on the right side of the selector transistor ST R arranged in a sub-group, while the word lines (e.g., WL) L1 ) on the left side of the selector transistor ST L are arranged in the other subgroup. The word lines (WL) S1 , WL S2 ) each control the selector transistors ST L and ST R .

[0014] The memory array 10 further comprises a large number of memory cells MC (e.g. MC) L11 , MC R11 , MC R12 , MC R13 and MC R14 ) and a multitude of sub-digital lines (or sub-bit lines, also referred to as segmented digital lines) SBL (which are indicated by dashed outlines 210). Each of the memory cells can have a cell size of 4 F 2 The sub-digital lines (e.g., SBL1-SBL7) generally extend parallel along a second direction, e.g., the reference x-axis. Each memory cell comprises a capacitor connected by a transistor to one of the sub-digital lines (or sub-bit lines) SBL. The transistors of the memory cells in the same column can be activated by a corresponding word line WL. Similarly, the memory cells in the same row can be divided into two subgroups by the selector region 20. Fig. 1 are, for example, memory cells (e.g., MC). R11 , MC R12 , MC R13 and MC R14 ) arranged in a sub-group on the right side of selector region 20, while the memory cells (e.g. MC) L11 ) are arranged on the left side of selector region 20 in the other sub-group. According to the embodiment, the number of memory cells in each sub-group can be in a range between 50 and 150; for example, each of the sub-digital lines (e.g., SBL1~SBL7) is coupled via selector region 20 to a corresponding main bit line (or main digital line) MBL, more precisely, via the selector transistors ST L and ST R For example, in Fig. 1. The sub-digital line SBL1 is coupled to the main bit line MBL1, the sub-digital line SBL2 is coupled to the main bit line MBL2, etc. According to the embodiment, each of the sub-digital lines is connected to the selector area 20.

[0015] In Fig. 1. Each main bit line MBL continues parallel to the sub-digital line SBL along the second direction, i.e., along the reference x-axis, and protrudes downwards in a repeating pattern. The continuous main bit lines, which essentially extend between two sub-digital lines, have recurring downward slope jumps. Each main bit line MBL is bent downwards at an angle of, for example, approximately 45° with respect to the reference x-axis in selector region 20, such that each main bit line connects to the selector transistors ST. L and ST R cuts. According to the embodiment of the invention, the selector transistors ST L and ST RVertical transistors are fabricated into the main surface of a semiconductor substrate (not shown). Each selector transistor has a drain region electrically coupled to the corresponding main bit line and a source region electrically coupled to the corresponding sub-digital line. A vertical channel (not shown) is formed between the drain region and the source region. In this embodiment, the main bit lines are arranged above the main surface of the semiconductor substrate, while the sub-digital lines are arranged below or buried beneath the main surface of the semiconductor substrate.

[0016] It will be directed to the Fig. 2A and Fig. 2B referred together. Fig. 2A and Fig. 2B are schematic, sectioned views along lines II' and II-II' in Fig. 1. As in the Fig. 2A and Fig. As shown in Figure 2B, a semiconductor substrate 100 is provided. The semiconductor substrate 100 has a main surface 100a. A plurality of vertical channel transistors 40a and 40b are formed in the semiconductor substrate 100 beneath the main surface 100a. According to the exemplary embodiment, the vertical channel transistors 40a and 40b are manufactured in respective silicon pillars 410, which are isolated from each other by insulating structures 150 and 160, while the vertical channel transistor 40a is arranged in the selector region 20 and operates as the selector transistor described above. The vertical channel transistor 40b, which is arranged outside the selector region 20, operates as an active switching component of each of the memory cells. The vertical channel transistors 40a and 40b can have identical structures and can have sidewall gates 402 (connected by respective word lines in Fig. 1) comprise a source region 404 in a lower part of each silicon column 410 and a drain region 406 in an upper part of each silicon column 410. As mentioned previously, the drain region 406 of the vertical channel transistor 40a is electrically coupled to the main bit line 310, and the source region 404 of the vertical channel transistor 40a is electrically coupled to the sub-digital line 210. A capacitance structure 60b is arranged on each side of the vertical channel transistor 40b and is electrically coupled to the drain region 406 of each of the vertical channel transistors 40b via a contact 50. A reactive capacitance structure 60a may be formed on the vertical channel transistor 40a.

[0017] The Fig. Figures 3A-3C are schematic diagrams illustrating the different layouts of the MBL, SBL (where only four SBL sections are shown and word lines have been ignored for simplicity), and selector area 20 according to an embodiment of the invention. The MBL can be coupled with a corresponding read amplifier (SA). Fig. In 3A, selector region 20 is essentially located in the center of each SBL section. As mentioned previously, at least one selector transistor is provided in selector region 20, and 50 to 150 memory cells can be coupled to the SBL region on each side of selector region 20. The detailed structure of the selector transistor is described in the Fig. 2A and Fig. 2B has been described. Fig. 3B provides two selector areas 20 to couple each SBL section at both ends. Fig. 3C provides three selector regions 20 to couple each SBL segment at both ends as well as in a middle section. By providing such a symmetrical selector configuration, the bit line resistance can be reduced and the signal margin at the line end of each SBL segment can be improved.

[0018] Fig. Figure 4 shows an alternative layout for the SBL sections and the selector regions 20 according to a further embodiment. For the sake of simplicity, the main bit lines, the memory cells arranged along each SBL section, and the word lines coupled to the memory cells are not shown in the figure. As in Fig. As shown in Figure 4, the SBL sections are arranged in an offset manner and alternately coupled to the corresponding selector regions 20, which are located at each end of each of the SBL regions. The offset SBL configuration, as shown in Figure 4, is a staggered arrangement of the SBL sections. Fig. As shown in Figure 4, this reduces the coupling effect that typically occurs between adjacent SBL segments.

[0019] Fig. Figure 5 shows a layout for the SBL sections and the selector areas 20 according to yet another embodiment. For the sake of simplicity, the main bit lines, the memory cells arranged along each SBL section, and the word lines coupled to the memory cells are not shown in the figure. As also in Fig. As shown in Figure 5, the SBL sections are arranged in an offset manner. The selector region 20 is essentially located in the center of each SBL.

[0020] Fig. Figure 6 shows another embodiment of a storage array according to this invention, wherein the same reference numerals denote the same levels, regions, or elements. As in Fig.As shown in Figure 6, the main bit line 310 is arranged lying above the capacitance structures 60 and is insulated from the capacitance structures 60 by at least one dielectric film 610. The main bit line 310 is electrically connected to the vertical channel transistor 40a via a selector contact 660.

[0021] In summary, a memory array (20) is proposed comprising: a plurality of word lines (WL) extending along a first direction; a plurality of memory cells (MC) coupled to a first sub-bit line (SBL) extending along a second direction that is substantially orthogonal to the first direction; a first selector region (20) located substantially in the middle of the first SBL, thereby dividing the plurality of memory cells (MC) into two sub-groups, the first selector region (20) comprising at least one selector transistor (SL) coupled to the first SBL; and a main bit line (MBL) extending substantially along the second direction and coupled to the selector transistor.

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