Amplifier circuit

Abstract

Amplifier circuit (100) comprising: a gain control (101); a first amplifier (103); a second amplifier (105) comprising a plurality of gain stages (401a-401c); wherein the plurality of amplification stages (401a-401c) are connected in series between an input (119) and an output (121) of the second amplifier (105), and each amplification stage (401a-401c) comprises a plurality of amplification units (401a-1 -401a-2; 401b-1 -401b-4; 401c-1 -401c-4) connected in parallel between an input and an output of the amplification stage; a digital-to-analog converter (201) connected between an output of the first amplifier (103) and an input of the second amplifier (105); and a power to gain mapper (203) configured to receive a power control value indicative of a desired power of an output signal at an output of the amplifier circuit (100); wherein the power-to-gain mapper (203) comprises an amplifier circuit-specific calibration pair consisting of a reference gain value and a resulting reference output power of the amplifier circuit (100); and wherein the power to gain mapper (203) is configured to provide a target gain value based on the received power control value and the calibration pair; wherein the gain controller (101) is designed to receive the desired gain value and, on the basis of the received desired gain value, to supply a gain adjustment signal to the first amplifier (103) and, on the basis of the received desired gain value, to provide for each gain stage of the second amplifier (105) an associated switching code which specifies the gain units of the gain stage to be activated in order to activate a specific combination of gain units (401a-1 - 401a-2; 401b-1 - 401b-4; 401c-1 - 401c-4) of the second amplifier (105), such that a combined gain of the first amplifier (103) and the active gain units (401a-1 - 401a-2; 401b-1 - 401b-4; 401c-1 - 401c-4) of the second amplifier (105) corresponds to the received target gain value; wherein the gain controller (101) comprises a discontinuity compensation lookup table (252) in which a discontinuity compensation value is provided for each desired gain value; and wherein the gain controller (101) is further configured to derive the gain adjustment signal in dependence on the discontinuity compensation value provided in the discontinuity compensation lookup table (252) for the desired gain value.

Description

Technical area

[0001] The present invention relates to an amplifier circuit. State of the art

[0002] In general, absolute and relative power adjustment accuracy may be required for any transmitting device. Due to time and cost constraints, this accuracy requirement should be achievable with minimal effort (e.g., calibration).

[0003] In conventional systems, the relationship between the output power and a control parameter for adjusting the power is nonlinear. One disadvantage is a complex (time-consuming) calibration process. Furthermore, the output power curve is highly dependent on process and temperature variations unless significant effort is put into the design.

[0004] US 8 004 368 B2 discloses an amplifier circuit comprising an amplifier controller and a first and a second amplifier, wherein the first and the second amplifier are connected in series, wherein the second amplifier comprises a plurality of gain units, wherein the gain controller is designed to receive a target gain value and, on the basis of the received target gain value, to supply a gain adjustment signal to the first amplifier and, on the basis of the received target gain value, to activate a specific combination of gain units of the plurality of gain units of the second amplifier such that a combined gain of the first amplifier and the active gain units of the second amplifier corresponds to the received target gain value.

[0005] The present invention is therefore based on the object of enabling a high line adjustment accuracy with a lower calibration effort. Summary of the invention

[0006] The present invention relates to an amplifier circuit according to the sole claim. Short description of the characters

[0007] The present invention is described in detail using the attached figures. They show: Fig. 1a is a block diagram of a mobile communication device; Fig. 1b a block diagram of an amplifier circuit; Fig. 2a and Fig. 2b Block diagrams of exemplary implementations of the Fig. amplifier circuit shown in Figure 1b; Fig. 3 is a block diagram of an exemplary implementation of a power to gain mapper and gain control in an amplifier circuit; Fig. 4a is a block diagram of an exemplary implementation of a second amplifier of an amplifier circuit; Fig. 4b to 4d show various exemplary implementations of a power to gain mapper and a gain control that can be implemented in the amplifier circuit that corresponds to the Fig. 4a shown second amplifier; Fig. 5a is a block diagram of an exemplary implementation for a first amplifier and how it may be used in an amplifier circuit; Fig. 5b shows another exemplary implementation of the first amplifier; Fig. 5c is a block diagram of an exemplary implementation of a power to gain mapper and a gain control that can be used in the amplifier circuit that implements the Fig. 5a shown first amplifier; Fig. 5d is a block diagram of an exemplary implementation of a power to gain mapper and a gain control that can be used in the amplifier circuit that implements the Fig. 5b shown first amplifier; Fig. 6a is a diagram showing a relationship between output power control and output power with discontinuities; Fig. 6b the diagram of Fig. 6a with additional discontinuity compensation; Fig. Figure 6c shows an example of how the combined gain can be derived in an exemplary amplifier circuit without discontinuity compensation; Fig. Figure 6d shows another example of how the combined gain can be derived without discontinuity compensation; Fig. 6e an example of how the combined gain can be derived with discontinuity compensation; Fig. 7 an application example for an amplifier circuit; and Fig. 8 a flowchart of a method for amplifying a signal. Detailed description

[0008] Fig. 1a shows a block diagram of an exemplary mobile communication device 800.

[0009] The mobile communication device 800 includes a digital baseband processor 801, an exemplary amplifier circuit 803 (e.g., one of the amplifier circuits described herein), and an antenna 211. The amplifier circuit 803 is coupled between the digital baseband processor 801 and the antenna 211. For example, the digital baseband processor 801 supplies a first amplifier input signal 113 to the amplifier circuit 803, and the antenna 211 is configured to forward an output signal 117 of the amplifier circuit 803.

[0010] The mobile communication device 800 may, in one embodiment, be a portable mobile communication device.

[0011] For example, the mobile communication device 800 can be configured to conduct voice and / or data communication (according to a mobile communication standard) with another (portable) mobile communication device and / or a mobile communication base station. Such a mobile communication device can be, for example, a mobile headset, such as a mobile phone (cell phone), a so-called smartphone, a tablet PC, a broadband modem, a notebook or laptop, as well as a router, switch, repeater, or a PC. Furthermore, such a mobile communication device can be a mobile communication base station.

[0012] The amplifier circuit 803 enables power adjustment in the mobile communication device 800 with low calibration effort, fewer calibration points, easy temperature correction, easy determination of power control values, and a very linear function between the power control values ​​and the achieved output power of the mobile communication device.

[0013] Although in Fig. While amplifier circuit 803 is shown in Figure 1a as part of mobile communication device 800, this amplifier circuit may also be used in other circuits or devices. Various examples of such an amplifier circuit are described in more detail below.

[0014] Fig. 1b shows an exemplary amplifier circuit 100.

[0015] The amplifier circuit 100 includes a gain controller 101, a first amplifier 103, and a second amplifier 105. The second amplifier 105 is connected in series with the first amplifier 103. Furthermore, the second amplifier 105 includes a plurality of amplification units 107a, 107b.

[0016] The gain controller 101 is configured to receive a target gain value 109 and to supply a gain adjustment signal 111 to the first amplifier 103 based on the target gain value 109. Furthermore, the gain controller 101 is configured to activate a specific combination of gain units 107a, 107b of the plurality of gain units 107a, 107b of the second amplifier 105 based on the received target gain value 109 such that a combined gain of the first amplifier 103 and the active gain units 107a, 107b of the second amplifier 105 corresponds to (e.g., is equal to) the received target gain value 109.

[0017] Improved gain adjustment of an amplifier circuit can be achieved when a first amplifier is used in conjunction with a second amplifier, wherein the second amplifier comprises a plurality of gain stages that can be activated and deactivated by the gain controller depending on a desired gain value. By using the combination of the first amplifier 103 and the second amplifier 105, for example, it can be achieved that a relationship between the gain adjustment signal 111 and a gain of the first amplifier 103 is linear. In contrast, the gain units 107a, 107b of the second amplifier 105 can be implemented such that one gain unit 107a, 107b has a fixed (non-adjustable) gain.By having the plurality of gain units 107a, 107b that can be activated and deactivated, a wide range of gain values ​​can be achieved compared to a continuous (and linear) approach. However, by activating and deactivating gain units of the second amplifier 105, discontinuities arise between different possible gain values ​​of the second amplifier 105. By connecting the first amplifier 103 in series with the second amplifier 105, gain values ​​between these discrete gain steps can also be achieved, since the first amplifier 103 provides continuous gain adjustment (without discrete gain steps). Therefore, the amplification circuit 100 provides continuous gain adjustment over a wide range of gain values.

[0018] Furthermore, the amplification circuit 100 includes the following additional features.

[0019] The first amplifier 103 is configured to receive a first amplifier input signal 113 (which is also an input signal 103 of the amplifier circuit 100). Further, the first amplifier 103 is configured to apply a first gain to the received first amplifier input signal 113 in dependence on the gain adjustment signal 111. Further, the first amplifier 103 is configured to supply a second amplifier input signal 115 to the second amplifier 105. The second amplifier input signal 115 is an amplified version of the first amplifier input signal 113. The first amplifier 103 may be a digital amplifier (such as a digital multiplier). Therefore, the first amplifier input signal 113 may be a digital signal. The second amplifier 105 may be an analog amplifier configured to receive the second amplifier input signal 115 as an analog signal.The amplification circuit 100 may include a digital-to-analog converter coupled between the first amplifier 103 and the second amplifier 105, the digital-to-analog converter being configured to convert the second amplifier input signal 115 from the digital domain (as provided by the first amplifier 103) to the analog domain (as received by the second amplifier 105).

[0020] The second amplifier 105 is configured to apply a second gain to the received second amplifier input signal 105 to derive an amplifier circuit output signal 117 (also referred to as output signal 117). The second gain applied by the second amplifier 105 is a sum of the gains applied by the activated gain units 107a, 107b of the second amplifier 105.

[0021] The combined gain of the amplifier circuit 100 (which could also be referred to as the overall gain of the amplifier circuit 100) is the gain difference between the first amplifier input signal 113 and the amplifier circuit output signal 117.

[0022] Furthermore, each of the amplification units 107a, 107b is a discrete amplification unit, which means that in an activated state, this amplification unit applies a gain to a signal received at its input and that in a deactivated state, this amplification unit omits applying the gain to the signal received at its input.

[0023] Furthermore, a gain applied by a gain unit 107a, 107b may be non-adjustable (ie, fixed).

[0024] Nevertheless, the different gain units 107a, 107b may include different gains. For example only, the gains applied by the gain units 107a, 107b may be binary scaled.

[0025] Furthermore, at least certain of the plurality of amplification units 107a, 107b of the second amplifier 105 are connected in parallel between an input 119 and an output 121 of the second amplifier 105. Although in the example in Fig. 1b, the second amplifier 105 comprises only two amplification units 107a, 107b, the number of amplification units in the second amplifier 105 may be different and depends on the number of desired discrete amplification steps to be provided by the second amplifier 105.

[0026] As in connection with Fig. As will be shown in Figure 4a, the second amplifier 105 may comprise a plurality of gain stages connected in series between the input 119 and the output 121 of the second amplifier 105. Each of these gain stages may comprise a plurality of gain units 107a, 107b connected in parallel between an input and an output of the respective gain stage.

[0027] As a Fig. In the example shown in Figure 1b, the gain controller 101 can be configured to supply the second amplifier 105 with a switching code 123 that indicates which of the gain units 107a, 107b of the second amplifier 105 are to be activated. Furthermore, if a plurality of gain stages are present, the gain controller 101 can be configured to supply each gain stage with its own switching code that indicates the gain units of the gain stage to be activated.

[0028] The gain controller 101 may be configured to provide the switching code 123 or the switching codes depending on the target gain value 109.

[0029] Fig. 2a shows another exemplary amplifier circuit 200.

[0030] The amplifier circuit 200 differs in this respect from that in Fig. 1b, as it additionally comprises a digital-to-analog converter 201 connected between the first amplifier 103 and the second amplifier 105. In Fig. 2a, it can therefore be seen that the first amplifier 103 is configured to provide the second amplifier input signal 115 in the digital domain (e.g., as a digital signal 115a), and the second amplifier 105 is configured to receive the first amplifier input signal in the analog domain (e.g., as an analog signal 115b). The digital-to-analog converter 201 is configured to convert the digital signal 115a into an analog signal 115b.

[0031] Furthermore, the first amplifier 103 is a digital gain amplifier. For example, the digital gain amplifier 103 is configured to multiply the first amplifier input signal 113 by the gain adjustment signal 111 provided by the gain controller 101 to derive the digital signal 115a (the first amplifier input signal 115 in the digital domain).

[0032] The receiver 200 further includes a power-to-gain mapper 203. The power-to-gain mapper 203 is configured to receive a power control value 205 indicating a desired output power and, based on the power control value 205, provide the desired gain value 109 (also referred to as TX_Gain). For example, the received power control value 205 may be based on a power adjustment command received from a base station communicating with a mobile communication device including the amplifier circuit 200.

[0033] Therefore, based on this power control value 205, the amplifier circuit 200 adjusts its combined gain by adjusting the gain of the first amplifier 103 and the second amplifier 105 such that the resulting output power at the output 121 of the second amplifier 105 corresponds to the desired output power specified by the power control value 205.

[0034] By the first amplifier 103 in series with the second amplifier 105, a very linear relationship is achieved between the (output) power control value 205 and the achieved output power of the output signal 117 at the output 121 of the second amplifier 105.

[0035] Example implementations for the power gain mapper are presented in conjunction with Fig. 3 to 5d given.

[0036] Furthermore, in one embodiment, the second amplifier 105 comprises four amplification units 107a-107d, nevertheless, as already mentioned, the number of amplification units in the second amplifier 105 may be different.

[0037] Furthermore, the gain control 101 comprises a lookup table 207 which includes an associated value of the switching code 123 for each desired gain value.

[0038] Different values ​​for the switching code 123 are assigned to different combinations of amplification units 107a-107d to be activated.

[0039] As from Fig. As can be seen from Figure 2a, it is not necessary to provide one table entry per possible value of the target gain value 109 in the lookup table 207. It is sufficient to provide one table entry for the values ​​of the target gain value 109 for which a state of the second amplifier 105 (e.g., the number of activated amplification units 107a-107d) is to be changed and for which the value of the switching code 123 is therefore to be changed. Therefore, each value of the switching code 123 can correspond to a predetermined range of (subsequent) values ​​of the target gain value 109.

[0040] Furthermore, the output 121 of the second amplifier 105 is coupled to an antenna 211 (which may be located outside the RF receiver 200).

[0041] Each of the gain units 107a-107d is configured, in an activated state, to apply a corresponding gain to the analog signal 115b received at input 119 of the second amplifier 105 (the second amplifier input signal 115 in the analog domain). Furthermore, a second amplifier gain to be applied by the second amplifier 105 to the analog signal 115b is a sum of the corresponding gains of the activated gain units 107a-107d of the second amplifier (where the combination of activated gain units 107a-107d is determined by the switching code 123).

[0042] Each of the gain stages 107a-107b is a discrete unit (discrete in the sense that it can be activated independently of the other gain units 107a-107d). Each of these discrete stages is configured, in an activated state, to apply a corresponding gain to the analog signal 115b received at the input 119 of the second amplifier 105, and, in a deactivated state, to omit applying the corresponding gain to the analog signal 115b.

[0043] For example, in a deactivated state of an amplification unit 107a-107d, the deactivated amplification unit 107a-107d is bypassed.

[0044] Furthermore, the respective gain of each amplification unit 107a-107d may not be adjustable. Furthermore, all amplification units 107a-107d may be configured to apply the same respective gain to the analog signal 115b.

[0045] Furthermore, at least certain of the amplification units 107a-107d may differ with respect to the respective amplification they apply to the analog signal 115b. For example, the respective amplifications of the amplification units 107a-107d may be binary scaled to each other. Furthermore, as can be seen from Fig. 2a, the first amplifier 103 is a digital amplifier 103 designed to amplify the first amplifier input signal 113 based on the gain adjustment signal 111.

[0046] Fig. 2b shows a block diagram of another exemplary amplifier circuit 250. The amplifier circuit 250 differs from the one shown in Fig. 2a, as an exemplary implementation of the first amplifier 103.

[0047] The amplifier 103 includes a digital multiplier 251 configured to multiply the first amplifier input signal 113 (also referred to as digital data signal 113, transmit signal 113, or input signal 113) by the gain adjustment signal 111 to derive the digital signal 115a (the second amplifier input signal 115 in the digital domain).

[0048] As from Fig. As can be seen in Figure 2b, the relationship between the gain adjustment signal 111 and the resulting power of the second amplifier input signal 115 is a linear relationship. Such a linear relationship can be easily calculated using the digital multiplier 103.

[0049] The gain controller 101 further includes a discontinuity compensation lookup table 252, in which a discontinuity compensation value 253 (also referred to as an error) is provided for each target gain value (and therefore for each target output power of the output signal 117). The gain controller 101 is configured to further derive the gain adjustment signal 111 as a function of the discontinuity compensation value 253 provided in the discontinuity compensation lookup table 252 for the target gain value 119 or the target output power of the output signal 117.

[0050] Discontinuity compensation allows discontinuities in the output power versus power control curves to be eliminated, so that the resulting relationship between the power control value 205, which indicates the target output power of the output signal 117, and the resulting output power of the output signal 117, is a linear relationship (without discontinuities).

[0051] Further details regarding discontinuity compensation can also be found in Fig. 6a-6e shown.

[0052] Fig. 3 shows a block diagram of an example implementation for the power to gain mapper 203 and the gain control 101 as they may be used for an example amplifier circuit.

[0053] The power to gain mapper 203 receives the power control value 205, which indicates the desired target output power of the output signal 117, and derives the target gain value 109 based on the power control value 205.

[0054] The power-to-gain mapper 203 includes an amplifier circuit-specific calibration pair consisting of a reference gain value (TX_Gain_REF) and a resulting reference output power (P_REF) of the gain circuit in which the power-to-gain mapper 203 is used (e.g., the gain circuit 200, 250). The power-to-gain mapper 203 is configured to further derive the target gain value 109 based on this calibration pair. The resulting reference output power at the gain circuit is measured once in a calibration process of the gain circuit and stored in the power-to-gain mapper 203. The meaning of amplifier circuit-specific is therefore that different amplifier circuits may include different resulting reference output powers for the same reference gain value (e.g., as a result of process variations).

[0055] In other words, for a reference gain value, it is sufficient to derive the resulting reference output power, which is then stored in the power-to-gain mapper 203. The desired gain value 109 (TX_Gain) can be derived based on the following formula: TX_Gain=TX_Gain_REF+(P_TARGET−P_REF)*k, where k could be, for example, 1, 2, 4, 8, ... and where P_TARGET is the desired output power of the output signal 117, which is specified by the power control value 205.

[0056] Furthermore, the gain controller 101 is designed to derive the gain adjustment signal 111 (in the logarithmic domain) based on the following formula: Gain_Adj_1=TX_Gain−Gain_Switch(+error_Gswitch), where Gain_Adj_1 is the gain adjustment signal 111 in the logarithmic domain, Gain_Switch is equal to the sum of the gains of the activated gain units 107a-107d of the second amplifier 205, and Error_Gswitch is the discontinuity compensation value 253 provided in the discontinuity compensation lookup table 252 for the target gain value 109 (TX_gain). Discontinuity compensation is optional.

[0057] Furthermore, the gain controller 101 is configured to perform an optional logarithmic-to-linear conversion to derive the gain adjustment signal 111 in the linear domain. Due to the fact that the first amplifier 103 (which is a linear amplifier) ​​can be implemented as a multiplier, the controller 101 is configured to convert the gain adjustment signal 111 from dB to linear (or, in other words, from the logarithmic domain to the digital domain). This dB-to-linear conversion can be performed using tables (e.g., lookup tables) or using an algorithm.

[0058] To control the second amplifier 105 (the discrete gain units 107a-107d), a flexible, reprogrammable strategy is used, implemented with tables (e.g., the lookup table 207 and the discontinuity compensation lookup table 252). It should be noted that no measurement results are necessary for the lookup table 207, since it is sufficient to simply define which value of the switching code 123 is to be provided for each target gain value 109.

[0059] The various forms for deriving the target gain value 109 and the gain adjustment signal 111 can be implemented in hardware or firmware. It should be noted that the discontinuity compensation applied by the gain controller 101 using the discontinuity compensation lookup table 252 is optional and is used to compensate for inaccurate discrete gain steps of the second amplifier 105. These inaccurate gain steps are measured (calibrated) and stored in the discontinuity compensation lookup table 252 prior to use of the gain controller 101. For example, the discontinuity compensation lookup table 252 can be an amplifier-specific discontinuity compensation lookup table 252, such as the calibration pair for determining the target gain value 109.

[0060] In other words, the gain controller 101 is configured to derive the gain adjustment signal 111 based on the difference between the target gain value 109 and the sum of the gains of the activated gain units 107a-107d (indicated by Gain_Switch) and further based on the discontinuity compensation value 253 provided in the discontinuity compensation lookup table 252 for the target gain value 109.

[0061] Fig. 4a shows a block diagram of an exemplary implementation of the second amplifier 105.

[0062] The second amplifier 105 includes a plurality of gain stages 401a, 401b, 401c. The plurality of gain stages 401a, 401b, 401c are connected in series between the input 119 and the output 121 of the second amplifier 105.

[0063] Although in the example of Fig. 4a shows only three gain stages 401a-401c, the number of gain stages connected in series between the input 119 and the output 121 of the second amplifier 105 depends on the number of desired discrete gain steps of the second amplifier 105. Each of the gain stages 401a-401c comprises a plurality of gain units connected in parallel between an input and an output of the respective gain stage 401a-401c. For example, a first gain stage 401a comprises a first gain unit 401a-1 and a second gain unit 401a-2 connected in parallel between an input 403 and an output 405 of the first gain stage 401a. A second amplification stage 401b comprises four amplification units 401b-1 to 401b-4, which are connected between an input 407 and an output 409 of the second amplification stage 401b.A third amplification stage 401c comprises four amplification units 401c-1 to 401c-4, which are connected in parallel between an input 411 and an output 413 of the third amplification stage 401c. Each of the amplification units 401a-1 to 401c-4 can be activated independently of the other amplification units 401a-1 to 401c-4. Furthermore, each of the amplification stages 401a-401c is configured to receive a respective switching code 123a-123c from the gain controller 101.

[0064] The gain control 101 provides the switching codes 123a-123c such that when an amplification circuit comprising the second amplifier 105 is operated as shown in Fig. 4a, at least one amplification unit 401a-1, 401c-4 of each amplifier stage 401a-401c connected in series between the input 119 and the output 121 of the second amplifier 105 is always active.

[0065] In other words, amplifier 105 includes a plurality of gain stages 401a-401c. An input of the first gain stage 401a is coupled to the input 119 of the second amplifier 105. The output 405 of the first gain stage 401a is coupled to the input 407 of the second gain stage 401b.

[0066] The output of the second amplification stage 401b is coupled to the input 411 of the third amplification stage 401c. The output 413 of the third amplification stage 401c is coupled to the output 121 of the second amplifier 105.

[0067] Fig. Figure 4b shows in a block diagram an implementation for the mapper 203 from power to gain and the gain control 101 as used in an amplification circuit together with the Fig. 4a shown second amplifier 105 can be used.

[0068] The Fig. The gain control 101 shown in Figure 4b differs from the one shown in Fig. 3, in that it further comprises a logic circuit 415 which is designed to derive, on the basis of the switching code 123 for the second amplifier 105, a first switching code 123a for the first amplification stage 401a, a second switching code 123b for the second amplification stage 101b and a third switching code for the third amplification stage 401c of the second amplifier 105.

[0069] In other words, the logic circuit 415 is configured to divide the switching code 123 for the second amplifier 105 into a plurality of switching codes 123a-123c for the various gain stages 401a-401c of the second amplifier 105. The switching codes 123a-123c may also be referred to as digital codes for the gain stages 401a-401c of the second amplifier 105.

[0070] Fig. 4c shows a block diagram of another exemplary implementation for the gain control 101, which is designed to provide the plurality of switching codes 123a-123c. In this Fig. 4c, the lookup table 407 includes for each target gain value 109 a respective value for each switching code 123a-123c for each gain stage 401a-401c of the second amplifier 105. In contrast to the Fig. In the implementation shown in Figure 4b, the logic circuit 415 is therefore no longer required, since the lookup table 207 already contains a value for the respective switching code 123a-123c for each gain stage 401a-401c of the second amplifier 105 for each target gain value 109. In other words, the switching codes 123a-123c for the separate gain stages 401a-401c are stored separately in the lookup table 207.

[0071] As from Fig. 4c, the same values ​​can be provided for the switching codes 123a-123c for different values ​​of the target gain value 109. For example, for values ​​1920 to 1951 of the target gain value 109, the first switching code 123a has the value 30, the second switching code 123b has the value 7, and the third switching code has the value 14. Therefore, each value of the switching code 123a-123c can correspond to a predetermined range of values ​​of the target gain value 109. Therefore, it is not necessary in the lookup table 207 to have a table entry for each possible value of the target gain 109. It is sufficient to have table entries provided for values ​​of the target gain 109 for which a state of the second amplifier 105 (ie the number of activated gain units) is to be changed and for which therefore at least one value of one of the switching codes 123a-123c must be changed.

[0072] Fig. Figure 4d shows a block diagram of another exemplary implementation for the power to gain mapper 203 and the gain control 101. The Fig. The implementation shown in Figure 4d differs from the ones shown in Fig. 4c, the power to gain mapper 203 is further configured to derive the target gain value 109 depending on environmental conditions of the gain circuit in which the power to gain mapper 203 is used.

[0073] In detail, the power-to-gain mapper 203 further derives the target gain value 109 based on one or more environmental conditions, such as a power amplifier bias change, the temperature of the amplifier circuit, the frequency of the first amplifier input signal 113, and the supply voltage (such as battery voltage). The power-to-gain mapper 203 may be configured to derive the target gain value 109 based on at least one of these environmental conditions. For example, the power-to-gain mapper 203 is configured to derive the target gain value 109 based on the current environmental condition (e.g.,a combination of the bias voltage of the amplifier circuit, the temperature of the amplifier circuit, the supply voltage of the amplifier circuit and the frequency of the first amplifier input signal 113) to select a compensation value from a plurality of (stored) compensation values ​​and to further derive the target gain value 109 on the basis of this selected compensation value.

[0074] For example, the Fig. 4d, the power to gain mapper 203 determines the target gain value 109 based on the following formula: TX_Gain=TX_Gain_REF+(P_TARGET−P_REF)*k+COMP, where COMP is the compensation value (e.g. power amplifier bias or power amplifier bias change, temperature, frequency, battery voltage or supply voltage).

[0075] The compensation value COMP can be a sum of various compensation values, where each of the various compensation values ​​corresponds to one of the environmental conditions. The compensation values ​​or the various compensation values ​​for the various environmental conditions can be derived, for example, based on one or more lookup tables or based on formulas. Each compensation value can be derived in conjunction with the amplifier-specific calibration pair, since the calibration pair is determined at a specific bias point (for a given power amplifier setting, temperature, battery voltage, and frequency) of the amplifier circuit, thus making it possible to take the fluctuations of these parameters into account when determining the target gain value 109.

[0076] Fig. 5a and Fig. 5b show exemplary implementations for the first amplifier 103, which are based on the assumption that a transmission signal to be amplified by the amplification circuit is a complex signal that can be represented by a real part and an imaginary part or by a magnitude part (or amplitude part) and a phase part. Fig. Figure 5a shows how the first amplifier 103 can be implemented when the transmit signal is represented by a real part and an imaginary part. In this case, the first amplifier input signal 113 is equal to the transmit signal. Fig. Figure 5b shows how the first amplifier 103 can be implemented when the transmit signal is represented by a magnitude part and a phase part. In this case, the first amplifier input signal 113 is equal to the magnitude part of the transmit signal, since only this part needs to be amplified.

[0077] Fig. 5a shows an implementation in which the first amplifier 103 is designed to apply a first gain to a real part 113-1 of the first amplifier input signal 113 and a second gain to an imaginary part 113-2 of the first amplifier input signal 113. Therefore, the Fig. The first amplifier 103 shown in Figure 5a includes a first multiplier 501a and a second multiplier 501b. The first multiplier 501a and the second multiplier 501b are digital multipliers. The first multiplier 501a is configured to receive a first gain adjustment signal 503a (also referred to as Gain_Amp1_RE) and multiply the first gain adjustment signal 503a by the real part 113-1 of the first gain input signal 113 to derive a first multiplier output signal 505a. The second multiplier 501b is configured to receive a second gain adjustment signal 503b (also referred to as Gain_Amp1_IM) and multiply the second gain adjustment signal 503b by the imaginary part 113-2 of the first amplifier input signal 113 to derive a second multiplier output signal 505b.

[0078] The first multiplier output signal 505a forms a real part of the digital signal 115a (the second amplifier input signal 115 in the digital domain), and the second multiplier output signal 505b forms an imaginary part of the digital signal 115a (the second amplifier input signal 115 in the digital domain).

[0079] If the Fig. 5a shown first amplifier 103 in the amplification circuit of Fig. 2a, the digital-to-analog converter 201 includes a first digital-to-analog conversion stage 507a and a second digital-to-analog conversion stage 507b. The first digital-to-analog conversion stage 507a is configured to convert the first multiplier output signal 505a from the analog domain to the digital domain to derive a first analog output signal 509a.

[0080] The second digital-to-analog conversion stage 507b is configured to convert the second multiplier output signal 505b from the digital domain to the analog domain to derive a second analog output signal 509b.

[0081] The first analog output signal 509a forms a real part of the analog signal 115b (the second amplifier input signal 115 in the analog domain), and the second analog output signal 509b forms an imaginary part of the analog signal 115b (the second amplifier input signal 115b in the analog domain).

[0082] In other words, the first amplifier 103 is as in Fig. 5a is configured to adjust the first gain for the real part 113-1 of the first amplifier input signal 113 independently of the second gain applied to the imaginary part 113-2 of the first amplifier input signal 113.

[0083] For example, each of the multipliers 501a, 501b can be implemented as a 12x12-bit multiplier (the gain adjustment signals 503a, 503b can have 12 bits, and the real part 113-1 and the imaginary part 113-2 of the first amplifier input signal 113 can have 12 bits). Furthermore, the first amplifier input signal 113 is supplied to the first amplifier 103 as a first stream of digital data comprising the real part 113-1 of the first amplifier input signal 113 and a second stream of digital data comprising the imaginary part 113-2 of the first amplifier input signal 113.

[0084] Fig. Figure 5b shows another exemplary implementation of the first amplifier 103, where a single multiplier is sufficient. As already mentioned, this implementation of the first amplifier 103 can be used in an amplifier circuit configured to receive the amplifier input signal 113 as a magnitude portion of a transmit signal. Therefore, the first amplifier 103 includes a multiplier 251 configured to multiply the first amplifier input signal 113 by the gain adjustment signal 111 to derive the digital signal 115a (the second amplifier input signal 115a in the digital domain).

[0085] Furthermore, the digital-to-analog converter 201 is shown, which is designed to convert the second amplifier input signal 115 from the digital domain to the analog domain.

[0086] Furthermore, the amplifier input signal 113 may be a transmission signal, which may be represented by the real part 113-1 and the imaginary part 113-2 or may be a magnitude part of a transmission signal.

[0087] The gain adjustment signal 111, 503a, 503b can therefore adjust the level of the magnitude of the transmission signal or the levels of the real part 113-1 and the imaginary part 113-2 of the transmission signal.

[0088] Fig. Figure 5c shows in a block diagram an exemplary implementation of the power to gain mapper 203 and the gain control 101, which in conjunction with the first amplifier 103 as in Fig. 5a. Therefore, the gain controller 101 is configured to provide the first gain adjustment signal 503a for adjusting the first gain applied to the real part 113-a of the first amplifier input signal 113 and to provide the second gain adjustment signal 503b for adjusting the second gain applied to the imaginary part 113-2 of the first amplifier input signal 113. As can be seen from Fig. As can be seen in Figure 5c, the gain controller 101 is configured to derive a base gain adjustment signal 511 based on the target gain value 109 and to scale the base gain adjustment signal 511 by a first scaling factor 513a (or referred to as Gain_Max_RE) to derive the first gain adjustment signal 503a. Furthermore, the gain controller 101 is also configured to scale the base gain adjustment signal 511 by a second scaling factor 513b (also referred to as Gain_Max_IM) to derive the second gain adjustment signal 503b.

[0089] The first scaling factor 513a may be different from the second scaling factor 513b. Therefore, the first gain adjustment signal 503a may be different from the second gain adjustment signal 503b.

[0090] In other words, the gain controller 101 is configured to individually vary the first gain adjustment signal 503a and the second gain adjustment signal 503b.

[0091] Fig. Figure 5c shows the implementation of the gain control 101, in which the base gain adjustment signal 511 is scaled after conversion from dB to linear before the level of the transmit signal is adjusted in the first amplifier 103.

[0092] Furthermore, Fig. 5c shows an exemplary implementation of the gain controller 101, in which the gain controller 101 is further configured to compensate for systematic errors. For this purpose, the gain controller 101 includes a systematic error lookup table 515, in which a respective systematic error compensation value (error_Gswitch_sys) is provided for each target gain value 109. The gain controller 101 is therefore configured to further derive the gain adjustment signals 503a, 503b based on the systematic error compensation value for the target gain value 109. For example, the base gain adjustment value 511 can be derived based on the following formula: Gain_Adj_1=TX_Gain−Gain_Switch(+error_Gswitch+error_Gswitch_sys), where Gain_Adj_1 represents the base gain adjustment value 511 in the logarithmic domain.

[0093] Therefore, Fig. 5c shows an implementation of the gain control 101 in which systematic inaccuracies (i.e., the same behavior for all amplifier circuits) are added to the formula for deriving the basic gain adjustment signal 511. Such systematic errors can be stored once in the integrated circuit (e.g., in the systematic error lookup table 515) and do not require a calibration process.

[0094] Although the compensation of systematic errors in Fig. 5c in connection with the gain control 101, such compensation of systematic errors can also be implemented in the other gain controls presented in the present application.

[0095] If the gain steps of the gain units of the second amplifier 205 are accurate enough, the calculation of the gain adjustment signal 111 or the gain adjustment signals 503a, 503b can be done very easily and the calibration efforts can be kept low.

[0096] In general, the implementation of gain controls can be done in hardware, firmware, or both.

[0097] Fig. Figure 5d shows a block diagram of another exemplary implementation for the power to gain mapper 203 and the gain control 101, which differs from the one shown in Fig. 5c, as the gain control 101 is designed to correspond to the Fig. 5b to supply the gain adjustment signal 111 to the first amplifier 103. The gain controller 101 is configured to derive, based on the desired gain value 109 and the base gain adjustment signal 511, and is configured to scale the base gain adjustment signal 511 by a scaling factor 513 (also referred to as Gain_Max) to derive the gain adjustment signal 111 for the first amplifier 103.

[0098] The following describes how the amplifier circuits described here enable a power adjustment strategy with very linear segments of the power curve (output power as a function of the output control parameter or value). One advantage is that these linear segments of the curve remain constant. Only the discontinuity points can be calibrated. This results in very precise power adjustment accuracy, achieved with less calibration effort.

[0099] Fig. Figure 6a shows a diagram illustrating the relationship between output power control and output power with discontinuities between the different linear segments. The length of the linear segment, or the number of discrete steps, depends on the implementation method (area, current). Using a calibration mechanism, it is possible to find the height of the steps. Thus, the linear segments can be shifted to achieve a linear function, as shown in the diagram. Fig. 6b shown.

[0100] For example, this discontinuity compensation may be performed in the gain controller 101 using the discontinuity compensation lookup table 252 to achieve a linear relationship between the output power control value 205 and the achieved output power of the output signal 117.

[0101] Fig. 6c shows an exemplary implementation for the power-to-gain mapper 203 and the gain controller 101, using a table 607 containing all possible control settings with all parameters for adjusting the power in the linear region and with discrete power steps. For example, the gain controller 101 can be configured to derive, using the table 607, the gain adjustment signal 111 for the first amplifier 103 for adjusting the first gain 601 of the first amplifier 103 and the switching code 123 for the second amplifier 105 for adjusting a second gain 603 of the second amplifier 105. The first gain 601 and the second gain 603 together form a combined gain 605 of the complete amplifier circuit comprising the first amplifier 103 and the second amplifier 105.

[0102] Another solution is in Fig. 6d, in which only the power control settings are used where power steps occur together with the discrete power steps themselves. Using digital hardware, similar sections between the discrete power points can be achieved. For example, the level of a signal can be scaled using a multiplier (e.g., with the multipliers 251, 501a, 501b) in digital signal processing. The linear functionality of the first amplifier 103 can be easily calculated. Such an implementation is shown in Fig. 6d shown.

[0103] Fig. Figure 6e shows another implementation in which inaccurate gain steps of the second amplifier 205 are compensated. These inaccurate gain steps can lead to discontinuities in the curve of output power versus power control (value). To eliminate these discontinuities in the curve of power versus power control, a calibration process can measure the steps and calculate the necessary shift values ​​for all linear segments to arrive at a highly linear function of output power versus power control value. The shift values ​​thus found can be added to the linear power adjustment function (in the gain controller 101 as the discontinuity compensation values). The shift information can be stored, for example, in the discontinuity compensation lookup table 252.In other words, the gain controller 101 is configured to perform discontinuity compensation of inaccurate gain steps of the second amplifier 105 based on the discontinuity compensation lookup table 252 applied to the gain adjustment signals 111, 503a, 503b for the first amplifier 103.

[0104] If the design of the discrete steps is subject to less process variation that can be identified (e.g., by measurement or simulation), the discontinuities can be taken into account in the implementation of the transmitter device and no calibration process is required.

[0105] It is also possible to achieve sufficient dynamic range with the linear power adjustment function; a very easy solution could be to use no power steps at all. Therefore, no calibration process or a very simple calibration process (measuring only the absolute power) may be sufficient, as in conjunction with Fig. 3 and the measurement of the calibration pair.

[0106] Fig. 7 shows an application example for the operation of an exemplary amplifier circuit.

[0107] First, a calibration of the amplifier circuit can be carried out to determine the calibration pair as described in connection with Fig. 3 described.

[0108] Furthermore, an error measurement may be performed during the calibration process to derive the discontinuity compensation lookup table 252. The discontinuity compensation lookup table 252 then includes a discontinuity compensation value for each desired gain value and therefore for each power control value.

[0109] The discontinuity compensation value is derived in such a way that no interpolation is necessary and can be added directly to the linear function to derive the gain adjustment signals 111, 503a, 503b.

[0110] If, in a simple example, the output power is to be increased by one dB (for example, from an actual power of 20 dBm to a target power of 21 dBm), the target gain value 109 is calculated using the gain function used in conjunction with Fig. 3 described formula: PC=PCref+(Psoll−Pref)*k(e.g. k=16).

[0111] In this formula, PC is equal to the target gain value 109, PCref is equal to the reference gain value, Psoll is equal to the target output power specified by the power control value 205, Pref is equal to the reference output power of the amplification circuit, and k is a proportionality constant.

[0112] Based on this formula, an actual gain value can be derived as 1975, and the target gain value can be derived as 1991.

[0113] Advantages of Fig. The advantages of the power adjustment strategy shown in Figure 7 are low calibration effort, fewer calibration points, easy temperature correction, easy determination of the power control values ​​(the target gain value), and a very linear function between the power control value 205 and the achieved output power of the amplification circuit.

[0114] Furthermore, as in Fig. 7 clearly shows a compensation of the ambient conditions (such as in connection with Fig. 4d), with additional compensation values ​​for different environmental conditions (such as cold, ambient or warm for the ambient temperature).

[0115] In addition, Fig. 3, in which the application example of Fig. 7 is also shown. For Fig. 3 shows that, based on the calculated target gain value 1991, the gain controller 101 selects the value for the switching code 123 that corresponds to the next largest target gain value in the lookup table 207. Therefore, the gain controller 101 maintains the value 30 for the switching code 123 corresponding to the target gain value 2015.

[0116] Further, the gain controller 101 selects the compensation value-2 based on the discontinuity compensation lookup table 252 and derives the gain adjustment signal 111 based on the target gain value 1991 and the discontinuity compensation value-2.

[0117] Fig. 8 shows a flowchart of an exemplary method 900 for amplifying a signal.

[0118] The method 900 includes a step 901 of receiving a desired gain value.

[0119] Further, at step 903, the method 900 includes providing a gain adjustment signal to a first amplifier based on the received desired gain value.

[0120] Further, at step 915, the method 900 includes activating a particular combination of gain units of a plurality of gain units of a second amplifier based on the received target gain value such that a combined gain of the first amplifier and the active gain units of the second amplifier corresponds to the received target gain value.

[0121] The method 900 may be supplemented by any of the features and functionalities described herein with respect to the device and may be implemented using the hardware components of the device.

[0122] Although certain aspects have been described in the context of an apparatus, it is understood that these aspects also represent a description of the corresponding method, where a block or device corresponds to a method step or a feature of a method step. Similarly, aspects described in the context of a method step also represent a description of a corresponding block, item, or feature of a corresponding apparatus. Some or all of the method steps may be performed by (or using) a hardware device, such as a microprocessor, a programmable computer, or electronic circuitry.In certain examples which merely describe how the invention can be implemented without these objects themselves constituting objects according to the invention, certain one or more of the most important method steps can be carried out by such an apparatus.

[0123] Depending on specific implementation requirements, examples may be implemented in hardware or software. The implementation may be performed using a digital storage medium, such as a floppy disk, DVD, Blu-ray, CD, ROM, PROM, EPROM, EEPROM, or FLASH memory, on which electronically readable control signals are stored that interact (or can interact) with a programmable computer system to perform the respective method. The digital storage medium may therefore be computer-readable.

[0124] Certain examples, which merely describe how the invention can be implemented without these objects themselves constituting objects according to the invention, comprise a data carrier having electronically readable control signals that can interact with a programmable computer system such that one of the methods described herein is carried out.

[0125] Examples that merely describe how the invention can be implemented, without these subject matters themselves constituting subject matters according to the invention, can generally be implemented as a computer program product with program code, which program code functions to perform one of the methods when the computer program product is run on a computer. The program code can, for example, be stored on a machine-readable medium.

[0126] Other examples which merely describe how the invention can be implemented without these objects themselves constituting objects according to the invention include the computer program for carrying out one of the methods described herein, which is stored on a machine-readable medium.

[0127] A further example, which merely describes how the invention can be implemented without these objects themselves constituting objects according to the invention, comprises a processing means, for example a computer or a programmable logic device, which is configured or adapted to carry out one of the methods described herein.

[0128] A further example, which merely describes how the invention can be implemented without these objects themselves constituting objects according to the invention, comprises a computer on which the computer program for carrying out one of the methods described here is installed.

[0129] A further example, which merely describes how the invention can be implemented without these objects themselves constituting objects according to the invention, comprises a device or system designed to transfer a computer program for carrying out one of the methods described here to a recipient (e.g., electronically or optically). The recipient may, for example, be a computer, a mobile device, a storage device, or the like. The device or system may, for example, comprise a file server for transferring the computer program to the recipient.

[0130] In certain examples that merely describe how the invention may be implemented without these subject matters themselves constituting subject matters of the invention, a programmable logic device (e.g., a field programmable gate array) may be used to perform some or all of the functionalities of the methods described herein. In certain embodiments, a field programmable gate array may cooperate with a microprocessor to perform any of the methods described herein. In general, the methods are preferably performed by any hardware device.

[0131] The examples described above are merely illustrative. It is understood that modifications and variations of the arrangements and details described herein will occur to others skilled in the art. Therefore, it is intended to be limited only by the scope of the appended claim and not by the specific details given herein to describe and explain the examples.

Claims

[1] Amplifier circuit (100) comprising: a gain control (101); a first amplifier (103); a second amplifier (105) comprising a plurality of gain stages (401a-401c); wherein the plurality of amplification stages (401a-401c) are connected in series between an input (119) and an output (121) of the second amplifier (105), and each amplification stage (401a-401c) comprises a plurality of amplification units (401a-1 -401a-2; 401b-1 -401b-4; 401c-1 -401c-4) connected in parallel between an input and an output of the amplification stage; a digital-to-analog converter (201) connected between an output of the first amplifier (103) and an input of the second amplifier (105); and a power to gain mapper (203) configured to receive a power control value indicative of a desired power of an output signal at an output of the amplifier circuit (100); wherein the power-to-gain mapper (203) comprises an amplifier circuit-specific calibration pair consisting of a reference gain value and a resulting reference output power of the amplifier circuit (100); and wherein the power to gain mapper (203) is configured to provide a target gain value based on the received power control value and the calibration pair; wherein the gain controller (101) is designed to receive the desired gain value and, on the basis of the received desired gain value, to supply a gain adjustment signal to the first amplifier (103) and, on the basis of the received desired gain value, to provide for each gain stage of the second amplifier (105) an associated switching code which specifies the gain units of the gain stage to be activated in order to activate a specific combination of gain units (401a-1 - 401a-2; 401b-1 - 401b-4; 401c-1 - 401c-4) of the second amplifier (105), such that a combined gain of the first amplifier (103) and the active gain units (401a-1 - 401a-2; 401b-1 - 401b-4; 401c-1 - 401c-4) of the second amplifier (105) corresponds to the received target gain value; wherein the gain controller (101) comprises a discontinuity compensation lookup table (252) in which a discontinuity compensation value is provided for each desired gain value; and wherein the gain controller (101) is further configured to derive the gain adjustment signal in dependence on the discontinuity compensation value provided in the discontinuity compensation lookup table (252) for the desired gain value.

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