Method for operating a flash memory device and image processing system

Abstract

A method for operating a flash memory device (300) in an image processing system (100) during the execution of a plurality of continuously capturing, CS, operations each generating CS image data, CSID, wherein a memory array of the flash memory device (300) includes a first memory area and a second memory area, the method comprising: - receiving area allocation information,RAI, from a host (200); - allocating a portion of the first memory area in response to the RAI as a reserved CSID buffer area (331B) used to temporarily store only CSID during execution of the CS operations; and - allocating a portion of the second memory area as a normal data area (331C) used to store normal data during a normal programming operation, wherein the first memory area is configured to support data access operations including the normal programming operation performed at a first speed, and the second memory area is configured to support data access operations performed at a second speed slower than the first speed.

Description

[0001] The invention relates to a method for operating a flash memory device and to an image processing system capable of carrying out the method. Such methods and systems are capable of processing continuously acquired image data (CSID). More specifically, the invention relates to devices and methods capable of real-time processing and storing the CSID generated by high-resolution continuously acquired functions in a non-volatile memory device, regardless of a particular data storage capacity (or available data storage capacity) of a single random access memory.

[0002] Many current mobile devices, such as smartphones, tablet personal computers (PCs), and digital cameras, include random access memory (RAM) used during application execution and operating systems, a non-volatile memory device used to store user data, and a camera module capable of generating image data (i.e., still image data and / or continuously captured image data). As the number of camera pixels contained in the camera module increases, the image resolution increases. A larger number of pixels also supports enhanced continuous capture capabilities.

[0003] Current mobile devices that support one or more continuous recording functions typically store the CSID generated by the continuous recording function in a reserved area of ​​RAM. Then, the CSID stored in the RAM is copied to the non-volatile memory device once the reserved area of ​​RAM is full. Such mobile devices repeat this two-step procedure (i.e., first filling a reserved area of ​​RAM and then moving the CSID stored in the RAM to the non-volatile memory) because the RAM can be operated in a write mode that is sufficiently fast to store the CSID in the RAM within given timing constraints. However, the write modes available for current non-volatile memory devices are too slow to meet comparable timing constraints.

[0004] Unfortunately, the size of the reserved RAM area allocated for CSID storage, as well as the size of the write block for the CSID stored in the RAM, as well as the corresponding number of continuously captured images that can be acquired by a given image processing system, are all limited. For example, it has become impractical in many cases to increase the size of the reserved RAM area allocated for CSID storage because certain applications executed by mobile devices during (or in relation to) a continuously capturing function also require considerable RAM space.In other conventional cases, when the data storage capacity of RAM is exceeded by extended continuous recording operations, either the continuous recording operation must be interrupted or the resolution of the resulting CSID is degraded.

[0005] US 2008 / 0 172 520 A1 discloses a memory device comprising a flash memory, a memory controller, and an MLC (multi-level cell) mode selector. A user can choose whether to increase programming speed and reduce the data error rate by selecting the SLC mode, or to expand data capacity by selecting the MLC mode.

[0006] US 2009 / 0 193 183 A1 discloses a non-volatile memory system comprising a non-volatile memory having a plurality of data areas and a memory controller that controls read and write operations to the non-volatile memory. The memory controller successively executes read / write operations in multiple sectors within a selected data area in the non-volatile memory in accordance with a command, sector number, and sector address supplied by a host device.

[0007] US 2006 / 0 171 703 A1 discloses an image capture device with a zoom function. Based on the image data obtained with the image capture device, image data for each of the first and second continuous zoom frames is generated by cropping processing and stored in the buffer memory. The obtained image data and the generated image data are stored in a flash memory.

[0008] The invention is based on the technical problem of providing a method and a system as initially mentioned which are capable of reducing or avoiding at least some of the difficulties found in the prior art as mentioned above.

[0009] The invention solves this problem by providing an operating method having the features of claim 1 and an image processing system having the features of claim 13. Advantageous developments of the invention are specified in the subclaims, the wording of which is hereby incorporated by reference in order to avoid unnecessary repetition.

[0010] Advantageous embodiments of the invention are described below and are shown in the drawings, in which Fig. 1 is a block diagram illustrating an image processing apparatus capable of performing a continuous recording operation and including a flash memory device; Fig. 2 is a block diagram illustrating the flash memory device of Fig. 1 further presents; Fig. 3 is a flowchart summarizing a procedure for performing a continuous recording operation, Fig. 4 is an operational diagram showing an example of an initialization step in the method of Fig. 3 represents; Fig. 5 is a flowchart showing an example of performing a step for a continuous recording operation in the method of Fig. 3 summarizes; Fig. 6 is a flowchart showing an example of performing a step for a shift operation in the method of Fig. 3 summarizes; Fig. 7 is a flowchart showing another example of performing the step for a shift operation in the method of Fig. 3 summarizes; Fig. Figure 8 is a flowchart illustrating a more specific example of moving the CSID to a second storage step of the methods of Fig. 6 and Fig. 7 summarizes; Fig. 9 is a block diagram illustrating a procedure for address mapping that may be performed after a continuous recording operation; and Fig. 10 is a block diagram illustrating another approach for address mapping that may be performed after a move operation.

[0011] Fig. Figure 1 illustrates an image processing system 100 capable of operating in one or more continuous capture (CS) modes of operation according to the invention. The image processing system 100 generally includes a host 200 and a flash memory device 300 and may be implemented within or as part of a personal computer (PC), a laptop computer, a smartphone, a tablet PC, a digital camera, etc.

[0012] In various configurations, host 200 can operate in one or more CS modes that generate "continuously captured image data" or "CSID." Examples of CS modes include a burst mode, a multi-shot mode, a continuous video mode, etc. In certain embodiments of the invention, the CSID generated by host 200 during operation in a CS mode is transmitted "on-the-fly" to flash memory device 300. In this context, those skilled in the art understand the term "on-the-fly" to refer to data processing techniques that process data in real time, immediately as it is generated.

[0013] In a relevant part, the host 200 includes a read-only memory (ROM) 210, a processor 220, a camera module 230, a random access memory (RAM) 240, a flash memory device interface controller 250, and a user interface (UI) 260. In corresponding embodiments of the invention, the host 200 is implemented using system-on-chip (SoC) manufacturing techniques.

[0014] During a CS mode, the camera module 230 can be used differently to generate CSID.

[0015] The ROM 210 may be used to store data defining one or more applications, associated files, and / or operating systems (OS) or host firmware necessary to control the operation of the host 200. The OS and / or host firmware may be executed under the control of the processor 220 after being loaded from the ROM 210 into the RAM 240. The ROM 210 may be implemented using one or more non-volatile memory devices.

[0016] As instructed by the OS and / or host firmware, the processor 220 may be used to control the operation of the camera module 230 and inter-operation of the camera module 230 with the RAM 240, the flash memory device interface controller 250, and the UI 260.

[0017] According to corresponding embodiments of the invention, the RAM 240 is implemented using a volatile memory, such as a dynamic RAM (DRAM), a static RAM (SRAM), a thyristor RAM (T-RAM), a zero-capacitor RAM (Z-RAM), a twin-transistor RAM (TTRAM), and the like. In the illustrated embodiment of Fig. 1, it is assumed that the RAM 240 is a DRAM capable of buffering the CSID on-the-fly.

[0018] During CS mode initialization, processor 220 may be used to generate "region allocation information" (RAI), which is communicated to flash memory device 300 via flash memory device interface controller 250. The RAI typically includes at least one of a defined image resolution, a CS frame rate, and a CS time. In certain embodiments of the invention, the RAI includes a CSID buffer area size or a CSID buffer area size value. A particular RAI may be specified by a manufacturer of image processing system 100 or a participating host including image processing system 100, or it may be defined according to user input communicated to image processing system 100 via UI 260. The provision and use of the RAI are described in some additional detail below.

[0019] In corresponding embodiments of the invention, the host 200 additionally includes an integral display (in Fig. 1 not shown) that can be used to display at least a portion of the UI 260. The display may be conventionally implemented using a thin-film transistor liquid crystal display (TFT-LCD), a light-emitting diode (LED) display, an organic light-emitting diode (OLED) display, an active matrix OLED (AMOLED) display, or a flexible display.

[0020] During a CS mode, the processor 220 may be used to generate a CSID flag (FLAG) indicating that the particular data being communicated from the processor 220 to the flash memory device 300 is the CSID. Furthermore, after (or near) completion of a CS mode, the processor 220 may be used to generate a relocation command (MC), which MC is communicated to the flash memory device 300 via the flash memory interface controller 250. In this regard, the MC may be communicated separately or in conjunction with the CSID flag and / or the RAI. Upon receipt from the flash memory interface controller 250, the MC is interpreted to secure or "allocate" an area within the flash memory device 300 reserved for storing the CSID (hereinafter, "the CSID area").

[0021] In a first hypothetical case (CASE I), the CSIDs provided by the camera module 230 are transmitted directly from the camera module 230 to the flash memory device 300 via the flash memory device interface controller 250. However, in a second hypothetical case (CASE II), the CSIDs provided by the camera module 230 are transmitted indirectly to the flash memory device 300 via the flash memory device interface controller 250, after being buffered in the RAM 240. The buffered CSIDs can then be provided from the RAM 240 to the flash memory device 300 via the flash memory device interface controller 250 under the control of the processor 220.

[0022] In either CASE I or CASE II, an image processing system according to the invention can be used to store the CSID during operation in a non-volatile memory device and at relatively high data processing speeds. That is, the host 200 of Fig. 1 can store the CSID in the flash memory device 300 during operation using the processor 220 and the flash memory device interface controller 250, without waiting until a certain area of ​​the RAM 240 used to store the CSID is completely filled. As a result, the host 200 can process the CSID provided by the camera module 230 on-the-fly and store it in the flash memory device 300 regardless of the specific CSID data storage capacity provided by the RAM 240. Accordingly, the ability of the host 200 to operate in a given CS mode and at a given data resolution is not inherently limited by the data storage capacity or available data storage capacity of the RAM 240.This result compares quite favorably with conventional approaches for providing CS operating modes for certain data processing systems whose data processing capabilities are limited by the use and size of RAM 240. Thus, image processing systems such as the one shown in . Fig. 1, a user a more pleasing functionality of the CS mode.

[0023] In the following description it is assumed that the host 200 of Fig. 1 according to CASE I and CASE II described above, can be selectively operated in any of the first and second modes, respectively. However, this need not always be the case, as further embodiments of the invention can provide a data processing system that can operate only in one of the first and second modes.

[0024] The illustrated embodiment of Fig. Returning to Figure 1, the flash memory device interface controller 250 is used to communicate "write data" during write operations and "read data" during read operations between the flash memory device 300 and the host 200. Furthermore, the flash memory device interface controller 250 can also be used to communicate the CSID, the RAI, the CSID flag, and / or the MC from the processor 220 to the flash memory device 300 (CASE II) and to communicate the CSID from the camera module 230 to the flash memory device 300 (CASE I).

[0025] In certain embodiments of the invention, data processing system 100 allows a user to enter one or more "resolution parameters" (e.g., an image resolution, a CS frame rate, and / or a CS time) via UI 260. Alternatively, one or more resolution parameters may be preset by the manufacturer of data processing system 100. In either case, processor 220 may be used to generate the RAI according to one or more resolution parameters.

[0026] The flash memory device 300 may be implemented in various ways, as will be understood by those skilled in the art. The flash memory device 300 may be physically embedded (or integrated) in the image processing system 100, or it may be provided in a manner that allows physical attachment / detachment to / from the image processing system 100 (e.g., an embedded multimedia card (eMMC)). In corresponding embodiments of the invention, the flash memory device 300 may be a solid-state drive (SSD), a universal flash memory (UFS), a digital security card (SD), a universal serial bus (USB) flash drive, a subscriber identification module (SIM) card, or a universal subscriber identification module (USIM) card.

[0027] For the illustrated embodiment of Fig. 1, a flash memory type memory device was assumed, however, other types of memory devices may be used instead of or in addition to the flash memory. For example, the flash memory device 300 of Fig. 1 may be replaced by another type of electrically erasable programmable read-only memory (EEPROM), magnetic random access memory (MRAM), spin-transfer torque MRAM, conductive bridging RAM (CBRAM), ferroelectric RAM (FeRAM), phase-change RAM (PRAM), resistive RAM (RRAM or ReRAM), nanotube RRAM, polymer RAM (PoRAM), nano-floating gate memory (NFGM), holographic memory, molecular electronics memory device, or insulator-resistance-change memory.

[0028] As described in some additional detail below, flash memory device 300 may include flash memory cells conventionally arranged in one or more memory cell arrays. The individual memory cells may be accessed using single-level data techniques and / or multi-level data techniques according to one or more designated areas in the memory cell array. Thus, in various embodiments of the inventive concept, flash memory device 300 may include single-level memory cells (SLCs) and / or multi-level memory cells (MLCs), such as triple-level cells (TLCs) and / or quad-level cells (QLCs).

[0029] Fig. 2 illustrates the flash memory device 300 of Fig. 1 according to an advantageous realization. Referring to the Fig. 1 and Fig. 2, the flash memory device 300 generally includes a flash controller 310 and a flash memory 330.

[0030] During a CS mode, for example, the flash control unit 310 can be used to control the definition and allocation of various memory areas within a memory cell array 331, the storage of the CSID, and the execution of a move operation, which is activated upon receipt of an MC. In this regard, the flash control unit 310 can be used to interpret a move command MC received from the host 200 and control the execution of a corresponding move operation by the flash memory 330. That is, the flash control unit 310 can be used to monitor a "nominal CSID period" during which the CSID is stored in an assigned CSID memory area. In this way, the flash control unit 310 can control the execution of a move operation according to a nominal CSID period.

[0031] In the Fig. 2, the flash control unit 310 generally includes a central processing unit (CPU) 311 and a RAM 313. The CPU 311 controls the overall operation of the flash memory device 300 as instructed (e.g.) by software located in (e.g.) the ROM 210 of Fig. 1 and / or the flash memory 330, but is loaded into the RAM 313 as firmware 315 for execution. The flash memory 330 of Fig. 1 includes, in addition to the memory array 331, a control logic circuit 333 and a page buffer 335.

[0032] In the Fig. In the embodiment illustrated in Figure 2, the flash memory 330 includes storage space specifically designated (or allocated) as a non-volatile firmware storage area 331A, a CSID buffer area 331B, and a normal data area 331C. In corresponding embodiments of the invention, the firmware storage area 331A and the CSID buffer area 331B may each include an SLC. In contrast, the normal data area 331C may include an SLC and / or an MLC. Consequently, the data access speed (e.g., the programming speed) for the firmware storage area 331A and the CSID buffer area 331B is comparatively faster than a data write speed for the normal data area 331C.In this regard, the firmware storage area 331A and the CSID buffer area 331B form a first storage area of ​​the flash memory 330 capable of supporting data access operations performed at a first speed, and the normal data area 331C forms a second storage area of ​​the flash memory 330 capable of supporting data access operations performed at a second speed, wherein the first speed is faster than the second speed.

[0033] This is consistent with the illustrated embodiment of Fig. 2, at least a certain portion of the first memory area is allocated and operatively designated as a CSID buffer area reserved for storing only the CSID. In contrast, the second memory area can be used to store "normal data" (e.g., user-defined data, payload data, etc.) generated during normally performed read and write operations.

[0034] As in Fig. 2, each of the firmware memory area 331A, the CSID buffer area 331B, and the normal data area 331C may include one or more allocated memory blocks, each memory block including either an SLC or an MLC according to the nature of the allocated area.

[0035] Memory firmware 315, executed by flash controller 310, may be used to interpret an RAI received from host 200. In response to the RAI, the flash controller may allocate one or more blocks (e.g., 331A, 331B-1, 331B-2, and 331C-1 through 331C-5) to each designated area of ​​flash memory 330. For example, assume that blocks 331A, 331B-1, and 331B-2 are blocks that include an SLC configured to support access operations performed at a relatively fast speed. Accordingly, flash controller 310 allocates block 331A to firmware memory area 331A and allocates blocks 331B-1 and 331B-2 to the reserved CSID buffer area.In contrast, the flash control unit 310 allocates to the normal data area 331C blocks 331C-1 to 331C-5, which include an MLC configured to support access operations performed at a comparatively slow speed.

[0036] As in Fig. As further illustrated in Figure 2, each SLC block and each MLC block typically includes a number of pages. In certain embodiments of the invention, a specific page is formed by memory cells (SLC or MLC) arranged along a common word line. In certain embodiments of the invention, the term "block" or "memory block" refers to a defined erase unit, and the term "page" refers to a write (programming) unit and a read unit for the flash memory device 330.

[0037] Under the control of the flash controller 310, the control logic circuit 333 may be used to control the execution of a data access operation (e.g., read, write (program), and / or erase operations) targeting selected memory cells of the flash memory 330. The page buffer 335 may be used to program data (e.g., normal write data or CSID) received from the host 200 into either the first memory area or the second memory area of ​​the flash memory 330, depending on the data type and / or the type of operation being performed.

[0038] Fig. 3 is a general flowchart illustrating one possible procedure for performing a continuous capture (CS) operation using the image processing system 100 of Fig. 1 according to the invention. The method of Fig. 3 includes: performing an initialization operation for the image processing system 100 (S100); then performing a CS operation (S200); and performing a shift operation (S300) as long as the CS operation is performed (S202=no), otherwise (S202=yes) exit. Operational examples for each of these steps are further described below using one or more corresponding embodiments.

[0039] Fig. 4 is an operational diagram illustrating initialization of the image processing system 100 during a CS operation (S100 in Fig. 2). Referring to the Fig. 1, Fig. 2, Fig. 3 and Fig. 4, the image processing system 100 performs an initialization (S100) by transmitting area allocation information (RAI) from the processor 220 via the flash memory device interface controller 250 to the flash controller 310 (S101). In response, the firmware 315 running on the flash controller 310 interprets the received RAI and allocates one or more memory blocks of SLC to a reserved CSID buffer area (S103).

[0040] For example, assuming a given image resolution of 8 MByte per frame, a CS frame rate of 10 frames per second, and a CS time of 2 seconds as resolution parameters conveyed by the RAI, the flash control unit 310 must allocate a minimum of 160 MByte (or 8 MByte x 10 / s x 2s) for the reserved CSID buffer area to store the CSID (S103).

[0041] Upon receipt, the RAI may be stored in a register or at a defined location in the flash memory 330. However, assuming that the flash memory device 300 is an eMMC with an extended card-specific data register (EXT_CSD register) according to certain embodiments of the inventive concept, the RAI may be stored in the conventionally understood VENDOR_SPECIFIC_FIELD of the EXT_CSD register according to a SWITCH command provided by the host 200. Consequently, the reserved CSID buffer area may be allocated according to a specific area allocation information (RAI) stored in the flash memory 330 or according to the VENDOR_SPECIFIC_FIELD field of an EXT_CSD register.In this regard, those skilled in the art will understand that various Joint Electron Devices Engineering Council (JEDEC) standards are available that characterize and / or define the structure, design, and / or operating conditions of eMMCs. These standards can be readily obtained and consulted by referring to http: / / www.jedec.org. For example, the Embedded Multimedia Card (eMMC) Electrical Standard, Version 4.51, published in June 2012 (i.e., JESD84-B451), contains many terms and technical definitions useful for understanding certain embodiments of the inventive concept that incorporate an eMMC.

[0042] Fig. 5 is a flowchart illustrating one possible procedure for storing CSID during the execution of a CS operation by the image processing system of Fig. 1. Referring to the Fig. 1, Fig. 2, Fig. 3 and Fig. 5, once a CS operation starts, a "value for the size of a CSID buffer area" that defines the current size of the reserved CSID buffer area in the flash memory 330 is set to '0' (S210).

[0043] The host 200 may then transmit the CSID flag (FLAG), which indicates that the transmitted data is actually a CSID. The host 200 may also transmit a CSID size value (CSIDSize) that defines the size of the CSID along with the CSID to be stored in the CSID buffer area of ​​the flash memory 330 (S212).

[0044] After receiving the CSID flag, the CSID size value, and the CSID, the flash control unit 310 controls the operation of the flash memory 330 in such a way that a "CSID write operation" is performed for the CSID according to the received CSID size value in the reserved CSID area. To perform the CSID write operation, the flash memory control unit 310 may first determine whether a currently calculated value for the remaining CSID buffer area (Remained_CSIDBufferSize), which indicates the size of the remaining storage space in the CSID buffer area, is larger than the received CSID size value (S214). If not (S214=no), and the remaining storage space in the CSID buffer area is insufficient for storing the CSID in an abnormal case, the incoming CSID must be stored in the second storage area (e.g., the normal data area 331C of Fig. 2) (S230).

[0045] It should be noted that the host 200 may nevertheless transmit the CSID to the flash memory 300 even if the reserved CSID buffer area is too small to store the received CSID in an abnormal case. That is, consistent with the embodiments described with respect to the Fig. 1 and Fig. 2, the flash control unit 310 may control the flash memory 330 such that the received CSIDs are stored in a defined second storage area of ​​the flash memory array 331 instead of in a first storage area. In this regard, an abnormal case may occur, for example, when a subsequent CS operation is performed before the execution of a move operation associated with a previous CS operation can be performed, when the incoming CSIDs are simply too large for a reserved CSID buffer area as currently defined, or when the frequency of CS operations increases.

[0046] However, if the remaining space in the CSID buffer area is sufficient to store the CSID in a normal case (S214=yes), the flash memory control unit 310 calculates a new value for the remaining CSID buffer area (Remained_CSIDBufferSize) by subtracting the CSID size value from the current CSID buffer area value (S216). Next, the flash memory may calculate a size value for a written portion of the CSID buffer area currently in use (Written_CSIDBufferSize). As understood from the above, a new value for the written portion of the CSID buffer area may be calculated by adding the CSID size value to a current value for the written portion of the CSID buffer area (S218).

[0047] Flash memory 330 can now store the CSID in the reserved CSID buffer area within first memory area 331B under the control of flash controller 310. Host 200 can then determine whether the CS operation is complete (S222). If not (S222=no), the process continues as described above until the CS operation is complete.

[0048] As described in the context of normal and abnormal cases, when the size of the available space in the reserved CSID buffer area is larger than the size of the incoming CSID, the flash control unit 310 controls the flash memory 330 in such a way that the CSID is stored in the reserved CSID buffer area in the first storage area 331B; otherwise, the flash control unit 310 controls the flash memory 330 in such a way that the CSID is stored somewhere other than the reserved CSID buffer area, such as in the normal data area in the second area 331C of the flash memory 330.

[0049] In corresponding embodiments of the invention in which the memory device 300 is implemented using an eMMC, the CSID flag may be transmitted using the conventionally understood command (CMD23), and the CSID may be transmitted using the conventionally understood command (CMD25), for example.

[0050] Fig. Figure 6 is a flowchart illustrating one possible operation that can be used to determine the position of a target during operation of an image processing system such as that shown in Fig. 1, to ensure (or reallocate) space in a reserved CSID buffer area. The Fig. The exemplary reassignment operation illustrated in Figure 6 may be performed, for example, during an initialization process for an image processing system or on-the-fly when multiple CS operations are performed by the image processing system.

[0051] Referring to the Fig. 1, Fig. 2, Fig. 3 and Fig. 6, the reallocation operation essentially initializes (involves flushing the CSID therefrom) the reserved buffer area (CSIDBuffer) to maintain acceptable write performance during continuous CS operation of a host device. Thus, it is assumed that multiple sequentially executed CS operations are performed during a period of continuous recording by the host 200. Such multiple sequentially executed CS operations include corresponding move commands transmitted to the flash memory device 300 (S310). Here, the host 200 may adjust the timing of the generation of the move command according to a size of a reserved CSID buffer area as defined by the received range allocation information (RAI).

[0052] For ease of explanation, it is assumed that the respective CSID blocks generated by the sequentially executed CS operations have the same size. Accordingly, the flash control unit 310 initializes a size (MigratedDataSize) of a relocated data unit (MU) to '0' after receiving the relocation command (S312). Subsequently, the flash control unit 310 determines whether the currently allocated size of the reserved CSID buffer area (CSIDBufferSize) matches the received RAI (S314).

[0053] If the size of the reserved CSID buffer area is sufficient to ensure acceptable write performance during CS operations (S314=yes), that is, if the size of the remaining memory space for the reserved CSID buffer area (Remained_CSIDBufferSize) following the execution of a current CS operation is at least equal to or greater than the size of the memory space in the reserved CSID buffer area remaining following the execution of a next CS operation (FCSIDBufferSize), then the operation of reallocating memory space for the reserved CSID buffer area is completed (S318).That is, if the currently remaining size of the available memory space in the reserved CSID buffer area (Remained_CSIDBufferSize) following the execution of a current CS operation is at least as large as the size of the memory space necessary for executing a next CS operation in a sequence of CS operations (FCSIDBufferSize), the write performance can be maintained at acceptable levels, and it is not necessary at this time to perform any further reallocation of memory space with respect to the sequence of CS operations.

[0054] However, if the size of the reserved CSID buffer area (CSIDBufferSize) is insufficient to ensure acceptable write performance (S314=no), that is, if (Remained_CSIDBufferSize) is less than (FCSIDBufferSize) with respect to current and next CS operations targeting the reserved CSID buffer area and considering the current RAI, then as much as one MU value of the CSID currently stored in the reserved CSID buffer area may be copied (or "moved") from the reserved CSID buffer area to the second storage area 331C (e.g., a normal data area) so as to increase the size of the remaining available storage space in the reserved CSID buffer area (i.e., increase Remained_CSIDBufferSize) (S320).

[0055] Once the CSID relocation from the reserved CSID buffer area is completed (S322=yes), a cumulative size of relocated CSID (MigratedDataSize) is increased by as much as MU according to the actual amount of CSID copied from the reserved buffer area (S324).

[0056] Steps S314 and S324 in the preceding reallocation operation may be repeated until the resulting remaining available memory size in the reserved CSID buffer area is sufficient to ensure acceptable write performance for continuous CS operations in a sequence of CS operations. Conversely, if the remaining memory size in the reserved CSID buffer area (Remained_CSIDBufferSize) is determined to be less than MU (S326), the reallocation operation directed to the reserved CSID buffer area is deemed unsuccessful (S328).

[0057] Fig. Figure 7 is a flowchart illustrating another possible operation that can be used to allocate the memory space in a reserved CSID buffer area during an operation of an image processing system such as that shown in Fig. 1 shown, ensure (or reassign).

[0058] The procedure of Fig. 7 is essentially the same as the one previously described in Fig. 6, except that the procedure of Fig. 7 instead of a move command (MC) received within a predetermined time period (S310 in Fig. 6), assumes that no move command will be received during this existing period (S301), and therefore, it is necessary to analyze the size of the current CSID (S303) to ensure acceptable write performance. That is, if the host 200 does not transmit a move command to the flash memory device 300 within a predetermined time (S301), the memory device 300 analyzes the size of the CSID transmitted from the host 200, regardless of the receipt of a move command, and then determines whether to perform a move operation based on a result of this analysis (S303).Thus, when multiple CS operations including a "last CS operation" are performed by the host 200, the CSID provided by the host 200 as the result of the last CS operation and written into the reserved CSID buffer area can be copied by the memory device 300 to the second memory area even without receiving a move command within a predetermined period of time.

[0059] Thus, as explained with reference to the Fig. 6 and Fig. 7, a move operation may be performed by the flash memory device 300 in response to a move command received from the host 200 or in response to the elapse of a predetermined period of time following the execution of a CS operation.

[0060] Fig. 8 is a flowchart further illustrating, in one possible embodiment, the step of moving the CSID from the reserved CSID buffer area to the second memory area (S320 of the Fig. 6 and Fig. 7).

[0061] Referring to the Fig. 6, Fig. 7 and Fig. 8, in order to increase the size of the remaining available storage space in the reserved CSID buffer area (Remained_CSIDBufferSize), as much as one MU value of the CSID currently stored in the reserved CSID buffer area may be moved from the reserved CSID buffer area to the second storage area (S320).

[0062] Subsequently, the flash control unit 310 may compare the size of the copied CSID with the size of a "free area" (ie, an available memory space) in the second memory area (S320-1). As a result of the comparison, if the size of the moved CSID is larger than the size of the free area of ​​the second memory area (S320-1=yes), the step of moving the CSID (S320 of Fig. 6 and Fig. 7) unsuccessful (S320-2).

[0063] However, if the size of the copied CSID is smaller than the size of the free area of ​​the second memory area (S320-1=no), the flash control unit 310 selects a "source block" (e.g., an SLC block) of the reserved CSID buffer area that stores the CSID (S320-3), and further selects a "destination block" (e.g., an MLC block) of the second memory area into which the copied CSID is programmed (S320-4).

[0064] Assuming that the flash control unit 310 selects, for example, the SLC block 331C-1 or the MLC block 331C-2, the value for the size for data (P_DataSize) programmed into the second memory area may be set to '0' (S320-5).

[0065] Flash control unit 310 can then compare the programmed data size (P_DataSize) with the displacement unit (MU) (S320-6). If the displacement unit MU is larger than the programmed data size (P_DataSize), flash memory 330 reads one read unit (RU) from the source block (S320-9).

[0066] Thus, flash memory 330 can store up to the value of one read unit in the destination block (S320-10). A move operation, that is, an operation to move or copy up to the value of the read unit RU from the source block to the destination block, includes an internal move operation using page buffer 335 or an external move operation using RAM 313 included in flash control unit 310, e.g., an SRAM.

[0067] The flash control unit 310 may increase the size of the programmed data (P_DataSize) by as much as the read unit and then perform step S320-6 again.

[0068] The Fig. 9 and Fig. 10 are respective conceptual drawings further illustrating recording of addresses after performing a CS operation according to embodiments of the inventive concept. Collectively, referring to the Fig. 8, Fig. 9 and Fig. 10, when the size of the programmed data P_DataSize is equal to or larger than one shift unit MU (S320-6), data of the source block is invalidated, and image data moved to the destination block is validated (S320-7).

[0069] As in the Fig. 9 and Fig. 10, mapping addresses of an address range for image data as much as the relocation unit MU reads from the source block of the reserved CSID buffer area to the first storage area 331B, and the source block is invalidated (S320-7a), and mapping addresses of an address range for image data stored in the destination block of the second storage area 331C reads as much as the relocation unit MU, and the destination block is validated (S320-7b).

[0070] After completing the address remapping (S320-7), a part of the continuously acquired image data CSID, e.g., the shift unit MU, stored in the reserved area CSIDBuffer of the first memory area 331B is shifted to the second memory area 331C.

[0071] Steps S320-1 to S320-8 are performed until all CSIDs stored in the reserved CSID buffer area of ​​the first memory area 331B have been copied to the second memory area 331C.

[0072] Certain methods and apparatus for processing continuously acquired image data according to embodiments of the invention can ensure acceptable write performance while writing continuously acquired high-resolution image data to a memory device regardless of the data storage capacity of a host-provided RAM used to buffer the CSID during continuous CS operations.

Claims

[1] A method for operating a flash memory device (300) in an image processing system (100) during the execution of a plurality of continuously capturing, CS, operations each generating CS image data, CSID, wherein a memory array of the flash memory device (300) includes a first memory area and a second memory area, the method comprising: - receiving area allocation information,RAI, from a host (200); - allocating a portion of the first memory area in response to the RAI as a reserved CSID buffer area (331B) used to temporarily store only CSID during execution of the CS operations; and - allocating a portion of the second memory area as a normal data area (331C) used to store normal data during a normal programming operation, wherein the first memory area is configured to support data access operations including the normal programming operation performed at a first speed, and the second memory area is configured to support data access operations performed at a second speed slower than the first speed. [2] The method of claim 1, wherein the RAI includes a value for the size of the CSID buffer area (331B) or at least two of an image resolution setting, a CS frame rate, and a CS time. [3] The method of claim 1 or 2, wherein the first memory area includes flash memory cells that are operated only as single-level memory cells, SLC, and / or the second memory area includes flash memory cells that are operated as multi-level memory cells, MLC. [4] The method of any one of claims 1 to 3, further comprising storing the RAI in a memory located in the host (200) during an initialization operation for the image processing system (100). [5] The method of any one of claims 1 to 4, wherein the flash memory device (300) is an embedded multimedia card, eMMC, including an extended card specific device register, EXT_CSD, the register having a VENDOR_SPECIFIC_FIELD field storing the RAI in response to a SWITCH command received from the host (200). [6] The method of any one of claims 1 to 5, wherein the host (200) includes a processor (220) and a camera module (230), and the method further includes for each of the CS operations: - generating the CSID in the camera module (230), generating a CSID flag associated with the CSID, and supplying the CSID and the CSID flag to the processor (220); - storing the CSID in a random access memory, RAM, (240) using the processor (220); and - programming the CSID into the reserved CSID buffer area (331B) using the processor (220) in response to the RAI and the CSID flag. [7] The method of any one of claims 1 to 5, wherein the host (200) includes a processor (220) and a camera module (230) and the flash memory device (300) is an eMMC, and wherein the method further includes for each of the CS operations: - generating the CSID in the camera module (230), generating a CSID flag associated with the CSID, and supplying the CSID and the CSID flag to the processor (220); - storing the CSID in a random access memory, RAM, (240) using the processor (220); and - programming the CSID into the reserved CSID buffer area (331B) using the processor (220) in response to the RAI and the CSID flag, - wherein the CSID flag is transmitted as a context ID in a command CMD23 from the host (200) to the eMMC and the CSID is transmitted as data in a command CMD25 from the host (200) to the eMMC. [8] The method of claim 6, further comprising: - transmitting a move command from the host (200) to the flash memory device (300) after the execution of at least one of the CS operations; and - performing a move operation in response to the move command that copies a portion of the CSID stored in the reserved CSID buffer area (331B) to the second memory area. [9] The method of claim 8, wherein the flash memory device (300) includes a flash controller (310) and a page buffer that, in conjunction with the processor (220), control programming of the CSID into the reserved CSID buffer area (331B). [10] The method of claim 8 or 9, wherein the move command is transmitted from the host (200) to the flash memory device (300) following a predetermined time after the execution of a CS operation. [11] The method of any one of claims 1 to 5, wherein the host (200) includes a processor (220) and a camera module (230), and wherein the method further includes for each of the CS operations: - generating the CSID in the camera module (230), generating a CSID flag indicating a size for the CSID, and providing the CSID and the CSID flag to the processor (220); - storing the CSID in a random access memory, RAM, (240) using the processor (220); and - comparing the size of the CSID with a size of a remaining available memory space in the reserved CSID buffer area (331B); and - programming the CSID into the reserved CSID buffer area (331B) using the processor (220) in response to the RAI and the CSID flag only if the size of the CSID is less than or equal to the size of the remaining available memory space in the reserved CSID buffer area (331B), otherwise programming the CSID into the second memory area using the processor (220). [12] The method of claim 11, wherein storing the CSID in the RAM (240) comprises: - Buffering the CSID in the RAM (240) and then transmitting the CSID on-the-fly from the RAM (240) to the flash memory device (300) during execution of the CS operations. [13] Image processing system with: - a host (200) that generates continuously recorded image data (CSID); and - a flash memory device (300) including a memory cell array (331) including a first storage area and a second storage area, wherein a portion of the first storage area is a reserved CSID buffer area (331B) that temporarily stores only CSID, and the second storage area stores normal data supplied to the flash memory device (300) from the host (200) during a normal programming operation, wherein the first storage area is configured to support data access operations including the normal programming operation performed at a first speed, and the second storage area is configured to support data access operations performed at a second speed slower than the first speed. [14] The system of claim 13, wherein the first memory area includes flash memory cells that operate only as single-level memory cells, SLC, and / or the second memory area includes flash memory cells that operate as multi-level memory cells, MLC. [15] The system of claim 14, wherein the host (200) includes: - a processor (220); - a camera module (230) that supplies the CSID to the processor (220); and - a random access memory, RAM, (240) that buffers the CSID received on-the-fly by the processor (220) during a sequence of continuously capturing, CS, operations performed by the image processing system (100). [16] The system of claim 15, wherein the flash memory device (300) includes a flash controller (310) that defines the reserved CSID buffer area (331B) in the first memory area in response to area allocation information, RAI, received from the processor (220). [17] The system of claim 16, wherein the processor (220) further provides a CSID flag indicating that data transmitted from the host (200) to the flash memory device (300) is the CSID, wherein the flash controller (310) stores the CSID in the reserved CSID buffer area (331B) in response to the CSID flag. [18] The system of claim 17, wherein the flash control unit (310) stores the CSID in the reserved CSID buffer area (331B) only when it first determines that a size of the CSID is less than or equal to a size of remaining available storage space in the reserved CSID buffer area (331B), and otherwise the flash control unit (310) stores the CSID in the second storage area. [19] The system of any one of claims 16 to 18, wherein the processor (220) further provides a move command to the flash memory device (300) and, in response to the move command, the flash controller (310) causes a portion of the CSID stored in the reserved CSID buffer area (331B) to be copied to the second memory area. [20] The system of claim 19, wherein the flash control unit (310) further causes a portion of the CSID stored in the reserved CSID buffer area (331B) to be copied to the second storage area if no move command is received from the host (200) after a predetermined time following the execution of a CS operation. [21] The system of claim 20, wherein the host (200) further includes a flash memory interface controller (250) configured to receive the CSID alternately from the processor (220) and directly from the camera module (230). [22] The system of any one of claims 15 to 21, wherein the RAM (240) is a dynamic RAM, DRAM, and / or wherein the host (200) and the flash memory device (300) are fabricated on a common substrate using a system-on-chip, SoC, fabrication technique.

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