Semiconductor device and method for its manufacture

Abstract

Semiconductor device comprising the following: a substrate (101) having several fins (103) extending from it; a first trough (207) of a first conductivity type in the substrate (101); a second well (209) of the first conductivity type in the substrate (101), wherein the first well (207) has a higher dopant concentration than the second well (209); a gate stack (401, 403, 405) that overlays a transition between the first trough (207) and the second trough (209); a source area (501) of a second conductivity type in the first basin (207); a drain area (503) of the second conductivity type in the second basin (209); wherein the source region (501) and the drain region (503) comprise a mechanical stress-inducing material; and wherein a channel has a first part with a first width (W1) between an edge of the mechanical stress-inducing material in the source region and a transition between the first trough (207) and the second trough (209) and a second part with a second width (W2) between an edge of the mechanical stress-inducing material in the drain region and the transition between the first trough (207) and the second trough (209), wherein the first width is not equal to the second width.

Description

GENERAL STATE OF THE ART

[0001] Semiconductor manufacturers face a constant challenge in adhering to Moore's Law. They continually strive to reduce feature sizes such as active and passive devices, interconnect widths and thicknesses, and power consumption, while simultaneously increasing component density, interconnect density, and operating frequencies.

[0002] As semiconductor devices become smaller, they exhibit a deterioration in performance characteristics. For example, planar metal-oxide-semiconductor field-effect transistor (MOSFET) gates cannot adequately control channels. Furthermore, size reduction leads to lower currents in the channels, leakage currents, and short-circuit channel effects, to name just a few.

[0003] The semiconductor industry has found a solution by moving away from planar structures and introducing three-dimensional (3D) features. For example, channels have the shape of a 3D rod or a similar 3D structure, commonly referred to as a "fin" in so-called FinFET transistors. The 3D channel can be controlled from more than one side, leading to improved device functionality. Furthermore, FinFET transistors exhibit higher drain currents, faster switching speeds, lower switching voltages, reduced leakage currents, and lower power consumption.

[0004] In addition to the challenges discussed above, semiconductor manufacturers must address more specific problems arising from individual component functionalities. For example, high-voltage MOSFETs, which can be used in switches or other high-power applications, must be designed to exhibit high breakdown voltages. This breakdown voltage is typically caused by Zener or avalanche effects and is highly dependent on a single component implementation.

[0005] Document US 2013 / 0200455A1 describes a finned FET with a substrate from which fins protrude, with gate stacks formed across the fins and perpendicular to them. Document KR10O725951B1 discloses a finned CMOS device in which a fin can have a different doping concentration than an underlying substrate, the doping concentration of the fin changing in the vertical direction but remaining constant along the length of the fin.

[0006] Another FinFET structure is described in US patent 9,917,192 B2. Patent DE 10 2013 104 019 A1 describes a method for forming a p-type field-effect transistor (pFET) structure. The method comprises forming a mask layer on a semiconductor substrate, wherein the mask layer has an opening that exposes a semiconductor region of the semiconductor substrate within the opening; forming an n-type wall (n-wall) in the semiconductor region by applying ion implantation of an n-type dopant onto the semiconductor substrate through the opening of the mask layer; and applying germanium (Ge) channel implantation onto the semiconductor substrate through the opening of the mask layer, thereby forming a Ge channel implantation region in the n-wall.

[0007] German patent application DE 10 2012 107 496 A1 describes a method and a component comprising a substrate with a fin. A metal gate structure is formed on the fin. The metal gate structure includes a stress-resistant metal layer formed on the fin such that the stress-resistant metal layer extends to a first height from an STI structural element, the first height being greater than the fin height. A conduction metal layer is formed on the stress-resistant metal layer.

[0008] The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following descriptions in conjunction with the accompanying drawings, whereby Fig. 1 - 5 three-dimensional views are shown, representing a semiconductor component manufacturing process according to one embodiment; Fig. 6 is a sectional view showing a semiconductor component structure according to one embodiment; Fig. 7 is a flowchart that represents a semiconductor component manufacturing process according to one embodiment.

[0010] The corresponding numbers and symbols in the various figures generally refer to corresponding parts, unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily to scale. DETAILED DESCRIPTION OF ILLUSTRATIVE EXECUTION FORMS

[0011] The present disclosure relates to the fabrication of a fin field-effect transistor (FinFET) with high breakdown voltage characteristics. As described in detail below, a substrate and fins are inhomogeneously doped to form regions of high and low dopant concentrations. Subsequently, sources and drains are formed in the high-dopant concentration region and the low-dopant concentration region, respectively. By appropriately adjusting the device parameters, improvements in performance characteristics are achieved, such as increasing the breakdown voltage while maintaining a high drain current.

[0012] Fig. Figures 1-5 represent various intermediate stages of a process for forming a semiconductor device 100 according to one embodiment. First, referring to Fig. Figure 1 shows a substrate 101 having fins 103 extending from it, and a shallow trench insulation (STI) layer 105 on top of the substrate 101 between the fins 103. In some embodiments, the substrate 101 comprises a crystalline silicon substrate (e.g., a wafer), doped or undoped. In other embodiments, the substrate 101 may be made of some other suitable semiconductors, such as gallium arsenide, silicon carbide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. Furthermore, the substrate 101 may include a strained epitaxial layer (EPI layer) to improve its performance characteristics.For example, in some embodiments, all or part of the fins 103 can be replaced by an epitaxial material having a lattice structure different from that of the substrate 101, so that mechanical stress can be applied to a channel region for improved performance characteristics. In still other embodiments, the substrate 101 can be a silicon-on-insulator (SOI) structure.

[0013] In one embodiment, the substrate 101 can comprise p-doped silicon doped with, for example, boron or other suitable acceptor dopants to form the body of an NMOS FinFET device or assembly. In one embodiment, the substrate 101 has a dopant concentration of approximately 1 × 10 15 cm -3 and about 1·10 17 cm -3This disclosure is presented with regard to the formation of an NMOS device or NMOS assembly. In other embodiments, dopants can be selected to form a PMOS device or PMOS assembly.

[0014] The substrate 101 can be formed to create the fins 103 using techniques such as photolithography. Generally, a photoresist material (not shown) is applied, irradiated (exposed), and developed to remove a portion of the photoresist. The remaining photoresist protects the underlying material from subsequent processing steps such as etching. In this example, the photoresist is used to form a structured mask (not shown) to protect sections of the substrate 101 while grooves are etched into the substrate, defining the fins 103. The photoresist is then removed using, for example, an ashing process combined with a wet cleaning process.

[0015] In some embodiments, it may be desirable to use an additional mask layer. During the etching process to shape the substrate 101, portions of the structured photoresist material may also be removed. In some cases, the entire photoresist material may be removed before the completion of the etching process to form the fins 103. In these situations, the additional mask, such as a hard mask, can be used. For example, a hard mask layer (not shown) may comprise an oxide layer (not shown) and an overlying nitride layer (not shown) and may be formed over the substrate 101 to further assist in the process of structuring the substrate 101. The oxide layer may be a thin film comprising silicon oxide, formed, for example, by a thermal oxidation process.In one embodiment, the silicon nitride layer is formed, for example, using low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or similar methods.

[0016] The substrate 101 is etched to remove exposed portions of the substrate 101, forming trenches in the substrate 101, with portions of the substrate 101 between adjacent trenches forming the fins 103. The substrate 101 is etched, for example, by an anisotropic wet etching process or an anisotropic dry etching process. In one embodiment, the anisotropic wet etching on the substrate 101, which comprises silicon, can be carried out using potassium hydroxide (KOH), ethylenediaminepyrocatechol (EDP), tetramethylammonium hydroxide (TMAH), or the like. The anisotropic dry etching process can involve physical dry etching, chemical dry etching, reactive ion etching, or the like. In one embodiment, the ions used in the chemical dry etching of silicon are tetrafluoromethane (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), chlorine gas (Cl2), or fluorine (F2).The typical gases for reactive ion etching of silicon are CF4, SF6, and BCl2 + Cl2. In some embodiments, the grooves can appear as parallel stripes when viewed from above and are closely spaced. In some embodiments, the grooves can be continuous and surround the fins 103. In other embodiments, the fins 103 can be formed using a suitable multi-stage forming process, such as the sidewall image transfer (SIT) process. In one embodiment, the fins 103 can have a height of between approximately 20 nm and approximately 50 nm.

[0017] In some embodiments, the grooves between the adjacent fins 103 in the substrate 101 are filled with a dielectric material to form the STI layer 105. The STI layer 105 can comprise silicon oxide, silicon nitride, fluoride-doped silicate glass (FSG), or a low-k dielectric material. In some embodiments, the STI layer 105 can be formed using a high-density plasma (HDP) CVD process with silane (SiH4) and oxygen (O2) as reaction precursors. In other embodiments, the STI layer 105 can be formed using a subatmospheric CVD process (SACVD process) or a high-aspect-ratio process (HARP), where process gases may include tetraethyl orthosilicate (TEOS) and ozone (O3).In other embodiments, the STI layer 105 can be formed using a dielectric rotational coating process (spin-on dielectric, SOD process), such as hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ). Other processes and materials can be used. Chemical-mechanical planarization (CMP) can be performed to remove excess dielectric material forming the STI layer 105, as shown in [reference]. Fig. Figure 1 shows the hard mask layer can act as a planarization stop layer during the CMP process.

[0018] With reference to Fig. 2 Subsequently, a structured mask layer 201 is used to assist in the further doping of parts of the substrate 101 and the fins 103. The structured mask layer 201 protects an area of ​​the substrate 101 and the fins 103 from additional doping. An unprotected area 203 of the substrate 101 and the fins 103 can be doped to achieve a doping level and / or profile that differs from a protected area 205 of the substrate 101 and the fins 103. Thus, a non-uniform doping profile can be formed in the substrate 101 and the fins 103. As discussed in more detail below, a high-voltage transistor is formed such that one of the source / drain regions is formed in the unprotected region 203 of the substrate 101, while the other of the source / drain regions is formed in the protected region 205 of the substrate 101.For example, as described below, the source region is formed in the unprotected area 203, which is more heavily doped, and the drain region is formed in the protected area 205, which is less heavily doped. The specific pattern of the structured mask layer 201, as described herein, is for illustrative purposes only, and other patterns can be formed depending on the design of the semiconductor device 100. In one embodiment, a photoresist layer is deposited, irradiated (exposed), and developed to remove some of the photoresist material, and is subsequently used as the structured mask layer 201.

[0019] In one embodiment, the protected area 205 has a first width W1 and a first length L1 (viewed from above), as shown in Fig. Figure 2 shows the first width W1, which is between approximately 0.2 µm and approximately 5 µm, and the first length L1, which is between approximately 0.05 µm and approximately 100 µm. The dimensions of the protected area 205 can be changed to fine-tune the performance characteristics of the semiconductor components 100, as shown below with reference to Fig. 6 is described.

[0020] In one embodiment, the substrate 101 can comprise p-doped silicon, which is further doped in the unprotected area 203, thereby forming a p + -Tub 207 in the unprotected area 203 of the substrate 101 and a p - -Tub 209 is formed in the protected area 205 of substrate 101. The dopant concentration of the p + -Tub 207 is determined by the dopant concentration of substrate 101 and the p - -Tub 209 different, and the dopant concentration of the p - -Tub 209 can contain between approximately 1% and approximately 50% of the dopant concentration of the p +-tub 207 lie. In one embodiment, the p + -Tub 207 the dopant concentration between approximately 1E17 cm -3 and about 5E18 cm -3 and indicates the p - -Tub 209 the dopant concentration between approximately 1E15 cm -3 and about 2.5 x 18 cm -3 on.

[0021] In another embodiment, the p + -Tub 207 can be formed before the formation of the trenches and fins 103. For example, the substrate 101 can be masked, and an implantation process, such as the one discussed above, can be carried out to form the p + -Tub 207 to create. As soon as the p + Once the -trough 207 has been formed, the substrate 101 can be masked and structured to form the trenches, and the STI layer 105 can be formed.

[0022] Now referring to Fig. 3. The STI layer 105 is deepened, for example, by a selective wet etching or a selective dry etching process to expose portions of the fins 103. In one embodiment, the (not shown) hard mask layer can be used to assist in etching the STI layer 105 to expose the fins 103. The STI layer 105 can be etched, for example, by anisotropic dry etching processes or an anisotropic wet etching process, as discussed above, to remove exposed portions of the STI layer 105. For example, the STI layer 105 can be deepened using a reactive ion etching process with tetrafluoromethane gas (CF4 gas). In another embodiment, the STI layer 105 can be deepened by a blanket etching process using HF or the like.

[0023] Fig. Figure 4 represents a gate structure comprising a first dummy gate stack 401, a second dummy gate stack 403, and a gate stack 405 formed over the fins 103. The gate stacks can be formed, for example, by depositing a gate dielectric layer and a gate conductive layer over the fins 103 by CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), other suitable methods, and / or combinations thereof. A photolithographic forming process, involving the application of a photoresist material, exposure according to a desired pattern, and development, is used to form the gate dielectric layer and the gate conductive layer to create a gate dielectric 407 and a gate electrode 409 of the first dummy gate stack 401, the second dummy gate stack 403, and the gate stack 405, as shown in Figure 4. Fig. Figure 4 illustrates this. The etching process can include, for example, dry etching, wet etching, and / or other etching methods (e.g., reactive ion etching). The gate dielectric layer can comprise any suitable material, such as silicon oxide, silicon nitride, or a high-k dielectric material. The gate conductive layer can comprise highly doped polysilicon, a metallic material, or any suitable conductive material. In one embodiment, the gate dielectric 407 can have a thickness between about 0.8 nm and about 1.5 nm, and the gate electrode 409 can have a thickness between about 20 nm and about 45 nm.

[0024] Fig. Figure 5 describes the formation of spacers 507, which can be formed along the first dummy gate stack 401, the second dummy gate stack 403, and the gate stack 405. The spacers 507 can comprise one or more layers of a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or combinations thereof. The spacers 507 can be formed, for example, by depositing a dielectric material over the gate structure and anisotropic etching of the dielectric material.

[0025] Fig. Figure 5 further describes the formation of an optional, mechanically stress-inducing material 505 in source regions 501 and drain regions 503 along opposite sides of the gate stack 405. Generally, an epitaxial material having a different lattice constant can be formed over the fins 103 or can replace a portion of the fins 103. The different lattice constants of the substrate 101 material and the epitaxial material can induce strain within the channel regions, thereby enhancing the device performance characteristics. For example, in embodiments where the substrate 101 is silicon, the epitaxial material can be Ge, SiC, GaAs, AlGaAs, SiGe, GaAsP, or another suitable material.In another example, the epitaxial material can be SiC to introduce mechanical stress into the channel and improve the performance characteristics of the NMOS FinFET device, and the epitaxial material can be SiGe to introduce mechanical stress into the channel and improve the performance characteristics of the PMOS FinFET device. In yet other embodiments, multiple epitaxial layers can be used.

[0026] In one embodiment, portions of the fins 103 are removed and replaced with the mechanically stress-inducing material 505. For example, the STI layer 105 can act as a hard mask for a selective etching process to recess exposed portions of the fins 103. In some embodiments, the etching process can be carried out using a chemical selected from Cl₂, HBr, NF₃, CF₄, and SF₆ as the etching gas. In some embodiments, the fins 103 in the source region 501 and the drain region 503 are recessed to a depth of approximately 30 nm to approximately 60 nm below an upper surface of the fins 103 in the channel region. In some embodiments, portions of the STI layer 105 can also be recessed, for example, to form a common source / drain channel. A suitable semiconductor material is epitaxially grown in depressions to form the source regions 501 and the drain regions 503, as shown in Fig. 5 shown.

[0027] The source regions 501 and the drain regions 503 can be doped in situ during the epitaxy process and / or one or more subsequent doping processes, e.g., by implantation. For example, epitaxially grown silicon source / drain regions can be doped with n-type dopants, e.g., phosphorous or the like, to form an NMOS device, or with p-type dopants, e.g., boron or the like, to form a PMOS device. Several doping processes can be used to create a desired doping profile that includes, for example, low-doped drain regions (LDD regions) and the like. In one embodiment, the source regions 501 and the drain regions 503 can have a dopant concentration of approximately 5 × 18 cm⁻¹. -3 and about 1E20 cm -3 exhibit.

[0028] Further manufacturing steps can be performed on the semiconductor component 100. For example, a (below with reference to Fig. 6. The interlayer dielectric (ILD) layer (discussed below) is applied over the source regions 501, the drain regions 503, the first dummy gate stack 401, the second dummy gate stack 403, and the gate stack 405. The ILD layer can be formed by a suitable technique, such as CVD, ALD, and spin coating (SOG). Subsequently (see below with reference to Fig. 6 contacts are formed to provide electrical contacts to the source areas 501, the drain areas 503, and the gate stack 405. The contacts can be formed by a suitable method, such as various deposition processes, damascene processes, dual damascene processes, or similar methods.

[0029] Fig. Figure 6 shows a sectional view of the area in the Fig. Figure 5 shows the semiconductor device 100 along a line AA' after the ILD layer and contacts have been formed. The ILD layer 601 is formed from one or more layers of dielectric material, such as silicon oxide, oxynitride, low-k dielectric, or other suitable materials, by a suitable technique, such as CVD, ALD, and spin coating (SOG). To remove excess dielectric material from the ILD layer 601, a CMP process can be performed.

[0030] The contacts 603 are formed in the ILD layer 601 to provide electrical contacts to the source regions 501, the drain regions 503, and the gate stack 405. The ILD layer 601 can be structured using photolithography techniques to form trenches and feedthroughs. The contacts 603 are formed by applying a suitable material to the trenches and feedthroughs of the ILD layer 601 using various deposition and coating processes or similar methods. Furthermore, the contacts 603 can include one or more barrier / adhesion layers (not shown) to protect the ILD layer 601 from diffusion and metallic contamination. The barrier layer can comprise titanium, titanium nitride, tantalum, tantalum nitride, or other alternatives. The barrier layer can be formed using PVD, CVD, or similar processes.

[0031] The contact material 603 can include copper, a copper alloy, silver, gold, tungsten, tantalum, aluminum, and the like. In one embodiment, the steps for forming the barrier layer and the contacts 603 can include blanket formation of the barrier layer, application of a thin nucleation layer of a conductive material, and filling the trenches and feedthroughs in the ILD layer 601 with the conductive material, for example, by coating. A CMP is then performed to remove excess barrier layer and conductive material.

[0032] With reference to Fig. Figure 6 shows various dimensions and relative distances that can be adjusted to achieve a desired component specification. A first distance X1 extends from a left edge of the mechanically stress-inducing material 505 to a right edge of the p + -Tub 207, and a second distance X2 extends from the right edge of the p+ -Tub 207 to a right edge of the mechanical stress-inducing material 505. In one embodiment, the ratio of the first distance X1 and the second distance X2 is between approximately 0.1 and approximately 10. A channel length between the source regions 501 and the drain regions is determined by adding the first distance X1 and the second distance X2 and is between approximately 0.01 µm and approximately 1 µm.

[0033] The first dummy gate stack 401 has a second width W2 between approximately 0.01 µm and approximately 1 µm, and the second dummy gate stack 403 has a third width W3 between approximately 0.01 µm and approximately 1 µm. In one embodiment, the second width W2 and the third width W3 can be equal. In another embodiment, the second width W2 and the third width W3 can be different. A third distance X3 between a right edge of the first dummy gate stack 401 and a left edge of the gate stack 405 is between approximately 0.05 µm and approximately 0.5 µm. A fourth distance X4 between a right edge of the gate stack 405 and a left edge of the second dummy gate stack 403 is between approximately 0.05 µm and approximately 0.5 µm. In one embodiment, the third distance X3 and the fourth distance X4 can be the same. In another embodiment, the third distance X3 and the fourth distance X4 can be different.

[0034] These widths and relative distances can be set for a single design or application. For example, in one embodiment with the first distance X1 greater than the second distance X2, the semiconductor device 100 can exhibit high breakdown voltage characteristics while exhibiting low drain current characteristics. In another embodiment with the first distance X1 smaller than the second distance X2, the semiconductor device 100 can exhibit low breakdown voltage characteristics while exhibiting high drain current characteristics. The first distance X1 and the second distance X2 can be selected according to the design specifications of the semiconductor device 100 to achieve the desired voltage and current performance characteristics. The second width W2 and the third width W3 can also be modified to control the dimensions of the source regions 501 and the drain regions 503.

[0035] Fig. 6 further states that the source areas 501 the p + -Tub 207 directly below, while the drain areas 503 the p - -Tub 209, e.g., the lightly doped substrate, directly below. The semiconductor component 100 with a drain-PN junction, which connects the drain regions 503 and the p - -Tub 209 includes a higher breakdown voltage V BR compared to the case where the drain-PN transition originates from drain areas 503 and p + -Tub 207 exists. In one embodiment, the breakdown voltage V BR of the semiconductor component 100 between approximately 8 V and approximately 15 V.

[0036] Fig. Figure 7 is a flowchart illustrating a process that can be carried out to fabricate a semiconductor device according to one embodiment. The process begins in step 701, where trenches are formed in a substrate, such as the one described above with reference to Fig. 1 was discussed. Adjacent trenches define a fin that is inserted between the trenches. In step 703, a trench insulation layer is formed above the substrate and between the fins by applying a dielectric material to the trenches and performing chemical-mechanical planarization to remove excess dielectric material. After forming the trench insulation layer, in step 705 an area of ​​the substrate and the fins is doped as described above with reference to Fig. 2 described.

[0037] In step 707, the trench insulation layer is deepened and part of the fins are exposed, as above with reference to Fig. 3 discussed. Then, in step 709, gate stacks are formed, such as the one discussed above with reference to Fig. 4 was discussed. The fins are deepened in step 711, and source / drain areas are epitaxially grown in openings of the fins, such as the one discussed above with reference to Fig. 5 was discussed. Finally, in step 713, a metallization layer is formed, such as the one described above with reference to Fig. 6 was discussed. The metallization layer can include an intermediate dielectric layer with contacts embedded in the intermediate dielectric layer to provide electrical contacts to source / gate / drain regions.

[0038] A method for manufacturing an NMOS FinFET device is described above in relation to Fig. The processes described in Figures 1-7 are for illustrative purposes only. However, it is obvious to those skilled in the art that similar manufacturing processes can be used to create a PMOS FinFET device.

[0039] In one embodiment, a semiconductor device comprises a substrate having multiple fins extending from it, a first well of a first conductivity type in the substrate, and a second well of the first conductivity type in the substrate, the first well having a higher dopant concentration than the second well. The semiconductor device further comprises a gate stack superimposed on a transition between the first well and the second well, a source region of a second conductivity type in the first well, and a drain region of the second conductivity type in the second well.

[0040] In one embodiment, a semiconductor device comprises a substrate having multiple grooves and fins inserted between adjacent grooves, the substrate being lightly doped with a first conductivity type. The semiconductor device further comprises a first region in the substrate, the first region being lightly doped with the first conductivity type, wherein the first region has a higher dopant concentration than the dopant concentration of the substrate and a second region in the substrate, the second region having the dopant concentration of the substrate. The semiconductor device further comprises a first source / drain region of a second conductivity type in the first region and a second source / drain region of the second conductivity type in the second region.

[0041] In one embodiment, a method for manufacturing a semiconductor device comprises providing a substrate, wherein the substrate has a first dopant concentration of a first conductivity type in a first region and a second dopant concentration of the first conductivity type in a second region, wherein the first dopant concentration is greater than the second dopant concentration, and wherein the substrate has one or more fins extending therefrom, the one or more fins extending through the first region and the second region.The method further comprises forming a gate stack over the one or more fins, wherein the gate stack overlaps a transition between the first region and the second region, and forming source / drain regions on opposite sides of the gate stack such that a first source / drain region is located in the first region and a second source / drain region is located in the second region.

Claims

[1] Semiconductor device comprising the following: a substrate (101) having several fins (103) extending from it; a first trough (207) of a first conductivity type in the substrate (101); a second well (209) of the first conductivity type in the substrate (101), wherein the first well (207) has a higher dopant concentration than the second well (209); a gate stack (401, 403, 405) that overlays a transition between the first trough (207) and the second trough (209); a source area (501) of a second conductivity type in the first basin (207); a drain area (503) of the second conductivity type in the second basin (209); wherein the source region (501) and the drain region (503) comprise a mechanical stress-inducing material; and wherein a channel has a first part with a first width (W1) between an edge of the mechanical stress-inducing material in the source region and a transition between the first trough (207) and the second trough (209) and a second part with a second width (W2) between an edge of the mechanical stress-inducing material in the drain region and the transition between the first trough (207) and the second trough (209), wherein the first width is not equal to the second width. [2] Semiconductor device according to claim 1, comprising the following: a first dummy gate (401) located above the first tub (207), and a second dummy gate (403) located above the second tub (209). [3] Semiconductor device according to claim 1 or 2, wherein the breakdown voltage is between about 8 V and about 15 V. [4] Semiconductor device according to one of the preceding claims, wherein a channel length between source region (501) and drain region (503) corresponds to the sum of the first distance (X1) and the second distance (X2). [5] Semiconductor device according to one of the preceding claims, wherein the channel length is between about 0.01 µm and about 1 µm. [6] Semiconductor device according to one of the preceding claims, wherein the first well (207) has a first dopant concentration of about 1.10 17 cm -3 and about 5·10 18 cm -3 exhibits. [7] Semiconductor device according to claim 5, wherein the second well (209) has a second dopant concentration and the second dopant concentration is between about 1% and about 50% of the first dopant concentration. [8] Semiconductor device according to one of the preceding claims, wherein the ratio of the first width (W1) and the second width (W2) is between 0.1 and 10. [9] Method for manufacturing a semiconductor device, the method comprising: Providing a substrate (101) wherein the substrate (101) has a first dopant concentration of a first conductivity type in a first region (207) and a second dopant concentration of the first conductivity type in a second region (209), wherein the first dopant concentration is greater than the second dopant concentration, wherein the substrate (101) has one or more fins (103) extending therefrom, the one or more fins (103) extending through the first region and the second region; Forming a gate stack (401, 403, 405) over the one or more fins (103) (103), wherein the gate stack (401, 403, 405) overlaps a transition between the first area and the second area; Forming source / drain regions (503) on opposite sides of the gate stack (401, 403, 405), such that a first source / drain region (503) is located in the first region and a second source / drain region (503) is located in the second region, wherein the source / drain regions (503) comprise a mechanical stress-inducing material; and Forming a channel with a first part with a first width between an edge of the mechanical stress introducing material in the source / drain region (503) in the first region and a transition between the first region (207) and the second region (209) and a second part with a second width between an edge of the mechanical stress introducing material in the source / drain region (503) in the second region and the transition between the first region (207) and the second region (209), wherein the first width is not equal to the second width. [10] Method according to claim 9, wherein the second dopant concentration is between about 1% and about 50% of the first dopant concentration. [11] The method of claim 9 or 10, further comprising: Deepening part of the fins (103) in the first area and in the second area and epitaxial growth of a semiconductor material over deepened parts of the fins (103). [12] Method according to any one of claims 9 to 11, further comprising forming a first dummy gate (401) in the first region and a second dummy gate (403) in the second region. [13] Method according to any one of claims 9 to 12, further comprising forming contacts (603) to provide electrical contacts to the sources, drains and gate. [14] Method according to any one of claims 9 to 13, wherein the first dopant concentration is between about 1.10 17 cm -3 and about 5·10 18 cm -3 lies. [15] Method according to any one of claims 9 to 14, wherein a channel length is between about 0.01 µm and about 1 µm.

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