CAPACITY BANK SYSTEM, CAPACITY CELL AND METHOD

Abstract

Capacity bank system (104; 500), comprising: several voltage-controlled capacity cells (200; 532) with an antiparallel configuration and designed for selective provision of cell capacities; and an output node (216; 534) coupled to the multiple capacitance cells (200; 532) designed to provide an input capacitance, wherein the capacitance cells (200; 532) have a capacitance step that is smaller than the smallest capacitor used in the capacitance cells (200; 532), wherein at least one of the capacitance cells (200; 532) is configured with a first capacitor (202) and a second capacitor (204) connected in opposite directions, wherein the first capacitor (202) has a first capacitance (C1) and the second capacitor (204) has a second capacitance (C2) that is greater than the first capacitance (C1) by a difference amount (ΔC), wherein the difference amount (ΔC) is smaller than the first capacitance (C1).

Description

STATE OF THE ART

[0001] Oscillators are types of electronic circuits that generate repeating, oscillating signals. Oscillators are used in a wide variety of electronic devices for diverse purposes, including timing, clock signals, communication signals, modulation signals, and the like.

[0002] In general, oscillator circuits are designed to provide a specific signal at a selected frequency. The type of signal depends on the device using it. The selected frequency can be static or vary over time, also depending on the device using the oscillation signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Fig. Figure 1 is a block diagram of an oscillation system that uses a capacitor bank with a relatively small capacitance step.

[0004] Fig. Figure 2 is a diagram of a capacity cell that can be used in a capacity bank.

[0005] Fig. Figure 3 is a circuit diagram of the capacitance cell with a control bit set to an ON state.

[0006] Fig. Figure 4 is a circuit diagram of the capacitance cell with a control bit set to an OFF state.

[0007] Fig. Figure 5 is a diagram of a capacity bank that provides an input capacity with a relatively small capacity step.

[0008] Fig. Figure 6 is a flowchart of a procedure for providing or generating input capacity. DETAILED DESCRIPTION

[0009] The present invention will now be described with reference to the accompanying drawing figures, whereby the same reference numerals are used throughout to designate the same elements, and wherein the structures and devices shown are not necessarily drawn to scale.

[0010] Systems and methods are disclosed that provide a capacitance step smaller than a minimum physical capacitor supported by a given technology.

[0011] The frequency resolution of a device or circuit is related to the capacitance resolution or capacitance step of the capacitor bank used. Certain applications may require a higher or larger frequency resolution. Consequently, a correspondingly higher capacitance resolution or smaller capacitance step size may also be necessary.

[0012] The capacitance step for capacitor banks is typically the smallest or minimum-sized capacitor in the capacitor bank for a given technology. Thus, the step size is limited by the size of available capacitors. Consequently, the frequency resolution for circuits using such a capacitor bank is also limited by the size of available capacitors.

[0013] Fig. Figure 1 is a block diagram of an oscillation system. 100 , which uses a capacity bank with a relatively small capacity step. The system 100 It can be used to generate an oscillation signal, such as one used for clock signals, communication devices, and the like. The system 100 uses a relatively small capacitance step to produce a selected frequency for the oscillation signal.

[0014] The system 100 includes an LC resonator circuit102 , a capacity bank 104 and a control system 106 The resonator circuit 102 is used to generate an oscillation signal 112 It is used as an output signal with a selected frequency. The frequency of the oscillation signal is determined by an input capacitance. 110 specified. The frequency can be adjusted by varying the input capacitance. 110 vary. A smallest amount of frequency variation for the oscillation signal 112 is referred to as the frequency step.

[0015] The capacity bank 104 It provides a capacity value that varies by one capacity step. This variation is the smallest capacity change that the capacity bank can handle. 104 can provide. The frequency step size is a function of the capacitance step size. The smaller the capacitance step, the smaller the frequency step.

[0016] The capacity bank 104represents the input capacity 110 selectively the resonator resonant circuit 102 ready. The input capacity 110 is according to a control word 108 provided. The control word 108 Selects states for one or more capacity cells in the capacity bank. The selected states result in a selected capacity and a selected capacity step for the input capacity. 110 .

[0017] The capacity bank 104It comprises one or more capacity cells with varying capacity values. Examples of suitable capacity cells are given below. Each cell operates with an OFF state and an ON state. The OFF state provides an initial capacity. The ON state provides a second capacity equal to the initial capacity plus a cell difference amount. The cell difference amount is based on an integer coefficient multiplied by a base capacity difference amount. The integer coefficient ranges from 1 to N. The base capacity difference amount correlates with the capacity step for the bank. 104 The capacitance step is smaller than the smallest capacitance size of capacitors in the capacitance cells.

[0018] The control 106 selects by setting the control word 108 The control word specifies a frequency and / or frequency change based on a particular value. 108In one example, it has several control bits, where each control bit represents a capacity cell of the capacity bank. 104 switches ON or OFF. The number of commands for the control word 108 The bit used can vary. In one example, the control word is... 108 an 8-bit word preceded by integer coefficients in the range of 1 to 128.

[0019] It goes without saying that a modification of the system 100 A (not shown) sigma-delta modulator can be used to dither the capacitor bank in order to achieve a finer step. This could be accomplished by switching the capacitor bank at a higher rate than required for oversampling. Thus, the capacitor bank can 104 can be combined with a sigma-delta modulator to control or adjust the capacitance step and frequency.

[0020] Fig. 2 is a diagram of a capacity cell 200, which can be used in a capacity bank. For example, the cell can 200 in the capacity bank described above 104 can be used. The capacity cell 200 provides a capacitance step that is smaller than capacitors used in the cell by using two antiparallel or oppositely connected voltage-controlled capacitors, such as MOS capacitors, where one capacitor is slightly larger than the other.

[0021] The capacity cell 200 includes a first capacitor 202 , a second capacitor 204 , a control node 206 , a central node 208 , a coupling resistor 210 , a split supply voltage 212 , a coupling capacitor 214 and an output node 216 The coupling capacitor 214 couples the central node 208 with the output node 216The coupling resistance 210 connects the central node 208 with the shared power supply 212 .

[0022] The first and second capacitor 202 and 204 These are voltage-controlled capacitors. The first capacitor 202 is opposite or antiparallel to the second capacitor 204 coupled. Thus, a positive end of the first capacitor 202 coupled to the central node and a negative end of the first capacitor 202 is coupled to the control node. A negative end of the second capacitor 204 is coupled to the center node and is a positive end of the second capacitor 204 is connected to the control node. Consequently, the positive end of the first capacitor 202 with the negative end of the second capacitor 204 coupled and the negative end of the first capacitor 202is connected to the positive end of the second capacitor 204 coupled. The first capacitor 202 and the second capacitor 204 are connected in opposite directions or antiparallel.

[0023] The first capacitor 202 It has a first capacitance. Typically, the first capacitor is 202 selected so that it has a relatively small capacitance value. In one example, the first capacitor 202 a smallest capacitance value for a type of capacitor. The second capacitor 204It has a second capacitance that is larger than the first capacitance. Generally, the second capacitance is slightly larger than the first. This difference is called the cell difference. Thus, the second capacitance can be described as equal to the first capacitance plus the cell difference. The cell difference is based on an integer coefficient multiplied by a base capacitance difference. The integer coefficient ranges from 1 to N. The capacitance step (also called the base capacitance difference) is typically smaller than the first capacitance of the first capacitor. 202 .

[0024] The control node 206It receives a control bit that corresponds to a state. In one example, the control bit corresponds to an OFF state and an ON state. In the OFF state, the control bit results in a 0 or ground connection. In the ON state, the control bit causes a supply voltage VDD to be applied to the control node. 206 The system is coupled. The supply voltage is higher than the divided supply voltage. 212 .

[0025] The exit node 216 provides a cell capacity that depends on the control bit. In one example, the cell capacity is part of an input capacity provided by a capacity bank from which the cell is drawn. 200 The antiparallel configuration results in a situation where, in one state, part of the cell capacity is equal to the first capacity, and in another state, part is equal to the second capacity. Further details regarding the functioning of the states are given below.

[0026] It goes without saying that variations of the cell 200 should be taken into consideration, and specific conditions and supply voltages should be provided to facilitate understanding.

[0027] Fig. 3 and Fig. Figure 4 shows an example of how the capacity cell works. 200 for different states. The figures show an ON state and an OFF state to aid understanding. However, it is understood that the capacity cell 200 and variations thereof may use other states besides those described below.

[0028] Fig. 3 is a circuit diagram of the capacitance cell 200 with a control bit set to an ON state. The cell components 200 are described in more detail above. In this example, the control bit set to ON results in an ON voltage. 318 at the control node 206 is created.

[0029] In this example, the ON voltage 318 set so that it is the supply voltage. Thus, one lower side of the capacitor configuration is at the control node. 206 connected to the supply voltage. The capacitor configuration includes the first and second capacitors. 202 and 204 , the control node 206 and the central node 208 . A top side of the configuration at the center node 208 is via the coupling resistance 210 with the shared supply 212 connected. Thus, the control node is located 206 at a higher potential than the central node 208 .

[0030] The first capacitor 202 is with its negative end with the relatively higher control node 206 connected. Thus, the first capacitor 202 OUT OF 320 switched and essentially from the cell 200removed. The first capacitor 202 and its first capacity does not contribute to that at the output node 216 provided cell capacity.

[0031] The second capacitor 204 is with its positive end with the relatively higher control node 206 connected and its negative end to the relatively lower central node 208 The connected capacitor is oriented. Consequently, its positive end is at a higher potential than its negative end. The second capacitor is switched ON and is part of the configuration. The second capacitor 204 and its second capacity contributes to that at the output node 216 provided cell capacity.

[0032] Fig. 4 is a circuit diagram of the capacitance cell 200 with a control bit set to an OFF state. In this example, the OFF control bit results in an OFF voltage. 424 at the control node206 is created.

[0033] In this example, OFF is set to 0 volts or ground. The lower side of the capacitor configuration at the control node. 206 is connected to ground. The upper side of the configuration at the center node 208 is via the coupling resistance 210 with the shared supply 212 connected. Thus, the control node is located 206 at a lower potential than the central node 208 .

[0034] The first capacitor 202 With its negative end, it is connected to the relatively lower control node. 206 connected in an oriented manner. Thus, the first capacitor 202 Switched ON. The first capacitor 202 and its first capacity contributes fully to that at the output node 216 provided cell capacity.

[0035] The second capacitor 204With its positive end, it has the relatively lower control node 206 connected and its negative end with the relatively higher central node 208 The connected capacitor is oriented in the same direction. Consequently, its positive end is at a lower potential than its negative end. The second capacitor is switched OFF and does not contribute to the current at the output node. 216 provided cell capacity.

[0036] Fig. 5 is a diagram of a capacity bank 500 , which provides input capacity with relatively small capacity increments. The capacity bank 500 includes capacitance cells which yield capacitance step values ​​that are smaller than the capacitors used in the cells.

[0037] The capacity bank 500 includes an output node 534 , a coupling capacitor 214 , a coupling resistor 210 , a split supply voltage 212, a fixed capacitor 530 and several capacity cells 532 The capacity bank 500 places at the output node 534 An input capacity is provided according to a digital control word. The input capacity varies selectively and exhibits a capacity step as described above.

[0038] The coupling resistance 210 is equipped with a split supply voltage 212 and with the capacity cells 532 connected. The coupling capacitor 214 is connected to the starting node 534 and the capacity cells 532 connected. The coupling resistance 210 and the coupling capacitor 214 They perform AC coupling to reduce DC bias and the like.

[0039] The fixed capacitor 530 is between the capacity cells 532 and ground switched. The fixed capacitor 530This further reduces the capacitance step of the input capacitance. Furthermore, the fixed capacitor can 530 a quality factor of the capacity bank 500 improve.

[0040] Each of the capacity cells 532 It works essentially the same way as the cell described above. 200 The cells 532 operate according to the digital control word, which defines the states for the cells. 532 controls. Thus, the digital control word assigns one of several states to each cell.

[0041] The capacity cells 532 They comprise several capacitors connected in opposite or antiparallel ways. For illustrative purposes, the cells are 532 The first and second capacitors are shown and described. However, it is understood that additional capacitors are present in the cells. 532 can be used.

[0042] In this example, the capacity cells comprise 532Each capacitor has a first capacitor and a second capacitor. The first capacitor has a first capacitance, and the second capacitor has a second capacitance. In this example, they each operate with an OFF state and an ON state. The OFF state provides the first capacitance. The ON state provides the second capacitance equal to the first capacitance plus a cell difference amount. The cell difference amount is based on an integer coefficient multiplied by a base or minimum capacitance difference amount. The integer coefficient ranges from 1 to N. The base capacitance difference amount depends on the capacitance step for the bank. 500 together. The capacity step is smaller than the first capacity.

[0043] For this example, the number of bits in the control word and the capacity bank is 8, so M = 8 and the multiplication coefficient N = 2^(M – 1). However, other suitable values ​​can be used. The control word is denoted by the control bits CB[0], CB[1], ... CB[M – 1]. The least significant control bit is CB[0].

[0044] The coupling capacitor 214 owns one with C C designated capacity value. The fixed capacitor 530 owns one with C ft The capacity value is designated. The first capacity is designated C1.

[0045] The base difference amount is denoted by ΔC. The second capacity, which is a combination of the first capacity and the base capacity difference amount, is given by C1 + NΔC (1)

[0046] The input capacity is given by

[0047] This is L = CB[0] + CB[1] × 2 + CB[2] × 22 + ... + CB[M – 1] × 2 M-1 (3)

[0048] And the capacity step is given by With C ft = C f + L bits × C1 (4)

[0049] This is L bits = 2 M – 1. (5)

[0050] It can be seen that the capacitance step is necessarily smaller than the first capacitance. Furthermore, if the first capacitor is the minimum rated capacitor for a given technology, such as MOS, then the step size is necessarily smaller than the minimum rated capacitor.

[0051] In one example, the minimum available capacitor size is 4.067 fF. Using an antiparallel capacitance configuration as described above, with two capacitors of 4.067 fF and 4.99 fF, results in a capacitance difference of 0.9 fF. A fixed capacitor of 4.25 pF and a coupling capacitor of 800 fF are used. In this example, the capacitance step can range from 11.5 aF to 19.5 aF, which is significantly smaller than the minimum available capacitor size. These example values ​​are given for illustrative purposes only; other values ​​can be used.

[0052] Fig. 6 is a flowchart of a process 600 to provide or generate an input capacitance. The input capacitance can then be used for a suitable purpose, such as selecting an oscillation frequency.

[0053] The procedure 600 begins in the block 602, where a first capacitor and a second capacitor are arranged in an antiparallel capacitance configuration. The first capacitor and the second capacitor are voltage-controlled capacitors, such as MOS capacitors. They are as above in Fig. 2 and elsewhere shown connected in opposite directions. A positive end of the first capacitor is connected to a negative end of the second capacitor, and a negative end of the first capacitor is connected to a positive end of the second capacitor.

[0054] The first capacitor has a first capacitance, and the second capacitor has a second capacitance. One of the capacitances is slightly larger than the other, so there is a difference, or base difference, between them. This difference can be multiplied by an integer coefficient with a value from 1 to N, where N is based on a control word length. In an example, the coefficients have values ​​of 1, 2, 4, 8, 16, 32, 64, and 128. Equations (1) through (5) above describe suitable ways of determining and assigning capacitance values ​​and the integer coefficients.

[0055] A control bit signal is applied to the first end of the capacity configuration (block 604The control bit signal, in one example, is a supply voltage or a ground connection. The first end is simply a connection point between the first capacitor and the second capacitor. For example, the first end could be a node or connection point with a positive end of the first capacitor and a negative end of the second capacitor. The applied control bit signal corresponds to a first state.

[0056] In the block 606A cell capacitance is provided based solely on the first capacitor. Cell capacitance is provided at a second end of the configuration. The first state results in a more positive or higher voltage being applied to the positive end of the first capacitor. As a consequence, the second capacitor is effectively removed from the cell and does not contribute to the output capacitance. The control bit signal is applied at a higher or lower voltage than that present at the second end of the configuration, so the positive voltage is applied to the first capacitor. Generally, the second end is on a split supply voltage to facilitate selection.

[0057] In the block 608A second control bit signal is applied to the first end of the capacity configuration. The second control signal can be a supply voltage or a ground connection. In this example, the second control signal is the one in the block. 604 The applied control signal is the opposite of the first. The second control bit signal corresponds to a second state.

[0058] The cell capacity is measured in the block 610The cell capacitance is provided at the second end of the capacitance configuration only by the second capacitor, which corresponds to the second state. The second state results in a more positive or higher voltage being applied to the positive end of the second capacitor. As a consequence, the first capacitor is essentially removed from the cell and does not contribute to the output capacitance. The second control bit signal is applied at a higher or lower voltage than that present at the second end of the configuration, so the positive voltage is applied to the second capacitor.

[0059] As a result, the procedure can 600Provide input capacitances for different states that vary by a differential amount. This allows for a smaller capacitance step and higher frequency resolution. Conventional methods are typically limited by a physical capacitor and exhibit a capacitance step equal to the size of the capacitor used.

[0060] Furthermore, the procedure can 600 repeated and controlled to operate the cell in one state, two states or more states, with each state resulting in a different cell capacity.

[0061] The procedure 600 The procedure is described with regard to a single capacity cell, but it is understood that it can be used for multiple capacity cells. It is also understood that the procedure 600 It can be used for a variety of purposes, including a capacity bank, communication systems, and the like.

[0062] Although the methods presented and described herein are depicted and described as a series of steps or events, the present disclosure is not limited by the depicted arrangement of such steps or events. For example, certain steps may occur in a different order and / or simultaneously with other steps or events besides those depicted and / or described herein. Additionally, not all of the depicted steps are necessary, and the signal waveforms are for illustrative purposes only; other signal waveforms may differ significantly from those depicted. Furthermore, one or more of the steps depicted herein may be executed in one or more separate steps or in one or more separate phases.

[0063] It is noted that the claimed subject matter can be implemented as a method, device, or manufactured article using standard programming and / or engineering methods to produce software, firmware, hardware, or any combination thereof for controlling a computer to implement the disclosed subject matter (e.g., the systems shown above are non-limiting examples of circuits that can be used to implement disclosed methods and / or variations thereof). The term "manufactured article" as used here is intended to include a computer program accessible from any computer-readable device, carrier, or medium. It is apparent to those skilled in the art that many modifications can be made to this configuration without altering the scope of protection or the concept of the disclosed subject matter.

[0064] A capacity bank system comprises multiple capacity cells and an output node. The multiple capacity cells have an antiparallel configuration. The multiple capacity cells are designed to selectively provide cell capacities. The output node is coupled to the multiple capacity cells. The output node is designed to provide an input capacity.

[0065] A capacitance cell comprises a first capacitor and a second capacitor. The first capacitor has a positive end coupled to a center node and a negative end coupled to a control node. The first capacitor has a first capacitance. The second capacitor has a positive end coupled to the control node and a negative end coupled to the center node. In a first state, the first capacitance is provided at the center node, and in a second state, the second capacitance is provided at the center node.

[0066] A method for using a capacitance cell is disclosed. A first capacitor and a second capacitor are configured in an antiparallel capacitance configuration. A control bit signal corresponding to a first state is applied to a first end of the capacitance configuration. At a second end of the capacitance configuration, a cell capacitance is provided based solely on the first capacitor.

[0067] Although the invention has been presented and described with reference to one or more implementations, modifications and / or alterations to the illustrated examples may be made without deviating from the concept and scope of protection of the appended claims. For example, it is apparent to those skilled in the art that, although the transmission circuit described here has been presented as a transmitter circuit, the invention provided here can also be applied to transmitter / receiver circuits. Furthermore, it should be noted that, particularly with regard to the various components or structures (assemblies, devices, circuits, systems, etc.) described above,Unless otherwise specified, the expressions (including any mention of a “means”) used to describe the various functions performed by the component described correspond to any component or structure that performs the specified function of the component described (which is, for example, functionally equivalent), even though it is not structurally equivalent to the disclosed structure that performs the function in the exemplary implementations of the invention presented here. Although a particular feature of the invention may have been disclosed with reference to only one of several implementations, such a feature may also be combined with one or more other features of the other implementations if desired and advantageous for any given or specific application.Insofar as the expressions “containing”, “includes”, “having”, “has”, “with” or variants thereof are used either in the detailed description or in the claims, these expressions shall furthermore be inclusive in a similar way to the expression “comprising”.

Claims

[1] Capacity banking system, encompassing: multiple voltage-controlled capacitance cells with an antiparallel configuration and designed for selective provision of cell capacities; and an output node coupled to the multiple capacity cells, designed to provide an input capacity. [2] System according to claim 1, wherein the capacity cells have a relatively small capacity step. [3] System according to claim 1 or 2, wherein the capacitance cells have a capacitance step that is smaller than the smallest capacitor used in the capacitance cells. [4] System according to claim 1 of any of the preceding claims, wherein at least one of the capacitance cells is configured with a first capacitor and a second capacitor connected in opposite directions, wherein the first capacitor has a first capacitance and the second capacitor has a second capacitance which is greater than the first capacitance. [5] System according to claim 4, wherein the second capacity is equal to the first capacity plus a difference amount, wherein the difference amount is smaller than the first capacity. [6] System according to any of the preceding claims, wherein the capacitance cells are designed to receive control bits. [7] System according to claim 6, wherein the capacity cells are designed to provide a first capacity or a second capacity according to the control bits. [8] System according to claim 6 or 7, wherein the control bits correspond to a frequency selection and a frequency step. [9] System according to one of the preceding claims, further comprising a coupling capacitor coupled between the output nodes and the multiple capacitance cells. [10] System according to one of the preceding claims, further comprising a fixed capacitor coupled to the multiple capacitance cells, wherein the fixed capacitor is designed to reduce the capacitance step of the system. [11] System according to one of the preceding claims, further comprising a resonator resonant circuit coupled to the output node. [12] System according to claim 11, wherein the resonator resonant circuit is designed to generate a selected frequency with a frequency step according to the antiparallel configuration of the multiple capacitance cells. [13] System according to one of the preceding claims, further comprising a sigma-delta modulator coupled to the capacitance band, wherein the sigma-delta modulator is designed to further reduce a capacitance step of the system. [14] Capacity cell, comprising: a first capacitor having a positive end coupled to a center node and a negative end coupled to a control node, wherein the first capacitor has a first capacitance; a second capacitor having a positive end coupled to the control node and a negative end coupled to the center node, wherein the second capacitor has a second capacitance; and wherein in a first state the first capacity is provided at the central node and in a second state the second capacity is provided at the central node. [15] Cell according to claim 14, wherein the central node receives a shared supply voltage and the control node receives a ground or a non-shared supply voltage. [16] Cell according to claim 14 or 15, wherein the first capacity is greater than the second capacity by a difference amount multiplied by an integer coefficient. [17] Cell according to one of claims 14 to 16, wherein the second capacity is greater than the first capacity by a difference amount. [18] Cell according to claim 17, wherein the first capacity can be a physical limit and the difference is smaller than the physical limit. [19] Cell according to any one of claims 14 to 18, wherein the first capacitor and the second capacitor are voltage-controlled MOS capacitors. [20] Method for using a capacity cell, comprising: Configuring a first capacitor and a second capacitor in an antiparallel capacitance configuration; Applying a control bit signal corresponding to a first state to a first end of the capacity configuration; and Providing cell capacity based solely on the first capacitor at a second end of the capacity configuration. [21] Method according to claim 20, further comprising applying a second control bit signal corresponding to a second state to the first end of the capacitance configuration and providing the cell capacitance only on the basis of the second capacitor at the second end of the capacitance configuration.