Method and apparatus for optimizing the log-likelihood ratio (LLR) used for a non-volatile storage device and for correcting errors in a non-volatile storage device

Abstract

Method for optimizing a log-likelihood ratio (LLR) used to correct errors concerning data stored in a non-volatile storage device, the method comprising: monitoring a change in a threshold voltage distribution for a plurality of memory cells contained in the non-volatile storage device (S110); and updating the LLR for the memory cells based on a result of the monitoring (S130), wherein the monitoring of the change in the threshold voltage distribution comprises: acquiring a current threshold voltage distribution for the memory cells (S111); and estimating a direction and degree of change of the threshold voltage distribution by comparing a previously stored initial threshold voltage distribution for the memory cells with the current threshold voltage distribution (S113).

Description

CROSS REFERENCE TO RELATED REGISTRATION

[0001] This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2013-0028266, filed on March 15, 2013, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. BACKGROUND 1. Technical field

[0002] Example embodiments relate generally to a non-volatile memory device, and more particularly to a method for optimizing a log likelihood ratio (LLR) used in a non-volatile memory device and a method for correcting errors in a non-volatile memory device using the same. 2. Description of the state of the art

[0003] Semiconductor memory devices can be classified into volatile memory devices and non-volatile memory devices depending on whether or not stored data is lost when a power supply is turned off. The operation modes of the non-volatile memory device are classified into a write mode (or program mode) for storing data in a memory cell, a read mode for reading data stored in the memory cell, and an erase mode for erasing the stored data to initialize the memory cell. Generally, in the non-volatile memory device, error correction encoding is performed with respect to programmed data, and error correction decoding is performed with respect to read-out data. SUMMARY

[0004] Some example embodiments provide a method for optimizing a log likelihood ratio (LLR) algorithm used when correcting errors associated with data stored in a non-volatile memory device.

[0005] Some example embodiments provide a method for correcting errors by the non-volatile memory device using the optimized LLR.

[0006] In a method for optimizing a log likelihood ratio (LLR) used to correct errors associated with data stored in a non-volatile memory device, a change in a threshold voltage distribution for a plurality of memory cells included in the non-volatile memory device is monitored, and the LLR for the memory cells is updated based on a result of the monitoring.

[0007] In exemplary embodiments, monitoring the change in the threshold voltage distribution may comprise detecting a current threshold voltage distribution for the memory cells and estimating a direction and degree of change in the threshold voltage distribution by comparing a previously stored initial threshold voltage distribution for the memory cells with the current threshold voltage distribution.

[0008] The initial threshold voltage distribution may correspond to a number of first memory cells among the memory cells of the non-volatile memory device having a threshold voltage smaller than a first voltage in an initial operating phase of the non-volatile memory device and a number of second memory cells among the memory cells of the non-volatile memory device having a threshold voltage larger than a second voltage in the initial operating phase of the non-volatile memory device.The current threshold voltage distribution may correspond to a number of third memory cells among the memory cells of the non-volatile memory device having a threshold voltage smaller than the first voltage in a current state and a number of fourth memory cells among the memory cells of the non-volatile memory device having a threshold voltage larger than the second voltage in the current state.

[0009] Each of the memory cells may be a single-level memory cell (ENZ) for storing one bit of data. The first voltage may be a voltage corresponding to an erased state, and the second voltage may be a voltage corresponding to a programmed state.

[0010] Each of the memory cells may be a multi-level memory cell (MNC) for storing a plurality of data bits therein. The first voltage may be a voltage corresponding to an erased state, and the second voltage may be a voltage corresponding to a programmed state with a highest level.

[0011] The MNZ can be a 2-bit memory cell to store 2-bit data or a 3-bit memory cell to store 3-bit data.

[0012] Monitoring the change in the threshold voltage distribution may include estimating a direction of change and a degree of change in the threshold voltage distribution based on a difference between a number of first memory cells among the memory cells of the non-volatile memory device having a threshold voltage between a first voltage and a second voltage in a current state and a number of second memory cells among the memory cells of the non-volatile memory device having a threshold voltage between the first voltage and a third voltage in the current state.

[0013] The first voltage may be a voltage corresponding to a hard-decision read operation and the second and third voltages may be voltages corresponding to a soft-decision read operation.

[0014] In exemplary embodiments, the threshold voltage distribution may be changed due to at least one of a disturbance between adjacent memory cells and an expiration of a data retention time.

[0015] The threshold voltage distribution may be shifted in a first direction due to the disturbance between the adjacent memory cells and may be shifted in a second direction different from the first direction due to the elapse of the data retention time.

[0016] In a method for correcting errors related to data when reading data stored in a non-volatile memory device, an LLR is optimized for a plurality of memory cells included in the non-volatile memory device, and error correction for the stored data is performed based on the optimized LLR. Optimizing the LLR includes monitoring a change in a threshold voltage distribution for the memory cells and updating the LLR for the memory cells based on a result of the monitoring.

[0017] In exemplary embodiments, performing error correction for the stored data may include performing error correction for the stored data by using a low-density parity check (LDPC) code.

[0018] In exemplary embodiments, optimizing the LLR and performing error correction may be performed with a memory controller external to the non-volatile memory device.

[0019] In exemplary embodiments, the non-volatile memory device may be a vertical type memory device in which a plurality of word lines are stacked vertically.

[0020] In exemplary embodiments, the non-volatile memory device may include a memory cell array including the memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder connected to the word lines, and a page latch connected to the bit lines.

[0021] An article of manufacture comprises: a log-likelihood ratio (LLR) optimizer configured to optimize a log-likelihood ratio for a plurality of memory cells included in a non-volatile memory device; and an error correction code (ECC) decoder configured to perform error correction for the stored data based on the optimized LLR. The log-likelihood ratio optimizer is configured to monitor a change in a threshold voltage distribution for the memory cells and update the LLR for the memory cells based on a result of the monitoring.

[0022] In exemplary embodiments, the article of manufacture includes a memory controller including the log-likelihood ratio optimizer and the ECC decoder.

[0023] In exemplary embodiments, the article of manufacture further comprises the non-volatile memory device.

[0024] In exemplary embodiments, the log-likelihood ratio optimizer is configured to monitor the change in the threshold voltage distribution by: detecting a current threshold voltage distribution for the memory cells; and estimating a change direction and a change degree of the threshold voltage distribution by comparing a previously stored initial threshold voltage distribution for the memory cells with the current threshold voltage distribution.

[0025] In exemplary embodiments, the log-likelihood ratio optimizer is configured to monitor the change in the threshold voltage distribution by: estimating a change direction and a change degree of the threshold voltage distribution based on a difference between a number of first memory cells among the plurality of memory cells of the non-volatile memory device that have a threshold voltage between a first voltage and a second voltage in a current state of the non-volatile memory device and a number of second memory cells among the memory cells of the non-volatile memory device that have a threshold voltage between the first voltage and a third voltage in the current state. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Illustrative, non-limiting example embodiments will become more clearly apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0027] Fig. 1 is a flowchart illustrating a method for optimizing a LLR (log likelihood ratio) used in a non-volatile memory device according to example embodiments.

[0028] Fig. 2A, Fig. 2B, Fig. 3A and Fig. 3B are views to illustrate the method for optimizing the LLR used in the non-volatile memory device of Fig. 1 is used.

[0029] Fig. 4A and Fig. 4B are views for explaining a situation in which the characteristics of memory cells included in the non-volatile memory device are deteriorated.

[0030] Fig. 5 is a flowchart illustrating an example of a step for monitoring the change in the threshold voltage distribution.

[0031] Fig. 6 and Fig. 7 are views to show the step of monitoring the change in the threshold voltage distribution of Fig. 5 explain.

[0032] Fig. Fig. 8 is a view to show another example of a step for monitoring the change in the threshold voltage distribution of Fig. 1 to explain.

[0033] Fig. 9 is a flowchart illustrating a method for correcting errors in a non-volatile memory device according to example embodiments.

[0034] Fig. 10 is a flowchart showing an example of a step for performing error correction of data stored in memory cells for the method shown in Fig. 9 is illustrated.

[0035] Fig. 11 is a view to explain an example of a 2-bit soft decision read operation.

[0036] Fig. 12 is a view to explain an example of a 3-bit soft decision read operation.

[0037] Fig. 13A to Fig. 13C are views for explaining an example of a soft decision read operation performed in a non-volatile memory device having a 3-bit multi-level cell.

[0038] Fig. 14 is a block diagram illustrating a non-volatile memory device according to example embodiments.

[0039] Fig. 15A, Fig. 15B and Fig. 15C are views illustrating examples of a memory cell matrix used in the non-volatile memory cell of Fig. 14 is included.

[0040] Fig. 16 is a block diagram illustrating an example of a memory system including a non-volatile memory device and a memory controller according to an example embodiment.

[0041] Fig. 17 is a block diagram illustrating another example of a memory system including a non-volatile memory device and a memory controller according to example embodiments.

[0042] Fig. 18 is a view illustrating an example in which a storage system according to exemplary embodiments is applied to a memory card.

[0043] Fig. 19 is a view illustrating an example in which the storage system according to exemplary embodiments is applied to a solid-state drive.

[0044] Fig. 20 is a block diagram illustrating a computer system according to example embodiments. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0045] Various exemplary embodiments will be described more fully with reference to the accompanying drawings, in which some exemplary embodiments are shown. The present inventive concept may, however, be embodied in many different forms and should not be considered limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present inventive concept to those skilled in the art. Like reference numerals refer to like elements throughout this application.

[0046] Although the terms first, second, etc., may be used herein to describe various elements, it will be appreciated that these elements should not be limited by these terms. These terms are used only to distinguish one element from another element. For example, a first element could be called a second element, and similarly, a second element could be called a first element, without departing from the scope of the present inventive concept. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed objects.

[0047] When an element is described as being "connected to" or "coupled to" another element, it is understood that it may be directly connected to or coupled to the other element, or that intervening elements may be present. Conversely, when an element is described as being "directly connected to" or "directly coupled to" another element, no intervening elements are present. Other words used to describe the relationship between elements should be interpreted in a similar way (e.g., "between" as opposed to "directly between," "adjacent" as opposed to "directly adjacent," etc.).

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. The singular forms "a" and "an" and "the" as used herein are intended to include the plural forms unless the context clearly indicates otherwise. It is further understood that the terms "having," "comprising," "comprising," and / or "comprising" when used herein specify the presence of stated features, integers, steps, acts, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, acts, elements, components, and / or groups thereof.

[0049] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one skilled in the art to which the inventive concept belongs. It is further understood that terms, such as those defined in relevant dictionaries, should be interpreted with a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0050] Fig. 1 is a flowchart illustrating a method for optimizing an LLR (log likelihood ratio) used in a non-volatile memory device according to example embodiments. Fig. 2A, Fig. 2B, Fig. 3A and Fig. 3B are views to illustrate the method for optimizing the LLR used in the non-volatile memory device of Fig. 1 is used.

[0051] The method for optimizing the LLR implemented in the non-volatile memory device used in Fig. 1 may be applied to the non-volatile memory device to perform error correction on data stored in the process of reading data. The read operation performed in the non-volatile memory device may include a hard-decision read operation and / or a soft-decision read operation. The LLR is used to correct errors on the data stored in the non-volatile memory device. In particular, the LLR may be used when correcting errors using a low-density parity check (LDPC) code. From now on, the exemplary embodiments will be described with a focus on a flash memory device.The method for optimizing the LLR used in the non-volatile memory device according to the exemplary embodiments can be used in predetermined non-volatile memory devices such as a phase change random access memory (PRAM), a resistance random access memory (RRAM), a magnetic random access memory (MRAM), or a ferroelectric random access memory (FRAM).

[0052] Referring to Fig. 1, Fig. 2A, Fig. 2B, Fig. 3A and Fig. 3B, in the method for optimizing the LLR used in the non-volatile memory device according to the exemplary embodiments, the change in the threshold voltage distribution for a plurality of memory cells included in the non-volatile memory device is monitored (step S110). The LLR is updated with respect to the memory cells based on the monitoring result (step S130).

[0053] The LLR is a value obtained by applying a logarithm (log) to the probability ratio with which data stored in the memory cells corresponds to "1" or "0." An initial threshold voltage distribution is estimated with respect to the memory cells at a time when the non-volatile memory device is designed / manufactured, and the initial value of the LLR can be determined based on an initial threshold voltage distribution. However, the initial threshold voltage distribution may be deformed / distorted due to deterioration in the characteristics of the memory cells. When the LLR is used with the initial value, if the initial threshold voltage distribution is deformed / distorted as described above, error correction cannot be performed with accuracy or precision.

[0054] For example, the non-volatile memory device may have the initial threshold voltage distribution as shown in Fig. 2A and Fig. 2B. The initial threshold voltage distribution may have a first state Si corresponding to data having a logical value of "1" and a second state Si+1 corresponding to data having a logical value of "0." When the non-volatile memory device performs the hard-decision read operation and the 2-bit soft-decision read operation, the initial threshold voltage distribution may be divided into four sections. 110 , 120 , 130 and 140 based on three voltages V1, V2 and V3. The hard-decision read operation and the 2-bit soft-decision read operation will be explained later with reference to Fig. 11 are described.

[0055] Because LLQs cannot be optimized for all memory cells, the initial values ​​of the LLQs can be determined such that the initial threshold voltage distribution is divided into four sections 110 , 120 , 130 and 140 and memory cells belonging to a section are set to the same values. In an example, the initial value of the LLR for section 120 based on the following equation 1. Equation 1

[0056] In equation 1, A1 can be assigned to an area A1 of Fig. 2A and B1 can correspond to an area B1 of Fig. 2B. A1 may represent a probability with which data stored in memory cells corresponds to a logical value of "1", and may represent the number of memory cells in which data corresponding to the logical value of "1" is stored, among a plurality of memory cells having a threshold voltage between the first and second voltages V1 and V2 in the initial threshold voltage distribution. B1 may represent a probability with which data stored in memory cells corresponds to a logical value of "0", and may represent the number of memory cells in which data corresponding to the logical value of "0" is stored, among a plurality of memory cells having the threshold voltage between the first and second voltages V1 and V2 in the initial threshold voltage distribution.

[0057] Similarly, the initial value of LLQs with respect to the remaining sections 110 , 130 and 140 detected. Accordingly, one of the four initial LLQ values ​​can be assigned to each of the memory cells included in the non-volatile memory device. When the non-volatile memory device corrects errors using LDPC code in the data readout process, the initial LLQ values ​​can be used.

[0058] If the characteristics of the memory cells are deteriorated, the non-volatile memory device may have a current threshold voltage distribution that is Fig. 3A and Fig. 3B. The current threshold voltage distribution may have a first state Si' corresponding to data having a logical value of "1" and a second state Si+1' corresponding to data having a logical value of "0". If the current threshold voltage distribution is identical to the initial threshold voltage distribution shown in Fig. 2A and Fig. 2B, it may be shifted in a direction (to the left) of decreasing the magnitude of the threshold voltage, and the position of a valley where two state graphs intersect may be changed. However, because voltages V1, V2, and V3 are fixed, sections 110' , 120' , 130' and 140' which are separated by the voltages V1, V2 and V3, and the number of memory cells, each section 110' , 120' , 130' and 140'In this case, the error correction performance may be degraded when using the initial values ​​of the LLQs determined with reference to Fig. 2A and Fig. 2B have been described.

[0059] In the method for optimizing the LLR used in the non-volatile memory device according to the exemplary embodiments, the change in the threshold voltage distribution resulting from the deterioration of the characteristics of the memory cells is monitored, and the LLR is updated based on the monitoring result. According to an exemplary embodiment, the updated value (ie, the optimal value) of the LLR for the section 120' can be obtained based on equation 2. Equation 2

[0060] In equation 2, A1' can be assigned to an area A1' of Fig. 3A and represent the number of memory cells storing data corresponding to the logical value of "1" among the plurality of memory cells having a threshold voltage between the first and second voltages V1 and V2 in the current threshold voltage distribution. In addition, B1' may have an area B1' of Fig. 3B and represent the number of memory cells in which data corresponding to the logic value of “0” is stored, out of the plurality of memory cells having the threshold voltage between the first and second voltages V1 and V2 in the current threshold voltage distribution.

[0061] Similarly, the optimal values ​​of LLQs regarding the remaining sections 110' , 130' and 140'detected. Accordingly, one of the four optimal LLQ values ​​can be assigned to each of the memory cells included in the non-volatile memory device. When the non-volatile memory device corrects errors by using an LDPC code in the data readout process, the optimal LLQ values ​​can be used. When the method for optimizing the LLR used in the non-volatile memory device according to the exemplary embodiments is used, the error correction performance and the data readout performance of the non-volatile memory device can be improved.

[0062] Although Fig. 2A, Fig. 2B, Fig. 3A and Fig. 3B illustrate the exemplary embodiments according to the 2-bit soft decision read operation, meanwhile, the LLR update operation (LLR optimization operation) shown in Fig. 2A, Fig. 2B, Fig. 3A and Fig. 3B, even when the non-volatile memory device performs a 3-bit soft decision readout operation. According to the 3-bit soft decision readout operation, the threshold voltage distribution can be divided into eight sections based on seven voltages, and the details thereof will be described below with reference to Fig. 12. Although Fig. 2A, Fig. 2B, Fig. 3A and Fig. 3B illustrate two adjacent states Si and Si+1, furthermore, the 2-bit soft decision readout operation and the 3-bit readout operation may be performed to distinguish two adjacent states among a plurality of states, and details thereof will be described below with reference to Fig. 13A, Fig. 13B and Fig. 13C are described.

[0063] Fig. 4A and Fig. 4B are views for explaining a situation in which the characteristics of memory cells included in the non-volatile memory device are deteriorated.

[0064] Referring to Fig. 4A and Fig. 4B, the threshold voltage distribution for the memory cells may be altered when the characteristics of the memory cells are degraded. For example, the threshold voltage distribution may be altered due to interference between neighboring memory cells and / or the expiration of the data retention time.

[0065] According to an exemplary embodiment, as in Fig. 4A, the threshold voltage distribution may be altered due to the disturbance between the adjacent memory cells and may be shifted in a first direction D1 from the initial threshold voltage distribution ITD to the first threshold voltage distribution DTD. For example, the disturbance may include programming disturbance, erase disturbance, and back-pattern dependency.

[0066] According to another embodiment, the threshold voltage distribution can be as shown in Fig. 4B, may be changed due to the expiration of the data retention time and may be shifted in a second direction D2 from the initial threshold voltage distribution ITD to the second threshold voltage distribution RTD. For example, when the data retention time expires, charge leakage may occur, discharging charges trapped in a floating gate or tunnel oxide. If a program operation and an erase operation are repeated, the tunnel oxide degrades, and charge leakage may be further increased.

[0067] Although it is in Fig. 4A and Fig. 4B, according to the exemplary embodiments, the threshold voltage distribution may be changed due to both the interference between the neighboring memory cells and the expiration of the data retention time.

[0068] Fig. 5 is a flowchart showing an example of a step of monitoring the change in the threshold voltage distribution of Fig. 1 illustrated. Fig. 6 and Fig. 7 are views to illustrate the step of monitoring the change in the threshold voltage distribution of Fig. 5 to explain.

[0069] Referring to Fig. 5, the current threshold voltage distribution for the memory cells can be acquired to monitor the change in the threshold voltage distribution (step S111). The direction and degree of change in the threshold voltage distribution can be estimated by comparing the previously stored initial threshold voltage distribution for the memory cells with the current threshold voltage distribution (step S113).

[0070] According to an exemplary embodiment, the initial threshold voltage distribution may correspond to the number of first memory cells having a threshold voltage lower than a first voltage in the initial operating phase of the non-volatile memory device among a plurality of memory cells and the number of second memory cells having a threshold voltage higher than a second voltage in the initial operating phase of the non-volatile memory device among the plurality of memory cells. The current threshold voltage distribution may correspond to the number of third memory cells having a threshold voltage lower than the first voltage among the plurality of memory cells in a current state and the number of fourth memory cells having a threshold voltage higher than the second voltage among the plurality of memory cells in the current state.

[0071] For example in Fig. As illustrated in Figure 6, each memory cell may be a single-level memory cell for storing one data bit. In this case, the initial threshold voltage distribution ITD1 may have a first state E (e.g., an erased state) and a second state P (e.g., a programmed state). An initial threshold voltage distribution ITD1 may correspond to the number N1 of first memory cells having a threshold voltage less than a first voltage VA in the initial operating phase of the non-volatile memory device and the number N2 of second memory cells having the threshold voltage greater than the second voltage VB in the initial operating phase of the non-volatile memory device. A current threshold voltage state CRD1 may have a first state E' and a second state P'.The current threshold voltage state CRD1 may correspond to the number N1' of third memory cells having a threshold voltage less than the first voltage VA and the number N2' of fourth memory cells having a threshold voltage greater than the second voltage VB.

[0072] According to the exemplary embodiment of Fig. 6, the number N1' of third memory cells increases compared to the number N1 of first memory cells, and the number N2' of fourth memory cells decreases compared to the number N2 of second memory cells. Accordingly, the direction of change of the threshold voltage distribution can be estimated as the direction of decrease in the magnitude of the threshold voltage (i.e., to the left). The degree of change ΔV of the threshold voltage distribution can correspond to the difference between the number N1' of third memory cells and the number N1 of first memory cells, and the difference between the number N2 of second memory cells and the number N2' of fourth memory cells.

[0073] Furthermore, according to the exemplary embodiment of Fig. 6 the first voltage VA may be a voltage corresponding to the erased state E, and the second voltage VB may be a voltage corresponding to the programmed state P. The first voltage VA may be a mean value or an average value of the threshold voltage in the erased state E in the initial operating phase, and the second voltage VB may be a mean value or an average value of the threshold voltage in the programmed state P in the initial operating phase.

[0074] According to another exemplary embodiment, each memory cell may be a multi-level memory cell (MNZ) for storing a plurality of data bits. More specifically, the multi-level memory cell may be, for example, a 2-bit memory cell for storing 2-bit data or a 3-bit memory cell for storing 3-bit data. When the memory cells are the multi-level memory cells, the initial threshold voltage distribution ITD2 may have the first state (i.e., the erased state) and second to eighth states P1, P2, P3, P4, P5, P6, and P7 (i.e., programmed states), as shown in Fig. 7. The initial threshold voltage distribution ITD2 may correspond to the number N3 of first memory cells having a threshold voltage lower than the first voltage VC in the initial operating phase and the number N4 of second memory cells having a threshold voltage higher than the second voltage VD in the initial operating phase. The current threshold voltage state CRD2 may have the first state E' and the second to eighth states P1', P2', P3', P4', P5', P6', and P7'. The current threshold voltage state CRD2 may correspond to the number N3' of third memory cells having a threshold voltage lower than the first current voltage VC and the number N4' of fourth memory cells having a threshold voltage higher than the second current voltage VD.

[0075] According to the exemplary embodiment of Fig. 7, the number N3' of third memory cells is decreased compared to the number N3 of first memory cells, and the number N4' of fourth memory cells is increased compared to the number N4 of second memory cells. Accordingly, the direction of change of the threshold voltage distribution can be estimated as the direction of increase in the magnitude of the threshold voltage (i.e., to the right). The degree of change ΔV' of the threshold voltage distribution can correspond to the difference between the number N3 of first memory cells and the number N3' of third memory cells, and the difference between the number N4' of fourth memory cells and the number N4 of second memory cells.

[0076] Furthermore, according to the exemplary embodiment of Fig. 7, the first voltage VC may be a voltage corresponding to the erased state E, and the second voltage VD may be a voltage corresponding to the programmed state with the highest level (e.g., a voltage corresponding to the eighth state P7). More specifically, the first voltage VC may be a mean value or an average value of the threshold voltage in the erased state E in the initial operating phase, and the second voltage VD may be a mean value or an average value of the threshold voltage in the programmed state with the highest level P7 in the initial operating phase.

[0077] Meanwhile, although not illustrated in the drawings, according to the exemplary embodiments of Fig. 6 and Fig. 7 the first voltages VA and VC and the second voltages VB and VD have a value which corresponds at least to a readout voltage.

[0078] According to other exemplary embodiments, the change direction and the degree of change of the threshold voltage distribution may be estimated based on the difference between the number of first memory cells having a threshold voltage between the first voltage and the second voltage in a current state, of the plurality of memory cells, and the number of second memory cells having a threshold voltage between the first voltage and the third voltage in the current state, of the memory cells, in order to estimate the change in the threshold voltage distribution for the memory cells that are in Fig. 1. In this case, unlike the exemplary embodiments described with reference to Fig. 5, Fig. 6 and Fig. 7, the direction and degree of change of the threshold voltage distribution can be estimated by using only the current threshold voltage distribution without the initial threshold voltage distribution.

[0079] For example, as in Fig. 8, the initial threshold voltage distribution ITD3 has the first state Si and the second state Si + 1. Fig. 8 illustrates two adjacent states Si and Si+1 of a plurality of states. The initial threshold voltage distribution ITD3 may correspond to the number N5 of first memory cells having a threshold voltage between the first voltage V1 and the second voltage V2 in the initial operating phase and the number N6 of second memory cells having a threshold voltage between the first voltage V1 and the third voltage V3 in the initial operating phase. The current threshold voltage state CRD3 may have the first state Si' and the second state Si+1' adjacent to each other. The current threshold voltage state CRD3 may correspond to the number N5' of third memory cells having a threshold voltage between the first voltage V1 and the second voltage V2 in the current state and the number N6' of fourth memory cells having a threshold voltage between the first voltage V1 and the third voltage V3 in the current state.In this case, the direction of change and the degree of change in the threshold voltage distribution can be estimated based on the difference between the number N5' of third memory cells having a threshold voltage between the first voltage V1 and the second voltage V2 in the current state, of the plurality of memory cells, and the number N6' of fourth memory cells among the memory cells having a threshold voltage between the first voltage V1 and the third voltage V3 in the current state, of the plurality of memory cells.

[0080] Because the number N5' of third memory cells is greater than the number N6' of fourth memory cells, according to the exemplary embodiment of Fig. 8, the direction of change of the threshold voltage distribution can be estimated as the direction of increase in the magnitude of the threshold voltage (i.e., to the right). The degree of change ΔV'' of the threshold voltage distribution can be proportional to the difference between the number N5' of third memory cells and the number N6' of fourth memory cells.

[0081] Furthermore, according to the exemplary embodiment of Fig. 8 the first voltage V1 may be a voltage corresponding to a hard-decision readout operation, and the second and third voltages V2 and V3 may be voltages corresponding to a soft-decision readout operation.

[0082] As with reference to Fig. 1 to Fig. As described in Figure 8, in the method for optimizing the LLR used in the non-volatile memory device according to the exemplary embodiments, the change in the threshold voltage distribution resulting from the deterioration in the characteristics of the memory cells is monitored, and the LLR is updated to the optimal value based on the monitoring result. Accordingly, even if the characteristics of the memory cells are deteriorated, the LLR can be permanently maintained at the optimal value.

[0083] Fig. 9 is a flowchart illustrating the method for correcting errors in the non-volatile memory device according to example embodiments.

[0084] The method for correcting errors in the non-volatile memory device described in Fig. 9 is applicable to a non-volatile memory device to perform error correction for data stored in the process of reading data. The readout operation performed in the non-volatile memory device may include a hard-decision readout operation and / or a soft-decision readout operation. Although the exemplary embodiments are described below with a focus on a flash memory device, the method for correcting errors in the non-volatile memory device according to the exemplary embodiments may be used in a predetermined non-volatile memory device, such as a phase-change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and a ferroelectric random access memory (FRAM).

[0085] Referring to Fig. 9, in the method for correcting errors in the non-volatile memory device according to the exemplary embodiments, an LLR is optimized with respect to a plurality of memory cells included in the non-volatile memory device (step S210). The method for correcting errors in the non-volatile memory device according to the exemplary embodiments may be implemented by the steps shown in Fig. 1. In other words, the change in the threshold voltage distribution for the memory cells is monitored to optimize the LLR for the memory cells included in the non-volatile memory device (S110), and the LLQs for the memory cells are updated based on the monitoring result (S130). Because the method for optimizing the LLQs for the memory cells included in the non-volatile memory device described in Fig. 1 is illustrated, with reference to Fig. 1 to Fig. 8, the details thereof are omitted to avoid redundancy.

[0086] Meanwhile, error correction for data stored in the non-volatile memory device is performed based on the optimized LLR (S230). Fig. 10 is a flowchart showing an example of a step for performing error correction of data stored in memory cells for the method shown in Fig. 9 is illustrated. Fig. 11 is a view to explain an example of a 2-bit soft decision read operation. Fig. 12 is a view to explain an example of a 3-bit soft decision read operation. Fig. 13A to Fig. 13C are views for explaining an example of a soft decision read operation performed in a non-volatile memory device having a 3-bit multi-level cell.

[0087] Fig. 10 illustrates an example of a procedure for correcting errors by performing the read operation for a page of data from a storage device.

[0088] According to one embodiment, the read operation performed by the non-volatile memory device may include a hard-decision read operation and / or a soft-decision read operation. The hard-decision read operation is to read hard-decision data from the memory cells according to an on / off state of the memory cells connected to a word line by applying a read voltage with a predetermined reference level to the word line. A memory controller may perform error correction based on a hard-decision scheme by using the hard-decision data and an error correction code (e.g., low-density parity check code).Furthermore, the soft-decision read operation is intended to read soft-decision data with the reliability information of the soft-decision data from the memory cells connected to the word line by applying a plurality of read voltages to the word line at a predetermined interval. The memory controller can perform error correction based on a soft-decision scheme by using the reliability information of the hard-decision data together with the hard-decision data and the error correction code (e.g., LDPC code).

[0089] Referring to Fig. 10, the non-volatile memory device may perform the hard decision operation to read hard decision data from a selected page (step S310). The non-volatile memory device may perform the hard decision read operation to read the hard decision data from the selected page with memory cells connected to a selected word line by applying the first read voltage with a predetermined reference level to the selected word line. The non-volatile memory device may output the hard decision data to the memory controller, and the memory controller may determine whether the errors of the hard decision data can be corrected using an error correction code (ECC) (step S320).

[0090] If the errors of the hard decision data cannot be corrected using the ECC (step S320: "No"), the non-volatile memory device may perform the soft decision readout operation to read the soft decision data from the selected page containing the reliability information for the hard decision data (step S330). The non-volatile memory device may read the soft decision data containing the reliability information for the hard decision data from the selected page including the memory cells connected to the selected word line by applying a plurality of voltages to the selected word line at a predetermined interval.

[0091] As in Fig. 11, the non-volatile memory device may, for example, perform a 2-bit soft-decision readout operation. The 2-bit soft-decision readout operation may include three readout operations using three voltages V1, V2, and V3 with a predetermined interval between them. For example, the three voltages V1, V2, and V3 may include a first voltage V1 with a predetermined reference level to distinguish between the first state Si, which corresponds to data with a logic value of "1," and the second state Si+1, which corresponds to data with a logic value of "0," a second voltage V2, which is smaller than the first voltage V1 by the predetermined level, and a third voltage V3, which is larger than the first voltage V1 by the predetermined level. Meanwhile, data 710which have been read out using the first voltage V1 with the reference level, hard decision data 710 that have been read out by the hard-decision read operation, and the 2-bit soft-decision read operation can read hard-decision data 710 that have been read out by the hard-decision readout operation without applying the first voltage V1 with the reference level. According to the 2-bit soft-decision readout operation, a predetermined logic operation (e.g., an XNOR operation 730 or coding) with respect to the data read out using the second voltage V2 and data read out using the third voltage V3, in order to produce soft decision data 720 with the reliability information for hard-decision data 710 Each bit of soft decision data 720 can determine the degree of reliability of the corresponding bit of hard-decision data710 For example, the bit of soft decision data 720 with the logical value of “1” indicates that the corresponding bit of hard decision data 710 has a high reliability and the bit of soft decision data 720 with the value of “0” represents that the corresponding bit of hard decision data 710 has low reliability.

[0092] According to another exemplary embodiment, as in Fig. 12, the non-volatile memory device may perform a 3-bit soft-decision read operation. The 3-bit soft-decision read operation may include seven read operations using seven voltages V1, V2, V3, V4, V5, V6, and V7 with a predetermined interval between each other. For example, the seven voltages V1, V2, V3, V4, V5, V6, and V7 may include the fourth voltage V4, which is lower than the second voltage V2, the fifth voltage V5 between the second voltage V2 and the first voltage V1, the sixth voltage V6 between the first voltage V1 and the third voltage V3, and the seventh voltage V7, which is higher than the third voltage V3, along with the three voltages V1, V2, and V3 used in the 2-bit soft-decision read operation. 710 which are read out using the first voltage V1, 2-bit soft decision data 710that are read by the hard-decision read operation. In addition, data 720 which are read out using the second and third voltages V2 and V3, HWB (most significant bit) – soft decision data 720 and can contain soft decision data 720 that are read out by the 2-bit soft-decision read operation. The 3-bit soft-decision read operation performs a predetermined logic operation (e.g., XNOR operation 750 or encoding) with respect to data read out using the fourth voltage V4, the fifth voltage V5, the fifth voltage V6 and the seventh voltage V7 to generate NWB soft decision data 740 Both soft decision data 720 as well as 740 with two bits can determine the degree of reliability of corresponding hard-decision data 710 For example, both soft decision data 720as well as 740 with the value of “11” represent that corresponding hard decision data 710 have a very high reliability (SH), both soft decision data 720 as well as 740 with the value of “10” can represent that corresponding hard decision data 710 have a high reliability (H), both soft decision data 720 as well as 740 with the value of “00” can indicate that corresponding hard decision data 710 have low reliability (N) and both soft decision data 720 as well as 740 with the value of “01” can indicate that corresponding hard decision data 710 have very low reliability (SN).

[0093] Although Fig. 11 and Fig. 12 illustrate two adjacent states Si and Si + 1, meanwhile, the 2-bit soft decision readout operation and the 3-bit soft decision readout operation shown in Fig. 11 and Fig. 12, to distinguish between two adjacent states from the multiple states. For example, if the memory cells are 3-bit MNZ with 8 states E, P1, P2, P3, P4, P5, P6, and P7, such that each cell stores 3-bit data, the non-volatile memory device can perform the 2-bit soft decision readout operation or the 3-bit soft decision readout operation by schemes shown in Fig. 13A to Fig. 13C are illustrated. Fig. 13A illustrates examples of the 2-bit soft decision readout operation and the 3-bit soft decision readout operation performed when the data of the first bit (e.g., NWB) stored in the 3-bit MNZ is read out by using a first reference voltage VREF1. Fig. 13B illustrates examples of the 2-bit soft decision readout operation and the 3-bit soft decision readout operation performed when the data of the second bit (e.g., CSB) stored in the 3-bit MNZ is read out by using second and third reference voltages VREF2 and VREF3. Fig. 13C illustrates examples of the 2-bit soft decision readout operation and the 3-bit soft decision readout operation performed when the third-bit data (e.g., HWB) stored in the 3-bit MNZ is read out by using fourth to seventh reference voltages VREF4, VREFS, VREF6, and VREF7.

[0094] Referring to Fig. 10, the non-volatile memory device may output soft decision data of the selected page read out by the soft decision read operation to the memory controller, and the memory controller may determine whether the errors of the hard decision data can be corrected based on the reliability information of the soft decision data (step S340).

[0095] If the errors of the hard decision data cannot be corrected based on the reliability information of the soft decision data (step S340: "No"), then the memory controller may make a determination of a data read error with respect to the selected page (step S360).

[0096] Meanwhile, the memory controller may perform error correction based on a hard decision scheme or a soft decision scheme using the error correction code and the hard decision data and / or the soft decision data. For example, if the errors of the hard decision data can be corrected without the reliability information (step S320: "YES"), the memory controller performs error correction (e.g., ECC decoding) based on the hard decision scheme with reference to the hard decision data of the selected page to restore the original data (step S350).In addition, if the errors of the hard decision data can be corrected based on the reliability information of the soft decision data (step S340: "Yes"), then the memory controller performs error correction based on the soft decision scheme with respect to the hard decision data of the selected page using the error correction code, the hard decision data, and the soft decision data to restore the original data (step S350).

[0097] According to an exemplary embodiment, the error correction code used in the error correction operation based on the hard decision scheme or the soft decision scheme may be a low density parity check (LDPC).

[0098] As above with reference to Fig. 1 to Fig. 13C, in the method for correcting errors in the non-volatile memory device according to the exemplary embodiments, the change in the threshold voltage distribution resulting from the deterioration of the characteristics of the memory cells is monitored, and the LLR is updated based on the monitoring result. Accordingly, when the characteristics of the memory cells are deteriorated, the LLR can be continuously maintained at an optimal value. Furthermore, the non-volatile memory device performs error correction using the LDPC code based on the optimized LLR in the process of reading out data, so that the error correction performance and the data readout performance of the non-volatile memory device can be improved.

[0099] Fig. 14 is a block diagram illustrating a non-volatile memory device according to example embodiments.

[0100] Referring to Fig. 14 has a non-volatile memory device 1900 a memory cell matrix 1910 , a page buffer circuit 1920 , a line decoder 1930 , a voltage generator 1940 , a circuit for an input / output buffer 1960 , and a control circuit 1950 According to an exemplary embodiment, the non-volatile memory device 1900 a flash memory device. According to another exemplary embodiment, the non-volatile memory device 1900 be a predetermined non-volatile memory device, such as a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), or a ferroelectric random access memory (FRAM).

[0101] Memory cell matrix 1910has a plurality of memory cells each connected to a plurality of word lines and a plurality of bit lines. As described below with reference to Fig. 15A to Fig. 15C, the memory cells may be NAND or NOR type flash memory cells and may be arranged in a 2D matrix structure or a 3D vertical matrix structure.

[0102] According to an exemplary embodiment, each of the memory cells may be a single-level memory cell (ENZ) for storing one bit of data, or a multi-level memory cell (MNZ) for storing a plurality of bits of data. In the case of the MNZ, the programming scheme in a write mode may include various programming schemes, such as a shadow programming scheme, a reprogramming scheme, and an on-chip caching programming scheme.

[0103] Page buffer circuit 1920is connected to the bit lines to store write data stored in memory cell matrix 1910 are to be written, or to store read data that is from memory cell matrix 1910 In other words, page buffer circuitry 1920 as a write driver or a sense amplifier according to the operating modes of flash memory device 1900 For example, page buffer circuitry 1920 act as the write driver in the write mode and / or act as the sense amplifier in the read mode. The circuit for the input / output buffer 1960 can store data stored in memory cell matrix 1910 be written, received from an external memory controller or can receive the data written by memory cell matrix 1910 are read out and transferred to the memory controller.

[0104] Line decoder 1930is connected to the word lines and can select at least one of the word lines in response to a row address. Voltage generator 1940 can generate word line voltages, a programming voltage, a forward voltage, a verify voltage, an erase voltage and a readout voltage according to the control of control circuit 1950 generate. Control circuit 1950 can page buffer circuit 1920 , line decoder 1930 , voltage generator 1940 and the circuit for the input / output buffer 1960 control to store data with reference to memory cell matrix 1910 to save, delete and read.

[0105] According to an exemplary embodiment, the non-volatile memory device 1900 a unit for optimizing the LLR 1970 The LLR optimization unit 1970can be inside or outside of control circuit 1950 The LLR optimization unit 1970 monitors the change in the threshold voltage distribution for the memory cells in the memory cell matrix 1910 and updates the LLR for the memory cells based on the monitoring result so that the LLR for the memory cells can be optimized. The LLR is a value obtained by applying a logarithm (log) to the probability ratio with which data stored in the memory cells corresponds to "1" or a "0". According to an exemplary embodiment, the LLR optimization unit 1970 an operation for optimizing the LLR for the memory cells in response to a command issued by control circuit 1950 According to another embodiment, the LLR optimization unit 1970perform the operation to optimize the LLR for the memory cells in response to a command received from an external memory controller. The LLR optimization unit 1970 performs the method for optimizing the LLR of the non-volatile memory device described in Fig. 1, and thereby optimizes the LLQs for the memory cells. Because the method for optimizing the LLR of the non-volatile memory device, which is described in Fig. 1 is illustrated, with reference to Fig. 1 to Fig. 8, the details of the operation of the LLR optimization unit 1970 be omitted.

[0106] Whenever the LLR optimization unit 1970 performs the operation to optimize the LLR for the memory cells, control circuit 1950provide the optimized LLR to the memory controller. The memory controller can perform error correction with respect to data stored in the non-volatile memory device 1900 stored based on the optimized LLR in the process of reading data from the non-volatile memory device 1900 For example, the memory controller can perform error correction using LDPC code based on the optimized LLR. Accordingly, the error correction performance and data readout performance of the non-volatile memory device can be improved.

[0107] As below with reference to Fig. 16 and Fig. 17, the LLR optimization unit can 1970 in the memory control.

[0108] Fig. 15A, Fig. 15B and Fig. 15C are circuit diagrams illustrating examples of the memory cells used in the non-volatile memory device of Fig. 14 are included.

[0109] Fig. 15A is a circuit diagram illustrating a memory cell matrix included in a NOR-type flash memory device, Fig. 15B is a circuit diagram illustrating an example of a memory cell array included in a NAND type flash memory device, and Fig. 15C is a circuit diagram illustrating an example of a memory cell array included in a vertical type flash memory device.

[0110] Referring to Fig. 15A can memory cell matrix 1910aa plurality of memory cells SZ1. The memory cells SZ1 arranged in the same column may be connected in parallel between one of bit lines BL(1), ..., and BL(m) and a common source line CSL, and the memory cells SZ1 arranged in the same row may be commonly connected to one of word lines WL(1), WL(2), ..., and WL(n). For example, the memory cells SZ1 arranged in a first column may be connected in parallel between the first bit line BL(1) and the common source line CSL. Gate electrodes of the memory cells SZ1 arranged in a first row may be commonly connected to the first word line WL(1). The memory cells SZ1 may be controlled according to the level of the voltage applied to the word lines WL(1), ..., and WL(n). The NOR-type flash memory device with memory cell array 1910acan perform a write operation and a read operation in the unit of one byte or the unit of one word and can perform an erase operation in the unit of one block 1912a carry out.

[0111] Referring to Fig. 15B can be a memory cell matrix 1910bString selection transistors SST, ground selection transistors GST, and memory cells SZ2. The string selection transistors SST are connected to the bit lines BL(1), ..., and BL(m); the ground selection transistors GST may be connected to the common source line CSL. The memory cells SZ2 arranged in the same column may be connected in series between one of the bit lines BL(1), and BL(m) and the common source line CSL; and the memory cells SZ2 arranged in the same row may be connected in common to one of the word lines WL(1), WL(2), WL(3), ..., WL(n-1), and WL(n). In other words, the memory cells SZ2 may be connected in series between the string selection transistors SST and the ground selection transistors GST; and 16, 32, or 64 word lines may be arranged between the string selection line SSL and the ground selection line GSL.

[0112] The string selection transistors SST are connected to a string selection line SSL, so that the string selection transistors SST can be controlled according to the level of a voltage applied thereto by the string selection line SSL. The ground selection transistors GST are connected to a ground selection line GSL, so that the ground selection transistors GST can be controlled according to the level of a voltage applied thereto by the ground selection line GSL. The memory cells SZ2 can be controlled according to the level of the voltage applied to the word lines WL(1) ... and WL(n).

[0113] The NAND type flash memory device with memory cell matrix 1910b can perform a write operation and a read operation in the unit of a page 1911b and can perform a delete operation in the unit of a block 1912bMeanwhile, according to an exemplary embodiment, each of the page latches may be connected to an even-numbered bit line and an odd-numbered bit line. In this case, even-numbered bit lines form even-numbered pages, and odd-numbered bit lines form odd-numbered pages. The write operations for the memory cells SZ2 may be performed sequentially by alternating the even-numbered page and the odd-numbered page.

[0114] Referring to Fig. 15C can memory cell matrix 1910c a plurality of chains 1913C with a vertical structure. A plurality of chains 1913c may be formed in a second direction to form a chain row, and a plurality of chain rows may be formed in a third direction to form a chain matrix. Each of chains 1913cmay comprise ground selection transistors GSTV, memory cells SZ3 and chain selection transistors SSTV connected in series in a first direction between the bit lines BL(1), ... and BL(m), and the common source line CSL.

[0115] The ground selection transistors GSTV are connected to ground selection lines GSL11, GSL12, ..., GSLi1, and GSLi2, and the string selection transistors SSTV may be connected to the string selection lines SSL11, SSL12, ..., SSLi1, and SSLi2. The memory cells SZ3 arranged in the same layer may be commonly connected to one of the word lines WL(1), WL(2), ..., WL(n-1), and WL(n). The ground selection lines GSL11, ..., and GSLi2 and the string selection lines SSL11, ..., and SSLi2 extend in the second direction and may be formed multiple times in the third direction. The word lines WL(1), ..., and WL(n) extend in the second direction and may be formed multiple times in the first and third directions. The bit lines BL(1), ..., and BL(m) extend in the third direction and may be formed multiple times in the second direction.The memory cells SZ3 can be controlled according to the level of a voltage applied to the word lines WL(1), ... and WL(n).

[0116] Because the vertical type flash memory device with the memory cell matrix 1910c NAND-type flash memory cells, the vertical-type flash memory device performs a write operation and a read-out operation in the unit of a page and performs an erase operation in the unit of a block similarly to the NAND-type flash memory device.

[0117] According to an exemplary embodiment, an implementation may be carried out in such a way that two chain selection transistors arranged in a chain 1913care connected to a chain selection line, and two ground selection transistors included in a chain are connected to a ground selection line. Furthermore, according to the exemplary embodiment, a chain may be implemented in such a way that a chain includes a chain selection transistor and a ground selection transistor.

[0118] Fig. 16 is a block diagram illustrating an example of a memory system including a non-volatile memory device and a memory controller according to an example embodiment.

[0119] Referring to Fig. 16 has a storage system 2000a a memory controller 2010a and a non-volatile storage device 2020a on.

[0120] The non-volatile storage device 2020a can be a memory cell matrix 2025awhich contains a plurality of memory cells for storing data. Memory controller 2010a controls the non-volatile memory device 2020a . Memory control 2010a can facilitate data exchange between an external host and the non-volatile storage device 2020a control. Memory control 2010a can have a processor 2011a such as a central processing unit (CPU), a cache 2012a , a host interface 2013a , a memory interface 2014a , an ECC block 2015a and a unit for optimizing the LLR 2018a Processor 2011a can perform the operation for data exchange. According to an exemplary embodiment, cache 2012abe realized by using a static random access memory (SRAM). According to other exemplary embodiments, cache 2012a be realized using a dynamic random access memory (DRAM), a PRAM, a FRAM, an RRAM, or an MRAM. According to the exemplary embodiment, cache 2012a inside or outside memory control 2010a condition.

[0121] Host interface 2013a is connected to the host (not shown in Fig. 16) connected and memory interface 2014a is connected to the non-volatile storage device 2020a connected. Processor 2011a can be connected to the host via the host interface 2013a communicate. For example, the host interface 2013adesigned to communicate with the host over at least one of various interface protocols, such as Universal Serial Bus (USB), Multi-Media Card (MMC), Peripheral Component Interconnect-Express (PCI-E), Serial-attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (EDSI), and Integrated Drive Electronics (IDE). In addition, the processor can 2011a with the non-volatile storage device 2020a via the memory interface 2014a communicate.

[0122] The LLR optimization unit 2018a monitors the change in the threshold voltage distribution for the memory cells in the memory cell matrix 2025aand updates the LLR for the memory cells based on the monitoring result, thereby optimizing the LLR for the memory cells. The LLR optimization unit 2018a performs the method for optimizing the LLR of the non-volatile memory device described in Fig. 1, so that the LLR for the memory cells can be optimized. Because the method for optimizing the LLR used in the non-volatile memory device shown in Fig. 1 is used, with reference to Fig. 1 to Fig. 8, the details of the operation of the LLR optimization unit 2018a be omitted.

[0123] ECC block 2015a performs an ECC coding operation with respect to data provided by the host and provides the data to the non-volatile storage device 2020a available. ECC block 2015aperforms an ECC decoding operation with respect to data received from the non-volatile memory device 2020a read out and makes the data available to the host. According to an exemplary embodiment, ECC block 2015a perform the ECC encoding operation and the ECC decoding operation using an LDPC code.

[0124] If ECC block 2015a Data from the non-volatile storage device 2020a reads, ECC block 2015a Error correction for data stored in the non-volatile storage device 2020a are stored, based on the optimized LLR generated by the LLR optimization unit 2018a For example, ECC block 2015aPerform error correction using the LDPC code based on the optimized LLR. Accordingly, the error correction performance and the data readout performance of the non-volatile memory device can be 2020a be improved.

[0125] According to the exemplary embodiment, memory control 2010a in the non-volatile storage device 2020a be built in to be realized, or memory control 2010a and non-volatile storage device 2020a can be implemented in separate chips.

[0126] Storage system 2000a can be implemented in the form of a memory card or a solid-state drive. Non-volatile storage device 2020a , memory control 2010a and / or storage system 2000acan be realized by using different package shapes, such as Package on Package (POP), Ball grid arrays (BGAs), Chip scale packages (SCPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline Integrated Circuit (SOIC), Shrink Small Outline Package (SSPOP), Thin Small Outline Package (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), and Wafer-Level Processed Stack Package (WSP).

[0127] Fig. 17 is a block diagram illustrating another example of a memory system including a non-volatile memory device and a memory controller according to example embodiments.

[0128] Referring to Fig. 17 has a storage system 2000b a memory controller 2010b , at least one non-volatile memory device 2020b and a cache 2017b According to an exemplary embodiment, the buffer 2017b be realized by using a DRAM (dynamic random access memory) and can be outside the memory controller 2010b The non-volatile storage device 2020b has a memory cell matrix 2025b on and memory control 2010b can be a RAM (random access memory) controller 2016b to have a processor 2011b , a host interface 2013b , a memory interface 2014b , an ECC block 2015b , a unit for optimizing the LLR 2018b and a cache 2017b to control. Storage system 2000b from Fig. 17, the design and operation can be similar to those of storage systems 2000a from Fig. 16, except that cache 2017b outside memory control 2010b is located.

[0129] Fig. 18 is a view illustrating an example in which a storage system according to the exemplary embodiment is applied to a memory card.

[0130] Referring to Fig. 18 has a memory card 2300 a plurality of connecting pins 2310 , a memory controller 2320 and a non-volatile storage device 2330 on.

[0131] connecting pins 2310 can be connected to the host so that signals between the host and memory card 2300 transmitted and received. Connection pins 2310 may include a clock pin, a command pin, a data pin, and / or a return pin.

[0132] Memory control 2320 can receive data from the host and can store the received data in the non-volatile memory device 2330 save.

[0133] The non-volatile storage device 2330 may comprise a memory cell matrix having a plurality of memory cells.

[0134] Memory control 2320 monitors the change in the threshold voltage distribution for the memory cells and updates the LLR for the memory cells based on the monitoring result, thereby optimizing the LLQs for the memory cells. In addition, memory control can 2320 Error correction for data stored in the non-volatile storage device 2330 stored based on the optimized LLR in the process of reading data from the non-volatile memory device 2330 For example, memory control 2320Perform error correction by using the LDPC code based on the optimized LLR. Accordingly, the error correction performance and the data read performance from memory cards can be 2300 be improved.

[0135] A storage system with storage control 2320 and non-volatile storage device 2330 can be realized by storage system 2000a , which is in Fig. 16 is used. Because the design and operation of storage systems 2000a , which is in Fig. 16, the details of the configurations and operations of memory control 2320 and non-volatile storage device 2330 be omitted.

[0136] memory card 2300may include an MMC (MultiMedia Card), an eMMC (embedded MultiMedia Card), a hybrid eMMC (hybrid embedded MultiMedia Card), an SD (Secure Digital) card, a micro SD card, a memory stick, an ID card, a PCMCIA (Personal Computer Memory Card International Association) card, a chip card, a USB card, a smart card and a CF card (Compact Flash Card).

[0137] According to the exemplary embodiment, memory card 2300 be installed in a host such as a computer, a laptop, a mobile phone, a smartphone, an MP3 player, a PDA (personal digital assistant), a portable multimedia player (PMP), a digital television, a digital camera and a portable game console.

[0138] Fig. 19 is a view illustrating an example in which the storage system according to the exemplary embodiments is applied to a solid state drive (SSD).

[0139] Referring to Fig. 19 has an SSD 2400 a memory controller 2410 , a cache 2420 and a plurality of non-volatile memory devices 2450 on.

[0140] Memory control 2410 can receive data from a host (not illustrated) and store the received data in non-volatile storage devices 2450 save. cache 2420 can temporarily store data transferred between the host and non-volatile storage devices 2450 exchanged, and can be implemented as a dynamic random access memory (DRAM) that is outside of memory control 2410 is located.

[0141] Memory control2410 can change the threshold voltage distribution for the memory cells used in each non-volatile memory device 2450 and can update the LLR for the memory cells based on the monitoring result, optimizing the LLQs for the memory cells. In addition, memory control can 2410 Error correction for data stored in the non-volatile storage device 2450 stored, based on the optimized LLR in the process of reading data from each non-volatile storage device 2450 For example, memory control 2410 Perform error correction by using an LDPC code based on the optimized LLR. Accordingly, the error correction performance and the data read performance of SSD 2400 be improved.

[0142] The storage system with storage control 2410, cache 2420 and non-volatile storage devices 2450 can be used as a storage system 2000b be realized that in Fig. 17. Because the configuration and operation for storage system 2000b , which is in Fig. 17, the details of the configuration and operation in Memory Control 2410 , cache 2420 and a plurality of non-volatile memory devices 2450 be omitted.

[0143] According to the exemplary embodiment, SSD 2400 be installed in a host such as a computer, a laptop, a mobile phone, a smartphone, an MP3 player, a PDA, a PMP, a digital TV, a digital camera and a portable game console.

[0144] Fig. 20 is a block diagram illustrating a computer system according to example embodiments.

[0145] Referring to Fig. 20 has a computer system 2500 a processor 2510 , a storage device 2520 , a user interface 2530 , a bus 2550 and a storage system 2560 According to the exemplary embodiment, the computer system 2500 also a MODEM 2540 such as a baseband chipset.

[0146] processor 2510 can perform special calculations and special tasks. For example, processor 2510 a microprocessor or a CPU. Processor 2510 can be used with storage device 2520 by bus 2550 be connected, for example, to an address bus, a control bus and / or a data bus. For example, memory device 2520be implemented using a DRAM, a mobile DRAM, an SRAM, a PRAM, an FRAM, an RRAM and / or an MRAM.

[0147] In addition, the processor 2510 connected to a plug-in card such as a PCI (Peripheral Component Interconnect) bus. Accordingly, the processor 2510 User interface 2530 with at least one input device such as a keyboard or mouse or at least one output device such as a printer or display device. MODEM 2540 can receive and transmit data wirelessly together with an external device.

[0148] The non-volatile storage device 2580 of storage system 2560 can process data that is 2510 processed, or data transmitted via MODEM 2540 via memory control 2570 received, save.

[0149] Memory control2570 monitors the change in threshold voltage distribution for the memory cells used in non-volatile memory device 2580 and updates the LLQs for the memory cells based on the monitoring result, optimizing the LLR for the memory cells. In addition, memory control can 2570 Error correction for data stored in the non-volatile storage device 2580 stored based on the optimized LLR in the process of reading data from the non-volatile memory device 2580 For example, memory control 2570 Perform error correction using an LDPC code based on the optimized LLR. Accordingly, the error correction performance and the data read performance of the memory system 2560 be improved.

[0150] Storage system 2560 can be used as a storage system 2000a , which is in Fig. 16 is illustrated. Because the design and operation of storage systems 2000a , which is in Fig. 16, the details of the design and operation of storage system 2560 be omitted.

[0151] computer system 2500 may further comprise a voltage supply to provide the operating voltage. Furthermore, according to the exemplary embodiment, the computer system 2500 an application chipset and an image processor.

[0152] The foregoing is illustrative of the present inventive concept and should not be construed as limiting thereof. Although some exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the present inventive concept. Accordingly, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims.Therefore, it should be understood that the foregoing is illustrative of various exemplary embodiments and is not to be construed as limited to the specific exemplary embodiments disclosed, and that modifications to the disclosed exemplary embodiments as well as other exemplary embodiments are intended to be included within the scope of the appended claims. QUOTES CONTAINED IN THE DESCRIPTION

[0153] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0154] KR 10-2013-0028266

[0001]

Claims

[1] A method for optimizing a log-likelihood ratio (LLR) used to correct errors in data stored in a non-volatile memory device, the method comprising: Monitoring a change in a threshold voltage distribution for a plurality of memory cells included in the non-volatile memory device (S110); and Updating the LLR for the memory cells based on a result of the monitoring (S130). [2] The method of claim 1, wherein monitoring the change in the threshold voltage distribution comprises: Detecting a current threshold voltage distribution for the memory cells (S111); and Estimating a direction of change and a degree of change of the threshold voltage distribution by comparing a previously stored initial threshold voltage distribution for the memory cells with the current threshold voltage distribution (S113). [3] The method according to claim 2, wherein the initial threshold voltage distribution corresponds to a number of first memory cells among the memory cells included in the non-volatile memory device that have a threshold voltage that is lower than a first voltage in an initial operating phase of the non-volatile memory device, and a number of second memory cells among the memory cells included in the non-volatile memory device that have a threshold voltage that is higher than a second voltage in an initial operating phase of the non-volatile memory device, among the memory cells, and the current threshold voltage distribution corresponds to a number of third memory cells among the memory cells included in the non-volatile memory device that have a threshold voltage that is lower than the first voltage in a current state of the non-volatile memory device,and a number of fourth memory cells among the memory cells included in the non-volatile memory device, which have a threshold voltage greater than the second voltage in the current state of the non-volatile memory device. [4] The method of claim 3, wherein each of the memory cells is a single-level memory cell (ENZ) for storing a data bit therein, and the first voltage is a voltage corresponding to an erased state and the second voltage is a voltage corresponding to a programmed state. [5] The method of claim 3, wherein each of the memory cells is a multi-level memory cell (MNZ) for storing a plurality of data bits therein, and the first voltage is a voltage corresponding to an erased state and the second voltage is a voltage corresponding to a programmed state having a highest level. [6] The method of claim 1, wherein monitoring the change in the threshold voltage distribution comprises: Estimating a direction of change and a degree of change of the threshold voltage distribution (S113) based on a difference between a number of first memory cells, among the plurality of memory cells of the non-volatile memory device, having a threshold voltage between a first voltage and a second voltage in a current state of the non-volatile memory device, and a number of second memory cells, among the memory cells of the non-volatile memory device, having a threshold voltage between the first voltage and a third voltage in the current state. [7] The method of claim 6, wherein the first voltage is a voltage corresponding to a hard decision read operation (S310), and the second and third voltages are voltages corresponding to a soft decision read operation (S330). [8] A method for correcting errors relating to data when reading out the data stored in a non-volatile memory device, the method comprising: Optimizing a log-likelihood quotient (LLR) for a plurality of memory cells included in the non-volatile memory device (S210); and Performing error correction for the stored data based on the optimized LLR (S230), where optimizing the LLR has: Monitoring a change in a threshold voltage distribution for the memory cells (S110); and Updating the LLR for the memory cells based on a result of the monitoring (S130). [9] The method of claim 8, wherein performing error correction for the stored data comprises: Perform error correction on the stored data using a Low Density Parity Check (LDPC) code (S350). [10] The method of claim 8, wherein optimizing the LLR and performing the error correction with a memory controller ( 2010a , 2010b , 2320 , 2410 , 2570 ) that are performed outside the non-volatile storage device ( 2020a , 2020b , 2330 , 2450 , 2580 ) is provided.

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