Semiconductor devices and processes for their formation

Abstract

A method of forming a semiconductor device, the method comprising: Forming a structured sacrificial layer over a first surface of a workpiece (10) having the first surface and an opposite second surface, wherein forming the structured sacrificial layer comprises forming a plurality of trenches (210) having a depth of at least 5 µm and at most 20 µm in the workpiece (10) from the first surface, filling the plurality of trenches (210) with a filler material (220) after forming the trenches (210), overfilling the first surface with the filler material (220), and structuring the filler material (220) over the first surface; forming a membrane (40) over the sacrificial layer; Forming a via through the workpiece (10) from the second surface, wherein forming a via through the workpiece (10) comprises etching the workpiece (10) from the second surface to expose a surface of the plurality of trenches (210), forming a plurality of pillars (225) by etching the fill material (220) in the plurality of trenches (210) from the second surface, and etching the plurality of pillars (225) from the second surface, or etching the workpiece (10) from the second surface to expose a surface of the plurality of trenches (210), removing a material of the workpiece (10) between the plurality of trenches (210) from the second surface, and etching the fill material (220) in the plurality of trenches (210) from the second surface; and Removing at least a portion of the sacrificial layer from the second surface to form a cavity beneath the membrane (40), wherein the cavity is aligned with the membrane (40).

Description

FIELD OF TECHNOLOGY

[0001] The present invention relates generally to semiconductor devices and, more particularly, to semiconductor devices and methods of forming them. BACKGROUND OF THE INVENTION

[0002] Small electromechanical components can be manufactured using microelectromechanical systems (MEMS) technology through microelectronics manufacturing processes. MEMS devices feature thin membranes and beams that function as mechanical and / or electrical components.

[0003] Silicon microphones are a type of MEMS device in which the MEMS structure or a membrane is excited by acoustic signals. However, process variations during silicon microphone manufacturing can lead to fluctuations in membrane sensitivity, noise, parasitic effects, and other issues. Documents EP 2 535 310 A2 and US 2009 / 0 029 501 A1 describe known semiconductor devices. BRIEF DESCRIPTION OF THE INVENTION

[0004] There is a need to provide a concept for an improved semiconductor device.

[0005] Such a need can be met by the subject matter of the claims.

[0006] Some embodiments relate to a method of forming a semiconductor device, the method comprising forming a sacrificial layer over a first surface of a workpiece having the first surface and an opposite second surface, forming a membrane over the sacrificial layer, forming a via through the workpiece from the second surface to expose a surface of the sacrificial layer, and removing at least a portion of the sacrificial layer from the second surface to form a cavity under the membrane, wherein the cavity is aligned with the membrane.

[0007] Optionally, an inner side wall of the membrane faces an outer side wall of the sacrificial layer.

[0008] The process may include further structuring of the sacrificial layer.

[0009] The method may further comprise forming the patterned sacrificial layer, exposing a region of the first surface of the workpiece using a hard mask, and forming an oxide layer by oxidizing the exposed region.

[0010] Optionally, forming the patterned sacrificial layer comprises exposing a plurality of regions of the first surface of the workpiece using a hard mask and forming a plurality of oxide regions by oxidizing the exposed plurality of regions.

[0011] In one aspect, forming the patterned sacrificial layer comprises forming a plurality of trenches in the workpiece from the first surface, filling the plurality of trenches with a fill material, overfilling the first surface with the fill material, and patterning the fill material over the first surface.

[0012] Optionally, the plurality of trenches comprise a matrix of trenches, wherein all trenches in the matrix are laid out adjacent to one another.

[0013] Further optionally, the plurality of trenches include concentric trenches.

[0014] In one aspect, the plurality of trenches comprise a matrix of trenches, wherein all trenches in the matrix are laid out adjacent to each other and a trench is laid out around the matrix of trenches.

[0015] Optionally, etching a via through the workpiece comprises etching the workpiece from the second surface to expose a surface of the plurality of trenches, forming a plurality of pillars by etching the fill material in the plurality of trenches from the second surface, and etching the plurality of pillars from the second surface.

[0016] Further optionally, etching a via through the workpiece comprises etching the workpiece from the second surface to expose a surface of the plurality of trenches, removing a material of the workpiece between the plurality of trenches from the second surface, and etching the fill material in the plurality of trenches from the second surface.

[0017] The method may further comprise forming a plurality of buried cavities in the workpiece from the first surface, wherein the plurality of buried cavities are aligned with the patterned sacrificial layer.

[0018] Optionally, etching a via through the workpiece comprises etching the workpiece from the second surface to expose a surface of the patterned sacrificial layer, and combining the plurality of buried cavities by subjecting the second surface of the workpiece to an isotropic etch process.

[0019] Further optionally, forming the sacrificial layer comprises forming a first plurality of trenches in the workpiece from the first surface, filling the first plurality of trenches with a first dielectric layer, the first dielectric layer sealing each of the first plurality of trenches to form a first plurality of buried cavities, forming a second plurality of trenches in the workpiece from the first surface, each trench of the second plurality of trenches being disposed between adjacent trenches of the first plurality of trenches, filling the second plurality of trenches with a second dielectric layer, the second dielectric layer sealing each of the second plurality of trenches to form a second plurality of buried cavities, and planarizing a top surface of the second dielectric layer over the first surface of the workpiece.

[0020] In one aspect, the first plurality of trenches comprises a first matrix of trenches, wherein all trenches in the first matrix are laid out next to each other, wherein the second plurality of trenches comprises a second matrix of trenches, wherein all trenches in the second matrix are laid out next to each other.

[0021] Optionally, the second matrix is ​​offset relative to the first matrix.

[0022] Further optionally, the first plurality of trenches comprise first concentric trenches, wherein the second plurality of trenches comprise second concentric trenches.

[0023] In one aspect, etching a via hole through the workpiece from the second surface comprises etching a first hole through the workpiece, the first hole exposing a bottom surface of the first dielectric layer in the first plurality of trenches and a bottom surface of the second dielectric layer in the second plurality of trenches, and etching the first dielectric layer in the first plurality of trenches and the second dielectric layer in the second plurality of trenches.

[0024] Some embodiments relate to a method of forming a semiconductor device, the method comprising, from a first surface of a workpiece having the first surface and an opposite second surface, forming a plurality of trenches comprising a fill material in the workpiece, forming a first sacrificial layer over the plurality of trenches, forming a membrane over the first sacrificial layer, from the second surface removing the fill material from the plurality of trenches to expose a surface of the first sacrificial layer, and removing at least a portion of the first sacrificial layer.

[0025] The method may further comprise forming a second sacrificial layer over the membrane, wherein exposing the membrane comprises removing at least a portion of the second sacrificial layer.

[0026] Optionally, the plurality of trenches comprise a matrix of trenches, wherein all trenches in the matrix are laid out adjacent to one another.

[0027] Further optionally, the plurality of trenches include concentric trenches.

[0028] In one aspect, the plurality of trenches comprise a matrix of trenches, wherein all trenches in the matrix are laid out adjacent to each other and a trench is laid out around the matrix of trenches.

[0029] Optionally, etching a via through the workpiece comprises anisotropically etching the workpiece from the second surface to expose a surface of the plurality of trenches, forming a plurality of pillars by etching the fill material in the plurality of trenches from the second surface, and etching the plurality of pillars from the second surface.

[0030] Further optionally, etching a via through the workpiece comprises anisotropically etching the workpiece from the second surface to expose a surface of the plurality of trenches, removing a material of the workpiece between the plurality of trenches from the second surface, and etching the fill material in the plurality of trenches from the second surface.

[0031] Some embodiments relate to a semiconductor device comprising a first cavity disposed in a substrate having a first surface and an opposite second surface, the first cavity extending from a first surface into a substrate, a second cavity disposed in the substrate, the second cavity extending from the second surface to the first cavity to form a continuous cavity, the first cavity comprising a first center point, the second cavity comprising a second center point, the first cavity at least partially overlapping the second cavity, and a movable membrane layer disposed over the second surface of the substrate, a movable portion of the movable membrane layer comprising a third center point, the third center point and the second center point being aligned.

[0032] Optionally, the first center point is spaced from the second center point along a plane parallel to the second surface.

[0033] Further optionally, the first cavity and the second cavity have a different critical dimension along a plane parallel to the second surface.

[0034] The device may further comprise a third cavity disposed above the second surface of the substrate between the movable membrane layer and the second cavity.

[0035] Optionally, the third cavity includes a fourth center point, wherein the fourth center point and the second center point are aligned.

[0036] Further optionally, an inner side wall of the movable membrane layer faces the third cavity.

[0037] Some embodiments relate to a method of forming a semiconductor device, the method comprising forming a first sacrificial layer in a workpiece having a first surface and an opposite second surface, forming a second sacrificial layer over the first surface of the workpiece, wherein the second sacrificial layer is aligned with the first sacrificial layer, forming a membrane over the second sacrificial layer, exposing a surface of the second sacrificial layer, and removing the first sacrificial layer and at least a portion of the second sacrificial layer to form a cavity beneath the membrane, wherein the cavity is aligned with the membrane.

[0038] Optionally, exposing a surface of the second sacrificial layer comprises thinning the workpiece from the second surface.

[0039] Further optionally, exposing a surface of the second sacrificial layer comprises etching a hole in the workpiece from the second surface.

[0040] In one aspect, forming a first sacrificial layer comprises forming a plurality of trenches in the workpiece and filling the plurality of trenches.

[0041] Some embodiments relate to a method of forming a semiconductor device, the method comprising forming a sacrificial layer over a first surface of a workpiece having the first surface and an opposite second surface, forming a membrane over the sacrificial layer, thinning the workpiece from the second surface, and after thinning the workpiece, removing at least a portion of the sacrificial layer to form a cavity beneath the membrane, wherein the cavity is aligned with the membrane.

[0042] The method may further comprise patterning the sacrificial layer, wherein forming the patterned sacrificial layer comprises exposing a region of the first surface of the workpiece using a hard mask and forming an oxide layer by oxidizing the exposed region.

[0043] The method may further comprise patterning the sacrificial layer, wherein forming the patterned sacrificial layer comprises exposing a plurality of regions of the first surface of the workpiece using a hard mask and forming a plurality of oxide regions by oxidizing the exposed plurality of regions.

[0044] The method may further comprise patterning the sacrificial layer, wherein forming the patterned sacrificial layer comprises forming a plurality of trenches in the workpiece from the first surface, filling the plurality of trenches with a fill material, overfilling with the fill material over the first surface, and patterning the fill material over the first surface.

[0045] The device may further comprise patterning the sacrificial layer and forming a plurality of buried cavities in the workpiece from the first surface, wherein the plurality of buried cavities are aligned with the patterned sacrificial layer.

[0046] Optionally, forming the sacrificial layer comprises forming a first plurality of trenches in the workpiece from the first surface, filling the first plurality of trenches with a first dielectric layer, the first dielectric layer sealing each of the first plurality of trenches to form a first plurality of buried cavities, forming a second plurality of trenches in the workpiece from the first surface, each trench of the second plurality of trenches being disposed between adjacent trenches of the first plurality of trenches, filling the second plurality of trenches with a second dielectric layer, the second dielectric layer sealing each of the second plurality of trenches to form a second plurality of buried cavities, and planarizing a top surface of the second dielectric layer over the first surface of the workpiece.

[0047] According to one embodiment of the present invention, a method of forming a semiconductor device comprises forming a sacrificial layer over a first surface of a workpiece having the first surface and an opposite second surface. A membrane is formed over the sacrificial layer. A via is formed through the workpiece from the second surface to expose a surface of the sacrificial layer. At least a portion of the sacrificial layer is removed from the second surface to form a cavity beneath the membrane. The cavity is aligned with the membrane.

[0048] According to one embodiment of the present invention, a method of forming a semiconductor device comprises forming a plurality of trenches comprising a fill material in a workpiece from a first surface of the workpiece having the first surface and an opposite second surface. A first sacrificial layer is formed over the plurality of trenches. A membrane is formed over the first sacrificial layer. The fill material is removed from the plurality of trenches to expose a surface of the first sacrificial layer from the second surface. At least a portion of the first sacrificial layer is removed.

[0049] According to an alternative embodiment of the present invention, a method of forming a semiconductor device comprises forming a first sacrificial layer in a workpiece having a first surface and an opposite second surface. A second sacrificial layer is formed over the first surface of the workpiece. The second sacrificial layer is aligned with the first sacrificial layer. The membrane is formed over the second sacrificial layer. The surface of the second sacrificial layer is exposed. The first sacrificial layer and at least a portion of the second sacrificial layer are removed to form a cavity beneath the membrane. The cavity is aligned with the membrane.

[0050] According to an alternative embodiment of the present invention, a method of forming a semiconductor device comprises forming a sacrificial layer over a first surface of a workpiece having the first surface and an opposite second surface. A membrane is formed over the sacrificial layer. The workpiece is thinned from the second surface. After thinning the workpiece, at least a portion of the sacrificial layer is removed to form a cavity beneath the membrane. The cavity is aligned with the membrane.

[0051] According to one embodiment of the present invention, a semiconductor device comprises a first cavity disposed in a substrate having a first surface and an opposite second surface. The first cavity extends from a first surface into a substrate. A second cavity is disposed in the substrate. The second cavity extends from the second surface to the first cavity to form a continuous cavity. The first cavity includes a first center point, while the second cavity includes a second center point. The first cavity at least partially overlaps the second cavity. A movable membrane layer is disposed over the second surface of the substrate. The movable portion of the movable membrane layer includes a third center point. The third center point and the second center point are aligned. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] For a more complete understanding of the present invention and its advantages, reference is now made to the following descriptions taken in conjunction with the accompanying drawings in which: Fig. 1, which the Fig. 1A and Fig. 1B illustrates a MEMS device according to an embodiment of the invention, wherein Fig. 1A illustrates a cross-sectional view and Fig. 1B illustrates a plan view; the Fig. 2-8 illustrate an embodiment for fabricating the semiconductor device comprising a movable membrane layer using a local oxidation process according to embodiments of the invention; the Fig. 9-16 illustrate an embodiment for fabricating the semiconductor device comprising a movable membrane layer with corrugations using a local oxidation process according to an alternative embodiment of the invention; the Fig. 17-23 illustrate an embodiment for fabricating the semiconductor device comprising a movable membrane layer by forming a plurality of trenches from the front surface and etching these trenches from the backside of a substrate according to an alternative embodiment of the invention; Fig. 24 illustrates an alternative embodiment for forming the semiconductor device including a movable membrane layer by forming a plurality of trenches from the front surface and etching these trenches from the backside of a substrate; Fig. 25, which the Fig. 25A-25C illustrates plan views of a semiconductor device according to an embodiment of the present invention; the Fig. 26-30 illustrate an alternative embodiment for fabricating the semiconductor device using fewer concentric trenches and / or having a central region without trenches; the Fig. 31-33 illustrate an alternative embodiment for fabricating the semiconductor device including a movable membrane layer by forming buried cavities from the front side and etching a cavity into the buried cavity from the back side; the Fig. 34-42 illustrate an alternative embodiment for fabricating the semiconductor device by forming a trench array in which adjacent trenches contact each other by means of a process for forming a plurality of trenches from the front side and removing the trench array from the back side; and the Fig. 43 and Fig. 44 illustrate an alternative embodiment for fabricating the semiconductor device by forming a trench array from the front side and removing the trench array from the back side after a thinning process.

[0053] Corresponding reference numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION OF EMBODIMENTS

[0054] The making and using of various embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that may be practiced in many different specific contexts. The specific embodiments discussed are intended to merely illustrate specific ways of making and using the invention and do not limit the scope of the invention.

[0055] The present invention is described with reference to various embodiments in a specific context, namely a microelectromechanical sensor (MEMS sensor). However, the invention can also be applied to other types of semiconductor devices.

[0056] A structural embodiment of the present invention is achieved by Fig. 1. A method for manufacturing the MEMS component is described by means of the Fig. 2 - 8. Furthermore, alternative embodiments are described by means of the Fig. 9 - 16, 17 - 23, 24, 25, 26 - 30, 34 - 42 described.

[0057] Fig. 1, which the Fig. 1A and Fig. 1B illustrates a MEMS device according to an embodiment of the invention, wherein Fig. 1A illustrates a cross-sectional view and Fig. 1B illustrates a top view.

[0058] With reference to Fig. 1A, the MEMS device includes a membrane layer 40 disposed over a substrate 10. The membrane layer 40 is held over the substrate 10 and may be supported by support structures such as spacers 55. As described with respect to alternative embodiments, the membrane layer 40 may have corrugations.

[0059] The MEMS device further includes a counter electrode 60 disposed above the membrane layer 40. A plurality of bumps 65 may be disposed on the rear surface of the counter electrode 60. Contacts 75 electrically couple to the counter electrode 60, the membrane layer 40, and the substrate 10. The plurality of bumps 65 may prevent the membrane layer 40 from adhering to the counter electrode 60 by minimizing the contact surface area when the membrane layer 40 is deflected toward the counter electrode 60. The counter electrode 60 may also include a plurality of etch holes 70.

[0060] The MEMS device further includes a central cavity comprising a plurality of connected cavities. Illustratively, a first cavity 110 is disposed in the substrate 10 and extends from the back surface 22 into the substrate 10. A second cavity 120 extends from the first cavity 110 to the front surface 21 of the substrate 10. A third cavity 140 is disposed above the front surface 21 of the substrate 10 and below the membrane layer 40. A gap 150 is disposed between the counter electrode 60 and the membrane layer 40 and may be disposed within a removable material layer 50. The third cavity 140 and the gap 150 enable the membrane layer 40 to vibrate.

[0061] In various embodiments, the third cavity 140 is aligned with the membrane layer 40. Furthermore, the second cavity 120 (if present) may be aligned with the third cavity 140. However, the first cavity 110 may not be aligned with the second cavity 120 or the third cavity 140.

[0062] As illustrated, the third cavity 140 may have a first diameter C1, while the membrane layer 40 has a second diameter M1. As shown in Fig. 1B, the membrane layer 40 is aligned with the third cavity 140 and the second cavity 120. However, the first cavity 110 may be misaligned relative to the second cavity 120 and the third cavity 140. For example, as shown in Fig. 1B, in one embodiment, the second cavity 120, the third cavity 140, and the membrane layer 40 have a common center point, while the first cavity 110 has a center point laterally spaced from this common center point.

[0063] In various embodiments, the degree of misalignment between the third cavity 140 and the membrane layer 40 is less than 0.1% or between about 0.01% and about 0.5%. The degree of misalignment is the distance from the center of the membrane layer 40 to the center of the third cavity 140 divided by the diameter of the membrane layer 40. Similarly, the degree of misalignment between the second cavity 120 and the membrane layer 40 is less than 0.1% or between about 0.01% and about 0.5%.

[0064] However, the degree of misalignment between the third cavity 140 and the membrane layer 40 may be greater than 0.1%, and in one or more embodiments, between about 1% and about 10%.

[0065] Advantageously, embodiments of the present invention enable closer control of the diameter of the suspended membrane layer 40. Further, in various embodiments, the surface of the membrane layer 40 may have a very low surface roughness, for example, a root mean square roughness between about 0.1 nm and about 1 nm. In some embodiments (e.g., as in Fig. 8), the side wall 41 of the membrane layer 40 may have a soft curvature, which helps to avoid any stress concentration at the corners.

[0066] The Fig. 2-8 illustrate an embodiment for fabricating the semiconductor device comprising a movable membrane layer using a local oxidation process according to embodiments of the invention.

[0067] Fig. 2 illustrates a semiconductor substrate after forming local oxidation regions according to an embodiment of the present invention.

[0068] Fig. 2 illustrates a masking layer 20 formed over a substrate 10. The substrate 10 may be a semiconductor substrate in various embodiments.

[0069] Substrate 10, in some embodiments, may be a bulk semiconductor substrate or a semiconductor-on-insulator substrate. Some examples of substrate 10 include a bulk monocrystalline silicon substrate (or a layer grown thereon or otherwise formed therein), a layer of {110} silicon on a {100} silicon wafer, a layer of a silicon-on-insulator (SOI) wafer, or a layer of a germanium-on-insulator (GeOI) wafer. In various embodiments, substrate 10 may include unpatterned epitaxial layers. In various embodiments, substrate 10 may be a silicon wafer, a germanium wafer, or may be a compound semiconductor substrate comprising indium antimonide, indium arsenide, indium phosphide, gallium nitride, gallium arsenide, gallium antimonide, or combinations thereof.In one embodiment, the substrate 10 may include a heteroepitaxial layer such as gallium nitride grown on a silicon wafer.

[0070] In various embodiments, the masking layer 20 comprises an insulating layer. In one embodiment, the masking layer 20 may be a nitride. In another embodiment, the masking layer 20 may be an oxide. The masking layer 20 may be formed by thermal oxidation or nitriding, or by means of vapor deposition processes such as chemical vapor deposition or plasma vapor deposition.

[0071] In one embodiment, the masking layer 20 may comprise a hard mask material. In various embodiments, the masking layer 20 may comprise a nitride material such as silicon nitride. In one or more embodiments, the masking layer 20 comprises a pad oxide layer and a silicon nitride layer over the pad oxide layer. In an alternative embodiment, the masking layer 20 comprises a pad oxide layer, a polysilicon layer over the pad oxide layer, and a silicon nitride layer over the polysilicon layer. In another alternative embodiment, the masking layer 20 comprises a pad oxide layer, an amorphous silicon layer over the pad oxide layer, and a silicon nitride layer over the amorphous silicon layer.

[0072] The masking layer 20 is patterned to form regions of local oxide. The masking layer 20 is patterned, for example, by depositing a layer of photosensitive material (not shown), such as photoresist, over the masking layer 20. The layer of photosensitive material is patterned using a lithography process, such as exposure to light or radiation, to transfer a pattern from a lithography mask (not shown) to the layer of photosensitive material, and the photosensitive material is developed. The layer of photosensitive material is then used as an etch mask while portions of the masking layer 20 are etched away, so that the Fig. The structure shown in Figure 2 remains.

[0073] Local oxidation is performed to form oxide regions 30. As further described below, the oxide regions 30 define the structures for the cavity over which a movable membrane is suspended. Exposed portions of the substrate 10 are oxidized using a thermal oxidation process to form oxide regions 30. The masking layer 20 blocks the oxidation of the underlying substrate 10. Therefore, the oxidation occurs locally. In one or more embodiments, the masking layer 20 protects other regions (such as other device regions) of the substrate 10 from oxidation while forming a thick local oxide in exposed portions of the substrate 10.

[0074] In various embodiments, the oxidation may be performed using dry oxidation, wet oxidation, a water environment, or a mixed environment. For example, the substrate 10 may be exposed to an oxygen-containing substance, a silicon-containing substance, and / or an elevated temperature to convert a portion of the substrate 10 into an oxide material.

[0075] During the oxidation process, a surface layer of silicon reacts to form an oxide. Subsequent oxidation occurs through oxygen diffusion through the oxide layer and reaction at the interface between the growing oxide and the substrate 10.

[0076] In an alternative embodiment, a smoothing layer may be deposited over the substrate 10 prior to forming the masking layer 20. The smoothing layer may be formed as an unpatterned layer or, alternatively, over the substrate 10 only in the regions of the MEMS device being fabricated. The smoothing layer may be a polysilicon layer in one embodiment and may result in smoother corners due to improved stress relaxation during the oxidation process.

[0077] Similarly, in an alternative embodiment, the substrate 10 may be etched using an anisotropic or isotropic etching before undergoing the oxidation process. This may allow the lateral profile of the oxide regions 30 formed beneath the masking layer 20 to be adjusted.

[0078] In various embodiments, the oxidation process is continued to form oxide regions 30 having a depth of about 1000 nm to about 6000 nm and a width of about 100 µm to about 2000 µm.

[0079] Due to the nature of the oxidation process, a portion of the oxide regions 30 protrudes above the top surface of the substrate 10. Furthermore, the oxide regions 30 have a smooth interface (silicon-oxide transition zone) due to the oxidation process. In contrast to deposition processes, oxidation is a diffusion reaction process associated with high temperatures and relatively slower oxidation rates, resulting in an interface without sharp edges between the substrate 10 and the oxide regions 30. In some embodiments, further smoothing may be performed, for example, by performing additional annealing processes, such as in a hydrogen atmosphere. The hydrogen annealing may further smooth the oxide regions 30, especially around the corners, resulting in a smooth profile.

[0080] Fig. 3 illustrates a semiconductor device after depositing a membrane layer, a removable material layer, and a counter electrode layer according to an embodiment of the present invention.

[0081] Next, as in Fig. As illustrated in Figure 3, a membrane layer 40 is deposited over the oxide regions 30. In various embodiments, the membrane layer 40 may form an electrode of a capacitor. In one embodiment, the membrane layer 40 forming the capacitor is part of a condenser microphone.

[0082] In one embodiment, membrane layer 40 comprises a polysilicon layer. In an alternative embodiment, membrane layer 40 comprises a layer of amorphous silicon. In alternative embodiments, membrane layer 40 comprises a conductive layer. In various embodiments, membrane layer 40 has a thickness of about 100 nm to about 2000 nm. In one or more embodiments, membrane layer 40 has a thickness of about 200 nm to about 1000 nm, and in one embodiment, about 330 nm.

[0083] Membrane layer 40 may be patterned. Membrane layer 40 is removed from other regions of substrate 10. In some embodiments, membrane layer 40 may be patterned in addition to the patterning of the subsequently deposited counter electrode.

[0084] A removable material layer 50 is deposited over the membrane layer 40. In one or more embodiments, the removable material layer 50 may comprise an oxide, such as a tetraethoxysilane (TEOS). In some embodiments, the removable material layer 50 may be patterned with a depression and filled with one or more layers of a coating that form the plurality of bumps 65 shown in Fig. 1A can be illustrated.

[0085] A counter electrode 60 is deposited over the removable material layer 50. In various embodiments, the counter electrode 60 forms a portion of a capacitor, for example, a portion of a condenser microphone. In one embodiment, the counter electrode 60 may comprise a polysilicon material.

[0086] Fig. 4 illustrates a semiconductor device after patterning the membrane layer, the removable material layer, and the counter electrode layer according to an embodiment of the present invention.

[0087] With reference to Fig. 4, the counter electrode 60 and the underlying removable material layer 50 are patterned. During the patterning of the counter electrode 60, a plurality of holes 70 can be formed within the counter electrode 60.

[0088] A dielectric layer 80 may be deposited and opened to form the contact. The dielectric layer may form the spacer 55 around the outer side walls of the membrane layer 40, the removable material layer 50, and the counter electrode 60 and helps secure these layers by providing mechanical support.

[0089] Contacts 75 may be formed to contact the substrate 10, the membrane layer 40, and the counter electrode 60. The contacts 75 are formed after masking and patterning the dielectric layer 80, which may also help protect the plurality of holes 70 during subsequent processing.

[0090] As in Fig. As illustrated in Figure 4, the inner side wall 41 of the diaphragm layer 40 is aligned with the outer upper surface of the oxide regions 30. Consequently, the diaphragm layer 40 is self-aligned with the oxide regions 30 and does not require a separate masking step to align the inner edge of the diaphragm layer 40 with the oxide regions 30. The distance between the inner edges of the diaphragm layer 40 determines the diameter of the suspended portion of the diaphragm layer 40, which directly affects the vibrational properties of the diaphragm layer 40.

[0091] Fig. 5 illustrates a semiconductor device after completion of front side processing prior to back side processing according to an embodiment of the present invention.

[0092] With reference to Fig. 5, the front side is protected by forming a protective layer 90. The protective layer 90 protects the front side during subsequent back side processing. In various embodiments, the protective layer 90 may comprise a silicon nitride or a silicon oxide.

[0093] Fig. 6 illustrates a semiconductor device after forming a cavity under the oxide regions according to an embodiment of the present invention.

[0094] The back processing is carried out in Fig. 6 to form a first cavity 110. The substrate 10 is flipped or turned upside down to expose the backside. Next, a resist is deposited and patterned (not shown) on the exposed backside, and a portion of the substrate 10 in the MEMS device region is exposed. The exposed substrate 10 is etched until the oxide regions 30 are exposed.

[0095] In various embodiments, the substrate 10 may be etched using a Bosch process or by depositing a hard mask layer and etching the substrate 10 using a vertical reactive ion etching process. In one embodiment, only a resist mask is used. If the resist budget is insufficient, a smooth sidewall can be created using the hard mask and the vertical reactive ion etching. However, this integration measure requires the removal of residual hard mask residues. Thus, in some embodiments, a Bosch process can be used without an additional hard mask.

[0096] In the Bosch process, an isotropic plasma etching step and a passivation layer deposition step are performed alternately. The etching / deposition steps are repeated multiple times during the Bosch process. The plasma etching is intended for vertical etches, e.g., using sulfur hexafluoride [SF6] in the plasma. The passivation layer is deposited using, for example, octafluorocyclobutane as the source gas. Each individual step can be set to last a few seconds or less. The passivation layer protects the substrate 10 and prevents further etching. However, during the plasma etching phase, the directed ions bombarding the substrate remove the passivation layer at the bottom of the trench (but not along the sides), and etching continues. The Bosch process is terminated once the oxide regions 30 are exposed.The Bosch process produces side walls that are cut out in an arc shape.

[0097] Fig. 7 illustrates a semiconductor device after removing the oxide region under the membrane layer according to an embodiment of the present invention.

[0098] Next, with reference to Fig. 7 oxide regions 30 are removed to form a second cavity 120, for which, for example, a wet chemical etching process is applied. The wet etching ends after the membrane layer 40 has been exposed. Advantageously, the location of the second cavity 120 relative to the membrane layer 40 is independent of the location of the first cavity 110. In other words, due to the misalignment of the backside mask process, the first cavity 110 may be formed without alignment with the oxide regions 30. However, the release etch process for removing the oxide regions 30 is terminated laterally and is therefore aligned with the membrane layer 40. Advantageously, this enables stable clamping of the membrane layer 40 and minimizes the overlap between the membrane layer 40 and the substrate 10, thereby reducing parasitic capacitance effects.

[0099] Fig. 8 illustrates a semiconductor device after forming the membrane layer according to an embodiment of the present invention.

[0100] With reference to Fig. 8, the front side is patterned to open the MEMS device area, while the remaining regions, for example, the contacts 75, are protected. A resist is deposited and patterned over the front side. The resist may comprise a silicon nitride material in one embodiment and may comprise a hard mask in one embodiment. Thus, the MEMS device region can be subjected to a wet etch process, which may efficiently remove material of a particular type.

[0101] The protective layer 90 may be removed according to an embodiment of the present invention. In one or more embodiments, the protective layer 90 may be etched using an anisotropic etch process to leave a support spacer. The removable material layer 50 may be etched using a wet etch process, for example, a timed isotropic wet etch, to form a gap 150. In some embodiments, the protective layer 90, the dielectric layer 80, and the removable material layer 50 may be removed during the same step. In an alternative embodiment, the oxide regions 30 and the removable material layer 50 may be etched using a common etch process.

[0102] Although embodiments of the invention are described with a counter electrode 60, they may not be used in other embodiments. For example, embodiments of the invention include MEMS applications that require a membrane layer 40 but without a counter electrode 60, e.g., pressure measurement using piezoelectric, piezoresistive, or optical techniques. Similarly, embodiments of the invention may include a plurality of counter electrodes, for example, of capacitive sensors / actuators, with the membrane layer 40 sandwiched between two counter electrodes for differential readout or push-pull actuation.

[0103] The Fig. 9-16 illustrate an embodiment for fabricating the semiconductor device comprising a movable membrane layer with corrugations using a local oxidation process according to an alternative embodiment of the invention.

[0104] The Fig. 9-16 illustrate an embodiment of a MEMS device in which the membrane layer has a plurality of corrugations. In various embodiments, the number of corrugations can be selected to optimize the stress in the membrane layer 40. Therefore, embodiments of the invention can be fabricated using a plurality of oxide regions 30, resulting in an increase in the number of corrugations. This embodiment illustrates three corrugations, and in various embodiments, more corrugations can be formed.

[0105] Fig. 9 illustrates a semiconductor device during manufacturing after forming a patterned masking layer according to an embodiment of the present invention.

[0106] With reference to Fig. 9, a masking layer 20 is deposited as in the previous embodiment. However, the masking layer 20 is structured differently in this embodiment. Several openings are formed in the masking layer 20.

[0107] Fig. 10, which the Fig. 10A-10C illustrates a semiconductor device during manufacturing after forming a patterned masking layer according to an embodiment of the present invention, wherein Fig. 10A illustrates a cross-sectional view and the Fig. 10B and Fig. 10C illustrate top views.

[0108] How next in Fig. 10A, a plurality of oxide regions 30 are formed after the substrate 10 has been subjected to an oxidation process. The oxidation process may be similar to the oxidation process described in the previous embodiment. In various embodiments, the oxide regions 30 may be formed as circular regions ( Fig. 10B), concentric trenches ( Fig. 10C) and / or rectangular trenches are formed. After the oxidation process, the masking layer 20 between the outermost oxide regions 30 is selectively removed, as shown by the mask 25.

[0109] Fig. 11 illustrates a semiconductor device during manufacturing after forming a resist and removing the masking layer from between the oxide regions according to an embodiment of the present invention. As in Fig. 11, the masking layer 20 is removed from between the oxide regions 30.

[0110] Fig. Figure 12 illustrates a semiconductor device during manufacturing after a second oxidation process according to an embodiment of the present invention. The exposed surface of the substrate 10 undergoes a further oxidation process. Accordingly, an oxide layer 130 is formed over the exposed front surface of the substrate 10 between the oxide regions 30 and connects the oxide regions.

[0111] Fig. Figure 13 illustrates a semiconductor device during manufacturing after completion of front-side processing according to an embodiment of the present invention. As described in previous embodiments, a membrane layer 40, a removable material layer 50, and a counter electrode 60 are deposited and patterned. Further, contacts, spacers, and protective layers may be formed, as described with respect to Fig. 4 - 5 illustrated and described.

[0112] Fig. 14 illustrates a semiconductor device during manufacturing after a backside cavity etch process according to an embodiment of the present invention.

[0113] As previously described, the substrate 10 is flipped over, and the backside of the substrate 10 is masked and patterned. A backside etch process forms the first cavity 110, which terminates at the oxide regions 30 and the oxide layer 130. The backside etch process may be misaligned at the location of the oxide regions 30, as described in the previous embodiment.

[0114] Fig. 15 illustrates a semiconductor device during manufacturing after a release etch process according to an embodiment of the present invention.

[0115] The oxide regions 30 and the oxide layer 130 are next removed in a single etching process. Since the oxide regions 30 and the oxide layer 130 comprise the same material, they both etch simultaneously. Thus, after the removal of the oxide regions 30 and the oxide layer 130, a second cavity 120 is formed. Furthermore, as long as the first cavity 110 completely overlaps the oxide regions 30 and has a smaller diameter than the second cavity 120 at the front surface 21 of the substrate 10 (the diameter of the first cavity C110 is smaller than the diameter of the second cavity C120), the membrane layer 40 is aligned with the second cavity 120, even though the second cavity 120 may not be aligned with the first cavity 110.

[0116] Fig. Figure 16 illustrates a semiconductor device during manufacturing after exposing the membrane layer according to an embodiment of the present invention. The removable material layer 50 is etched from the front side, as described in previous embodiments, to form a gap 150.

[0117] The Fig. 17-23 illustrate an embodiment for fabricating the semiconductor device including a MEMS sensor, for forming a plurality of trenches from the front surface and for etching these trenches from the backside of a substrate according to an alternative embodiment of the invention.

[0118] In this embodiment, several trenches are formed in the substrate and filled with a sacrificial material. Furthermore, overfilling with the sacrificial material allows the inner walls of the membrane layer to be aligned. Thus, a local oxidation process can be avoided in this embodiment.

[0119] Fig. 17 illustrates a semiconductor device during manufacturing after forming a plurality of trenches in a substrate according to an embodiment of the present invention.

[0120] In various embodiments, a plurality of trenches 210 are formed from the front side of the substrate 10. The plurality of trenches 210 may be formed by an anisotropic etching process, for example, by a reactive ion etching process. The plurality of trenches 210 may be formed in different shapes and configurations, for example, concentric trenches, circular trenches, rectangular trenches, and rectangular trenches that are concentric, and combinations thereof. Some examples are described below in Fig. 25 described.

[0121] In various embodiments, the plurality of trenches 210 may have a depth of about 5 µm to about 20 µm from the front surface into the substrate 10. In one or more embodiments, the plurality of trenches 210 may be separated by about 2 µm to about 4 µm. In one or more embodiments, the plurality of trenches 210 may have a width (cross-sectional diameter) of about 1 µm to about 2 µm.

[0122] Fig. 18 illustrates a semiconductor device during manufacturing after filling the plurality of trenches according to an embodiment of the present invention.

[0123] A fill material 220 is deposited within the plurality of trenches 210. In one or more embodiments, the fill material 220 may be deposited using vapor deposition processes such as chemical vapor deposition, physical vapor deposition, or plasma-enhanced vapor deposition. In alternative embodiments, the fill material 220 may be deposited using a coating process such as a spin-on process.

[0124] In various embodiments, the fill material 220 comprises a dielectric such as an oxide, glass, or other low-k dielectrics that can be selectively removed relative to the silicon.

[0125] In one or more embodiments, the fill material 220 may form an overfill layer over the front surface 21. In one embodiment, the overfill material 220 may be planarized using a chemical mechanical planarization process. Next, the overfill material 220 is patterned to form the overfill layer 230.

[0126] Fig. 19 illustrates a semiconductor device during manufacturing after completion of front-side processing according to an embodiment of the present invention. An insulating layer 235 may be deposited and patterned. This may be performed in some embodiments before the formation of the overfill layer 230. As described in previous embodiments, a membrane layer 40, a removable material layer 50, and a counter electrode 60 are deposited and patterned. Further, contacts, spacers, and protection layers may be formed, as described with respect to the Fig. 4 - 5 illustrated and described.

[0127] Fig. 20 illustrates a semiconductor device during manufacturing after a backside cavity etch process according to an embodiment of the present invention.

[0128] As previously described, the substrate 10 is flipped over, and the backside of the substrate 10 is masked and patterned. A backside etch process forms the first cavity 110, which terminates at the plurality of trenches 210 comprising the fill material 220. The backside etch process may be misaligned at the location of the plurality of trenches 210, as shown in the figure.

[0129] Fig. 21 illustrates a semiconductor device during manufacturing after a second backside etch process according to an embodiment of the present invention.

[0130] Next, in one or more embodiments, a selective etch process may be applied to remove the fill material 220 within the plurality of trenches 210 to form a plurality of pillars 225. In various embodiments, an oxide etch may be applied if the fill material 220 comprises oxide. The selective etch process may be timed and terminated at the overfill layer 230. In this embodiment, the diameter of the first cavity 110 at the bottom surface of the plurality of trenches 210 is larger than the diameter of the total area of ​​the plurality of trenches 210. In other words, the first cavity 110 overlaps all of the plurality of trenches 210. Otherwise, some of the plurality of trenches 210 with fill material 220 may remain unetched after this process.

[0131] Fig. 22 illustrates a semiconductor device during manufacturing after a second backside etch process according to an embodiment of the present invention.

[0132] Next, with reference to Fig. 22, the plurality of pillars 225 are removed using an isotropic etching process to form a second cavity 120 that forms a continuous cavity beneath the membrane layer 40. Overetching may be performed during the isotropic etching process to ensure that all of the plurality of pillars 225 are removed and also to laterally expand the sidewalls of the second cavity 120.

[0133] Fig. 23 illustrates a semiconductor device during manufacturing after a release etch process according to an embodiment of the present invention.

[0134] The overfill layer 230 is removed using a wet etching process. Thus, a third cavity 140 is formed. Furthermore, as long as the first cavity 110 completely overlaps the plurality of trenches 210, the membrane layer 40 is aligned with the third cavity 140, although the third cavity 140 may not be aligned with the first cavity 110. Furthermore, the membrane layer 40 is aligned with the second cavity 120. As described in previous embodiments, the removable material layer 50 is etched from the front side to form a gap 150.

[0135] Fig. Figure 24 illustrates an alternative embodiment for forming the semiconductor device. This embodiment is governed by the Fig. 17-20. However, instead of removing the fill material 220, the material that subsequently forms the plurality of pillars 225 in the previous embodiment is removed before etching the fill material 220. Then, the fill material 220 in the plurality of trenches 210 and the overfill layer 230 may be removed, for example, by means of a single wet etching process.

[0136] Fig. 25, which the Fig. 25A-25C illustrates plan views of a semiconductor device according to an embodiment of the present invention.

[0137] The plan views illustrate the design of the several trenches 210 that are located in the Fig. 17 - 24 are described. Fig. Figure 25A illustrates that the plurality of trenches 210 are formed as circular holes. In this embodiment, the shape of the third cavity 140 (inner side wall 41 of the membrane layer 40) is irregular. Fig. 25B shows that the plurality of trenches 210 are formed as concentric trenches. In this embodiment, the shape of the third cavity 140 (inner sidewall 41 of the membrane layer 40) is circular. Fig. Figure 25C illustrates a modification of the embodiment of Fig. 25A, which has a trench surrounding the circular holes. The plurality of trenches 210 are in the Fig. 25B and Fig. 25C shaded to clearly distinguish the trenches from the surrounding areas.

[0138] The Fig. 26-30 illustrate an alternative embodiment for fabricating the semiconductor device using fewer concentric trenches and / or with a central region without trenches. In various embodiments, the processing is performed as in the Fig. 17-23. However, the structure of the multiple trenches 210 is different. In this embodiment, only a single outer trench is formed along the perimeter of the membrane layer 40. In an alternative embodiment, two or more concentric trenches are formed. However, even in the alternative embodiment, a central region beneath the membrane layer 40 has no trenches. In various embodiments, the concentric trench may be circular or rectangular in shape.

[0139] Fig. 26 illustrates a semiconductor device during manufacturing after front side processing according to an embodiment of the present invention.

[0140] The plurality of trenches 210 are filled with a fill material 220, and an overfill layer 230 is formed as described in previous embodiments. Further layers (membrane layer 40, removable material layer 50, counter electrode 60, contacts, protective layer, and others) are formed as in previous embodiments.

[0141] Fig. 27 illustrates a semiconductor device during manufacturing after forming a backside cavity according to an embodiment of the present invention.

[0142] With reference to Fig. 27, a first cavity 110 is formed from the backside of the substrate 10. The first cavity 110 extends to the overfill layer 230. In various embodiments, the diameter of the first cavity 110 is smaller than the diameter of the concentric plurality of trenches 210.

[0143] Fig. Figure 28 illustrates a semiconductor device during manufacturing after expanding the cavity from the backside according to an embodiment of the present invention.

[0144] As in Fig. 28, the first cavity 110 is expanded by means of an isotropic etching process. As shown in Fig. 28, the isotropic etching process is completed at the plurality of trenches 210. Therefore, the first cavity 110 is between the plurality of trenches 210, even if the first cavity 110 is in Fig. 27 was possibly misaligned, was aligned with the membrane layer 40 after isotropic etching.

[0145] Fig. 29 illustrates a semiconductor device during manufacturing after removing the fill material from the plurality of trenches according to an embodiment of the present invention.

[0146] Fig. 30 illustrates a semiconductor device during manufacturing after removal of the overfill layer according to an embodiment of the present invention.

[0147] In various embodiments, the fill material 220 from the plurality of trenches 210 and the overfill layer 230 may be removed by means of a single etching step in which the fill material 220 is selectively etched relative to the substrate 10. A small portion of the overfill layer 230 may remain in some embodiments. Subsequent processing may be performed as previously described in other embodiments.

[0148] The Fig. 31-33 illustrate an alternative embodiment for fabricating the semiconductor device including a movable membrane layer by forming buried cavities from the front side and etching a cavity into the buried cavity from the back side.

[0149] Fig. 31, which the Fig. 31A - 31C illustrates a substrate comprising buried cavities, wherein Fig. 31A illustrates a cross-sectional view and the Fig. 31B and Fig. 31C illustrate plan views.

[0150] With reference to Fig. 31A, a buried cavity 310 may be formed beneath the front surface of the substrate 10. The buried cavity 310 may be formed by patterning multiple trenches with a very high aspect ratio, which may be covered, for example, with the overfill layer 230. The substrate 10 is then annealed in a hydrogen atmosphere so that adjacent trenches merge to form a buried cavity 310.

[0151] The buried cavity 310 may be supported by several supporting columns 320. The Fig. 31B and Fig. 31C illustrate different structures of the buried cavity 310. Fig. Figure 31B illustrates a single buried cavity 310 supported by multiple supporting columns 320, while Fig. 31C illustrates several buried cavities 310.

[0152] The overfill layer 230 may be deposited and patterned over the front surface of the substrate 10, followed by the formation of the membrane layer 40, the removable material layer 50, and the counter electrode 60, as previously described.

[0153] After completion of the front side processing, the substrate 10 is turned over as previously described.

[0154] Fig. Figure 32 illustrates a semiconductor device after forming a first cavity and a second cavity according to an embodiment of the present invention. The substrate 10 is etched from the backside, as described in previous embodiments. The dimensions of the second cavity 120 are determined by the shape of the buried cavity 310. The diameter of the first cavity 110 is smaller than the diameter of the grouping region with the buried cavity 310. Consequently, the second cavity 120 is aligned with the overfill layer 230 and the inner side walls of the membrane layer 40.

[0155] Fig. Figure 33 illustrates a semiconductor device after forming a third cavity according to an embodiment of the present invention. An overetch process is performed, terminating at the overfill layer 130. This extends or widens the buried cavity to the surface of the substrate 10. As previously described, the overfill layer 230 is etched, forming the third cavity 140. Further processing is performed as in previous embodiments.

[0156] The Fig. 34-42 illustrate an alternative embodiment for fabricating the semiconductor device by forming a trench array in which adjacent trenches contact each other by a process of forming a plurality of trenches from the front side and removing the trench array from the back side.

[0157] Fig. 34 illustrates a semiconductor device after forming a first plurality of trenches according to an embodiment of the present invention.

[0158] With reference to Fig. 34, a first hard mask layer 410 is deposited and patterned. Using the first hard mask layer 410, a first plurality of trenches 420 are formed within the substrate 10. The openings or the width of the openings in the first hard mask layer 410 are about 0.5 µm to about 2 µm. The first plurality of trenches 420 may, in one or more embodiments, be about 5 µm to about 20 µm deep. In one or more embodiments, the first plurality of trenches 420 may be formed using an anisotropic etching process, such as a reactive ion etching process.

[0159] Fig. 35 illustrates a semiconductor device after widening the first plurality of trenches according to an embodiment of the present invention. The first plurality of trenches 420 are widened using an isotropic etching process, as shown in Fig. 35 illustrates.

[0160] Fig. 36 illustrates a semiconductor device after closing the widened first plurality of trenches according to an embodiment of the present invention.

[0161] A first fill layer 415 is deposited over the substrate 10. The first fill layer 415 may comprise an oxide, which in one embodiment is configured to flow into the first plurality of trenches 420. The first fill layer 415 may comprise a tetraethylorthosilicate (TEOS) in one embodiment. The first fill layer 415 forms an empty space within the first plurality of trenches 420.

[0162] Fig. 37 illustrates a semiconductor device after forming openings in the first fill layer and in the first hard mask layer for a second plurality of trenches according to an embodiment of the present invention. A resist layer (not shown) is deposited and patterned. Openings 430 are formed in the first hard mask layer 410 and the first fill layer 415 using the patterned resist layer. The openings 130 for the second plurality of trenches are formed between the openings for the first plurality of trenches 420.

[0163] Fig. 38 illustrates a semiconductor device after forming a second plurality of trenches according to an embodiment of the present invention. Second plurality of trenches 440 are formed using an anisotropic etching process. The second plurality of trenches 440 may, in one embodiment, be formed to the same depth as the first plurality of trenches 420.

[0164] Fig. 39 illustrates a semiconductor device after widening the second plurality of trenches according to an embodiment of the present invention. The second plurality of trenches 440 are widened using an isotropic etch process that is selective for the substrate 10. Consequently, the first fill layer 415 is not removed. The isotropic etch is terminated when the etch front reaches the sidewall of the first plurality of trenches 420, thereby forming interconnection trenches 450 between the first plurality of trenches 420.

[0165] Fig. 40 illustrates a semiconductor device after filling the second plurality of trenches with a second fill layer according to an embodiment of the present invention. A second fill layer 460 is deposited over the substrate 10. The second fill layer 460 may form an empty space within the interconnect trench 450 and coats the sidewalls of the interconnect trench 450. Thus, the second fill layer 460 contacts the first fill layer 415. The second fill layer 460, in one embodiment, may comprise an oxide configured to flow into the interconnect trenches 450. The second fill layer 460, in one embodiment, may comprise a tetraethyl orthosilicate (TEOS). The first fill layer 415 and the second fill layer 460, in various embodiments, may comprise a same material.

[0166] Fig. 41 illustrates a semiconductor device after forming a backside cavity according to an embodiment of the present invention.

[0167] A backside hardmask 470 is deposited and patterned on the back surface of the substrate 10. The first cavity 110 is etched from the backside of the substrate 10 as in previous embodiments. The diameter of the first cavity 110 is, in various embodiments, smaller than the diameter of the trench array comprising the first plurality of trenches 420 and the interconnect trenches 450. The first cavity 110 may be misaligned at the location of the first plurality of trenches 420 and the interconnect trenches 450. The cavity etch forming the first cavity 110 terminates at the first plurality of trenches 420 and the interconnect trenches 450 due to the slower or negligible etch rates of the first fill layer 415 and the second fill layer 460, for example, when subjected to a silicon etch chemistry.

[0168] Fig. 42 illustrates a semiconductor device after exposing the membrane layer according to an embodiment of the present invention.

[0169] The first fill layer 415 and the second fill layer 460, the overfill layer 230, may be removed using a single etching process. For example, the first fill layer 415 and the second fill layer 460, and the first hard mask layer 410 may be removed using a single etching process. In another embodiment, after etching the first fill layer 415 and the second fill layer 460, the first hard mask layer 410 may be etched.

[0170] The Fig. 43 and Fig. 44 illustrate an alternative embodiment for fabricating the semiconductor device by forming a trench array from the front side and removing the trench array from the back side after a thinning process.

[0171] In this embodiment, a thinning process is used instead of the deep etching process as described in various embodiments. The thinning process can be performed in any of the Fig. 1 - 42 described embodiments. For illustration purposes, Fig. 43 Thinning the substrate 10 to expose a lower surface of the plurality of trenches 220, for example as shown in the Fig. 17 - 19. Instead of an etching process, as in Fig. 20, a grinding process may be used to thin the substrate 10. Accordingly, subsequent processes after the thinning process may be carried out according to the Fig. 21 - 23 described embodiment to form the second cavity 120 and the third cavity 140, as shown in Fig. 44 illustrates.

[0172] Although this invention has been described with reference to exemplary embodiments, this description is not intended to be limiting. Those skilled in the art will recognize various modifications and combinations of the exemplary embodiments and other embodiments of the invention upon reference to the description. For illustration, the Fig. 1-42 may be combined in alternative embodiments. The appended claims are therefore intended to encompass all such modifications or embodiments.

[0173] Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, those skilled in the art will readily understand that many of the features, functions, processes, and materials described herein may be varied and still remain within the scope of the present invention.

[0174] Furthermore, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manner of manufacture, composition of matter, means, methods, and steps described in the specification. As will be readily appreciated by one of ordinary skill in the art from the disclosure of the present invention, existing or later developed processes, machines, manners of manufacture, compositions of matter, means, methods, or steps that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be employed in accordance with the present invention. Accordingly, the scope of the appended claims is intended to include such processes, machines, manners of manufacture, compositions of matter, means, methods, or steps.

Claims

[1] A method of forming a semiconductor device, the method comprising: Forming a structured sacrificial layer over a first surface of a workpiece (10) having the first surface and an opposite second surface, wherein forming the structured sacrificial layer comprises forming a plurality of trenches (210) having a depth of at least 5 µm and at most 20 µm in the workpiece (10) from the first surface, filling the plurality of trenches (210) with a filler material (220) after forming the trenches (210), overfilling the first surface with the filler material (220), and structuring the filler material (220) over the first surface; forming a membrane (40) over the sacrificial layer; Forming a via through the workpiece (10) from the second surface, wherein forming a via through the workpiece (10) comprises etching the workpiece (10) from the second surface to expose a surface of the plurality of trenches (210), forming a plurality of pillars (225) by etching the fill material (220) in the plurality of trenches (210) from the second surface, and etching the plurality of pillars (225) from the second surface, or etching the workpiece (10) from the second surface to expose a surface of the plurality of trenches (210), removing a material of the workpiece (10) between the plurality of trenches (210) from the second surface, and etching the fill material (220) in the plurality of trenches (210) from the second surface; and Removing at least a portion of the sacrificial layer from the second surface to form a cavity beneath the membrane (40), wherein the cavity is aligned with the membrane (40). [2] The method of claim 1, wherein the plurality of trenches (210) comprise a matrix of trenches (210), all of the trenches (210) in the matrix being laid out adjacent to one another. [3] The method of any preceding claim, wherein the plurality of trenches (210) comprise concentric trenches (210). [4] The method of any preceding claim, wherein the plurality of trenches (210) comprise: a matrix of trenches (210), wherein all trenches (210) in the matrix are laid out next to one another; and a trench laid out around the matrix of trenches (210). [5] The method of any preceding claim, further comprising forming a plurality of buried cavities in the workpiece (10) from the first surface, wherein the plurality of buried cavities are aligned with the patterned sacrificial layer. [6] A method of forming a semiconductor device, the method comprising: from a first surface of a workpiece (10) having the first surface and an opposite second surface, forming a single outer trench comprising a filler material (220) in the workpiece (10); Forming an overfill layer (230) formed by the backfill material (220) over the outer trench; Forming a membrane layer (40) over the overfill layer, wherein the outer trench is formed along a circumference of the membrane layer (40), wherein there are no trenches in a central region under the membrane layer (40); Forming a cavity (110) from the second surface to the overfill layer; and Expanding the cavity (110), wherein the expansion of the cavity is terminated at the at least one trench. [7] A method according to claim 6, further comprising: Forming a second sacrificial layer (50) over the membrane layer (40), wherein exposing the membrane layer (40) comprises removing at least a portion of the second sacrificial layer.

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