TFT array substrate and manufacturing process as well as display device

Abstract

TFT array substrate with a display area (A) and a non-display area (B), wherein the display area (A) comprises: a first metal layer (11) comprising a first common electrode line (111); and a second metal layer (12) comprising a second common electrode line (121); and wherein the non-display area (B) comprises a third common electrode line (21), wherein the third common electrode line (21) is electrically connected to at least one of the first common electrode line (111) and the second common electrode line (121), and wherein the first common electrode line (111) is not electrically connected to the second common electrode line (121) in the display area (A).

Description

CROSS REFERENCES TO RELATED APPLICATIONSThis application claims priority to Chinese Patent Application No. 201310326789.5, filed on Jul. 30, 2013, the contents of which are incorporated herein by reference in their entirety.Field of the InventionThe present invention relates to the technical field of displays (displays), in particular to a TFT array substrate and a production method thereof, and to a display device having a TFT array substrate.Prior ArtCurrently, flat panel displays such as liquid crystal displays (LCDs) take a dominant position in the market for flat panel displays, which suggest certain features such as a small volume, a low weight, their thinness, low power consumption, freedom from radiation and the like. In one imaging method, each liquid crystal pixel dot in a flat panel LCD display is driven by a thin film transistor (TFT) integrated into a TFT array substrate and is placed in cooperation with peripheral drive electronics to display images. The TFT is a luminescence controlling switch and thus an essential point for realizing large sizes of liquid crystal displays and OLED displays, and is directly related to the development of high performance flat panel displays. With still higher demands on the resolution of products, in the TFT substrate structure, such as the delay of the common electrode line signal (common signal) as well as flicker phenomena and crosstalk (crosstalk) can be reduced without reducing the aperture ratio and the display quality can be improved becomes a problem which can be solved urgent by those skilled in the art.CN 101 770 125 A discloses a dual scan line pixel array substrate comprising a substrate, a first conductive layer, a grid insulating layer, a semiconductor layer, a second conductive layer, a protective layer and a transparent electrode layer. The first conductive layer is comprised of a plurality of gratings and a plurality of scanning lines. The mesh insulation layer is deposited on the first conductive layer. The semiconductor layer is disposed on the lattice insulation layer; the semiconductor layer is composed of a plurality of channel regions, a plurality of first common wires, and a plurality of capacitance electrodes; and the first common wires are crossed with the sense lines and connected to the capacitance electrodes. The second conductive layer is disposed on a part of the semiconductor layer and the lattice insulation layer, and is composed of a plurality of sources, a plurality of drains, and a plurality of data wires, the first common wires being parallel to the data wires. The transparent electrode layer is electrically connected to each drain through each contact window of the protection layer; and the transparent electrode layer overlaps with the protection layer and the capacitance electrodes of the semiconductor layer to form a storage capacitor.U.S. Pat. No. 8,072,570 B2 discloses a liquid crystal display panel comprising a plurality of scan lines, a plurality of data lines, a pixel array, a plurality of first common electrode lines and at least one second common electrode line. The first common electrode lines receive a common electrode signal via at least one first input node positioned on a first side of the pixel array. The second common electrode line receives the common electrode signal via at least one second input node positioned on a second side of the pixel array. Moreover, at least one first common electrode line is electrically connected to the second common electrode lines in the pixel array.U.S. Pat. No. 7,800,704 B2 discloses a liquid crystal display. The liquid crystal display includes a gate line, a data line, a first common line, and a continuous second common line. The gate line is disposed on a substrate, and the data line intersects the gate line. The first common line is parallel to the gate line, and the second common line intersects the gate line. By this invention, the first common lines and the second common pixel lines can form a net-like structure to reduce the RC delay effect of the common line.CN 202 975 548 U relates to the technical field of liquid crystal display technology and discloses an array substrate and a display device for improving the resistance uniformity of a public electrode matrix network. The array substrate includes a plurality of groups of combined wires arranged in the row direction and a plurality of data lines and a plurality of second public electrode wires arranged in the row direction and alternately distributed, each group of combined wires including two grid scan lines and a first public electrode wire; the plurality of groups of combined lines, the plurality of data lines, and the plurality of second public electrode wires define a plurality of pixel units; in each group of combined lines, one grid sense line is connected to grids of pixel units in odd rows in one row of adjacent pixel units, the other grid sense line is connected to grids of pixel units in even rows in the other row of adjacent pixel units, the first public electrode line is connected to the public electrode of the corresponding row of pixel units; each data line is connected to sources of two adjacent rows of pixel units; and the second public electrode lines and the first public electrode lines are in conductive connection at junctions.SUMMARY OF THE INVENTIONIn view of these circumstances, the present invention provides a TFT array substrate and a manufacturing method thereof, and a display device including a TFT array substrate.A TFT array substrate includes a display region and a non-display region, wherein the display region includes a first metal layer having a first common electrode line and a second metal layer having a second common electrode line; and the non-display region includes a third common electrode line, and the third common electrode line is electrically connected to at least one of the first common electrode line and the second common electrode line.Accordingly, the present invention further provides a method of manufacturing a TFT array substrate, the method comprising: forming a first metal layer having a first common electrode line in a display region; forming a second metal layer having a second common electrode line on the first metal layer; and forming a third common electrode line in a non-display region.The present invention further provides a display device comprising said TFT array substrate and a color filter substrate disposed opposite to said TFT array substrate, wherein a transparent common electrode is disposed on one side of said color filter substrate and the side of said color filter substrate faces said TFT array substrate.Compared with the prior art, the present invention has at least one of the following particular advantages.According to the TFT array substrate and the manufacturing method thereof, and the display device of the present invention, the first common electrode line is disposed in the first metal layer (in the same layer as a gate line), and the second common electrode line is disposed in the second metal layer (in the same layer as a data line), so that a certain number of data lines can be reduced. The second common electrode line is arranged by skillfully utilizing the reduced number of data lines in the present invention so that the aperture ratio does not become smaller, especially since the third common electrode line is electrically connected to at least one of the first common electrode line and the second common electrode line, so that in the gate line driving process, the TFT array structure can perform current conduction in the longitudinal direction (data line direction) and the lateral direction (gate line direction) to at least reduce the delay of the common electrode line signal (common signal), reduce flicker noises and crosstalk, and improve the display quality; In addition, the cost of a source drive (not shown in the figures) is higher than that of a gate drive (not shown in the figures), and a certain number of data lines is reduced, so that the number of gate drives is reduced, resulting in that at least one of the advantages of reducing the manufacturing cost and simplifying the process flow can be obtained.Brief Description of the DrawingsFIG. 1 is a schematic diagram of a structure of a TFT array substrate in an embodiment of the present invention; FIG. 2 is a schematic diagram of a structure of a TFT array substrate in another example not according to the present invention; FIG. 3 is a schematic diagram of a structure of a TFT array substrate in another example not according to the present invention; FIG. 4 is a schematic diagram of a structure of a TFT array substrate in another embodiment of the present invention; FIG. 5( a) is a schematic diagram of a structure of a manufacturing process of the TFT array substrate in the fourth embodiment of the present invention; FIG. 5( b) is a schematic diagram of a structure of a manufacturing process of the TFT array substrate in the fourth embodiment of the present invention; FIG. 5( c) is a schematic diagram of a structure of a manufacturing process of the TFT array substrate in the fourth embodiment of the present invention.DETAILED DESCRIPTION OF THE EMBODIMENTSIn order to better explain the stated aim, the features and advantages of the present invention, a further illustration of the present invention in combination with the drawings and exemplary embodiments follows below.It is to be understood that in the following description, specific details are set forth in order to fully understand the present invention. However, the present invention may be implemented in many ways other than the described implementations, and those skilled in the art may make similar extensions without departing from the concept of the present invention. The present invention is therefore not limited to the specific implementations disclosed below.In an embodiment shown in FIG. 1, the present invention provides a TFT array substrate having a display region A and a non-display region B. The display region A includes: a first metal layer 11 having a first common electrode line 111 and a second metal layer 12 having a second common electrode line 121; the non-display region B includes a third common electrode line 21 used for providing a common signal, and the third common electrode line 21 is electrically connected to the first common electrode line 111, the third common electrode line 21 is electrically connected to the second common electrode line 121, and the first common electrode line 111 is not electrically connected to the second common electrode line 121 in the display region (A).The first metal layer 11 further includes a gate line 112, wherein the gate line 112 has a double gate line structure, and the gate line 112 is separated from the first common electrode line 111; in particular, the gate line 112 is not cut by the first common electrode line 111 to meet an insulation purpose. The first common electrode line 111 is not limited to a straight line or a curved line, and in this embodiment, the first common electrode line 111 is a straight line and parallel to the gate line 112; the second metal layer 12 further includes a data line 122, and the data line 122 is separated from the second common electrode line 121, in particular, the data line 122 is not cut by the second common electrode line 121 to meet an isolation purpose. The second common electrode line 121 is not limited to a straight line or a curved line, and in this embodiment, the second common electrode line 121 is a straight line and parallel to the data line 122.Although the first common electrode line 111 and the second common electrode line 121 are arranged in different layers in this embodiment, the wiring shape of the first common electrode line 111 and the second common electrode line 121 forms a plurality of connected rectangular frames on the plane at a plan view angle and collectively represents the shape of a mesh.In this embodiment, the TFT array substrate further includes the pixel electrodes 13 arranged on the second metal layer 12, and since a double-gate line structure is formed, the number of the pixel electrodes 13 in each row is larger than or twice as large as the number of the second common electrode lines 121. Following this principle, those skilled in the art can adjust the number of the pixel electrodes 13 and the second common electrode lines 121 as needed.In this embodiment, the material of the first metal layer 11 and the second metal layer 12 may be selected in accordance with different device structures and process requirements, wherein the metal generally used is a single layer structure of Mo, Cr, W, Ti, Ta, Mo, Al or Cu, or a composite structure of a combination of two or more of Mo, Cr, W, Ti, Ta, Mo, Al and Cu, and the thickness is generally 200-350 nm. The pixel electrode 13 may be made of transparent materials such as indium tin oxide, aluminum zinc oxide, indium zinc oxide, tin oxide, indium oxide, indium gallium oxide, zinc oxide, and the like.Due to the dual gate line structure 112 used, the number of data lines 122 may be reduced to half in this embodiment. The second common electrode line 121 is arranged by skillfully utilizing the space originally occupied by the reduced data lines 122 in the present invention, so that the aperture ratio does not become smaller. Further, the first common electrode line 111 is electrically connected to the third common electrode line 21 to receive the common signal; the second common electrode line 121 is electrically connected to the third common electrode line 21 to receive the common signal; the delay of the common signal can be prevented by the net-shaped distribution of the first common electrode line 111 and the second common electrode line 121, so that various defects caused by the delay of the common signal can be avoided and the display quality is improved. In addition, since the cost of the source drive (not shown in the figures) is higher than that of the gate drive (not shown in the figures) and the number of data lines is reduced in this embodiment, the number of source drives is also reduced accordingly, resulting in lower manufacturing cost.In another non-inventive example, the TFT array substrate of the foregoing embodiment is partially modified. The repeated parts are omitted, and the difference between this example and the above embodiment lies in the connection relationship between the first, second and third common electrode lines. As shown in FIG. 2, the first common electrode line 111 is electrically connected to the second common electrode line 121 via a hole 14, and the first common electrode line 111 is also electrically connected to the third common electrode line 21, while the second common electrode line 121 is not connected to the third common electrode line 21.In this example, the TFT array substrate further includes an insulating layer (not shown in the figures) between the first metal layer 11 and the second metal layer 12, the first and second common electrode lines are electrically connected via a hole 14 penetrating the insulating layer, and the insulating layer is made of a composite structure composed of a combination of two or more of silicon oxide, silicon oxynitride, and silicon nitride.In this example, the first and second common electrode lines are electrically connected via a through hole 14 penetrating the insulating layer, and the first common electrode line 111 is electrically connected to the third common electrode line 21 while the second common electrode line 121 is not connected to the third common electrode line 21, however, the first and second common electrode lines can receive the common signal from the third common electrode line and delay of the common signal can be avoided by means of the mesh-shaped wiring of the first common electrode line 111 and the second common electrode line 121, so that various defects caused by delay of the common signal can be prevented without reducing the aperture ratio and display quality is improved. Further, since the number of data lines is reduced in this embodiment, the number of source drives is also reduced accordingly, resulting in lower manufacturing cost.In another example not according to the invention, the TFT array substrate of the second embodiment is partially modified. The repeated parts are omitted, and the difference between this example and the second example is that, as illustrated in FIG. 3, the second common electrode line 121 is electrically connected to the third common electrode line 21 but the first common electrode line 111 is not connected to the third common electrode line 21.In another embodiment, the TFT array substrate of the second embodiment is partially modified. The repeated parts are omitted, and the difference between this embodiment and the second embodiment is that, as illustrated in FIG. 4, the third common electrode line 21 is also electrically connected to the second common electrode line 121.In this embodiment, the first and second common electrode lines are electrically connected to the third common electrode line 21, and thus are capable of better reducing the impedance of the common electrode lines to further mitigate the signal delay of the common electrode lines.As shown in FIGS. 5(a) to 5(c), the present invention further provides a manufacturing method of the TFT array substrate. Taking the structure of the fourth embodiment as an example, the manufacturing method includes the following steps.As shown in FIG. 5 ( a), a first metal layer 11 is formed, the first metal layer including a first common electrode line 111 in a display region A and a third common electrode line 21 in a non-display region B.As shown in FIG. 5( b), a second metal layer 12 is formed on the first metal layer 11, and the second metal layer 12 includes a second common electrode line 121.Generally, the first common electrode line and the third common electrode line 21 are integrally formed and arranged in the same layer, but are not limited to this configuration. The third common electrode line 21 and the second common electrode line may also be integrally formed and arranged in the same layer.Further detailed description will be made below on the manufacturing method of the TFT provided by the present invention.As shown in Fig. 5(a), the first metal layer 11 is deposited on a substrate (not shown in the figure) by sputtering or evaporation, then an insulating layer (not shown in the figure) and a resist layer (not shown in the figure) are deposited to a certain thickness on the first metal layer 11 in plasma chemical vapor deposition, and the resist layer is exposed and developed by a gate mask plate to form a resist pattern; then, the first metal layer 11 is etched to remove the excess resist layer. A gate line 112, a first common electrode line 111, and a third common electrode line 21 are formed, and the gate line 112 has a double gate line structure.On this basis, as shown in FIG. 5 (b), a second metal layer 12 having a certain thickness is deposited, a data line 122, and a second common electrode line 121 cut by the gate line 112 and the first common electrode line 111 are formed by a mask plate of the data line 122, the second common electrode line 121 is cut from the first common electrode line 111 in an isolated manner, the gate line 112 is separated from the first common electrode line 111, and in this embodiment, the first common electrode line 111 is a straight line and parallel to the gate line 112; the data line 122 is separated from the second common electrode line 121 in this embodiment, the second common electrode line 121 is a straight line and parallel to the data line 122.As shown in FIGS. 5( a) to 5( c), a through hole 14 is formed in the insulating layer, and a pixel electrode 13 is formed on the second common electrode line 121.Accordingly, in other embodiments, the manufacturing methods are as follows.The first embodiment provides a TFT array substrate, and the fourth embodiment also provides a TFT array substrate. In the method for manufacturing the TFT array substrate of the first embodiment, the method for manufacturing the TFT array substrate provided in the fourth embodiment is partially modified. The repeated parts are omitted, and the difference between the method of manufacturing the TFT array substrate in the first embodiment and the method of manufacturing the TFT array substrate in the fourth embodiment is that no hole is formed in the insulating layer, that is, the through hole 14 is not present. Since the first and second common electrode lines are electrically connected to the third common electrode line, the process is simpler and smoother.The second embodiment provides a TFT array substrate. In the method of the second embodiment for manufacturing the TFT array substrate, the method of the fourth embodiment for manufacturing the TFT array substrate is partially modified. The repeated parts are omitted, and the difference between the method for manufacturing the TFT array substrate in the second embodiment and the method for manufacturing the TFT array substrate in the fourth embodiment is that the second common electrode line 121 is not connected to the third common electrode line 21.The third embodiment provides a TFT array substrate. In the method of the third embodiment for manufacturing the TFT array substrate, the method of the fourth embodiment for manufacturing the TFT array substrate is partially modified. The repeated parts are omitted, and the difference between the method for manufacturing the TFT array substrate in the third embodiment and the method for manufacturing the TFT array substrate in the fourth embodiment is that the first common electrode line 111 is not connected to the third common electrode line 21.The present invention further provides a display device (not shown in the figures) including a TFT array substrate and a color filter substrate (not shown in the figures) disposed opposite to the TFT array substrate, the TFT array substrate being selected from any of the TFT array substrates in the first embodiment, the second embodiment, the third embodiment and the fourth embodiment. A transparent common electrode (not shown in the figures) is disposed on a side of the color filter substrate, the side of the color filter substrate facing the TFT array substrate. The transparent common electrode and the pixel electrode form a vertical electric field such as a TN or a VA display device. As another preferred embodiment, the TFT array substrate may also include the transparent common electrode for forming a transverse electric field with the pixel electrode, for example, an IPS or FFS display device. Generally, the display device is a liquid crystal display device.Note also that a TFT active layer in the TFT array substrate of the present invention may be amorphous silicon, low temperature polysilicon, or metal oxide, and the manufacturing method thereof may employ the technology known in the art, which will not be described in detail herein. 2. in the present invention, the first common electrode line 111 may be formed by the same mask plate method as the gate line 112, and the first common electrode line 111 may also be formed by a different method from the mask plate method of the gate line 112, the second common electrode line 121 may be formed by the same mask plate method as the data line 122, and the second common electrode line 121 may also be formed by a different method from the mask plate method of the data line 122; it is only necessary that the first common electrode line 111 and the gate line 112 be arranged in the same metal layer and the second common electrode line 121 and the data line 122 be arranged in the same metal layer. 3. the pattern forming method of the present invention includes methods such as coating of resist, exposing through a mask, developing, etching, abrading resist, and the like; the resist is not limited to positive resist or negative resist, and in the above embodiments, the positive resist is exemplified.In summary, according to the TFT array substrate and the manufacturing method thereof, and the display device including the TFT array substrate of the present invention, it is to be noted that the first common electrode line 111 is disposed in the first metal layer 11 (the same layer as the gate line 112), the second common electrode line 121 is disposed in the second metal layer 12 (the same layer as the data line 122), and the double gate line structure is adopted, so that a certain number of data lines can be reduced. The second common electrode line 121 is arranged in the present invention by skillfully utilizing the reduced number of data lines so that the aperture ratio is not decreased; moreover, the delay of the common signal by the mesh-shaped wiring of the first common electrode line 111 and the second common electrode line 121 can be avoided. In the gate line control method of the gate line 112, the TFT array structure may perform the power conduction in the longitudinal direction (direction of the data line 122) and the lateral direction (gate line 112) to at least reduce the common signal delay, reduce flicker noise and crosstalk without reducing the aperture ratio, and improve the display quality. In addition, since the cost of the source drive (not shown in the figures) is higher than that of the gate drive (not shown in the figures) and a certain number of data lines are reduced, so that the number of source drives is correspondingly smaller, at least one of the effects of reduced manufacturing cost and simplified process operations can be achieved.It is to be understood that various modifications and variations may be made by those skilled in the art without departing from the principle and scope of the present invention. Accordingly, the present invention is intended to extend to these modifications and variations as well, provided that these modifications and variations are within the scope of the claims of the present invention and their equivalents.

Claims

A TFT array substrate having a display region (A) and a non-display region (B), the display region (A) comprising: a first metal layer (11) comprising a first common electrode line (111); and a second metal layer (12) comprising a second common electrode line (121); and wherein the non-display region (B) comprises a third common electrode line (21), wherein the third common electrode line (21) is electrically connected to at least one of the first common electrode line (111) and the second common electrode line (121), and wherein the first common electrode line (111) is not electrically connected to the second common electrode line (121) in the display region (A).The TFT array substrate according to claim 1, wherein the first and second common electrode lines (111, 121) are electrically connected to the third common electrode line (21) in the non-display area (B).The TFT array substrate according to claim 1, wherein the first metal layer (11) further comprises a gate line (112), and the second metal layer (12) further comprises a data line (122).The TFT array substrate according to claim 3, wherein the gate line (112) has a double gate line structure.The TFT array substrate according to claim 3, wherein the gate line (112) is separated from the first common electrode line (111), and the data line (122) is separated from the second common electrode line (121).The TFT array substrate according to claim 5, wherein the first common electrode line (111) and the second common electrode line (121) are straight lines or bent lines.The TFT array substrate according to claim 1, further comprising: an insulating layer disposed between the first metal layer (11) and the second metal layer (12).The TFT array substrate according to claim 1, wherein, in a plan view angle, a wiring shape of the second common electrode line (121) and the first common electrode line (111) is formed as an over-plane mesh.The TFT array substrate according to claim 1, further comprising: pixel electrodes (13) in the second metal layer (12); wherein the number of the second common electrode lines (121) in the TFT array substrate is i, the number of the pixel electrodes (13) in each row is j, 2*i is less than or equal to j, and i and j are positive integers.A manufacturing method of the TFT array substrate according to any one of the preceding claims 1-9, comprising: forming a first metal layer (11) comprising a first common electrode line (111) in a display area (A); forming a second metal layer (12) comprising a second common electrode line (121) on the first metal layer (11), wherein the first common electrode line (111) is not electrically connected to the second common electrode line (121) in the display area (A); and forming a third common electrode line (21) in a non-display area (B), wherein the third common electrode line (21) is electrically connected to at least one of the first common electrode line (111) and the second common electrode line (121).The manufacturing method of the TFT array substrate according to claim 10, wherein an insulating layer is formed between the first metal layer (11) and the second metal layer (12).A display device comprising: a TFT array substrate according to any one of claims 1-9; and a color filter substrate disposed opposite to the TFT array substrate; wherein another transparent common electrode is disposed on a side of the color filter substrate, and the side of the color filter substrate faces the TFT array substrate.

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