CIRCUIT WITH A PLURALITY OF BIPOLAR TRANSISTORS AND METHOD FOR CONTROLLING SUCH A CIRCUIT

Abstract

Method for operating a circuit, wherein the circuit comprises a first circuit node (21), a second circuit node (22) and a plurality of bipolar transistors (131-13 m ) which are connected in parallel between the first circuit node (21) and the second circuit node (22), the method comprising in one switching cycle: Selecting a first group of bipolar transistors of the plurality of bipolar transistors (131-13 m ); Selecting a first subgroup of the first group of bipolar transistors such that the first group has a first subgroup and a second subgroup, and the first subgroup and the second subgroup each comprise one or more of the plurality of bipolar transistors (131-13 m ), wherein a selection of the first subgroup of bipolar transistors depends on a load state of the circuit; Switching on the first group of bipolar transistors at the beginning of a first time interval (T on ); Switching off the bipolar transistors of the first subgroup at the end of the first time interval (T on ); and Switching off the bipolar transistors of the second subgroup at a time before the end of the first time interval (T on ).

Description

[0001] Embodiments of the present invention relate to a circuit having a plurality of bipolar transistors and a method for controlling such a circuit.

[0002] Bipolar transistors, such as IGBTs (insulated gate bipolar transistors), are widely used in various automotive and industrial applications. For example, in motor control or drive applications, IGBTs are often used in a power stage to drive a load. In such applications, the IGBTs can be switched on and off periodically.

[0003] From the publication US 2013 / 0 106 469 A1, a control contact driver circuit for driving a plurality of power semiconductors is known. The circuit comprises a driver unit configured to provide reference currents for pulling up and / or pushing down control terminals of the semiconductor components, and a distribution unit configured to amplify and / or distribute the reference currents to the control terminals.

[0004] US 5 337 254 A relates to an integrated semiconductor circuit chip and, in particular, to a circuit provided to programmably modify a drive signal output to a connection pad on a chip in accordance with process, temperature and output load parameters.

[0005] In electronic circuits, especially in power circuits that drive a load, diodes can be used as freewheeling elements that prevent damage to the transistors by suppressing voltage spikes or transients that can occur during switching operations.

[0006] During operation of bipolar semiconductor components, such as bipolar transistors and diodes, conduction losses occur. These conduction losses depend on the voltage across and the current through the respective component.

[0007] Furthermore, a charge carrier plasma with n-type and p-type charge carriers is stored in a bipolar semiconductor component when the semiconductor component is in a conducting state, i.e., when the semiconductor component carries a current. When the operating state of the semiconductor component changes from a conducting state to a non-conducting state, these charge carriers must be removed from the corresponding component. This process is often referred to as the reverse recovery process. During the reverse recovery process, the charge carriers flowing out of the component cause a reverse current. This reverse current, multiplied by the voltage across the component during the reverse recovery process, corresponds to the power losses resulting from the reverse recovery process.The time integral of these losses corresponds to the energy consumed each time the device changes from the conducting state to the non-conducting state.

[0008] In a half-bridge circuit, for example, which has two semiconductor components connected in series, losses are generated not only in the component that is turned off, but also in the other component that will subsequently take over the load current, since this component typically sees a very high voltage, where this component can be, for example, a freewheeling diode.

[0009] In general, components with a low forward voltage (and low conduction losses) have a higher reverse recovery charge for a given current rating and voltage blocking capability, and vice versa. Typically, a component's current rating is selected based on the highest currents encountered in the application in which it is used. A component with a high current rating has a large die size and a high reverse recovery charge. If the component operates at currents below its current rating, the component is oversized, resulting in relatively high reverse recovery losses at low currents.

[0010] The task is therefore to reduce transistor and diode losses in electronic circuits, especially in power electronics applications.

[0011] This object is achieved by a method according to claim 1 and by a circuit according to claim 19.

[0012] A method for driving a circuit is disclosed. The circuit has a first circuit node, a second circuit node, and a plurality of bipolar transistors connected in parallel between the first circuit node and the second circuit node. According to one embodiment of the present invention, the method comprises, in a drive cycle, selecting a first group of bipolar transistors from the plurality of bipolar transistors, and selecting a first subgroup of the first group of bipolar transistors, such that the first group of bipolar transistors has a first subgroup and a second subgroup, wherein the first subgroup and the second subgroup each comprise one or more of the bipolar transistors, and wherein a selection of the first subgroup of bipolar transistors depends on a load state of the circuit.The method further comprises turning on the first group of bipolar transistors at the beginning of a first time interval, turning off the bipolar transistors of the first subgroup at the end of the first time interval, and turning off the bipolar transistors of the second subgroup at a time before the end of the first time interval.

[0013] A circuit is further disclosed. According to one embodiment of the present invention, the circuit comprises a bipolar transistor circuit having a first circuit node, a second circuit node, and a plurality of bipolar transistors connected in parallel between the first circuit node and the second circuit node. A control circuit is configured to select a first group of the plurality of bipolar transistors and to select a first subgroup of the first group of bipolar transistors, such that the first group comprises a first subgroup and a second subgroup, wherein the first subgroup and the second subgroup each comprise one or more of the bipolar transistors, and wherein the first subgroup of bipolar transistors is selected depending on a load state of the circuit.The control circuit is further configured to switch on the first group at the beginning of a first time interval, to switch off the first subgroup at the end of the first time interval, and to switch off the second subgroup at a time before the end of the first time interval.

[0014] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and examining the accompanying drawings.

[0015] Examples will now be described with reference to the drawings. The drawings serve to illustrate the basic principle, so only those aspects necessary for understanding the basic principle are shown. The drawings are not to scale. In the drawings, like reference numerals indicate like features. Fig. 1 shows a first embodiment of a bipolar transistor circuit comprising a plurality of bipolar transistors; Fig. 2 shows timing diagrams illustrating an operating state of the circuit according to Fig. 1 represent; Fig. 3 shows an embodiment of a circuit arrangement comprising the bipolar transistor circuit of Fig. 1; Fig. 4 shows an embodiment of a circuit comprising a plurality of diodes; Fig. 5 shows a modification of the diode circuit from Fig. 4; Fig. 6 shows timing diagrams showing an operating state of the circuit according to Fig. 4 represent; Fig. 7 shows an embodiment of a diode circuit; Fig. 8 shows an embodiment of the circuit arrangement of Fig. 3; Fig. 9 shows an embodiment of a bipolar transistor circuit; Fig. 10 shows an embodiment of a diode circuit; and Fig. Figure 11 shows an example of chip-on-chip integration of a diode and a vertical p-MOS switch.

[0016] In the following detailed description, reference is made to the accompanying figures. The figures form a part of the description and, for illustrative purposes, show various embodiments in which the invention may be applied. It is understood that the features of the various embodiments described herein may be combined with one another, unless otherwise stated.

[0017] Fig. Figure 1 shows an embodiment of a circuit 40, which is referred to below as a bipolar transistor circuit. The bipolar transistor circuit 40 comprises a plurality of m bipolar transistors 131-13 m , where m≥2. The bipolar transistors 131-13 mare implemented as IGBTs in the present embodiment. However, other types of bipolar transistors may also be used, such as BJTs (Bipolar Junction Transistors). With reference to Fig. 1 are the load paths (collector-emitter paths) of the individual IGBTs 131-13 m connected in parallel between a first circuit node 21 and a second circuit node 22. This means that each of the IGBTs 131-13 m with its collector connected to the first circuit node 21 and with its emitter connected to the second circuit node 22.

[0018] The Fig. The circuit shown in Figure 1 comprises m=3 IGBTs. However, this is only an example. The total number of IGBTs may vary depending on the specific application in which the bipolar transistor circuit 40 is used.

[0019] Each of the individual IGBTs 131-13 mreceives a corresponding control signal S11-S1 m by a driver circuit 30. Each of these control signals S11-S1 m is designed to operate the corresponding IGBT 131-13 m on or off, whereby the individual IGBTs 131-13 m can be switched on and off independently of each other. Each of the control signals S11-S1 m can have a first signal level (on-level), which the corresponding IGBT 131-13 m switches on, or a second signal level (off level), which switches on the corresponding IGBT 131-13 mturns off. When the drive signal of an IGBT has the on level, a voltage level of the gate-emitter voltage (which is a voltage between the gate terminal and the emitter terminal) of the corresponding IGBT is above a threshold voltage, and when the drive signal of an IGBT has the off level, a voltage level of the gate-emitter voltage is below the threshold voltage.

[0020] In the Fig. 1, each of the IGBTs 131-13 m an individual control signal S11-S1 m However, this is only an example. It is also possible to combine two or more IGBTs 131-13 m with just one control signal.

[0021] The individual IGBTs 131-13 m can be integrated in a common semiconductor body (semiconductor chip) or in two or more different semiconductor bodies (semiconductor chips). It is also possible to integrate each of the IGBTs 131-13m to be integrated on its own semiconductor chip.

[0022] An operating state of the bipolar transistor circuit 40 from Fig. 1 is described below. For the purpose of explanation, it is assumed that the individual IGBTs 131-13 m have the same chip size so that they have the same current carrying capacity.

[0023] If the IGBTs 131-13 m are switched on, conduction losses occur. The conduction losses that occur at a certain load current I through the bipolar transistor circuit 40 depend, among other things, on the number of IGBTs 131-13 connected in parallel. m dependent, with the conduction losses decreasing as the number of IGBTs 131-13 m increased. An increase in the number of IGBTs 131-13 m results in an increase in the total chip size, which is the sum of the chip sizes of the individual IGBTs 131-13 m is.

[0024] However, increasing the chip size can result in an increase in switching losses. Switching losses occur in each of the IGBTs 131-13 m occurs when an operating state of the IGBT changes from an on state to an off state. This is described with reference to the j-th IGBT 13 j the variety of IGBTs 131-13 m described below. When the IGBT 13 j is in the switched-on state and conducts part of the load current I, a charge carrier plasma, which comprises electrons and holes, is present in the semiconductor regions of the IGBT 13 j present. If the j-th IGBT 13 j is switched off, the electrical charge resulting from this plasma (reverse recovery charge) is released from the IGBT 13 j The removal of the charge carrier plasma causes a reverse recovery current, which is discharged from the j-th IGBT 13 j Losses which occur in the j-th IGBT 13j (and an optional additional component which transfers the current from the IGBT 13 j takes over) in connection with the reverse recovery process are defined by the reverse recovery current multiplied by the voltage across the IGBT 13 j (and the other component) during the reverse recovery process. The “other component” (in Fig. 1 not shown) is, for example, a freewheeling element, such as a diode, which is connected in parallel to the IGBT 13 j This will be described in more detail below. The losses in the j-th IGBT 13 j increase towards the end of the reverse recovery process when the reverse recovery current is still high and when the voltage across the IGBT 13 j has already increased. The time integral of these losses corresponds to the energy stored in the j-th IGBT 13 j is consumed during each switching operation. The energy in each of the IGBTs 131-13m stored reverse recovery charge depends on the chip size of each individual IGBT 131-13 m and the current I through each IGBT 131-13 m , where for a given current I, the stored reverse recovery charge increases as the chip size increases.

[0025] In the bipolar transistor circuit 40 of Fig. 1, the total losses, which include the conduction losses and the switching losses, can be reduced by suitably insulating individual IGBTs 131-13 m be activated and deactivated during a switching cycle. A switching cycle comprises two consecutive time intervals, namely a first time interval T on and a second time interval T off , which are described in more detail below. Since switching losses during the transition of the IGBTs 131-13 mfrom the on state to the off state, in general, some of the variety of IGBTs 131-13 m initially at the beginning of the first time interval T on be switched on, and can then be switched on at the end of the first time interval T on Other IGBTs 131-13 m can also initially at the beginning of the first time interval T on be switched on and can be switched on before the end of the first time interval T on At least one of the IGBTs 131-13 m However, at the end of the first time interval T on off.

[0026] If one of the IGBTs 131-13 m before the end of the first time interval T on is turned off while at least one of the plurality of IGBTs 131-13 mis still switched on, the voltage across the switched-off IGBT corresponds at most to the voltage across the IGBT that is still switched on, with no current flowing through the corresponding further component that takes over the current after the IGBT has been switched off. The charge stored in the switched-off IGBT is removed from this IGBT at a relatively low voltage, namely the voltage across the switched-on IGBT. Therefore, the switching losses that occur in the IGBT that is switched on before the end of the first time interval t on is switched off, is lower than switching losses that would occur in this IGBT and the corresponding further component if the IGBT were not switched off prematurely, but at the end of the first time interval T on , and thus at the same time as at least one of the plurality of IGBTs 131-13 mThe difference between the switching losses actually occurring in the switched-off IGBT and the switching losses that would occur if the IGBT were switched off at the end of the first time interval T on would be switched off are referred to below as switching loss gain.

[0027] In the bipolar transistor circuit 40, the voltage across the IGBTs remaining in the on state increases when at least one of the other IGBTs is turned off. This results in an increase in the conduction losses in the bipolar transistor circuit 40. However, if the at least one IGBT is turned off relatively shortly before the end of the first time interval T on is turned off, this increase in conduction losses is less than the switching loss gain achieved by turning off at least one of the IGBTs early.

[0028] In this way, the active chip size can be optimized with regard to conduction losses and switching losses. At the beginning of the first time interval T on A first group of the multitude of IGBTs 131-13 m switched on. This first group may comprise all of the m IGBTs or fewer than the total number m, but at least one. From this first group of IGBTs, at least one IGBT is switched off before the end of the first time interval T on switched off. There are therefore two subgroups of IGBTs, namely a first subgroup of IGBTs that are switched on during the entire first time interval T on are switched on and a second subgroup of IGBTs which are switched off before the end of the first time interval T on be switched off.

[0029] With reference to Fig. 1, the driver circuit 30 receives an input signal S in . The input signal S incan assume a first signal level (on level) or a second signal level (off level). The on level can be a high level and the off level can be a low level, or vice versa. According to one embodiment, the input signal S in a PWM signal (PWM= pulse-width modulated) which alternates between the on level and the off level.

[0030] Referring to Fig. 2, which timing diagrams of the input signal S in , and control signals S1 x , S1 y , S1 z three different IGBTs of the bipolar transistor circuit 40, a switching cycle begins when the input signal S in assumes the first level at a first time t11.

[0031] With reference to the above description, there is a first group of IGBTs that are switched on at the beginning of the switching cycle. This first group of IGBTs comprises two subgroups, namely a first subgroup with at least one IGBT that is switched on for a first time interval, and a second subgroup with at least one IGBT that is switched on simultaneously with the at least one IGBT of the first subgroup and before the end of the first time interval T on is switched off. Optionally, there is a second group with at least one IGBT, which is not switched during the switching cycle. In Fig. 2 represents the control signal S1 x the control signal of the at least one IGBT of the first subgroup, the control signal S1 y the control signal of the at least one IGBT of the second subgroup and the control signal S1 zthe control signal of the at least one IGBT of the optional second group. In the embodiment in Fig. 2, a high level of the signal represents an on level of the corresponding control signal S1 x , S1 y and S1 z and a low level of the signal represents an off level of the corresponding control signal S1 x , S1 y and S1 z .

[0032] In the Fig. 2, the IGBTs of the first group (i.e. the IGBTs of the first and second subgroups) are switched on in dependence on the input signal S in switched on, that is, when the input signal assumes the on level. In a switching cycle, at least one IGBT (controlled by the signal S1 x ) of the first subgroup at the end of the first time interval T on , which in the Fig. 2 embodiment corresponds to the time t12, is switched off and the at least one IGBT (controlled by the signal S1 y ) of the second subgroup is before the end of the first time interval T on , in the embodiment in Fig. 2 at a time t1 x , switched off. Referring to Fig. 2, the turn-off time of the at least one IGBT of the second subgroup can be determined by the input signal S in be defined so that the at least one IGBT of the second subgroup switches off when the input signal S in from the on-level to an off-level. It should be noted that unavoidable delay times resulting from propagation delays in the control circuit (30 in Fig. 1) and which can cause the at least one IGBT of the second subgroup to switch shortly after the input signal S in has assumed the off-level, in the representation in Fig. 2 are not shown. In Fig. 2 indicates T on ' the time interval for which the input signal S in assumes the on-level, whereby this time interval is shorter than the first time interval T on .

[0033] The turn-off time of at least one IGBT of the first subgroup, i.e. the end of the first time interval T on , can be controlled by the input signal S in be defined such that the at least one IGBT of the first subgroup after a delay time T D turns off after the input signal S in has switched to the off level. In this case, the delay time T D the time interval by which the at least one IGBT of the second subgroup is switched off before the end of the first time interval T on turns off, that is, before at least one IGBT of the first subgroup turns off.

[0034] Referring to Fig. 2, a switching cycle comprises a second time interval T off (off period), which occurs at the end of the first time interval T on begins. During the second time interval T off each of the IGBTs of the first group is in an off state. The switching cycle ends and a new switching cycle begins at the end of the second time interval T off .

[0035] The number of IGBTs in the bipolar transistor circuit 40 which are switched on at the beginning of the first time interval T on are activated, i.e. the number in the first group, may vary based on a load condition of the bipolar transistor circuit 40. That is, there may be a second group of IGBTs which are activated during the first time interval T onare not switched on at all, whereby the number of IGBTs in this second group can vary depending on the load state of the bipolar transistor circuit 40. If m is the total number of IGBTs in the bipolar transistor circuit 40, then: m=m1+m2 where m1 ≥ 1 and m2 ≥ 0, and m1=m11+m12 where m11 ≥ 1 and m12 ≥ 1, and where m1 is the number of IGBTs in the first group, m2 is the number of IGBTs in the optional second group, m11 is the number of IGBTs in the first subgroup, and m12 is the number of IGBTs in the second subgroup. The number of IGBTs that are switched on at the beginning of the first time interval is m11 + m12, where m12 IGBTs are switched off before the end of the first time interval and m11 IGBTs are switched on throughout the entire first time interval.

[0036] According to one embodiment, the load state is represented by the load current I through the bipolar transistor circuit 40 when at least one of the IGBTs is turned on. In this embodiment, the drive circuit 30 receives a current signal S l , which represents the load current I and selects the first number m1 depending on this current signal S l . According to one embodiment, the control circuit 30 is designed to generate the current signal S I in a control cycle and to adjust the first number m1 of IGBTs which are switched on in a following control cycle, based on the evaluated current signal S I . According to one embodiment, the first number m1 of IGBTs which are switched on at the beginning of the first time interval T on switched on when the load current I decreases.

[0037] Accordingly, the number m 12 of IGBTs of the second subgroup can be adjusted depending on the current signal S I This number can be increased as the current I decreases. This corresponds to a reduction in the number of IGBTs in the first subgroup as the load current decreases.

[0038] The selection of IGBTs belonging to the first group and the optional second group, as well as the selection of IGBTs belonging to the first subgroup and the second subgroup, can change within each drive cycle or can change after multiple drive cycles. Especially in operating scenarios where there is a second group with at least one IGBT that is not activated at all, this can help to minimize losses between the IGBTs 131-13. m more evenly, since the selection of at least one IGBT belonging to the second group may change from time to time.

[0039] The first group and the optional second group, as well as the first subgroup and the second subgroup, represent a chip size that is the sum of the chip sizes of the IGBTs in the individual (sub)groups. In this case, the control circuit 30 can not only adjust the number of IGBTs in the first and second groups and the first and second subgroups depending on the current signal S I The IGBTs of the first and second groups can be selected such that the chip size represented by the first group increases as the load current increases. Similarly, the chip size represented by the second subgroup can increase as the load current decreases. This means that more chip size is deactivated before the end of the first time interval as the load current decreases.

[0040] According to another embodiment, at the beginning of the first time interval, only the transistors of the first subgroup are turned on, while the transistors of the second subgroup remain turned off during the first time interval. In this embodiment, the first group comprises the plurality of transistors, and there is no second group.

[0041] Fig. 3 shows schematically a circuit arrangement comprising a first bipolar transistor circuit 40 H and a second bipolar transistor circuit 40 L for driving a load L. The first and second bipolar transistor circuits 40 H , 40 L are in Fig. 3 are only shown schematically as circuit blocks and can each be used as the ones related to Fig. 1 bipolar transistor circuit 40 described above or as described with respect to the Fig. 8 and Fig. 10 described below. That is, the first and second bipolar transistor circuits 40 H , 40 L each comprise a plurality of IGBTs, each of these IGBTs having a control terminal and a load path. The load paths of the IGBTs in the first bipolar transistor circuit 40 H are connected between a first circuit node 21 H and a second circuit node 22 H switched and the load paths of the IGBTs of the second bipolar transistor circuit 40 L are connected between a third circuit node 21 L and a fourth circuit node 22 L switched on.

[0042] Referring to Fig. 3 form the first bipolar transistor circuit 40 H and the second bipolar transistor circuit 40 L a half-bridge circuit. This means that the load paths of the IGBTs of the first bipolar transistor circuit 40 Hand the load paths of the IGBTs of the second bipolar transistor circuit 40 L are connected in series between the first and fourth circuit nodes 21 H and 22 L switched. The second and third circuit nodes 22 H , 21 L are connected and form an output of the half-bridge to connect a load. The first circuit node 21 H is designed to receive a first supply potential and the fourth circuit node 22 L is configured to receive a second supply potential. The first supply potential can be a positive supply potential, while the second supply potential can be a negative supply potential or a reference potential, such as ground.

[0043] The first bipolar transistor circuit 40 H is also referred to as high-side transistor circuit and the second bipolar transistor circuit 40L is also referred to as low-side transistor circuit.

[0044] In Fig. 3 is of the first and second bipolar transistor circuit 40 H , 40 L One IGBT is shown schematically in each case. The IGBTs of the first and second bipolar transistor circuits 40 H , 40 L are as in Fig. 3. This means that the emitter terminals of IGBTs of the first bipolar transistor circuit 40 H with exit 21 L , 22 H and the emitter terminals of IGBTs of the second bipolar transistor circuit 40 L with the fourth circuit node 22 L are connected.

[0045] Referring to Fig. 3 is a freewheeling circuit parallel to each of the load paths of the bipolar transistor circuits 40 H , 40 L switched. A first freewheel circuit 10 His parallel to the load path of the high-side bipolar transistor circuit 40 H and a second freewheel circuit 10 L is parallel to the load path of the low-side bipolar transistor circuit 40 L switched. The freewheel circuits 10 H , 10 L each comprise at least one rectifier element, such as a diode. The at least one rectifier element in the first freewheeling circuit 10 H has a polarity such that the first freewheel circuit 10 H blocks when a voltage V H between the first and second circuit node 21 H , 22 H is a positive voltage (that is, when the voltage V H one like in Fig. 3 shown polarity), and that the first freewheel circuit 10 H conducts when the voltage V H between the first and second circuit node 21 H , 22 Ha negative voltage. Similarly, the at least one rectifier element in the second freewheeling circuit 10 L a polarity such that the second freewheel circuit 10 L blocks when a voltage V L between the third and fourth circuit node 21 L , 22 L is a positive voltage (that is, when the voltage V L one like in Fig. 3 shown polarity), and that the second freewheel circuit 10 L conducts when the voltage V L between the third and fourth circuit nodes 21 L , 22 L is a negative voltage.

[0046] Referring to Fig. 3, a load L, such as an inductive load, can be connected to the output node 21 L , 22 H The half-bridge circuit can be connected to this load L. This load L can be controlled PWM-like by the high-side transistor circuit 40H PWM-like on and off and by the low-side transistor circuit 40 L complementary to the high-side transistor circuit 40 H is switched on and off. This means that the low-side transistor circuit 40 L is turned off when the high-side transistor circuit 40 H is switched on, and that the low-side transistor circuit 40 L is switched on when the high-side transistor circuit 40 H is switched off. To avoid cross currents, a delay time (dead time) is required between the switching off of the high-side transistor circuit 40 H or the low-side transistor circuit 40 L and switching on the high-side transistor circuit 40 H or the low-side transistor circuit 40 L During this delay time, one of the freewheeling circuits 10 H , 10 L the current through the (inductive) load.

[0047] In the embodiment in Fig. 3, a control circuit 30 controls the operation of the high-side transistor circuit 40 H , the low-side transistor circuit 40 L and the freewheel circuits 10 H , 10 L . The freewheel circuits 10 H , 10 L are in Fig. 3 are shown merely as circuit blocks and can be implemented in various ways. Some embodiments for implementing these freewheeling circuits 10 H , 10 L are with reference to the Fig. 4, Fig. 5, Fig. 7 and Fig. 9 described below.

[0048] Fig. 4 shows a first embodiment of a freewheeling circuit 10 which can be used to control the first or the second freewheeling circuit 10 H , 10 L out of Fig. 3. The freewheel circuit 10 from Fig. 4 comprises a plurality of n diodes 111-11 n , with n≥2, and is referred to as a diode circuit. The individual diodes 111-11 n are parallel to each other between a first circuit node 21 D and a second circuit node 22 D switched on. In the embodiment in Fig. 4 shows n=4 diodes. However, this is an example. The number of diodes is 111-11 n may vary depending on the specific application in which the diode circuit 11 is used. In the present embodiment, the diodes 111-11 n with their cathodes to the first circuit node 21 D and with their anodes to the second circuit node 22 D tied together.

[0049] The circuit nodes 21 D , 22 Dare designed to receive a voltage. This voltage V can have a first or second polarity. The first polarity forward-biases the diodes 111-112, while the second polarity reverses the diodes 111-11 n polarity in reverse. A voltage level of the voltage V with the first polarity is also referred to as the first voltage level V1, and a voltage level with the second polarity is also referred to as the second voltage level V2.

[0050] In the embodiment in Fig. 4 the individual diodes 111-11 n can be activated or deactivated independently of each other. For this purpose, a corresponding switch 121, 122, 123, 12 n in series with each of the diodes 111-11 n switched. A control circuit 30 D is designed to control the control signals S1, S2, S3, S n which the individual switches 121-12 non and off. The functional principle of the control circuit 30 D is described below. Each of the multitude of diodes 111-11 n is activated when the corresponding switch 121, 12 n , which is connected in series to the respective diode, is switched on (is in an on state) and each of the diodes 111-11 n is deactivated when the corresponding switch 121-12 n , which is connected in series with this diode, is switched off (is in an off state). The individual diodes 111-11 n can be integrated on a single semiconductor chip or on two or more different semiconductor chips. It is also possible to integrate each of the diodes 111-11 n on a single semiconductor chip.

[0051] The possibilities of each of the variety of diodes 111-11 nActivating or deactivating them independently is merely an example. According to a further embodiment, at least one of the diodes 111-11 n always activated. According to a further embodiment, at least two of the diodes 111-11 n activated and deactivated together. An embodiment of a diode circuit 10 in which both of these options are implemented is shown in Fig. 5 shown.

[0052] In the diode circuit 10 in Fig. 5, a first diode 111 is always activated. This means that the first diode 111 is directly connected with its cathode to the first circuit node 21 D and with its anode directly to the second circuit node 22 D connected so that no switch is connected between the first diode 111 and one of these circuit nodes 21 D , 22 D A second diode 112 and a third diode 113 are connected via a common switch 12 23, which activates or deactivates the second and third diodes 112, 113, with the circuit nodes 21 D , 22 D tied together.

[0053] The functional principle of the diode circuits 10 from the Fig. 4 and Fig. 5 is described below. For the purpose of explanation, it is first assumed that each of the diodes 111-11 n is activated. This means that each of the diodes 111-11 n can carry a current when the first voltage level V1 is applied to the circuit nodes 21 D , 22 D For the purpose of explanation only, it is further assumed that the individual diodes 111-11 n have the same chip size so that they have the same current carrying capacity.

[0054] If the diodes 111-11 n are forward-biased, conduction losses occur. For a given load current I Dby the parallel circuit with the diode 111-11 n These conduction losses can be reduced by increasing the number of diodes 111-11 n of the diode circuit 10 is increased, which means that the overall chip size is increased. The overall chip size is the sum of the chip sizes of the individual diodes 111-11 n .

[0055] However, an increase in chip size can result in an increase in commutation losses. Commutation losses occur in each of the diodes 111-11 n occurs when an operating state of the respective diode changes from a forward-biased state to a reverse-biased state, that is, when the voltage V changes from the first voltage level V1 to the second voltage level V2. This is described with reference to the j-th diode 11 j of the multitude of diodes is described below. If the j-th diode 11 jis forward-biased and conducts part of the current I, a charge carrier plasma, which contains electrons and holes, is formed in the semiconductor regions of the diode 11 j present. If the j-th diode 11 j is reversely polarized, the electrical charge resulting from this plasma (reverse recovery charge) is discharged from the diode 11 j The removal of the charge carrier plasma generates a reverse recovery current (often referred to as I RR denoted) by the j-th diode 11 j flows. Losses in the j-th diode 11 j in connection with the reverse recovery process are determined by the reverse recovery current multiplied by the voltage across diode 11 j during the reverse recovery process. These losses in the j-th diode 11 jincrease towards the end of the reverse recovery process when the reverse recovery current is still high and when the voltage across diode 11 j has already increased. The time integral of these losses corresponds to the power dissipated in diode 11 j during each switching process. The reverse recovery charge, which is stored in each of the diodes 111-11 n stored at a given current I depends on the chip size and the current through each of the diodes 111-11 n where the reverse recovery charge at a given current increases as the chip size increases.

[0056] Furthermore, losses resulting from the reverse recovery current of a diode can occur in a component that takes over the current from the diode. For example, if one assumes that in the circuit according to Fig. 3 the high-side transistor circuit 40 H and the low-side transistor circuit 40L are alternately switched on and off, and that there is a dead time between switching off one of the high-side transistor circuits 40 H and the low-side transistor circuit 40 L and switching on the other of the high-side transistor circuit 40 H and the low-side transistor circuit 40 L For example, if the low-side transistor circuit 40 L has been switched off, the diode circuit 10 takes over L , which is parallel to the low-side transistor circuit 40 L connected, the load current I through the inductive load L. If the high-side transistor circuit 40 H turns on, the current I decreases L through the diode circuit 10 L and the current through the high-side transistor circuit 40 H (which is in one of the Fig. 3) increases. Towards the end of this process, a reverse recovery current flows through the diode circuit 10 L in one of the Fig. 3 shown current I L opposite direction. This reverse recovery current flows in addition to the load current I through the high-side transistor circuit 40 H . The voltage across the high-side transistor circuit 40 H However, at the time when the reverse recovery current in the diode circuit 10 L occurs still be relatively high, since the high-side transistor circuit 40 H may not be fully switched on at this point. Therefore, the reverse recovery current can cause relatively high losses in the high-side driver circuit 40 H which causes the load current I from the diode circuit 10 L will take over.

[0057] In the diode circuits 10 in the Fig. 4 and Fig. 5, the total losses, which include the conduction losses and the switching losses, can be minimized by the individual diodes 111-11 n be activated and deactivated in a suitable manner during the commutation process. This process comprises two successive time intervals, namely an on-time during which the voltage V assumes the first voltage level V1 and during which it is desired that at least one of the diodes 111-11 n carries a current, and an off-time during which the voltage V assumes the second voltage level V2 and during which it is desired that no current flows between the circuit nodes 21, 22. In general, some of the plurality of diodes 111-11 n be activated at the beginning of the turn-on time, since commutation losses during the transition of the diodes 111-11 nfrom the forward biased state (on state) to the reverse biased state (off state), and some of the multitude of diodes 111-11 n can be deactivated before this transition occurs. At least one of the diodes 111-11 n remains activated.

[0058] In the Fig. 4, some diodes of the diode circuit 10 L for example, be deactivated before the high-side transistor circuit 40 H a current. Between a point in time when at least one control signal S1 1H -S1 nH assumes an on-level and a time when the high-side transistor circuit 40 H (at least one transistor in the high-side transistor circuit 40 H) begins to conduct, there is an unavoidable delay time. This delay time corresponds to the time required to charge an internal gate-source capacitance of the at least one transistor to a threshold voltage at which the at least one transistor begins to conduct.

[0059] If one of the diodes 111-11 n is deactivated, while at least one other of the plurality of diodes 111-11 nis still activated, the voltage across the deactivated diode (or diodes) corresponds at most to the voltage across the diode that is still forward biased. The charge stored in the deactivated diode decreases when the current through the diode decreases to zero. Therefore, the amount of switching losses that occur in the deactivated diode before a voltage that reverse biases the diode is applied to circuit nodes 21, 22 is less than a second amount of switching losses that would occur in this diode if the diode were not deactivated but instead were reverse biased by the voltage V between circuit nodes 21, 22. The difference between the first amount and the second amount is referred to below as the switching loss gain.

[0060] In diode circuit 10, the voltage across the activated diodes increases when at least one of the diodes is deactivated. This results in an increase in conduction losses in diode circuit 10 after deactivation. However, particularly when the at least one diode is deactivated relatively shortly before the end of the on-time, this increase in conduction losses is smaller than the commutation loss gain achieved by deactivating the at least one of the diodes earlier.

[0061] In this way, the active chip size can be optimized with respect to conduction losses and commutation losses. At the beginning of the turn-on time, a first number of diodes 111-112 are activated. This first number can be equal to the total number n or can be less than the total number, but at least one (1). Of this number of diodes, at least one diode is deactivated before the end of the turn-on time. There are therefore two groups of diodes: a first group of diodes that are always activated during the turn-on time, and a second group of diodes that are deactivated before the end of the turn-on time. The first group can include diodes that cannot be deactivated (for example, because there is no switch connected in series with the diode) or diodes that can be activated and deactivated and that are always activated during the turn-on time.

[0062] According to another embodiment, the diodes of the second group are not activated at all during the turn-on time. This means that these diodes remain deactivated during the turn-on time, while only the diodes of the first group are activated.

[0063] Fig. 6 shows timing diagrams that illustrate the operating principle of the Fig. 4 and Fig. 5 shown diode circuits 10. In Fig. 6 shows the timing diagram of the voltage V which is applied between the first circuit node 21 D and the second circuit node 22 D as well as the activation states of the diodes of the first group and the second group. The activation state of the diodes of the first group is determined by a control signal S2 k which activates at least one of the diodes of this group, and the activation state of the diodes of the second group is determined by a control signal S2 jwhich activates or deactivates at least one of the diodes of this group. For the purpose of explanation, it is assumed that the corresponding diode is activated when the control signal S2 j , S2 k assumes a high level (logical state “1”) and is deactivated when the control signal assumes a low level (logical state “0”).

[0064] In Fig. 6, T1 is the turn-on time, which lasts from a first time t21 to a second time t22. During the turn-on time T1, the voltage V applied between the first circuit node 21 and the second circuit node 22 assumes the first voltage level V1, which activates the activated diodes of the plurality of diodes 111-11 nin the forward direction. T2 is the off-time between the second time t22 and a third time t23. During the off-time T2, the voltage V, which is present between the first circuit node 21 and the second circuit node 22, assumes the second voltage level V2, which activates the activated diodes of the plurality of diodes 111-11 n polarity in reverse direction. The voltage V is in Fig. 6 is only shown schematically. In a real circuit, the edges of the voltage V are of course not vertical (as in Fig. 6).

[0065] Referring to Fig. 6, the second group of diodes is activated for most of the turn-on time T1. At a time t2 x However, shortly before the end of the on-time T1, at least one diode of the second group is deactivated (in Fig. 6 represented by the control signal S2 j , which at time t2 xassumes a low level), while at least one diode of the first group is still activated.

[0066] According to one embodiment, a time difference between the time t2 x , at which the at least one diode of the second group is deactivated, and the time t22, at which the diode circuit 10 is reverse-biased, is between one and five times the charge carrier lifetime of the charge carriers in the diodes. This time difference can, in particular, be between one microsecond (µs) and 10 µs.

[0067] In the embodiment in Fig. 6, a new operating cycle begins at time t23, when the voltage V again assumes the first voltage level V1, which forward-biases the diode circuit 10. At this time, the diodes of the first group and the second group are reactivated. In contrast to the representation in Fig. 6, the activation can also take place at an earlier time between t22 and t23. This is the case for the control signal S2 j in Fig. 6 represented by dashed lines.

[0068] In the Fig. In the embodiment illustrated in Figure 6, the at least one diode of the first group is deactivated (at time t22) when the voltage V reverse-biases the diode circuit 10. However, this is only an example.

[0069] It is also possible to permanently activate at least one diode of the first group. This is done in Fig. 6 is represented by dashed lines. In this case, an activation and deactivation circuit of the at least one diode of the first group can be omitted.

[0070] The deactivation of at least one diode of the second group at a time before the voltage V reverse polarizes the diode circuit 10 requires advance information about the time (in Fig. 6 Time t22), at which the voltage V will reverse polarize the diode circuit. In general, the polarity of this voltage V depends on a control signal (drive signal), so that the information about the time at which the voltage V will reverse polarize the diode circuit can be obtained from this control signal. In the circuit in Fig. 3 depends on the polarity of the voltages V H and V L via the diode circuits 10 H , 10 L of control signals S1 14 -S1 nH , S1 1L -S1 nL which are controlled by the high-side and low-side transistor circuits 40 H , 40 Lare received, these signals depending on the input signal Sin. According to one embodiment, the control circuit 30 introduces a delay time between rising and falling edges of the input signal S in , and corresponding rising and falling edges of at least some of the signals S1 1H -S1 nH , S1 1L -S1 nL (e.g. as in relation to the signals S in and S1 x in Fig. 2). In this case, the information about the time at which the high-side or low-side transistor circuit 40 H , 40 L completely on or off (and the polarity of one of the voltages V H , V L causes) in advance from the input signal S in be obtained.

[0071] The selection of diodes 111-11 nwhich belong to the first group and the second group can change in each drive cycle or can change after several drive cycles. Especially in operating scenarios in which at least one diode is not activated at all, this can help to reduce the losses among the diodes 111-11. n more evenly, since the selection of at least one diode that is not activated may change from time to time.

[0072] The number of diodes that are activated at the beginning of the on-time, i.e., the sum of the number of diodes in the first group and the number of diodes in the second group, can change depending on the load state of the diode circuit 10. This means that there can be another group of diodes that are not activated at all during the on-time, whereby the number of diodes in this additional group can change depending on the load state of the diode circuit 10. If n is the total number of diodes in the diode circuit, the following applies: n=n1+n2+n3 where n1 is the number of diodes in the first group, n2 is the number of diodes in the second group, and n3 is the number of diodes in the next group. The number of diodes activated at the beginning of the on-time is n1 + n2, with n1 diodes activated during the entire time interval T1 (and optionally also during the off-time T2) and n2 diodes deactivated before the end of the on-time T1.

[0073] According to one embodiment, the load state is determined by the load current I D represented by the diode circuit 10 in the forward-biased state. In this embodiment, the control circuit 30 receives D the current signal S ID , which determines the load current I D represents and selects the first number depending on the current signal S ID . The control circuit 30 D can be designed to measure the current signal S Iin one control cycle and the total number of diodes that are activated in a subsequent control cycle depending on the evaluated current signal S ID According to a further embodiment, the control circuit 30 D designed to adjust the number of activated diodes in a control cycle. In the same way, the number of diodes in the second group can be adjusted depending on the current signal S ID This number can increase if the current I D According to one embodiment, the total number of diodes activated at the beginning of the turn-on time decreases as the load current I D reduced.

[0074] According to a further embodiment, all diodes 111-11 nactivated at the beginning of the switch-on time, while the number of diodes of the first group is variable, depending on the current signal S ID .

[0075] The first group and the second group each represent a chip size which is the sum of the chip sizes of the diodes in the respective group. According to one embodiment, the individual diodes have different chip sizes. In this case, the control circuit 30 D not only the number of diodes of the first and second group depending on the current signal S IThe diodes of the first and second groups can also be selected such that the chip size represented by the first group and the chip size represented by the second group increase as the load current increases. Similarly, the chip size represented by the second group can increase as the load decreases, meaning that more chip size is deactivated before the end of the on-time when the load current decreases.

[0076] The control circuit 30 D can be designed to detect the beginning of the switch-on time T1 by detecting the polarity of the voltage between the circuit nodes 21 D , 22 D Of course, the diodes that are activated at the beginning of the switch-on time can already be activated during the switch-off time preceding the switch-on time (e.g. by switching the corresponding switch 121-12 n).

[0077] The diodes 111-11 n The diode circuit 10 can be integrated into a semiconductor body. The diodes 111-11 n can, for example, be isolated from each other by dielectric regions.

[0078] Referring to Fig. 7, switches 121-12 n to activate and deactivate the diodes 111-11 n MOS transistors, such as MOSFETs. In the Fig. In the embodiment shown in Figure 7, the MOSFETs are p-type. However, any other type of MOSFET or any other type of circuit element may be used instead.

[0079] The switches 121-12 n can be implemented with relatively low blocking voltage capability. Any of the individual switches 121-12 n blocks when the diode circuit 10 is forward biased and when the corresponding diode 111-11 nshould be deactivated. In this case, however, at least one of the other diodes 111-11 n activated, so that the voltage between circuit nodes 21, 22, which corresponds to the voltage across the blocking switch, essentially corresponds to the forward voltage of the at least one forward-biased diode. This voltage is at most a few volts. Switch 121-12 n with a low blocking voltage capability that can be used in the diode circuit 10, usually have a low on-resistance, so that the in series with the diodes 111-11 n switched switch 121-12 n do not significantly increase the conduction losses of the diode circuit 10. Protection diodes (not shown), such as Zener or avalanche diodes, can be connected in parallel with the switches to reduce the voltage across the switches 121-12 n to limit.

[0080] If the diode circuit 10 is reverse polarized, the diodes 111-11 n the reverse biasing voltage and thereby protect the switches 121-12 n . According to one embodiment, the switches 121-12 n switched on when the diode circuit 10 is reverse polarized. This helps to reduce the voltage across the individual switches 121-12 n to keep low and the switches 121-12 n to protect. If switches 121-12 n are implemented as MOSFETs, whose internal body diode is directly connected to the corresponding diode 111-11 n is switched back-to-back, there is no reason to switch the switches 121-12 n to turn on when the diode circuit 10 is reverse biased. In this case, the body diode of each MOSFET limits the voltage across the MOSFET to the forward voltage of the body diode. Referring to Fig. 7 is the internal body diode of a p-type MOSFET, which has its drain terminal connected to the anode terminal of the corresponding diode (or has its source terminal connected to the cathode terminal of the corresponding diode), connected immediately after the corresponding diode.

[0081] Fig. 8 shows an embodiment of the circuit arrangement of Fig. 3 in more detail. In this circuit, the high-side transistor circuit comprises 40 H a variety of IGBTs 13 1H -13 mH , which are connected with their load paths (collector-emitter path) parallel to each other between the first and the second circuit node 21 H , 22 H The low-side transistor circuit 40 L includes a variety of IGBTs 13 1L -13 mL , which are connected with their load paths (collector-emitter path) parallel to each other between the third and fourth circuit nodes 21 L , 22L The first and second freewheel circuits 10 H , 10 L are as with reference to the Fig. 7 and each comprise a plurality of diodes 11 1H -11 nH and 11 1L -11 nL , which can be activated and deactivated by switches connected in series with the diodes. These freewheeling circuits 10 H , 10 L However, as with reference to the Fig. 4 to 7 described above may be modified.

[0082] In the embodiment in Fig. 8 corresponds to the number of diodes 11 1H -11 nH the first freewheel circuit 10 H the number of IGBTs in the high-side transistor circuit 40 H and the number of diodes 11 1L -11 nL the second freewheel circuit 10 L corresponds to the number of IGBTs in the low-side transistor circuit 40 LHowever, this is only an example. The number of diodes is 11 1H -11 nH the first freewheeling circuit can also depend on the number of IGBTs of the high-side transistor circuit 40 H differ and the number of diodes 11 1L -11 nL the second freewheel circuit 10 L may differ from the number of IGBTs in the low-side transistor circuit 40 L Furthermore, each of the diodes 11 1H -11 nH , 11 1L -11 nL in the Fig. 8 shown first and second freewheel circuits 10 H , 10 L activated and deactivated. This means that each of these diodes 11 1H -11 nH , 11 1L -11 nL a corresponding switch S2 connected in series. However, it is also possible that one of these diodes is permanently activated, with no switch connected in series with this diode.

[0083] The circuit with the half-bridge circuit 40 H , 40 L and the freewheel circuits 10 H , 10 L can be used in any type of circuit arrangement in which a half-bridge is required. According to one embodiment, the circuit is used in a drive application for driving an electric motor. In this type of application, the IGBTs in the bipolar transistor circuits 40 H , 40 L and the diodes 11 1H -11 nH , 111 L -11n L in the freewheel circuits 10 H , 10 L are subjected to different loads at different times during operation. The IGBTs 12 1H -12 nH , 12 1L -12 nL can be loaded more during such time intervals in which the motor (connected to the output 21 L , 22 H is connected to Fig. 8 not shown) from the supply connections 21 H , 22 L via the half-bridge circuit 40 H , 40 L Energy is provided. The diodes 11 1H -11 nH , 11 1L -11 nL can be subjected to greater load during braking, while energy is transferred from the motor via the freewheel circuits 10 H , 10 L to the power supply connections 21 H , 22 L The IGBTs 12 1H -12 nH , 12 1L -12 nL in the biopolar transistor circuits 40 H , 40 L and the diodes 11 1H -11 nH , 11 1L -11 nL in the freewheel circuits 10 H , 10 L can therefore be controlled individually. A control circuit 30 controls the operation of the high-side transistor circuit 40 H , the low-side transistor circuit 40 L and the freewheel circuits 10H , 10 L .

[0084] According to one embodiment, the control circuit 30 is designed to control the high-side transistor circuit 40 H and the low-side transistor circuit 40 L to switch on and off depending on an input signal, as described above with reference to the Fig. 1 to 3, wherein the high-side transistor circuit 40 H can be switched on when the input signal S in assumes a high level, and the low-side transistor circuit 40 L can be switched on when the input signal S in assumes a low level. The high-side transistor circuit 40 H “Turn on” means that a first group of IGBTs in the high-side transistor circuit 40 H switches on as determined by the input signal S incontrolled, wherein a first subgroup remains in the switched-on state for a first time interval and a second subgroup is switched off before the end of the first time interval. Optionally, a second group of IGBTs of the high-side transistor circuit 40 H cannot be switched on. The control circuit 30 can control the number of IGBTs in the first group and the second group as well as the number of IGBTs in the first and second subgroups based on a load current signal S IH , which causes a load current through the high-side transistor circuit 40 H represents, control.

[0085] Likewise, the low-side transistor circuit 40 L “switch on” that a first group of IGBTs of the low-side transistor circuit 40 L as from the input signal S in, controlled, wherein a first subgroup remains in the switched-on state for a first time interval and a second subgroup is switched off before the end of the first time interval. Optionally, a second group of IGBTs of the low-side transistor circuit 40 L not switched on. The control circuit 30 can control the number of IGBTs in the first group and the second group and the number of IGBTs in the first and second subgroups based on a load current signal S IL , which generates a load current through the low-side transistor circuit 40 H represents select.

[0086] Furthermore, the control circuit 30 controls the freewheel circuit 10 H based on a load current signal S IH , which determines the load current I H through the high-side transistor circuit 40 H and the freewheel circuit 10 Hrepresents, and the control circuit 30 controls the freewheeling circuit 10 L depending on the load current signal S IL , which determines the load current I L through the low-side transistor circuit 40 L and the freewheel circuit 10 L represents.

[0087] According to one embodiment, one or more IGBTs of the high-side circuit 40 H or the low-side circuit 40 L and one or more diodes of this high-side circuit 40 H or low-side circuit 40 Lintegrated into a power semiconductor module, which comprises a module with a substrate, such as a DCB (Direct Copper Bonding) substrate, on which the at least one IGBT and the at least one diode are located, and a housing. In this case, and in the case where there is a second group of IGBTs and the diodes that are permanently deactivated during a switching cycle, the at least one IGBT and the corresponding diode of a module are deactivated.

[0088] Under certain conditions, the bipolar transistor circuit 40 can Fig. 1, a peak voltage (overvoltage) may occur when at least one IGBT is switched off. According to one embodiment, the bipolar transistor circuit 40 comprises a protection device that switches on at least some of the switched-off IGBTs in the event of an overvoltage. One embodiment of a bipolar transistor circuit 40 with an overvoltage protection device is shown in Fig. 9. In this bipolar transistor circuit 40, those of the IGBTs 131-13 m which are switched off are switched on whenever the voltage V reaches a voltage level that is higher than a predetermined voltage level. The predetermined voltage level is selected such that the voltage V reaches this voltage level only in the event of an overvoltage. In the embodiment in Fig. 9, the protective device has Zener diodes 151-15 m Each of these Zener diodes 151-15 m is between the collector terminal and the gate terminal of one of the IGBTs 131-13 m Each of the Zener diodes 151-15 m is connected in such a way that it connects the corresponding IGBT 131-13 m turns on when a voltage across the load path (collector-emitter voltage) of the IGBT essentially exceeds the breakdown voltage (Zener voltage) of the Zener diode 151-15 m The Zener diode 151-15 mswitches the IGBT 131-13 m independent of the corresponding control signal S11-S1 m This means that the Zener diode 151-15 m the control signal S11-S1 m overruled when the voltage V reaches the specified threshold. When the IGBT 131-13 m that was originally switched off, it takes over part of the total current and thereby reduces the current through the IGBTs that were already switched on. The individual Zener diodes 151-15 m keep the IGBTs in a conducting state until the voltage V between the circuit nodes 21, 22 falls below the specified threshold. Optionally, a bipolar diode 151-15 m directly after each of the Zener diodes 151-15 m be switched on.

[0089] Furthermore, a peak current (overcurrent) may also occur in the diode circuit 10 if it is forward-biased. Particularly in operating scenarios in which at least one of the diodes 111-11 n is deactivated, there is a risk that the peak current will overload these activated diodes.

[0090] According to one embodiment, the diode circuit 10 includes a protection device that activates at least some of the deactivated diodes in the event of an overcurrent condition. Another embodiment of a diode circuit 10 with an overcurrent protection device is described in Fig. 10. In this diode circuit 10, the switches 121-12 n , which are switched off to the respective diodes 111-11 nto turn off, whenever the voltage V has a polarity that forward-biases the diode circuit 10 and has a voltage level that is higher than a predetermined voltage level. The predetermined voltage level is selected such that the voltage V reaches this voltage level only in the event of an overcurrent. In the embodiment in Fig. 10, the protective device has Zener diodes 141-14 n Each of these Zener diodes 141-14 n is between the drain terminal D and the gate terminal G of one of the switches 121-12 n , which in the embodiment in Fig. 10 are implemented as p-type (enhancement-mode) MOSFETs. Each of these Zener diodes 141-14 n is connected in such a way that it connects the corresponding MOSFET 121-12 nturns on when a voltage across the load path (drain-source voltage) of the MOSFET essentially exceeds the breakdown voltage (Zener voltage) of the Zener diode 141-14 n The Zener diode 141-14 n switches the MOSFET 111-11 n independent of the corresponding control signal S21-S2 n This means that the Zener diode controls the control signal S1-S n overruled when the voltage V reaches the specified threshold. When the MOSFET 121-12 n a diode that was deactivated switches on, the corresponding diode 111-11 takes over n a portion of the total current, thereby reducing the current through the diodes that were previously activated. The individual Zener diodes keep the MOSFETs of deactivated diodes in a conducting state until the voltage V between circuit nodes 21, 22 falls below the specified threshold.

[0091] The deactivation means (switch) 121-12 nand the diodes 111-11 n can be integrated in the same package or module. According to one embodiment, a switch and the corresponding diode are integrated in a chip-on-chip arrangement, wherein a first semiconductor chip comprises the diode and a second semiconductor chip comprises the switch.

[0092] Fig. 11 shows an embodiment of such a chip-on-chip arrangement. In Fig. 11 denotes the reference number 11 i the i-th diode of the diodes 111-11 n as described above, and the reference numeral 12 i indicates the corresponding switch. With reference to Fig. 11 is the i-th diode 11 iimplemented as a vertical diode and comprises a first semiconductor body 100 having a first emitter region (anode region) 111 of a first conductivity type and a second emitter region (cathode region) 112 of the second conductivity type. The first and second emitter regions 111, 112 are arranged at a distance from one another in a vertical direction of the first semiconductor body 100. A base region 113 of the first or second conductivity type, which has a lower doping than the first and second emitter regions 111, 112, is arranged between the first and second emitter regions 111, 112.The first emitter region 111 is electrically connected to a first contact electrode 121 arranged on a first surface 101 of the first semiconductor body 100, and the second emitter region 112 is electrically connected to a second contact electrode 112 arranged on a second surface 102 opposite the first surface 101.

[0093] In the embodiment in Fig. 11, the MOSFET is 12 iimplemented as a vertical MOSFET having at least one transistor cell in a second semiconductor body 200. The transistor cell has a source region 211 electrically connected to a source (S) electrode 221, a body region 212 adjoining the source region 211, and a drift region 213. The body region 212 is arranged between the drift region 213 and the source region 211. The MOSFET further has a drain region 214 electrically connected to a drain electrode 223, wherein the drift region 213 is arranged between the drain region 214 and the body region 212. The MOSFET further has a gate electrode 231 adjacent to the body region 212 and dielectrically insulated from the body region 212 by a gate dielectric 232.The gate electrode 231 includes various gate electrode sections, each gate electrode section being arranged adjacent to the source and body regions 211, 212 of each transistor cell. Each of these gate electrode sections is electrically connected to the gate terminal G (although in . Fig. 10 only shows the connection between a gate electrode portion and the gate terminal G. Gate electrode 231 serves, in a conventional manner, to control a conductive channel in the body region 212 between the source region 211 and the drift region 213. Gate electrode 231 is electrically connected to the gate terminal G.

[0094] The MOSFET may comprise a plurality of transistor cells, wherein the individual transistor cells are connected in parallel to one another by being electrically connected to a common source electrode 221 via their source region 211. Furthermore, the individual transistor cells share the drift region 213 and the drain region 214. The source electrode 221 is further connected to the body regions 212 of the individual transistor cells.

[0095] The MOSFET can be implemented as an n-type MOSFET or a p-type MOSFET. In an n-type MOSFET, the source region 211, the drift region 213, and the drain region 214 are n-doped, while the body region 212 is p-doped. In a p-type MOSFET, the source region 211, the drift region 213, and the drain region 214 are p-doped, while the body region 212 is n-doped.

[0096] Referring to Fig. 11 is the drain electrode 223 with an anode electrode 221 of the diode 11 ielectrically connected. A connecting layer 300, such as a solder layer, an electrically conductive adhesive layer, or the like, may be arranged between the anode electrode 121 and the drain electrode 223.

[0097] According to one embodiment, the MOSFET 12 i a p-type MOSFET, wherein the first emitter region 111 of the diode is p-doped to form an anode region of the i-th diode 11 i while the second emitter region 112 is n-doped to form a cathode region. The base region 113 can be either n-doped or p-doped.

[0098] Fig. 11 shows a diode 11 i and the corresponding switch 12 iAccording to a further embodiment (not shown), multiple diodes may be integrated in a semiconductor body 100. In this case, the individual diodes share the second emitter region 112 and the base region 113. The first emitter regions 111 of the individual diodes are arranged spaced apart from one another in a lateral direction of the semiconductor body 100. Optionally, vertical dielectric layers are arranged between the individual first emitter regions 111 of the different diodes. A MOSFET or another type of switch may be applied to each of the first emitter regions 111 to activate or deactivate the corresponding diode.

[0099] In the embodiments described above, the circuit symbols of the individual diodes are the circuit symbols of bipolar diodes (PIN diodes). However, it is also possible to implement the individual diodes as other types of diodes, such as Schottky diodes. A Schottky diode has a lower reverse recovery charge than a bipolar diode. It is even possible to implement different types of diodes in a diode circuit 10. This means that at least one of the diodes of the diode circuit 10 can be implemented as a Schottky diode, while at least one other diode is implemented as a bipolar diode. In this embodiment, the Schottky diode can be connected such that it is always activated (has no deactivation means). For example, the diode 111 in Fig. 4 be designed as a Schottky diode.

[0100] According to a further embodiment, at least one of the diodes 111-11 nThe diode circuit 10 is optimized such that a low reverse recovery charge is stored in the diode when it is forward biased. A diode with a low reverse recovery charge can be obtained, for example, by arranging one of the emitter regions of the diode, such as the emitter regions 111, 112 in Fig. 11, with a low emitter efficiency. In this embodiment, the diode with the low emitter efficiency can be connected in such a way that it is always activated (has no deactivation means). For example, the diode 111 in Fig. 4 be implemented as a diode with low emitter efficiency.

[0101] It should be noted that features explained with reference to certain figures can be combined with features of other figures, even in cases where this was not explicitly mentioned.

Claims

[1] Method for operating a circuit, wherein the circuit comprises a first circuit node (21), a second circuit node (22) and a plurality of bipolar transistors (131-13 m ) which are connected in parallel between the first circuit node (21) and the second circuit node (22), the method comprising in one switching cycle: Selecting a first group of bipolar transistors of the plurality of bipolar transistors (131-13 m ); Selecting a first subgroup of the first group of bipolar transistors such that the first group has a first subgroup and a second subgroup, and the first subgroup and the second subgroup each comprise one or more of the plurality of bipolar transistors (131-13 m ), wherein a selection of the first subgroup of bipolar transistors depends on a load state of the circuit; Switching on the first group of bipolar transistors at the beginning of a first time interval (T on ); Switching off the bipolar transistors of the first subgroup at the end of the first time interval (T on ); and Switching off the bipolar transistors of the second subgroup at a time before the end of the first time interval (T on ). [2] A method according to claim 1, wherein the load condition depends on a current (I) through the circuit. [3] Method according to one of the preceding claims, wherein the circuit is operated with a plurality of consecutive switching cycles, where the load state is determined in a switching cycle, and where the determined load condition is used to select the first subgroup for the next switching cycle. [4] The method of claim 2, wherein the second subset of bipolar transistors has an overall chip size, and wherein the second subset is selected such that the overall chip size increases as the current (I) through the circuit decreases. [5] A method according to any one of the preceding claims, further comprising: Switching off a second group of the plurality of bipolar transistors (131-13 m ) during the first time interval. [6] The method of claim 5, wherein a selection of the second subset of bipolar transistors depends on a load condition of the circuit. [7] A method according to claim 6, wherein the load state depends on a current (I) through the circuit. [8] Method according to claim 5, wherein the circuit is operated with a plurality of consecutive switching cycles, where the load state is determined in a switching cycle, and wherein the determined load condition is used to select the second subgroup for the next switching cycle. [9] The method of claim 6, wherein the second group of bipolar transistors has a total chip size, and wherein the second group is selected such that the total chip size of the second group increases as the current (I) through the circuit decreases. [10] A method according to any one of the preceding claims, wherein the bipolar transistors are IGBTs. [11] Method according to one of the preceding claims, further comprising: Applying a first voltage between the first circuit node (21) and the second circuit node (22) for a switch-on time, wherein the first voltage is designed to switch on a plurality of diodes (111-11 n) which are connected in parallel to each other between the first circuit node (21) and the second circuit node (22) in parallel to the plurality of bipolar transistors (131-13 m ) are connected in forward polarity; Applying a second voltage between the first circuit node (21) and the second circuit node (22) for a switch-off time after the switch-on time, wherein the second voltage is designed to switch the plurality of diodes (111-11 n ) in reverse polarity; and Switching a first group of diodes from an activated state to a deactivated state at a time before the end of the on-time, wherein the first group of diodes comprises one or more but less than all of the plurality of diodes (111-11 n ). [12] The method of claim 11, wherein a selection of the first group of diodes depends on a load condition of the circuit. [13] Method according to claim 12, wherein the load condition is determined by a current (I D ) depends on the circuit. [14] The method of claim 11, further comprising: Deactivating another group of the multitude of diodes (111-11 n ) during the switch-on time, with the further group one or more but less than all of the plurality of diodes (111-11 n ). [15] A method according to claim 11, wherein a selection of the further group of diodes depends on a load condition of the circuit. [16] A method according to claim 15, wherein the load condition depends on a current (I) through the circuit. [17] The method of claim 1, wherein a plurality of diodes (111-11 n ) parallel to each other between the first circuit node (21) and the second circuit node (22) parallel to the plurality of bipolar transistors (131-13 m), the method further comprising: Switching a group of diodes from an activated state to a deactivated state during time intervals in which the second subgroup of bipolar transistors is turned off, wherein the group of diodes comprises one or more but less than all of the plurality of diodes (111-11 n ). [18] A method according to claim 5, wherein a plurality of diodes (111-11 n ) parallel to each other between the first circuit node (21) and the second circuit node (22) parallel to the plurality of bipolar transistors (131-13 m ), the method further comprising: Switching a group of the multitude of diodes (111-11 n) from an activated state to a deactivated state during time intervals in which the second group of bipolar transistors is switched off, wherein the group of diodes comprises one or more but less than all of the plurality of diodes (111-11 n ). [19] Circuit with a bipolar transistor circuit comprising a first circuit node (21), a second circuit node (22) and a plurality of bipolar transistors (131-13 m ) which are connected in parallel between the first circuit node (21) and the second circuit node (22); and a control circuit (30) which is designed to: a first group of the multitude of bipolar transistors (131-13 m ), to select a first subgroup of the first group of bipolar transistors, such that the first group has a first subgroup and a second subgroup, and the first subgroup and the second subgroup each comprise one or more of the plurality of bipolar transistors (131-13 m ), wherein the first subgroup of bipolar transistors is selected depending on a load condition of the circuit, the first group at the beginning of a first time interval (T on ) to turn on, the first subgroup at the end of the first time interval (T on ) off, and the second subgroup at a time before the end of the first time interval (T on ) off. [20] A circuit according to claim 19, wherein the load condition depends on a current (I) through the circuit. [21] Circuit according to one of claims 19 or 20, wherein the bipolar transistor circuit is designed to be operated with a plurality of successive switching cycles, wherein the control circuit (30) is designed to detect the load state in a switching cycle and to use the detected load state to select the first group in a next switching cycle. [22] A circuit according to any one of claims 19 to 21, wherein the first subgroup of bipolar transistors has an overall chip size, and wherein the drive circuit (30) is configured to select the first subgroup such that the overall chip size increases as the current (I) through the circuit increases. [23] Circuit according to one of claims 19 to 22, wherein the drive circuit (30) is further configured to control a second group of the plurality of bipolar transistors (131-13 m) during the first time interval, wherein the second group comprises one or more but less than all of the plurality of bipolar transistors (131-13 m ). [24] Circuit according to claim 23, wherein the drive circuit (30) is designed to select the second group of bipolar transistors depending on a load state of the circuit. [25] A circuit according to claim 24, wherein the load condition depends on a current (I) through the circuit. [26] A circuit according to any one of claims 19 to 25, further comprising: a diode circuit (10) comprising a plurality of diodes (111-11 n ) which are arranged parallel to one another between the first circuit node (21) and the second circuit node (22) in parallel with the plurality of bipolar transistors (131-13 m), wherein the diode circuit (10) is designed to be forward-biased during a switch-on time and reverse-biased during a switch-off time; and a deactivation circuit configured to deactivate a second group of the plurality of diodes (111-11 n ) from an activated state to a deactivated state at a time before the end of the switch-on time, wherein the second group of diodes comprises one or more but less than all of the plurality of diodes (111-11 n ). [27] The circuit of claim 26, wherein the deactivation circuit comprises: at least one switch (121-12 n ) which is connected in series to at least one of the plurality of diodes (111-11 n ) is switched on; and wherein the control circuit (30) is further configured to control the at least one switch (121-12 n ) on and off. [28] A circuit according to claim 26 or 27, wherein the deactivation circuit is configured to select the second group of diodes in dependence on a load condition of the circuit. [29] A circuit according to claim 28, wherein the load condition depends on a current (I) through the circuit. [30] A circuit according to any one of claims 26 to 29, wherein the deactivation circuit is further configured to deactivate a further group of the plurality of diodes (111-11 n ), during the switch-on time, wherein the further group of diodes one or more but less than all of the plurality of diodes (111-11 n ). [31] The circuit of any one of claims 26 to 30, wherein the deactivation circuit is further configured to include a third group of the plurality of diodes (111-11 n) from an activated state to a deactivated state during time intervals in which the second subgroup of bipolar transistors is switched off, wherein the third group of diodes switches one or more, but less than all, of the plurality of diodes (111-11 n ). [32] The circuit of any one of claims 26 to 30, wherein the deactivation circuit is further configured to include a fourth group of the plurality of diodes (111-11 n ) from an activated state to a deactivated state during time intervals in which the second group of bipolar transistors is switched off, wherein the fourth group of diodes switches one or more, but less than all, of the plurality of diodes (111-11 n ).

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