Method for manufacturing an optoelectronic semiconductor chip

Abstract

Method for manufacturing an optoelectronic semiconductor chip, comprising the steps: - Fabrication of a semiconductor layer sequence (2) on a growth substrate (20), - Application of a dielectric encapsulation layer (8), - Creating an opening (17) in the encapsulation layer (8), - Applying a mirror layer (6) in the opening (17) of the encapsulation layer (8), wherein the mirror layer (6) comprises silver, - Applying an electrically conductive protective layer (7), wherein the protective layer (7) covers the mirror layer (6) including the side faces (6A) of the mirror layer (6), - Connecting the semiconductor chip (1) to a substrate (11), - Detaching the growth substrate (20), - Creating a mesa structure in the semiconductor layer sequence (2), thereby exposing an area of ​​the encapsulation layer (8) next to the semiconductor layer sequence (2), - Applying a dielectric transparent cover layer (18) which at least partially covers the area of ​​the encapsulation layer (8) next to the semiconductor layer sequence (2) and the semiconductor layer sequence (2), wherein - the creation of the opening (17) in the encapsulation layer (8) is carried out by applying a mask carrier layer (15), applying a mask layer (16) and a subsequent etching process in which the mask layer (16) is partially undercut, - the mirror layer (6) is applied in the opening (17) in the partially underetched mask layer (16) in such a way that a gap is created between the mirror layer (6) and the encapsulation layer (8), and - the electrically conductive protective layer (7) is applied through the mask layer (16).

Description

[0001] The invention relates to a method for manufacturing an optoelectronic semiconductor chip.

[0002] In particular, the present application relates to a so-called thin-film LED chip in which the original substrate of the semiconductor layer sequence has been removed and the semiconductor layer sequence is instead connected on a side opposite the original substrate to a support substrate that is not the same as the substrate. In such a thin-film LED chip, it is advantageous if the side of the semiconductor layer sequence facing the support substrate is provided with a reflective layer in order to redirect radiation emitted towards the support substrate towards the radiation emission surface and thereby increase the radiation yield.

[0003] For the visible spectral range, silver is particularly suitable as a material for the mirror layer, as it is characterized by high reflectivity, but silver is also sensitive to corrosion, especially from moisture penetrating the semiconductor chip.

[0004] Document DE 10 2011 016 302 A1 describes an optoelectronic semiconductor chip.

[0005] The publication DE 10 2010 035 966 ​​A1 relates to an optoelectronic semiconductor chip and a method for manufacturing an optoelectronic semiconductor chip.

[0006] In publication WO 2010 / 114 250 A2, a light-emitting component with several light-emitting cells is described.

[0007] Document US 2002 / 0 009 881 A1 describes a method for manufacturing a thin conductor with high precision.

[0008] The invention is based on the objective of providing an advantageous method for manufacturing an improved optoelectronic semiconductor chip that is particularly well protected against the ingress of moisture.

[0009] This problem is solved by a method according to independent claim 1. Advantageous embodiments and further developments of the invention are the subject of dependent claims.

[0010] According to at least one embodiment, the optoelectronic semiconductor chip comprises a substrate and a sequence of semiconductor layers containing a first semiconductor region of a first conductor type, a second semiconductor region of a second conductor type, and an active layer arranged between them. The first semiconductor region can, for example, face the substrate and is preferably a p-type semiconductor region. The second semiconductor region can, for example, face a radiation emission surface of the semiconductor chip and is preferably an n-type semiconductor region.

[0011] The semiconductor layer sequence of the optoelectronic semiconductor chip exhibits a mesa structure. The lateral extent of the semiconductor layer sequence is therefore smaller than the lateral extent of the substrate. The mesa structure can be fabricated by a photolithographic process in which the semiconductor layer sequence is partially ablated to shape and size as desired. For example, angled side faces can be created during the fabrication of the mesa structure.

[0012] The optoelectronic semiconductor chip is preferably a so-called thin-film semiconductor chip in which the original growth substrate has been detached from the semiconductor layer sequence and the semiconductor layer sequence is connected to the substrate on the side opposite the original growth substrate.

[0013] A reflective layer containing or consisting of silver is advantageously arranged between the substrate and the semiconductor layer sequence. Silver is particularly well-suited as a material for the reflective layer because it exhibits high reflectivity in the visible spectral range. The reflective layer can also form an electrical contact with the first semiconductor layer.

[0014] Furthermore, the optoelectronic semiconductor chip features a dielectric encapsulation layer, which serves in particular to protect the mirror layer. The dielectric encapsulation layer is partially located between the semiconductor layer sequence and the substrate. Specifically, the dielectric encapsulation layer extends from the side faces of the semiconductor chip formed by the mesa structure to beneath the semiconductor layer. The dielectric encapsulation layer is arranged laterally adjacent to the mirror layer and advantageously extends laterally into a region adjacent to the mesa structure.

[0015] Furthermore, the optoelectronic semiconductor chip advantageously features a dielectrically transparent cover layer that at least partially covers a portion of the dielectric encapsulation layer arranged next to the mesa structure and the semiconductor layer sequence. Preferably, the dielectrically transparent cover layer covers all otherwise exposed areas of the semiconductor layer sequence, in particular the side faces of the semiconductor layer sequence. Furthermore, the dielectrically transparent cover layer advantageously also covers the radiation emission surface of the semiconductor layer sequence facing away from the substrate, with the exception of areas covered by an electrical contact layer such as a bond pad.

[0016] Through the interaction of the encapsulation layer, which extends beneath the semiconductor layer sequence, and the cover layer, which covers exposed areas of the semiconductor layer sequence not adjacent to the encapsulation layer, the semiconductor chip, and in particular the mirror layer, are exceptionally well protected against environmental influences, especially against the ingress of moisture. The dielectric encapsulation layer is also advantageously suited to preventing unwanted current injection into the adjacent area of ​​the first semiconductor region. For example, a portion of the dielectric encapsulation layer, viewed vertically, faces a contact, particularly a bond pad, on the radiation-emitting surface.In this case, it is advantageous if no current is injected into the area of ​​the semiconductor layer sequence located below the contact, because the radiation generated in this area would otherwise be at least partially absorbed in the contact.

[0017] In an advantageous embodiment of the optoelectronic semiconductor chip, the reflective layer is covered by an electrically conductive protective layer. The electrically conductive protective layer covers the reflective layer, particularly on the side of the reflective layer facing away from the semiconductor layer sequence.

[0018] Preferably, the reflective layer, including its side faces, is covered by the electrically conductive protective layer. In this case, the reflective layer is also encapsulated at its side faces by the electrically conductive protective layer, thus providing particularly good protection. The electrically conductive protective layer protects the reflective layer, in particular, from the diffusion of components from adjacent layers into the reflective layer and vice versa. Specifically, the electrically conductive protective layer prevents the diffusion of silver from the reflective layer into areas arranged laterally adjacent to the reflective layer and / or into the layers following the substrate. Furthermore, the electrically conductive protective layer protects the reflective layer, in particular, from oxidation.

[0019] The electrically conductive protective layer can, in particular, contain or consist of a transparent conductive oxide. Particularly preferably, the electrically conductive protective layer contains or consists of ZnO, since ZnO is especially well suited as a protective layer for a silver layer.

[0020] In a preferred embodiment of the optoelectronic semiconductor chip, the dielectric encapsulation layer is an ALD layer, i.e., a layer produced by atomic layer deposition. This method advantageously allows for the creation of very dense layers with a low defect density. An ALD layer therefore offers particularly good protection against the ingress of moisture.

[0021] Furthermore, the dielectric cover layer is preferably also implemented, at least partially, as an ALD layer. The dielectric cover layer can, for example, have a first sublayer that is an ALD layer. At least one further sublayer can be applied to the first sublayer of the dielectric cover layer, which does not necessarily have to be produced using an ALD process.

[0022] The formation of the dielectric encapsulation layer and / or the dielectric cover layer as an ALD layer has the advantage that layers produced using ALD are particularly dense and therefore offer particularly good protection against the ingress of moisture.

[0023] The dielectric encapsulation layer preferably comprises an aluminum oxide, particularly Al₂O₃. It has been found that aluminum oxide, especially aluminum oxide applied via ALD, offers particularly good protection against moisture ingress and thus effectively protects the semiconductor chip and the mirror layer against corrosion. The dielectric encapsulation layer is preferably between 5 nm and 100 nm thick.

[0024] The dielectric transparent top layer preferably comprises an aluminum oxide, particularly Al₂O₃, and / or a silicon oxide, particularly SiO₂. For example, the dielectric transparent top layer can have a first sublayer of an aluminum oxide, advantageously produced by ALD, and a second sublayer of a silicon oxide. The silicon oxide layer can also be produced by an ALD process or by another coating process such as vapor deposition or sputtering.

[0025] In addition to or as an alternative to the silicon oxide layer, the dielectric transparent cover layer can have a silicon nitride layer, taking advantage of the fact that silicon nitride is at least partially absorbing in the visible spectral range. It is therefore possible to selectively adjust the brightness of the radiation emitted by the optoelectronic semiconductor chip by applying a silicon nitride layer of a suitable thickness.

[0026] In a preferred embodiment of the optoelectronic semiconductor chip, a contact is arranged at a radiation emission surface of the semiconductor chip, wherein a portion of the dielectric encapsulation layer is positioned opposite the contact in the vertical direction in order to reduce current injection into the region of the semiconductor layer sequence below the contact. In this way, the electrically insulating properties of the encapsulation layer reduce radiation generation below the contact and thus decrease absorption at the contact.

[0027] According to at least one embodiment of the method for manufacturing an optoelectronic semiconductor chip, the semiconductor layer sequence is grown on a growth substrate in a first step. The growth substrate can, for example, be a sapphire substrate. The semiconductor layer sequence preferably comprises a first semiconductor region of a first conductor type, a second semiconductor region of a second conductor type, and an active layer arranged between them. Preferably, the n-type semiconductor region faces the growth substrate and the p-type semiconductor region faces away from the growth substrate.

[0028] In a further process step, a dielectric encapsulation layer is applied to the semiconductor layer sequence. In particular, the dielectric encapsulation layer is applied to the first semiconductor region facing away from the growth substrate, especially a p-type semiconductor region. The dielectric encapsulation layer is preferably applied using an ALD process and is preferably about 5 nm to 100 nm thick.

[0029] According to one embodiment, the dielectric encapsulation layer is first applied over the entire surface of the semiconductor layer sequence, and in a subsequent process step, an opening is created in the dielectric encapsulation layer. This opening is created by applying a mask layer and then etching it, in which the mask layer is partially undercut. After the etching process, the mask layer has an undercut, so that the mask layer and the encapsulation layer form a T-shaped cross-sectional profile (T-topping).

[0030] According to at least one embodiment, a reflective layer is applied in a further process step, the reflective layer preferably comprising silver. The reflective layer is applied through the opening in the partially underetched mask layer in such a way that a gap is created between the reflective layer and the dielectric encapsulation layer. This can be achieved, for example, by applying the reflective layer using a directional coating process, such as thermal vapor deposition. Because the particles of the coating material are directed, particularly substantially perpendicularly, onto the mask layer during thermal vapor deposition, the reflective layer is applied essentially only in the opening of the mask layer, but not in the underetched areas of the mask layer.This creates a gap between the reflective layer and the dielectric encapsulation layer, so that the reflective layer is not directly adjacent to the dielectric encapsulation layer. The reflective layer is preferably annealed after deposition to improve electrical contact with the adjacent semiconductor area.

[0031] In a further process step, an electrically conductive protective layer is advantageously applied to the mirror layer in such a way that the electrically conductive protective layer covers the surface facing away from the semiconductor layer sequence and the side flanks of the mirror layer.

[0032] The reflective layer is thus completely covered by the electrically conductive protective layer on the side facing away from the semiconductor layer sequence. This can be achieved, for example, by applying the electrically conductive protective layer to the reflective layer using a non-directional coating process, particularly sputtering, so that during the coating process the material of the electrically conductive protective layer is also applied in the areas where the mask layer is undercut. The electrically conductive protective layer is applied through the mask layer, through which the reflective layer was previously applied.

[0033] In a subsequent process step, the semiconductor chip is connected to a substrate. This connection is made on the side facing away from the substrate, for example, by means of a bonding layer, particularly a solder layer. The substrate can be, for example, a semiconductor substrate such as a silicon substrate.

[0034] In a subsequent process step, the growth substrate is detached from the semiconductor layer sequence. This detachment of the growth substrate can be achieved, for example, using a laser lift-off process.

[0035] In a further process step, a mesa structure is created in the semiconductor layer sequence, thereby exposing the dielectric encapsulation layer in an area next to the semiconductor layer sequence.

[0036] In a further process step, the dielectric cover layer is advantageously applied, which at least partially covers the area of ​​the dielectric encapsulation layer arranged next to the semiconductor layer sequence and the semiconductor layer sequence itself. The dielectric transparent cover layer is preferably applied at least partially by an ALD process. In particular, a first sublayer of the dielectric transparent cover layer can be applied by an ALD process and a second sublayer by vapor deposition or sputtering.

[0037] Further advantageous embodiments of the method result from the description of the optoelectronic semiconductor chip and vice versa.

[0038] The invention is described below with reference to exemplary embodiments in connection with the Fig. 1 and Fig. 2 explained in more detail.

[0039] They show: Fig. 1 a schematic representation of a cross-section through an optoelectronic semiconductor chip according to an exemplary embodiment, and Fig. 2A to 2H a schematic representation of a method for manufacturing the optoelectronic semiconductor chip according to the exemplary embodiment, including intermediate steps.

[0040] Identical or similarly functioning components are marked with the same reference symbols in the figures. The depicted components and their relative sizes are not to be considered to scale.

[0041] The in Fig. 1. An optoelectronic semiconductor chip 1, schematically depicted in cross-section, contains a sequence of semiconductor layers 2, comprising a first semiconductor region 5 of a first conductor type and a second semiconductor region 3 of a second conductor type. Preferably, the first semiconductor region 5 is a p-type semiconductor region and the second semiconductor region 3 is an n-type semiconductor region. An active layer 4 is arranged between the first semiconductor region 5 and the second semiconductor region 3.

[0042] The active layer 4 of the optoelectronic semiconductor chip 1 is preferably an active layer suitable for emitting radiation. The active layer 4 can, for example, be configured as a pn junction, a double heterostructure, a single quantum well structure, or a multiple quantum well structure.

[0043] The semiconductor layer sequence 2 of the semiconductor chip 1 is preferably based on a III-V compound semiconductor material, in particular on an arsenide, nitride, or phosphide compound semiconductor material. For example, the semiconductor layer sequence 2 can be in x Al y Ga 1-x-y N, In x Al y Ga 1-x-y P or In x Al y Ga 1-x-y A S , each with 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and x + y ≤ 1. The III-V compound semiconductor material does not necessarily have to have a mathematically exact composition according to one of the formulas above. Rather, it can contain one or more dopants as well as additional components that do not substantially alter the physical properties of the material. For the sake of simplicity, however, the formulas above only include the essential components of the crystal lattice, even though these may be partially replaced by small amounts of other substances.

[0044] The optoelectronic semiconductor chip 1 has a support substrate 11, which is preferably not the same as the growth substrate of the semiconductor layer sequence 2 and is connected to the semiconductor chip 1, for example, by means of a bonding layer 10, which may in particular be a solder layer made of a metal or a metal alloy. Alternatively, the support substrate 11 may also be electroplated. Preferably, the support substrate 11 is electrically conductive and serves for electrical contacting the first semiconductor region 5. The support substrate 11 preferably comprises silicon, nickel, copper, or molybdenum.

[0045] To improve the radiation efficiency of the optoelectronic semiconductor chip 1, a mirror layer 6 is arranged between the semiconductor layer sequence 2 and the substrate 11. The mirror layer 6 is located downstream of the first semiconductor region 5 on the side facing the substrate 11 and can, in particular, be adjacent to the semiconductor layer sequence 2. It is also possible that an intermediate layer, for example a thin adhesion promoter layer (not shown), is arranged between the first semiconductor region 5 and the mirror layer 6. For example, the interconnect layer 10, in particular a solder layer made of a metal or metal alloy, and a barrier layer 9, which can be, for example, a Ti, TiW, or TiW(N) layer, are arranged between the substrate 11 and the mirror layer 6.The barrier layer 9, in particular, prevents the diffusion of components of the mirror layer 6 into the bonding layer 10 and vice versa.

[0046] The reflective layer 6 contains or consists of silver. Silver is characterized by high reflectivity in the visible spectral range and good electrical conductivity. The reflective layer 6 serves two functions: firstly, to reflect radiation emitted from the active layer 4 towards the substrate 11 to the radiation output coupling surface 12; and secondly, to electrically contact the first semiconductor region 5.

[0047] The electrical contact of the second semiconductor region 3 is effected, for example, by means of a contact 14, which may be designed, for example, as a bond pad. The surface of the semiconductor layer sequence 2, which forms the radiation emission surface 12 of the semiconductor chip 1, preferably has a roughening or an extraction structure 13 to improve the radiation extraction from the semiconductor layer sequence 2.

[0048] In the optoelectronic semiconductor chip 1, a dielectric encapsulation layer 8 is advantageously arranged laterally adjacent to the reflective layer 6. The dielectric encapsulation layer 8 is located at least partially between the semiconductor layer sequence 2 and the substrate 11. The semiconductor layer sequence 2 is designed as a mesa structure, having been structured, for example, by an etching process to achieve a desired shape and width. In particular, the lateral extent of the semiconductor layer sequence 2 is smaller than the lateral extent of the substrate 11. The dielectric encapsulation layer 8 extends laterally into a region adjacent to the semiconductor layer sequence 2. The encapsulation layer 8 has the particular advantage of protecting the corrosion-sensitive reflective layer 6 from the penetration of moisture from the lateral direction.The dielectric encapsulation layer 8 is preferably an ALD layer, since a layer produced by atomic layer deposition is characterized by a high density and thus particularly good protection against the ingress of moisture.

[0049] Preferably, the dielectric encapsulation layer 8 is an Al2O3 layer. The thickness of the dielectric encapsulation layer is preferably between 5 nm and 100 nm, for example about 40 nm.

[0050] Particularly good corrosion protection in the semiconductor chip 1 is achieved by covering at least part of a dielectric transparent cover layer 18 of an area of ​​the dielectric encapsulation layer 8 located next to the mesa structure and the semiconductor layer sequence 2. The transparent dielectric cover layer 18 covers, in particular, the side faces 21 of the semiconductor layer sequence 2. In this way, the cover layer 18 protects the semiconductor chip 1, especially from the ingress of moisture in the area where the side faces 21 of the semiconductor layer sequence 2 abut the dielectric encapsulation layer 8. Otherwise, there could be a risk of moisture diffusing at the interface between the semiconductor layer sequence 2 and the dielectric encapsulation layer 8 towards the mirror layer 6.

[0051] The dielectric cover layer 18 preferably covers all areas of the semiconductor layer sequence 2 that do not border another layer. In particular, the dielectric cover layer 18 covers the side faces 21 of the semiconductor layer sequence and the radiation emission surface 12. Since part of the dielectric cover layer 18 is applied to the radiation emission surface, the dielectric cover layer is advantageously transparent to the radiation emitted by the active layer 2. A recess for the contact 14 for the electrical connection of the second semiconductor region 3 can be provided in the cover layer 18 on the top side of the semiconductor layer sequence 2.

[0052] The dielectric cover layer 18 can be formed from a single layer or from two or more sublayers (not shown). Preferably, at least one sublayer of the dielectric cover layer 18 is an ALD layer. In the case of a dielectric cover layer 18 formed from several sublayers, preferably a first sublayer, which is directly adjacent to the semiconductor layer sequence 2 and the dielectric encapsulation layer 8, is an ALD layer, in particular an Al₂O₃ layer. The dielectric cover layer 18, or at least a first sublayer thereof, can therefore be formed from the same material as the dielectric encapsulation layer 8. The thickness of the first sublayer of the dielectric cover layer 18 is, for example, between 5 and 100 nm, preferably about 40 nm.The dielectric cover layer 18 can have a second sublayer that provides additional protection against moisture ingress and also mechanical protection. The second sublayer can be thicker than the first sublayer and, in particular, be a silicon oxide layer, for example, a SiO2 layer. The second sublayer can, in particular, be between 50 nm and 1000 nm thick.

[0053] Further improved protection of the mirror layer 6 is achieved by covering the mirror layer 6 on a side facing the substrate 11 with an electrically conductive protective layer 7. The electrically conductive protective layer 7 is preferably a ZnO layer. Advantageously, the electrically conductive protective layer 7 completely covers the mirror layer 6, including the side faces 6a of the mirror layer 6. The electrically conductive protective layer 7 has the particular advantage of preventing the diffusion of silver from the mirror layer 6 towards the side faces 21 of the semiconductor layer sequence 2.

[0054] On the side of the dielectric encapsulation layer 8 and the electrically conductive protective layer 7 facing the support substrate 11, a barrier layer 9 is advantageously arranged, which in particular reduces the diffusion of components of the bonding layer 10, for example a gold-containing solder layer, into the mirror layer 6. The barrier layer 9 preferably contains a metallic compound, which may in particular contain Ti, TiW or TiW(N). The barrier layer 9 is, for example, between 300 nm and 500 nm thick, in particular 450 nm.

[0055] The bonding layer 10 is, for example, a solder layer that may contain, in particular, gold. Bonding layer 10 is, for example, designed as a multilayer structure that, in addition to the solder material such as gold, contains one or more further sublayers that function, in particular, to improve adhesion, improve wettability, or act as diffusion barriers. For this purpose, one or more sublayers may be provided that contain, for example, titanium, platinum, gold, nickel, and / or tin.

[0056] An embodiment of a method for manufacturing the semiconductor chip 1 of the Fig. 1 will be explained below using the Fig. Sections 2A to 2H are explained.

[0057] At the in Fig. In the intermediate step of the process shown in Figure 2A, the semiconductor layer sequence 2, comprising the first semiconductor region 5, the active layer 4, and the second semiconductor region 3, is grown onto a growth substrate 20. The growth is preferably epitaxial, in particular using MOVPE. The semiconductor layer sequence 2 can, for example, contain nitride compound semiconductor materials, and the growth substrate 20 can be a sapphire substrate. The first semiconductor region 5 is preferably a p-type semiconductor region, and the second semiconductor region 3 is preferably an n-type semiconductor region.

[0058] Furthermore, a dielectric encapsulation layer 8 is deposited onto the p-type semiconductor region 5 by atomic layer deposition (ALD). The dielectric encapsulation layer 8 advantageously has a thickness of approximately 5 nm to 100 nm, for example, 40 nm. A mask carrier layer 15 and a mask layer 16 are deposited onto the dielectric encapsulation layer 8, the mask layer 16 having an opening for depositing the mirror layer in a further process step. The mask carrier layer 15 serves to create a gap between the mask layer 16 and the dielectric encapsulation layer 8. The mask carrier layer 15 can, for example, be a SiO2 layer and be approximately 50 nm to 1000 nm thick.

[0059] At the in Fig. In the intermediate step shown in Figure 2B, an opening 17 is created in the dielectric encapsulation layer 8 and the mask carrier layer 15 using the mask layer 16 as an etching mask. An etching process can be used for this purpose, for example, a plasma etching process and / or an etching process using phosphoric acid (H3PO4). During the etching process, the mask layer 16 is advantageously partially undercut, resulting in a T-shaped cross-sectional profile (T-topping). In other words, the mask layer 16 has an undercut. The opening created in the dielectric encapsulation layer 8 during the etching process is therefore slightly larger than the opening in the mask layer 16.

[0060] At the in Fig. In the intermediate step shown in Figure 2C, the reflective layer 6 is deposited through the opening in the mask layer 16 onto the p-type semiconductor region 5. The reflective layer 6 is preferably applied using a directional coating process in which the material of the reflective layer 6 impacts the mask layer 16 at a near-perpendicular angle. This is approximately the case, for example, when the reflective layer 6 is applied by thermal vapor deposition at a large distance from the vaporization source. By applying the reflective layer 6 using a directional coating process, the reflective layer 6 is deposited essentially only in the opening of the mask layer 16, but not under the etched areas of the mask layer 16. The side faces 6a of the reflective layer are therefore spaced apart from the dielectric encapsulation layer 8. Thus, a gap is created between the reflective layer 6 and the dielectric encapsulation layer 8.The reflective layer 6 is preferably a silver layer. After application, the silver layer can undergo a heat treatment, particularly at a temperature above 200 °C, to improve the electrical contact between the reflective layer 6 and the p-type semiconductor region 3.

[0061] In the Fig. In the intermediate step shown schematically in 2D, an electrically conductive protective layer 7 is deposited through the opening in the mask layer 16 onto the mirror layer 6. In contrast to the mirror layer 6, an omnidirectional coating process is used to apply the electrically conductive protective layer 7, in which the material of the electrically conductive protective layer 7 impacts the mask layer 16 at least partially at oblique angles of incidence. This ensures that the electrically conductive protective layer 7 is also applied to the undercut areas of the mask layer 16 and thus extends to the dielectric encapsulation layer 8. In particular, the electrically conductive protective layer 7 also covers the side faces 6A of the mirror layer 6. In the finished component, this has the advantage that diffusion of silver from the mirror layer 6 towards the dielectric encapsulation layer 8 is effectively prevented.The electrically conductive protective layer 7 can, in particular, be a ZnO layer. After the application of the electrically conductive protective layer 7, the mask carrier layer 15 and the mask layer 16 are removed. Buffered hydrofluoric acid (BOE, Buffered Oxide Etch) can be used for this purpose, for example.

[0062] At the in Fig. In the intermediate step shown in Figure 2E, a barrier layer 9 has been applied to the sides of the dielectric encapsulation layer 8 and the electrically conductive protective layer 7 facing away from the semiconductor layer sequence 2. The barrier layer 9 contains, for example, Ti, TiW or TiW(N) and has the function of preventing diffusion of the material from subsequent metallization layers into the mirror layer and vice versa.

[0063] On the side of barrier layer 9 facing away from the semiconductor layer sequence 2, the semiconductor chip is connected to a substrate 11 by means of a bonding layer 10. The bonding layer 10 can, in particular, comprise a solder layer, for example, gold. The bonding layer 10 can be a multilayer system that may contain further layers on the side of barrier layer 8 and / or on the side of the substrate 11, which, for example, improve the adhesion of the solder layer or the use of the solder layer on the components to be joined. The multilayer system may, for example, comprise layers of Ti, Pt, Au, Ni, or Sn. The substrate 11 can, in particular, be electrically conductive and preferably comprises silicon, nickel, copper, or molybdenum.

[0064] At the in Fig. In the intermediate step shown in Figure 2F, the growth substrate 20 has been detached from the semiconductor layer sequence 2. The optoelectronic semiconductor chip 1 is shown rotated by 180° compared to the previous figures, since the support substrate 11, which is opposite the original growth substrate 20, now serves as the sole support for the semiconductor chip 1. The growth substrate 20, in particular a sapphire substrate, can be detached from the semiconductor layer sequence 2, for example, by means of a laser lift-off process.

[0065] Furthermore, in the intermediate step of the Fig. 2F The now exposed surface of the n-type semiconductor region 3 has been provided with an output coupling structure 13. The output coupling structure 13 can be fabricated, in particular, by means of an etching process. The output coupling structure 13 improves the radiation extraction of the radiation emitted by the active layer 4, since the surface of the n-type semiconductor region 5 serves as a radiation emission surface 12 in the finished semiconductor chip.

[0066] At the in Fig. In the intermediate step shown in Figure 2G, the semiconductor layer sequence 2 was structured into a mesa structure. In this process, edge regions of the semiconductor layer sequence 2 were ablated down to the dielectric encapsulation layer 8 to produce a semiconductor layer sequence 2 with a desired shape and size. The semiconductor layer sequence 2, formed as a mesa structure, has a smaller lateral extent than the support substrate 11. It is possible that inclined side faces 21 were generated in the semiconductor layer sequence during this step. The structuring of the semiconductor layer sequence 2 is preferably carried out photolithographically, whereby, for example, a plasma etching process can be used for etching.

[0067] At the in Fig. In the further intermediate step shown in Figure 2H, the dielectric cover layer 18 is applied to the exposed areas of the dielectric encapsulation layer 8 adjacent to the semiconductor layer sequence 2, as well as to all exposed areas of the semiconductor layer sequence 2. The dielectric cover layer 18 covers, in particular, the side faces 21 and the radiation emission surface 12 of the semiconductor layer sequence 2. The dielectric cover layer 18 can be a single layer or a multilayer. For example, the dielectric cover layer 18 can have an Al2O3 layer produced by ALD as the first sublayer and a SiO2 layer as the second sublayer. For the sake of simplicity, the two sublayers are shown in Fig. 2H is not shown separately. Alternatively or additionally to the SiO2 layer, the dielectric cover layer can have a silicon nitride layer. The silicon nitride layer can, for example, be used to selectively adjust the brightness of the radiation emitted by the optoelectronic semiconductor chip.

[0068] To complete the in Fig.In a further intermediate step, an opening for a contact 14 can be created in the dielectric cover layer 18 of the optoelectronic semiconductor chip 1 shown in Figure 1, and a bond pad, for example, can be applied therein. The contact 14 is preferably arranged on a radiation emission surface 12 of the semiconductor chip such that a portion of the dielectric encapsulation layer 8 faces the contact 14 in the vertical direction, in order to reduce current injection into the region of the semiconductor layer sequence 2 below the contact 14. In this way, the electrically insulating properties of the encapsulation layer 8 reduce radiation generation below the contact 14 and thus also reduce absorption in the contact 14.

[0069] Furthermore, when manufacturing multiple optoelectronic semiconductor chips 1 in a wafer array, a separation trench can be created in the dielectric top layer 18 between the mesa structures to facilitate the separation of the wafer array into individual semiconductor chips. This can be seen in the finished semiconductor chip 1 by the fact that the dielectric top layer 18 is removed in an edge region 19 on the outside of the semiconductor chip 1.

Claims

[1] Method for manufacturing an optoelectronic semiconductor chip, comprising the steps: - Fabrication of a semiconductor layer sequence (2) on a growth substrate (20), - Application of a dielectric encapsulation layer (8), - Creating an opening (17) in the encapsulation layer (8), - Applying a mirror layer (6) in the opening (17) of the encapsulation layer (8), wherein the mirror layer (6) comprises silver, - Applying an electrically conductive protective layer (7), wherein the protective layer (7) covers the mirror layer (6) including the side faces (6A) of the mirror layer (6), - Connecting the semiconductor chip (1) to a substrate (11), - Detaching the growth substrate (20), - Creating a mesa structure in the semiconductor layer sequence (2), thereby exposing an area of ​​the encapsulation layer (8) next to the semiconductor layer sequence (2), - Applying a dielectric transparent cover layer (18) which at least partially covers the area of ​​the encapsulation layer (8) next to the semiconductor layer sequence (2) and the semiconductor layer sequence (2), wherein - the creation of the opening (17) in the encapsulation layer (8) is carried out by applying a mask carrier layer (15), applying a mask layer (16) and a subsequent etching process in which the mask layer (16) is partially undercut, - the mirror layer (6) is applied in the opening (17) in the partially underetched mask layer (16) in such a way that a gap is created between the mirror layer (6) and the encapsulation layer (8), and - the electrically conductive protective layer (7) is applied through the mask layer (16). [2] Method according to claim 1, wherein after the application of the mirror layer (6) the electrically conductive protective layer (7) is applied to the mirror layer (6), the gap being closed when the protective layer (7) is applied. [3] Method according to any of the preceding claims, wherein the encapsulation layer (8) is applied by an ALD method. [4] Method according to any of the preceding claims, wherein the encapsulation layer (8) comprises Al2O3. [5] Method according to any of the preceding claims, wherein the top layer (18) is applied at least partially by an ALD method. [6] Method according to any of the preceding claims, wherein the cover layer (18) comprises Al2O3 and / or SiO2.

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