METHOD FOR PRODUCING A MOSFET WITH AN UNDOTATED CHANNEL

Abstract

Method for fabricating a MOSFET (302, 304) with an undoped silicon channel (342, 344), the method comprising: Fabricating a semiconductor structure with a dummy poly-gate (316, 326), a dummy interlayer oxide (318, 328), hereinafter referred to as dummy IL oxide, and a doped channel (314, 324) over a doped well (312, 322) in a substrate, wherein the doped channel (314, 324) and the doped well (312, 322) are formed from silicon; Removal of the dummy poly gate (316, 326) and dummy IL oxide (318, 328) to expose the doped channel (314, 324); Removal of the doped channel (314, 324) from an area on the substrate; Formation of an undoped silicon channel (342, 344) for the semiconductor structure in the area on the substrate; and Forming a metal gate for the semiconductor structure, wherein the removal of the dummy IL oxide (318, 328) includes dry etching operations to partially remove the dummy IL oxide (318, 328) prior to removing the doped channel (314, 324) in order to expose the doped channel (314, 324), and wherein the removal of the dummy IL oxide (318, 328) further includes performing etching operations after the removal of the doped channel (314, 324) in order to remove the remaining dummy IL oxide (318, 328).

Description

BACKGROUND

[0001] The technology described in this patent document relates to a metal oxide semiconductor field-effect transistor (MOSFET), and in particular to channel engineering for HKMG-CMOS devices.

[0002] The scaling of semiconductor devices, such as MOSFETs, has enabled the continued improvement of speed, performance, density, and cost per functional unit in integrated circuits over the past decades. Improvements to the transistor channel fabrication process can further optimize the scaling of integrated circuits.

[0003] A MOSFET can be fabricated on a bulk semiconductor substrate (planar devices) or on a silicon-on-insulator (SOI)-type structure. In a gate replacement process, a dummy gate structure, for example made of polysilicon (Poly), can be formed. After source-drain (S / D) processing has been initiated or continued, the dummy gate structure is removed and replaced by an electrically conductive, metal-containing gate stack located over a channel region between the S / D in the bulk semiconductor substrate or in the silicon layer of the SOI structure. Methods for manufacturing a MOSFET are known, for example, from US 2006 / 0166417A1, US 2014 / 0027854A1, US 2011 / 0042758A1, US 2006 / 0046399A1, US 2013 / 0149821A1, US 2014 / 0001540A1, US 2013 / 0270628A1, US 2009 / 0302412A1, US 2013 / 0285138A1, and CN 103715092A BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood with reference to the following detailed description, when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale. The dimensions of illustrated structural elements may be enlarged or reduced as necessary for the clarity of the discussion. Fig. Figure 1A is a diagram of an exemplary transistor illustrating that functional doping techniques can leave the channel region of a transistor with uneven concentrations of impurity atoms. Fig. Figure 1B is a diagram of an exemplary transistor in which impurity atoms have been removed from at least one section of the channel region of the transistor as a result of functional doping techniques, according to some embodiments. Fig. Figure 2 is a process flow diagram showing an exemplary method for manufacturing a semiconductor device with an undoped channel according to some embodiments. Fig. Figure 3 shows a cross-sectional view of an exemplary semiconductor structure after partial fabrication according to some embodiments. Fig. Figure 4 shows a cross-sectional view of an exemplary semiconductor structure after removal of the dummy poly-gate according to some embodiments. Fig. Figure 5 shows a cross-sectional view of an exemplary semiconductor structure after removal of the dummy IL oxide according to some embodiments. Fig. Figure 6 shows a cross-sectional view of an exemplary semiconductor structure after removal of the channel from certain areas on the substrate according to some embodiments. Fig. Figure 7 shows a cross-sectional view of an exemplary semiconductor structure after removal of the dummy IL oxide from additional dummy IL oxide according to some embodiments. Fig. Figure 8 shows a cross-sectional view of an exemplary semiconductor structure after the formation of new undoped channels according to some embodiments. Fig. Figure 9 shows a cross-sectional view of an exemplary semiconductor structure after the re-growth of IL oxide according to some embodiments. DETAILED DESCRIPTION

[0005] The present invention provides a method for fabricating a MOSFET with an undoped silicon channel having the features of claim 1, and a method for replacing a doped channel over a doped well in a substrate in a semiconductor structure with an undoped silicon channel having the features of claim 6. Exemplary embodiments are given in the dependent claims.

[0006] The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples. For instance, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not automatically create a relationship between the various designs and / or configurations discussed.

[0007] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or structural element to one or more other elements or structural elements, as illustrated in the figures. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also other orientations of the device during use or operation. The device may also be oriented differently (rotated 90 degrees or otherwise), and the spatially relative descriptors used in this text may be interpreted accordingly.

[0008] Well doping, light drain doping (LDD), and pocket doping are functional doping techniques that can be used during semiconductor manufacturing. In some cases, such as with short-channel devices, these functional doping techniques can complicate carrier delivery and reduce the global or local uniformity of the threshold voltage (Vt) due to random dopant fluctuation (RDF). Fig. Figure 1A is a diagram of an exemplary transistor illustrating that functional doping techniques can leave the channel region of a transistor with non-uniform concentrations of impurity atoms 10, which can complicate carrier delivery and decrease the global or local uniformity of the Vt.

[0009] In Fig. Figure 1B shows a diagram of a transistor in which impurity atoms 10 have been removed from at least one section of the channel region 12 of the transistor as a result of functional doping techniques. A transistor in which impurity atoms have been removed from channel region 12 (i.e., a transistor with a clean channel) may be able to achieve better Vt uniformity and higher performance. The following examples illustrate exemplary techniques for fabricating a semiconductor device with a clean channel even when functional doping is applied.

[0010] Fig. Figure 2 is a process flow diagram illustrating an exemplary procedure for fabricating a semiconductor device with an undoped channel. The procedure begins after a semiconductor structure with a dummy polygate, a dummy interlayer (IL) oxide, and a doped channel has been fabricated on a substrate (Operation 102). Following this initial fabrication, the dummy polygate is removed (Operation 104) to expose the doped channel to be removed. Removing the dummy polygate in this example involves dry and wet etching operations (Operation 204). After removing the dummy polygate, dummy IL oxide ablation operations can begin (Operation 106). In this example, removing the dummy IL oxide involves dry etching operations (Operation 206). Next, the channel is removed from a region on the substrate (Operation 108).In this example, the channel removal operations can involve anisotropic etching of the Si substrate at a slow etch rate to prevent damage to the source-drain regions (Operation 208). Additional dummy IL oxide can be removed (Operation 110). Further dummy oxide removal can be achieved by a second dummy IL etching operation (Operation 210). A new undoped channel is formed in the area on the wafer previously occupied by the doped channel, which was then removed (Operation 112). The formation of a new channel in this example is achieved through an epitaxial growth process (Operation 212). After growing a new channel, IL oxide can be grown again over the new channel region (Operation 114). The regeneration of IL oxide in this example is accomplished by applying wet chemicals to the new undoped Si channel (Operation 214).After regrowing an IL, a metallic gate can be formed (Operation 116). In this example, the formation of a metallic gate involves Hi-K deposition and metal-gate deposition operations (Operation 216).

[0011] The Fig. Figures 3-9 show cross-sectional views of an exemplary semiconductor structure during different stages of manufacturing. Fig. Figure 3 shows a cross-sectional view of the exemplary semiconductor structure after partial fabrication. The exemplary semiconductor structure contains an n-channel MOSFET (NFET) 302 and a p-channel MOSFET (PFET) 304, separated from each other by a shallow trench insulation (STI) 306. The NFET 302 and the PFET 304 are each formed over a doped well in a substrate. The NFET 302 contains source and drain regions 310 formed above a doped well 312 in a substrate, a channel region 314 in the doped well 312, a dummy poly-gate 316, and a dummy IL oxide 318. The PFET 304 contains source and drain regions 320 formed above a doped well 322 in the substrate, a channel region 324 in the doped well 322, a dummy poly-gate 326, and a dummy IL oxide 328.The exemplary semiconductor structure further includes an interlayer dielectric (ILD0) 330 and a contact etch stop layer (CESL) 332, which are common to both the NFET 302 and the PFET 304. The channel regions 314, 324 and the doped wells 312, 322 in this example are formed from silicon (Si). The source and drain regions 310 of the NFET 302 are formed from silicon phosphorus (SiP) in this example. The source and drain regions 320 of the PFET 304 are formed from silicon germanium (SiGe) in this example.

[0012] Fig. Figure 4 shows a cross-sectional view of the exemplary semiconductor structure after removal of the dummy polygate. Vacancies 334 and 336 are shown, where the dummy polygates were previously present in NFET 302 and PFET 304, respectively. Removing the dummy polygate in this example involves both dry and wet etching operations.

[0013] Fig. Figure 5 shows a cross-sectional view of the exemplary semiconductor structure after removal of the dummy IL oxide. A reduced amount of dummy IL oxide 318, 328 is shown. In this example, the dummy IL oxide 318, 328 was removed by dry etching.

[0014] Fig. Figure 6 shows a cross-sectional view of the exemplary semiconductor structure after removal of the channel from specific regions 338 and 340 on the substrate. Channel removal in this example is performed by anisotropic etching of the Si substrate using a slow etch rate to prevent damage to the source-drain regions.

[0015] Fig. Figure 7 shows a cross-sectional view of the exemplary semiconductor structure after removal of residual dummy IL oxide. In this example, the dummy IL oxide was removed by dry etching.

[0016] Fig. Figure 8 shows a cross-sectional view of the exemplary semiconductor structure after the formation of new undoped channels 342 and 344 in the specific regions 338 and 340. In this example, the new channels 342 and 344 are formed by epitaxial growth processes. This results in two undoped channel regions 342 and 344 in doped trough regions 312 and 322 in the substrate. The undoped channel regions 342 and 344 are coupled between the source and drain regions 310 and 320, respectively, of their corresponding transistors.

[0017] Fig.Figure 9 shows a cross-sectional view of the exemplary semiconductor structure after re-growth of IL oxide 346, 348 over the new channel regions 342, 344. In this example, the IL oxide 346, 348 is grown by applying wet chemicals to the new undoped Si channel regions 342, 344. After re-growth of IL oxide 346, 348, fabrication of the semiconductor structure can continue, including the formation of a gate stack over the undoped Si channel regions 342, 344 and other semiconductor fabrication operations.

[0018] The examples mentioned above provide techniques for obtaining a lightly doped channel and higher Vt uniformity through re-growth of silicon (or another channel material). These examples illustrate techniques that can be implemented to meet the high Vt uniformity requirements for IC devices below the 28 nm threshold. The novel buried channel fabrication technique disclosed in this text can be fully integrated into metal-gate replacement technology.

[0019] In one embodiment, a method for fabricating a MOSFET with an undoped channel is disclosed. The method comprises fabricating a semiconductor structure on a substrate, consisting of a dummy polygate, a dummy interlayer (IL) oxide, and a doped channel. The method further comprises removing the dummy polygate and the dummy IL oxide to expose the doped channel, removing the doped channel from a region on the substrate, forming an undoped channel for the semiconductor structure in that region on the substrate, and forming a metal gate for the semiconductor structure.

[0020] These aspects and further embodiments may include one or more of the following features. Dummy polygate removal may include dry and wet etching operations to remove the dummy polygate. Dummy IL oxide removal may include dry etching operations to remove the dummy IL oxide. Doped channel removal may include anisotropic etching operations on the substrate. Undoped channel formation may include the application of an epitaxial process to grow the undoped channel. The process may further include growing IL oxide over the undoped channel by applying wet chemicals to the undoped channel. Dummy IL oxide removal may include performing etching operations both before and after the removal of the doped channel.

[0021] In a further embodiment, a method for replacing a doped channel on a substrate in a semiconductor structure with an undoped channel is disclosed. The method comprises removing a dummy polygate and a dummy interlayer (IL) oxide to expose the doped channel, removing the doped channel from a region on the substrate, and growing an undoped channel for the semiconductor structure in that region on the substrate.

[0022] These aspects and further embodiments may include one or more of the following features. Dummy polygate removal may include dry and wet etching operations to remove the dummy polygate. Dummy IL oxide removal may include dry etching operations to remove the dummy IL oxide. Doped channel removal may include anisotropic etching operations on the substrate. Growing an undoped channel may include applying an epitaxial process to grow the undoped channel. The method may further include growing IL oxide over the undoped channel by applying wet chemicals to the undoped channel. Dummy IL oxide removal may include performing etching operations both before and after removing the doped channel.

Claims

[1] Method for fabricating a MOSFET (302, 304) with an undoped silicon channel (342, 344), the method comprising: Fabricating a semiconductor structure with a dummy poly-gate (316, 326), a dummy interlayer oxide (318, 328), hereinafter referred to as dummy IL oxide, and a doped channel (314, 324) over a doped well (312, 322) in a substrate, wherein the doped channel (314, 324) and the doped well (312, 322) are formed from silicon; Removal of the dummy poly gate (316, 326) and dummy IL oxide (318, 328) to expose the doped channel (314, 324); Removal of the doped channel (314, 324) from an area on the substrate; Formation of an undoped silicon channel (342, 344) for the semiconductor structure in the area on the substrate; and Forming a metal gate for the semiconductor structure, wherein the removal of the dummy IL oxide (318, 328) includes dry etching operations to partially remove the dummy IL oxide (318, 328) prior to removing the doped channel (314, 324) in order to expose the doped channel (314, 324), and wherein the removal of the dummy IL oxide (318, 328) further includes performing etching operations after the removal of the doped channel (314, 324) in order to remove the remaining dummy IL oxide (318, 328). [2] Method according to claim 1, wherein the removal of the dummy poly gate (316, 326) comprises dry and wet etching operations to remove the dummy poly gate (316, 326). [3] Method according to claim 1 or 2, wherein the removal of the doped channel (314, 324) comprises anisotropic etching operations on the substrate. [4] Method according to any of the preceding claims, wherein forming an undoped silicon channel (342, 344) comprises applying an epitaxial process to grow the undoped silicon channel (342, 344). [5] Method according to any of the preceding claims, further comprising growing IL oxide (346, 348) over the undoped silicon channel (342, 344) by applying wet chemicals to the undoped silicon channel (342, 344). [6] Method for replacing a doped channel (314, 324) over a doped well (312, 322) in a substrate in a semiconductor structure with an undoped silicon channel (342, 344), wherein the doped channel (314, 324) and the doped well (312, 322) are formed of silicon and the method comprises: Removal of a dummy poly gate (316, 326) and a dummy interlayer oxide (318, 328), hereinafter referred to as dummy IL oxide, to expose the doped channel (314, 324); Removal of the doped channel (314, 324) from an area on the substrate; and Growing an undoped silicon channel (342, 344) for the semiconductor structure in the area on the substrate, wherein the removal of the dummy IL oxide (318, 328) includes dry etching operations to partially remove the dummy IL oxide (318, 328) prior to removing the doped channel (314, 324) in order to expose the doped channel (314, 324), and wherein the removal of the dummy IL oxide (318, 328) further includes performing etching operations after the removal of the doped channel (314, 324) to remove the remaining dummy IL oxide (318, 328). [7] Method according to claim 6, wherein the removal of the dummy poly gate (316, 326) comprises dry and wet etching operations to remove the dummy poly gate (316, 326). [8] Method according to claim 6 or 7, wherein the removal of the doped channel (314, 324) comprises anisotropic etching operations on the substrate. [9] Method according to any one of claims 6 to 8, wherein the growth of an undoped silicon channel (342, 344) comprises applying an epitaxial process to grow the undoped silicon channel (342, 344). [10] Method according to any one of claims 6 to 9, further comprising growing IL oxide (346, 348) over the undoped silicon channel (342, 344) by applying wet chemicals to the undoped silicon channel (342, 344).

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