CHARGE COMPENSATION STRUCTURE

Abstract

Charge compensation semiconductor component, comprising: - a nominal breakdown voltage; - a semiconductor body (40) comprising a first surface (101), a border (41) limiting the semiconductor body (40) in a horizontal direction which is substantially parallel to the first surface (101), an active region (110) and a border region (120) arranged between the active region (110) and the border (41); - a source metallization (10) arranged on the first surface (101); and - a drain metallization (11) arranged opposite the source metallization (10), wherein the semiconductor body (40) further comprises in a vertical cross-section that is substantially orthogonal to the first surface (101) of the semiconductor body (40): - an intrinsic semiconductor region (2) located in the boundary region (120); - a potential equalization area (8, 11a) that is in ohmic contact with the drain metallization (11) and is located next to the edge (41) and the first surface (101): and - a plurality of first column regions (1) alternating with second column regions (6) in the active region (110) and in the edge region (120), wherein the first column regions (1) have a higher doping concentration than the intrinsic semiconductor region (2), wherein the first column regions (1) are in ohmic contact with the drain metallization (11), wherein the second column regions (6) of the active region (110) are in ohmic contact with the source metallization (10) via corresponding body regions (5, 5') with a higher doping concentration than the second column regions (6), wherein at least a plurality of the second column regions (6) of the edge region (120) are adjacent to a connection region (17) of the same conductivity type as the second column regions (6) and with a lower doping concentration than an adjacent outer of the body regions (5, 5'),wherein a corresponding pn junction is formed between each adjacent first column region (1) and second column region (6), and wherein an outer of the first column region (1) and / or an outer of the second column region (6) forms an interface (46) to the intrinsic semiconductor region (2) at a horizontal position (x0), where a voltage on the first surface (101) is at least approximately one-fifth of the nominal breakdown voltage when the nominal breakdown voltage is applied between the source metallization (10) and the drain metallization (11), wherein a horizontal distance between the interface (46) and the equipotential bonding region (8) divided by a horizontal distance between the source metallization (10) and the interface (46) is in a range of approximately 0.2 to approximately 5, and wherein the equipotential bonding region (8) is a field plate (11a) arranged on the first surface (101) and / or a field stop region (8),which borders the intrinsic semiconductor region (2) and has a higher average concentration of dopants of the first conductivity type than the intrinsic semiconductor region (2).

Description

TECHNICAL AREA

[0001] Embodiments of the present invention relate to field-effect semiconductor devices with a charge compensation structure and manufacturing methods for such a structure, in particular to power semiconductors with a charge compensation structure in an active region. BACKGROUND

[0002] Semiconductor transistors, especially field-effect controlled semiconductor switches such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs), are widely used, including as switches in power supplies and power converters, electric cars, air conditioners, and even stereo systems, but these applications are not limited to these. Particularly with regard to power semiconductors designed for switching large currents and / or operating at high voltages, a low on-resistance (Rn) and a high breakdown voltage (Ur) are frequently required. bd , a high degree of robustness and / or good softness is required.

[0003] To achieve low on-resistance Ron and high breakdown voltages U bdTo achieve this, compensation semiconductor devices were developed, as described, for example, in US publications 7,737,469 B2 and US 8,716,792 B2. The compensation principle is based on the mutual compensation of the charges of n- and p-doped regions, often also referred to as n- and p-doped column regions, in the drift zone of a vertical MOSFET.

[0004] Typically, the charge compensation structure formed by p- and n-regions is provided under the actual MOSFET structure, with its source, body and gate regions, and also under the associated MOS channels, which are arranged side by side in the semiconductor volume of the semiconductor device or are nested together in such a way that their charges can be mutually depleted in the off state, and that in the activated or on state an uninterrupted conduction path of low impedance is created from a source electrode near the surface to a drain electrode on the back.

[0005] Due to the compensation of the p- and n-type doping, the doping of the current-carrying region in the compensation components can be significantly increased, thereby substantially reducing the on-resistance (Ron) despite the loss of a current-carrying region. The reduction in the on-resistance (Ron) of such power semiconductors is associated with a reduction in the heat generated by the current in the on-state, so that such charge-compensated power semiconductors remain "cool" compared to conventional power semiconductors.

[0006] Switching losses in power semiconductor devices have become increasingly important. Depending on the device's operating conditions, the initial charge Q is the primary factor determining these losses. OSS (or the initial capacity C) OSS ) and switching losses E OSSThe switching losses are generated in the space charge region in the off state or during the application of a reverse bias voltage. The stored charge Q OSS The switching losses of semiconductor devices with charge compensation structures can be comparatively high. This can lead to significant switching losses E. OSS lead to this if significant portions of the stored charge Q OSS At high voltages, the current must be dissipated via the load terminals of the power semiconductor. Furthermore, the output charge Q must be... OSS They must be removed to allow locking. This leads to switching delays and / or increased losses.

[0007] To achieve high breakdown voltages U bdAn edge termination structure can be used in a border region surrounding the active area with active MOSFET cells. However, the border region occupies chip area and therefore increases the cost. Furthermore, both the edge termination structure and the border region can each substantially affect the output charge Q. OSS and to the initial capacity C OSS contribute. The switching losses can even be dominated by the edge area.

[0008] Accordingly, there is a need to improve semiconductor components with charge compensation structures and to manufacture such semiconductor components. SUMMARY

[0009] According to one embodiment of a charge-compensating semiconductor device, the device has a nominal breakdown voltage and a semiconductor body comprising a first surface, a boundary that limits the semiconductor body in a horizontal direction substantially parallel to the first surface, an active region, and a boundary region arranged between the active region and the boundary. A source metallization is provided on the first surface. Opposite the source metallization, a drain metallization is arranged. In a vertical cross-section substantially orthogonal to the first surface, the semiconductor body further comprises an intrinsic semiconductor region arranged in the boundary region and a plurality of first column regions alternating with second column regions in the active region and in the boundary region.The first column regions have a higher doping concentration than the intrinsic semiconductor region and are in ohmic contact with the drain metallization. The second column regions of the active region are in ohmic contact with the source metallization via corresponding body regions with a higher doping concentration than the second column regions. At least a majority of the second column regions of the boundary region border a junction region of the same conductivity type as the second column regions and have a lower doping concentration than an adjacent outermost body region. A corresponding pn junction is formed between adjacent first column regions and second column regions.At least one of the outermost regions of the first column and one of the outermost regions of the second column forms an interface with an intrinsic semiconductor region at a horizontal position where the voltage on the first surface is at least about one fifth of the nominal breakdown voltage when the nominal breakdown voltage is applied between the source metallization and the drain metallization.

[0010] According to one embodiment of a charge compensation semiconductor component, the charge compensation semiconductor component includes a semiconductor body with a first surface, a second surface opposite the first surface, a border bounding the semiconductor body in a horizontal direction substantially parallel to the first surface, a drain region of a first conductivity type extending to the second surface, an active region and a border region arranged between the active region and the border, a source metallization arranged on the first surface and a drain metallization arranged on the drain region in ohmic contact with the drain region.In a vertical cross-section that is essentially orthogonal to the first surface, the charge-compensated semiconductor device further comprises: a potential equalization region located at the edge and adjacent to the first surface in ohmic contact with the drain metallization; a low-doped semiconductor region located at the edge with a first concentration of dopants; and a multitude of first-pillar regions alternating with second-pillar regions in the active region and at the edge. The first-pillar regions exhibit a second concentration of dopants of the first conductivity type, which is higher than the first concentration, and are in ohmic contact with the drain metallization. The second-pillar regions exhibit a second conductivity type and are in ohmic contact with the source metallization.At least one of the outermost regions of the first column and one of the outermost regions of the second column form an interface with the low-doped semiconductor region. The horizontal distance between the interface and the potential equalization region, divided by the vertical distance between the first surface and the drain region, lies in the range of approximately 0.5 to approximately 3.

[0011] According to one embodiment of a charge-compensated semiconductor device fabrication method, the method includes providing a semiconductor body comprising a first surface, a second surface opposite the first surface, a drain region of a first conductivity type extending to the second surface, an active region, and a perimeter region surrounding the active region. In a vertical cross-section that is substantially orthogonal to the first surface, the semiconductor body further includes a low-doped semiconductor region located in the perimeter region with a first concentration of dopants and a plurality of first pillar regions alternating with second pillar regions in the active region and in the perimeter region. The first pillar regions have a second concentration of dopants of a first conductivity type that is higher than the first concentration.A pn junction is formed between adjacent first and second column regions. At least one of the outermost first column regions and one of the outermost second column regions forms an interface with the low-doped semiconductor region. A junction of the second conductivity type is located in the boundary region and borders at least a majority of the second column regions in the boundary region.The method further includes forming a potential equalization structure in the boundary region, at least adjacent to the first surface; forming a source metallization on the first surface in ohmic contact with the second column regions of the active region and with the junction region; forming a drain metallization opposite the source metallization in ohmic contact with the potential equalization structure and the first column regions; and cutting through the semiconductor body to form a boundary extending between the first surface and the second surface and surrounding the active region. The process is carried out such that the horizontal distance between the interface and the potential equalization structure, divided by the vertical distance between the first surface and the drain region, is in the range of approximately 0.5 to approximately 3.

[0012] The expert will recognize further features and advantages upon reading the following detailed description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0013] The components in the figures are not necessarily to scale; the emphasis is instead on illustrating the principles of the invention. Furthermore, identical reference symbols in the figures denote corresponding parts. In the drawings: Fig. Figure 1 shows a vertical cross-section through a semiconductor body of a semiconductor component according to one embodiment; Fig. Figure 2 shows part of the vertical cross-section through the in Fig. 1 Semiconductor component shown according to one embodiment; Fig. Figure 3 shows a vertical cross-section through a semiconductor body of a semiconductor component according to one embodiment; Fig. Figure 4 shows a vertical cross-section through a semiconductor body of a semiconductor component according to one embodiment; Fig. Figure 5 shows a vertical cross-section through a semiconductor body of a semiconductor component according to one embodiment; Fig. Figure 6 shows a vertical cross-section through a semiconductor body of a semiconductor component according to one embodiment; Fig. Figure 7 shows a vertical cross-section through a semiconductor body of a semiconductor component according to one embodiment; Fig. Figure 8 shows a vertical cross-section through a semiconductor body of a semiconductor component according to one embodiment; Fig. Figure 9 shows a vertical cross-section through a semiconductor body of a semiconductor component according to one embodiment; Fig. Figure 10 shows a top view of the in Fig. 2 Semiconductor component shown according to one embodiment; Fig. Figure 11 shows a top view of the in Fig. 2 semiconductor component shown according to another embodiment; Fig. Figure 12 shows a top view of a semiconductor component, as in Fig. 2 shown, according to a further embodiment; Fig. Figure 13 shows a top view of a semiconductor component, as in Fig. 2 shown, according to a further embodiment; Fig. Figure 14 shows a mask layout according to one embodiment; and Fig. Figure 15 shows a mask layout according to one embodiment. DETAILED DESCRIPTION

[0014] The following detailed description refers to the accompanying figures, which form part thereof and illustrate certain embodiments in which the invention can be practiced. In this respect, directional terms such as "above," "below," "front," "back," "leading," "trailing," etc., are used with reference to the orientation of the respective figure(s) described. Since components of the embodiments can be positioned in a wide variety of orientations, these directional terms are used for clarification purposes and are in no way to be understood as limiting. It should be noted that other embodiments can be used and structural or logical modifications can be made without departing from the scope of the present invention.The following detailed description is therefore not to be understood in a limiting sense, and the scope of the present invention is defined by the attached claims.

[0015] Various embodiments will now be described in detail, one or more examples of which are shown in the figures. Each example is introduced by explanation and is not to be understood as a limitation of the invention. The drawings are not to scale and serve only for illustrative purposes. For clarity, the same reference numerals are assigned to identical elements or manufacturing steps in the different drawings, unless otherwise specified.

[0016] In this description, the term "horizontal" refers to an orientation that is essentially parallel to a horizontal first or main surface of a semiconductor substrate or body. This could be, for example, the surface of a wafer or die.

[0017] In this description, the term "vertical" refers to an orientation that is essentially perpendicular to the first surface, i.e., parallel to the normal direction of the first surface of the semiconductor substrate or body. Similarly, in this description, the term "horizontal" refers to an orientation that is essentially parallel to the first surface.

[0018] In this description, a second surface of a semiconductor substrate or semiconductor body is considered to be formed by the lower or rear surface, while the first surface is considered to be formed by the upper, front, or main surface of the semiconductor substrate. The terms "above" and "below" in this description are therefore intended to denote the relative position of one structural feature with respect to another, taking this orientation into account.

[0019] In this description, n-doped devices are referred to as the first conductivity type, while p-doped devices are referred to as the second conductivity type. Alternatively, the semiconductor devices can be formed with opposite doping relationships, so that the first conductivity type can be p-doped and the second conductivity type can be n-doped. Furthermore, some figures indicate relative doping concentrations by specifying "-" or "+" next to the doping type. For example, "n" denotes - “a doping concentration that is lower than the doping concentration of an “n” doping area, while an “n +The “-doping area has a higher doping concentration than the “n” doping area. However, specifying the relative doping concentration does not mean that doping areas with the same relative doping concentration must have the same absolute doping concentration, unless otherwise stated. Two different n + Doping regions can, for example, exhibit different absolute doping concentrations. The same applies, for example, to an n + -doping- and a p + -Award area.

[0020] Certain embodiments of this description relate to, but are not limited to, field-effect semiconductor devices, in particular field-effect compensation semiconductor devices, and fabrication methods for such devices. In this description, the terms "semiconductor device," "semiconductor element," and "semiconductor component" are used synonymously. The field-effect semiconductor device is typically a vertical semiconductor device, such as a vertical MOSFET, with a source metallization and an insulated gate electrode located on the first surface and a drain metallization located on a second surface opposite the first. Typically, the field-effect semiconductor device is a power semiconductor with an active region containing a plurality of MOSFET cells for guiding and / or controlling a load current.Furthermore, the power semiconductor typically has a peripheral region with at least one edge termination structure that, viewed from above, at least partially surrounds the active region.

[0021] In this description, the term "power semiconductor" refers to a semiconductor component on a single chip capable of switching at high voltage and / or high current. In other words, power semiconductors are designed for high current, typically in the ampere range, and / or high voltages of more than approximately 10 V, or even more than approximately 100 V or approximately 500 V. In this description, the terms "power semiconductor" and "power semiconductor component" are used interchangeably.

[0022] The term "edge termination structure" in this description refers to a structure that represents a transition region in which the high electric fields around an active area of ​​the semiconductor device gradually change to the potential at or near the edge of the device and / or between a reference potential such as ground and a high voltage, for example, at the edge and / or on the back side of the semiconductor device. The edge termination structure can, for example, reduce the field intensity around a termination region of a rectifier junction by distributing the electric field lines across the termination region.

[0023] The term "field effect" in this description refers to the formation of a conductive "channel" of a first conductivity type (conductor type) and / or the control of the conductivity and / or shape of the channel in a semiconductor region of a second conductivity type, typically a body region of the second conductivity type, mediated by the electric field. Due to the field effect, a unipolar current path is formed through the channel region and / or controlled between a source region of the first conductivity type and a drift region of the first conductivity type. The drift region may be in contact with the drain region. The drift region and the drain region are in low-resistance contact with a drain electrode (drain metallization). The source region is in low-resistance contact with a source electrode (source metallization).In the context of this description, the term "in ohmic contact" means that a low-resistance ohmic current path exists between corresponding elements or sections of a semiconductor device when no voltages or only small probe voltages are applied to and / or across the semiconductor device. In this description, the terms "in ohmic contact," "in electrical resistance contact," "electrically coupled," and "in electrical resistance connection" are used synonymously.

[0024] In the context of this description, the term "MOS" (metal-oxide semiconductor) is to be understood as including the more general term "MIS" (metal-insulator semiconductor). For example, the term MOSFET (metal-oxide semiconductor field-effect transistor) is to be understood as including FETs with a gate insulator that is not an oxide; that is, the term MOSFET is used in the more general sense of both IGFET (insulated-layer field-effect transistor) and MISFET (metal-insulator semiconductor field-effect transistor). The term "metal" for the MOSFET gate material is to be understood as including or encompassing electrically conductive materials such as metals, alloys, doped polycrystalline semiconductors, and metal-semiconductor compounds such as metal silicides.

[0025] In the context of this description, the term "gate electrode" shall refer to an electrode that is located next to the body area, isolated from it, and configured for the formation and / or control of a channel area by the body area.

[0026] In the context of the present description, the term "field electrode" shall refer to an electrode which is arranged next to a semiconductor region, typically the drift region, partially isolated from the semiconductor region, and is configured for expanding a depleted section in the semiconductor region by charging to an appropriate voltage, typically a negative voltage with respect to the surrounding semiconductor region for an n-type semiconductor region (n-type semiconductor region).

[0027] In the context of this description, the term "depletable region" or "depletable zone" refers to the fact that, in the off-state of the semiconductor component, when a reverse voltage above a given threshold is applied, the corresponding semiconductor region or zone is essentially entirely depleted (essentially free of free charge carriers). For this purpose, the doping charge of the depletable region is adjusted accordingly, and in one or more embodiments, the depletable region is a lightly doped region. In the off-state, the depletable region(s), also called a space charge region, typically forms a continuous depleted zone, thereby preventing current flow between two electrodes or metallizations connected to the semiconductor body.

[0028] In the context of this description, the term “mesa” or “mesa region” shall refer to a semiconductor region between two adjacent trenches extending into the semiconductor substrate or semiconductor body in a vertical cross-section.

[0029] The term "commuting" in this description refers to switching the current of a semiconductor device from a conducting direction, in which a pn load junction, for example, the pn load junction between the body region and the drift region of a MOSFET, is under forward bias, to the opposite direction or reverse bias, in which the pn load junction is under reverse bias. The term "hard commutating" in this description refers to commutating at a rate of at least approximately 10 9 V / s, typically with a speed of at least approximately 5*10 9 V / s is denoted.

[0030] The following sections describe embodiments of semiconductor devices and manufacturing processes for semiconductor devices, primarily with reference to silicon semiconductor devices (Si semiconductor devices). Accordingly, a monocrystalline semiconductor region or layer is typically a monocrystalline Si region or layer. However, it should be noted that the semiconductor body can be made from any semiconductor material suitable for manufacturing a semiconductor device.Examples of such materials include, but are not limited to, elemental semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductors such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AllnN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indium gallium arsenide phosphide (InGaAsP), and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name a few. The semiconductor materials listed above are also known as homojunction semiconductor materials. Combining two different semiconductor materials creates a heterojunction semiconductor material.Examples of heterojunction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN)-aluminium gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminium gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminium gallium nitride (AlGaN), silicon-silicon carbide (Si. x C 1-x ) and silicon-SiGe heterojunction semiconductor materials. For power semiconductor applications, Si, SiC, GaAs, and GaN materials are currently the most commonly used. If the semiconductor body comprises a high bandgap energy material such as SiC or GaN, which each exhibits a high breakdown field strength and a high critical avalanche field strength, a higher doping level can be chosen for the corresponding semiconductor regions, thereby reducing the on-resistance Ron, also referred to as the on-resistance Ron.

[0031] With reference to Fig. 1 A first embodiment of a charge compensation semiconductor component 100 is described. Fig. Figure 1 shows a vertical cross-section through a semiconductor body 40 of the semiconductor device 100. The semiconductor body 40 extends in a vertical direction z between a first surface 101 and a second surface 102, which is opposite the first surface 101. In a horizontal direction x, which is essentially parallel to the first surface 101, the semiconductor body 40 is bounded by a border 41, for example a saw edge, which is essentially orthogonal to the first surface 101. The semiconductor body 40 has an active region 110 and a border region 120, which is located between the active region 110 and the border 41. Typically, the border region 120 surrounds the active region 110 when viewed from above.

[0032] A source metallization 10 is provided on the first surface 101. A drain metallization 11 is provided on the second surface 102, i.e., opposite the source metallization 10. Furthermore, a plurality of gate electrodes 12 are typically arranged on the first surface 101 in the active region, insulated from the source metallization 10 and the semiconductor body 40 by a dielectric region 13. The gate electrodes 12 are connected to a gate metallization that is located in Fig. Figure 1 is not shown. Accordingly, the semiconductor component 100 can be used as a component with three terminals.

[0033] The semiconductor body 40 typically includes a monocrystalline bulk material 4 and at least one epitaxial layer 3, 2, 1 formed thereon. The use of the epitaxial layer(s) 3, 2, 1 offers greater freedom in fine-tuning the background doping of the material, since the doping concentration can be controlled during deposition of the epitaxial layer(s).

[0034] At the in Fig. In the exemplary embodiment shown in Figure 1, the semiconductor body 40 includes a highly doped n-drain region 4 extending to the second surface 102 and in ohmic contact with the drain metallization 11 and with an n-field-stop region 3 adjacent to the drain region 4, which has a lower maximum doping concentration than the drain region 4. The drain region 4 and the optional field-stop region 3 are typically located in the active region 110 and edge region 120, respectively, and can extend to the edge 41.

[0035] A multitude of alternating n-drift sections 1 and p-compensation regions 6, forming the respective pn transitions, are arranged in the active region 110 and in the adjacent part of the boundary region 120. The drift sections 1 have a first maximum doping concentration, which is typically higher than the maximum doping concentration of the field stop region 3. The drift sections 1 are in ohmic contact with the drain metallization 11 (in the exemplary embodiment via the adjacent field stop region 3 and the drain region 4) and typically extend in the active region 110 to the first surface 101. For the sake of clarity, in Fig. Figure 1 shows only some drift sections 1 and compensation areas 6. As indicated by the two dashed lines in Fig. As shown in Figure 1, a multitude of drift sections 1 and compensation areas 6 can be arranged in the boundary region 120. The drift sections 1 and the compensation areas 6 of the boundary region are typically arranged at a distance from the first surface 101. In the following, the n-drift sections 1 are also referred to as n-column regions 1 and first column regions 1 (of the first conductivity type), while the p-compensation areas 6 are also referred to as p-column regions 6 and second column regions 6 (of the second conductivity type).

[0036] A (mathematically) integrated doping concentration of the drift sections 1 essentially coincides with an integrated doping concentration of the compensation regions 6, at least in the active region 110. Accordingly, the drift sections 1 and the compensation regions 6 form a pn compensation structure 1, 6. The mean doping concentration of the drift sections 1 and compensation regions 6, i.e., the mathematically integrated difference between the donor and acceptor concentrations per volume, is typically lower than the maximum doping concentration of the field stop region 3, and even more typically lower than the mean doping concentration of the field stop region 3. Even more typically, the mean doping concentration of the drift sections 1 and the compensation regions 6 is less than 10% or less than 5% of the maximum doping concentration of the drift sections 1 and / or the compensation regions 6.Even more typical is the average doping concentration of drift sections 1 and compensation areas 6, which is essentially zero.

[0037] In the exemplary embodiment, the p-compensation regions 6 are formed as vertically oriented columns. Alternatively, the p-compensation regions 6 are formed as substantially vertically oriented strip-like parallelepipeds, rectangles, or ellipsoids.

[0038] Depending on the manufacturing of the pn compensation structure 1, 6, the doping concentration in the drift sections 1 and / or in the compensation areas 6 can vary.

[0039] The compensation areas 6 of the active area 110 are in ohmic contact with the source metallization 10 via the body areas 5, 5'.

[0040] This refers to Fig. 2, which have an enlarged upper part of the in Fig. Figure 1 shows the semiconductor component 100, which is explained in more detail. The one in Fig. The part shown in section 2 typically corresponds to a top part of a plurality of unit cells 111 in the active region 110 of the semiconductor component 100.

[0041] In the exemplary embodiment, a p + -Body contact area 5c and two n + -Source regions 15 are formed within a p-body region 5. Furthermore, an optional p extends + -Contact area 6c between body contact area 5c and compensation area 6. For clarity, body contact area(s) 5c and contact area(s) 6c are shown in Fig. 1 and not shown in the following figures.

[0042] A section 13a of the dielectric region 13 is provided between the first surface 101 and each of the gate electrodes 12 and extends in a horizontal direction from the drift section 1 along the body region 5 at least to the source region 15, such that an inversion channel, also referred to here as a MOS channel, can be formed by the field effect in a channel region of the body region 5 along the section(s) 13a forming a dielectric gate region. Accordingly, the semiconductor device 100 can be used as a MOSFET.

[0043] The remaining section of the dielectric region 13 forms an intermediate layer dielectric between the source metallization 10 and the gate electrode 12 and the first surface 101.

[0044] In the exemplary embodiment, the source metallization 10 is electrically connected to the source regions 15 and the body contact region 5c via a shallow trench contact formed in the semiconductor body 40 by the interlayer dielectric 13. In other embodiments, the source metallization 10 is electrically connected to the source region 15 and the body contact region 5c essentially at the first surface 101.

[0045] According to another embodiment, the gate electrode(s) 12 and gate dielectric(s) 13a are formed in a corresponding trench extending from the first surface 101 into the semiconductor body 40. In this embodiment, the body region 5 and source regions 15 border an upper part of the respective trench, while the drift sections 1 border a lower part of the respective trench. In this embodiment, the drift sections 1 may not extend to the first surface 101 in the active region 110. With further reference to Fig. 1. Further embodiments are explained.

[0046] According to one embodiment, the doping concentrations of the p-compensation regions 6 and the drift sections 1 are chosen such that their charges can be mutually depleted in the off state, and that in the on state an uninterrupted conduction path of low impedance is formed from the source metallization 10 to the drain metallization 11.

[0047] The active region 110 can be defined by the presence of source regions 15 and isolated gate electrodes 12 configured to form and / or modify a channel region adjacent to the body region 5. The active region 110 can also be defined by the presence of active cells, typically MOSFET cells, for conducting a load current between the source metallization 10 and the drain metallization 11.

[0048] As in Fig. As shown in Figure 1, the interlayer dielectric 13 typically also covers the semiconductor body 40 in the edge region 120. The interlayer dielectric 13 can extend essentially to the edge 41.

[0049] According to one embodiment, the semiconductor body 40 further encloses a low-doped semiconductor area 2 in the edge region 120 which is in ohmic contact with the drift sections 1.

[0050] The lightly doped semiconductor region 2 can be lightly p-doped or it can be a lightly n-doped semiconductor region. Using a lightly doped semiconductor region 2 in the edge region 120 typically reduces switching losses.

[0051] Typically, the low-doped semiconductor region 2 has a maximum doping concentration of less than approximately 10 15 cm -3 or even less than approximately 10 14 cm -3More typically, the low-doped semiconductor region 2 is an intrinsic semiconductor region. Typically, the doping concentration of the first and second column regions is at least approximately ten times the maximum doping concentration of the low-doped semiconductor region 2.

[0052] Unless otherwise specified, the term doping concentration of a semiconductor region or layer, when used to compare it with the doping concentration of another semiconductor region or layer, may also refer to a maximum and / or mean or average concentration of dopants in that particular semiconductor region or layer. The doping concentration may vary within the semiconductor region or layer.

[0053] The doping concentration of the low-doped semiconductor region 2 is typically at least a factor of five, more typically at least a factor of approximately ten, even more typically at least a factor of approximately 20, and even more typically at least a factor of approximately 50, for example, a factor of approximately 100 lower than the doping concentration of the drift sections 1 (and the compensation regions 6).

[0054] Furthermore, the doping concentration of the low-doped semiconductor region 2 typically depends on the voltage class of the semiconductor device. For example, the maximum doping concentration of donors in a low-doped n- - -Semiconductor region 2 in the range of approximately 2*10 13 cm -3 up to approximately 2*10 14 cm -3 for a semiconductor component 100 with a nominal blocking voltage of 600 V.

[0055] The maximum doping concentration (of donors) of the low-doped semiconductor region 2 can essentially correspond to the average doping concentration (of donors) of the low-doped semiconductor region 2 and is typically lower than approximately 10 15 cm -3 , even more typically lower than approximately 5*10 14 cm -3 or even lower than approximately 10 14 cm -3 , i.e., the low-doped semiconductor region 2 can be an essentially intrinsic semiconductor region with a doping concentration in a range of approximately 10 13 cm -3 up to about 10 14 cm -3 be.

[0056] Furthermore, the low-doped semiconductor region 2 is typically only provided in the edge region 120 and can extend to the first surface 101 in the edge region 120.

[0057] In the exemplary embodiment, the p-column regions 6 (compensation regions) of the boundary region 120 border a p-connection region 17, which is in ohmic contact with the source metallization 10 via an outermost of the body regions 5'.

[0058] The junction region 17 is typically a depletable semiconductor region, i.e., a semiconductor region that is essentially already depleted when a reverse bias is applied between the drain metallization 11 and the source metallization 10 in an off-state. This subjects the pn junctions formed between adjacent n-column regions and p-column regions 6 to a reverse bias that is lower than the nominal breakdown voltage of the semiconductor device 100. Due to the use of a depletable junction region 17, or at least a partially depletable one, a large portion of the potential of the edge region 120 adjacent to the first surface source 101 differs from the source potential at higher reverse bias. This prevents a reduction in the breakdown voltage.The doping concentration of the junction area 17 is typically chosen such that the junction area 17 is only substantially depleted above a sufficiently high applied blocking voltage, e.g., when at least approximately one fifth or half of the nominal breakdown voltage is applied between the source metallization 10 and the drain metallization 11.

[0059] At the in Fig. In the exemplary embodiment shown in Figure 1, the first and second column regions 1, 6 of the edge region 120 extend essentially to the same depth as the first and second column regions 1, 6 in the active region 110.

[0060] According to one embodiment, an outermost of the p-column regions 6 of the edge region 120, i.e., the p-column regions 6 of the edge region 120 closest to the edge 41, forms an interface 46 to the low-doped semiconductor region 2 at a horizontal position x0, where a voltage on the first surface 101 is at least approximately one fifth of the nominal breakdown voltage when the nominal breakdown voltage is applied between the source metallization 10 and the drain metallization 11.

[0061] The interface 46 can be formed as a pn junction between the outermost p-column region 6 and a low-doped n-semiconductor region 2 or between an outermost n-column region 1 and a low-doped p-semiconductor region 2.

[0062] Alternatively, the interface 46 can be formed as a transition between an outermost column region 1, 6 and a less doped semiconductor region 2 of the same conductivity type.

[0063] In the context of this description, the term "transition" is intended to refer to the interface between adjacent semiconductor regions, i.e., semiconductor regions in direct mechanical contact or adjacent semiconductor sections of the same conductivity type, but with significantly different doping concentrations.

[0064] In the context of this description, the term “pn junction”, as used here, is intended to refer to the interface between adjacent semiconductor regions or semiconductor sections of different conductivity types.

[0065] Typically, the interface 46 is formed at a horizontal position x0 where the stress on the first surface 101 is at least approximately one third, or more typically at least approximately one half, of the nominal breakdown stress when the nominal breakdown stress is applied between the source metallization 10 and the drain metallization 11.

[0066] Numerical simulation shows that the switching losses of the semiconductor device 100 of the edge region 120 can be reduced by up to approximately a factor of 10 compared with a similar structure but without alternating n- and p-column regions 1, 6 in the edge region, or with alternating n- and p-column regions 1, 6 in the edge region extending closer to the edge and to semiconductor regions at the edge that are essentially at drain potential when the nominal breakdown voltage is applied between the source metallization 10 and the drain metallization 11, without substantially reducing the breakdown voltage.This is because the low-doped semiconductor region 2 (intrinsic semiconductor region 2) is located in a region of the edge area 120 where the electric field during the blocking mode (blocking bias) is sufficiently low so that the symmetry breaking of the semiconductor structure caused by the transition from the compensation structure 1, 6 to the low-doped semiconductor region 2 and to the edge 41 does not lead, or almost does not lead, to a reduction in the nominal breakdown voltage.

[0067] It was found that a chip design with a horizontal distance d1 between the edge 41 and the interface 46 divided by a horizontal distance d3 between the source metallization 10 and the interface 46 in a range of approximately 0.1 to approximately 0.9, typically in a range of approximately 0.2 to approximately 0.5, leads to particularly low switching losses at a given nominal breakdown voltage.

[0068] As in Fig. As shown in Figure 1, the boundary region 120 typically includes an inner section 120a with alternating n and p column regions 1, 6 and an outer section 120b without column regions 1, 6.

[0069] In the exemplary embodiment, a highly doped field stop region 8, which is in ohmic contact with the drain metallization 11 and forms a potential equalization region, is arranged in the edge region 120 (outer section 120b) and between the low-doped semiconductor region 2 and the edge 41.

[0070] The field stop region 8 can also extend to the first surface 101 and / or to the drain region 4. In embodiments where the field stop region 8 is of the same conductivity type as the low-doped semiconductor region 2 (n-type in the case of the Fig. In the exemplary embodiment shown in Figure 1, the field-stopping region 8 can also be removed from the field-stopping region 3 by a lower section of the low-doped semiconductor region 2.

[0071] As in Fig. As shown in Figure 1, the connection area 17 typically extends to close to the field stop area 8.

[0072] Because of the field-stopping region 8, the electric field in the off state does not extend, or at least hardly extends, to the edge 41. Consequently, a low leakage current is ensured, since crystal defects that may be caused by sawing are shielded by the highly doped field-stopping region 8.

[0073] It was also found that a chip design with a horizontal distance d2 between the interface 46 and the equipotential bonding area 8 divided by a vertical distance d4 between the first surface 101 and the drain area 4 in a range of approximately 0.5 to approximately 3, typically from approximately 0.8 to approximately 1.5, leads to particularly low switching losses at a given nominal breakdown voltage.

[0074] The potential equalization region can also be formed and / or enclosed by a field plate 11a arranged on the first surface 101, separated from the semiconductor body 40 by the dielectric region 13 and in ohmic contact with the drain metallization 11 and the drain region 4. The field plate 11a can be connected via the field stop region 8 and a conductive connector (in Fig. 1 not shown), e.g. a polysilicon connector extending through the dielectric region 13, in ohmic contact with the drain metallization 11.

[0075] Typically, the semiconductor body 40 of the semiconductor device 100 further encloses a depletable n-type semiconductor region 18 (second depletable semiconductor region) in the edge region 120. This region is located between the junction region 17 (first depletable semiconductor region) and the first surface 101 and forms a pn junction with the junction region 17. The second depletable semiconductor region 18 typically has a higher maximum doping concentration than the maximum doping concentration of the low-doped semiconductor region 2. Typically, the vertically integrated doping concentration of the second depletable semiconductor region 18 is equal to or lower than the vertically integrated doping concentration of the junction region 17.The second depletable semiconductor region 18 typically stabilizes the edge termination structure against surface charges on the first surface 101 and reduces the injection of holes into the dielectric region 13.

[0076] The doping concentration of the second depletable semiconductor region 18 can be constant, or decrease continuously, or decrease in discrete steps with decreasing distance from the edge 41 and the field-stopping region 8. The vertical extent of the second depletable semiconductor region 18 can be constant, or increase continuously, or increase in discrete steps with decreasing distance from the edge 41 and the field-stopping region 8.

[0077] Similarly, the doping concentration of the compound region 17 can be constant, or decrease continuously, or decrease in discrete steps with decreasing distance from the edge 41 and the field stop region 8. The vertical extent of the compound region 17 can be constant, or decrease continuously, or decrease in discrete steps with decreasing distance from the edge 41 and the field stop region 8.

[0078] At the in Fig. In the exemplary embodiment shown in 1, the semiconductor component 100 further includes a gate electrode 12 and a gate metallization (in Fig. (1 not shown) in ohmic contact field plate 12a. Consequently, the electric field distribution in the off state (blocking bias) can be further smoothed and / or the sensitivity of the semiconductor component 100 with respect to mobile charges in the dielectric region 13 can be further reduced.

[0079] The field plate 12a is typically located between the field plate 11a and the source metallization 10.

[0080] The field plate 11a and / or the field plate 12a can be configured in a stepped manner, i.e., the vertical (minimum) distance of the field plate 11a and / or 12a from the first surface 101 can change significantly in steps in the horizontal direction. In other embodiments, only one or even none of the field plates 11a, 12a are provided on the first surface 101.

[0081] Typically, the field plate 11a, the field plate 12a, the field-stopping region 8, and the low-doped semiconductor region 2 are essentially ring-shaped, for example, in a ring-shaped top view. In these embodiments, the field plate 11a and the field plate 12a each form a drain ring 11a and a gate ring 12a, respectively.

[0082] Fig. Figure 3 shows a vertical cross-section through a semiconductor body 40 of a charge compensation semiconductor device 200. The semiconductor device 200 is similar to the one shown above with respect to the Fig. 1 and Fig. The semiconductor device 100 described in Section 2 is similar. The semiconductor body 40 of the semiconductor device 200 also extends between a first horizontal surface 101 and a second surface 102. In a horizontal direction, the semiconductor body 40 of the semiconductor device 200 is also bounded by an edge 41 that extends between the first and second surfaces 101, 102. A highly doped n-drain region 8 is located on the second surface 102 both in an active region 110 and in an edge region 120 provided between the active region and the edge 41. The drain region 8 typically extends to the edge 41. A source metallization 10 is provided on the first surface 101, and a drain metallization 11 is provided on the second surface 102 and the drain region 8, and is in ohmic contact with the drain region 8.

[0083] In the exemplary embodiment, a low-doped semiconductor region 2, which is typically an intrinsic semiconductor region, and two potential equalization regions 8, 11a in ohmic contact with the drain metallization 11 are arranged in the edge region 120 and next to the first surface 101. The potential equalization region 11a is formed on the first surface as a field plate 11a, and the potential equalization region 8 is formed in the semiconductor body 40 as an n-field stopping region 8, which borders the low-doped semiconductor region 2 and has a higher doping concentration than the low-doped semiconductor region 2.

[0084] In other embodiments, only one of the potential equalization areas 8, 11a can be used.

[0085] In the exemplary embodiment, the low-doped semiconductor region 2 and the field-stopping region 8 extend to the first surface 101.

[0086] A plurality of first n-column regions 1, alternating with second p-column regions 6, 6', are arranged in the active region 110 and in an adjacent section of the edge region 120 between the low-doped semiconductor region 2 and the active region 110. The first column regions 1 are in ohmic contact with the drain region 8 via an n-field-stopping region 3. The second column regions 6, 6' of the edge region 120 are in ohmic contact with the source metallization 10 via a depletable p-semiconductor region 17 and a more highly p-doped outermost body region 5' adjacent to an outermost plurality of gate electrodes 13 of the active region, which are arranged on the first surface separated from the adjacent body region(s) and the adjacent corresponding first column region 1 by a dielectric region 13.

[0087] The field stop region 8 can extend vertically deeper into the field stop region 3 due to production constraints. For example, the field stop region 3 can be formed as an n-doped epitaxial layer 3 on a highly n-doped substrate 4. Subsequently, an essentially intrinsic layer 2 can be epitaxially deposited onto the epitaxial layer 3. Donors and acceptors can then be implanted using masks, such that more donors are implanted into a field stop region 8 zone than into zones for the first column regions 1, which are formed after subsequent thermal treatment. Due to the higher doping of the field stop region 8 zone compared to the zones for the first column regions 1, donors from the field stop region zone can spread deeper into the typically less densely doped epitaxial layer 3 during thermal treatment.

[0088] At the in Fig. In the exemplary embodiment shown in Figure 3, an outermost of the second column regions 6' forms an interface 46 to the low-doped semiconductor region 2, wherein a horizontal distance d2, d2' between the interface 46 and the potential equalization region 8, 11a divided by a vertical distance d4 between the first surface 101 and the drain region 5 lies in a range of approximately 0.5 to approximately 3, typically from approximately 0.8 to approximately 1.5. As above with regard to Fig. As explained in section 1, such a chip design leads to particularly low switching losses at a given nominal breakdown voltage.

[0089] In the case of embodiments in which a field plate 11a and a field stop area 8 are used as potential equalization areas 8, 11a, the horizontal distance d2' between the interface 46 and the field plate 11a is typically smaller than the horizontal distance d2 between the interface 46 and the field stop area 8.

[0090] In the exemplary embodiment, an outermost section of the source metallization 10 forms a stepped source field plate. The interface 46 is arranged between the source field plate and the drain field plate 11a.

[0091] Both the maximum horizontal distance d3 between the source metallization 10 and the interface 46 and the minimum horizontal distance d3' between the source metallization 10 and the interface 46 can be in a range of approximately 0.1 to approximately 0.9, more typically in a range of approximately 0.2 to approximately 0.5.

[0092] Furthermore, a horizontal distance d1 between the edge 41 and the interface 46 divided by one of the horizontal distances d3, d3' between the source metallization 10 and the interface 46 can be in a range of approximately 0.1 to approximately 0.9, more typically in a range of approximately 0.2 to approximately 0.5.

[0093] Fig. Figure 4 shows a vertical cross-section through a semiconductor body 40 of a charge compensation semiconductor device 201. The semiconductor device 201 is similar to the one described above with respect to Fig. 3 explained semiconductor component 200 similarly. However, in the semiconductor body 40, only one field plate 11a next to the first surface 101 in the edge region 120 of the semiconductor component 201 is provided as a potential equalization area.

[0094] Furthermore, a polysilicon layer 11b can be provided in ohmic contact with the field plate 11a and embedded in the dielectric region 13 next to the edge 41 and between the field plate 11a and the first surface 101.

[0095] In the exemplary embodiment, a gate field plate 12a can be configured as above with regard to Fig. 2 explained on the first surface 101 in the edge region 120 and brought into contact with a gate metallization not shown via a further polysilicon layer 12b embedded in the dielectric region 13.

[0096] Furthermore, a polysilicon source contact 10a is located between the source metallization 10 and the outermost body region 5' in Fig. 4 shown.

[0097] Fig. Figure 5 shows a vertical cross-section through a semiconductor body 40 of a charge compensation semiconductor device 202. The semiconductor device 202 is similar to the one described above with respect to Fig. 4 explained semiconductor component 201 similarly.

[0098] In the exemplary embodiment, the doping concentration of the outermost second column region 6' is, for example, in the range of approximately 50% to approximately 80% lower than the doping concentration of the second column region 6 in the active region 120 and the other second column regions 6 of the boundary region 120. This smooths the transition between the compensation structure 1, 6 and the low-doped semiconductor region 2, i.e., the electric field distribution in blocking mode leads to even lower switching losses during component operation.

[0099] Furthermore, a depletable n semiconductor region 18, as above with regard to Fig. 1 explained, in the edge region 120 of the semiconductor component 202.

[0100] Fig. Figure 6 shows a vertical cross-section through a semiconductor body 40 of a charge compensation semiconductor device 203. The semiconductor device 203 is similar to the one described above with respect to Fig. 4 explained semiconductor component 201 similarly.

[0101] The vertical extent of the outermost first column regions 1' and the outermost second column regions 6' is, however, less than the vertical extent of the first and second column regions 1, 6 in the active region 110. Furthermore, the second column region 6' (second from the right) adjacent to the outermost first column region 1' and the first column region 1" (second from the right) adjacent to the second column regions 6" exhibit an intermediate vertical extent. Accordingly, the transition between the compensation structure 1, 6 and the low-doped semiconductor region 2 is also smoothed. The vertical extent of the column regions 1, 6 of the boundary region 120 can also be reduced to the boundary 41 in one or more steps.

[0102] Fig. Figure 7 shows a vertical cross-section through a semiconductor body 40 of a charge compensation semiconductor device 204. The semiconductor device 204 is similar to the one described above with respect to Fig. The semiconductor component 202 described in section 5 is similar. However, the outermost body region 5' has a section that extends further towards the edge 41 and connects one or more of the inner second column regions 6 of the edge region 120, which are thus connected to the source metallization via non-depletable semiconductor regions.

[0103] Fig. Figure 8 shows a vertical cross-section through a semiconductor body 40 of a charge compensation semiconductor device 205. The semiconductor device 205 is similar to the one described above with respect to Fig. 7 described semiconductor component 204 similarly. However, the depletable semiconductor regions 17, 18 extend to the edge 41.

[0104] Furthermore, the outermost second column region 6' is less heavily doped, as above with regard to Fig. 5 explained.

[0105] A field stop zone 8 is even more extensive, as mentioned above with regard to the Fig. 1 and Fig. 3 explained, provided at margin 41.

[0106] Fig. Figure 9 shows a vertical cross-section through a semiconductor body 40 of a charge compensation semiconductor device 206. The semiconductor device 206 is similar to the one described above with respect to Fig. The semiconductor component 202 described in section 4 is similar. However, at least one outermost first column region 1' and a second column region 6" adjacent to the outermost first column region 1' have a higher doping concentration than a corresponding first and second column region 1, 6 closer to and within the active region 110, respectively. Accordingly, the transition between the compensation structure 1, 6 and the low-doped semiconductor region 2 is also smoothed.

[0107] Fig. Figure 10 shows a top view of the above with regard to Fig. 3 explained semiconductor component 200. Fig. 10 can also correspond to a horizontal cross-section through the semiconductor body 40 of the semiconductor component 200.

[0108] In the exemplary embodiment, the semiconductor body 40 has a rectangular shape in both horizontal cross-sections and when viewed from above, while the boundary 45 between the active region 110 and the inner section 120a of the active region 120 is essentially octagonal (typically a closed chain of eight non-overlapping straight segments or sides). However, the active region 110 is typically not octagonal in horizontal cross-sections and when viewed from above. This may be due to the presence of a gate pad 12', which is typically at least partially enclosed when viewed from above. For clarity, the alternating first column regions 1 and second column regions 6, which may extend in the x-direction, are shown in Fig. 10 not shown. The doping concentrations of the first and second column regions 1, 6 under the gate pad 12' can be the same as in the active region 110.

[0109] The first and second column regions 1, 6 can essentially be shaped as bands and elongated parallel rectangles, each with a large aspect ratio of more than 10 or even more than approximately 100, extending in the y-direction when viewed from above.

[0110] While the left and right boundary 46 between the inner section 120a and the outer section 120b is defined by the pn junction 46 between the low-doped semiconductor region 2 and the corresponding outermost second column region 6 (6' in Fig. 3) The boundaries 46' between the inner section 120a and the outer section 120b are typically formed between the low-doped semiconductor region 2 and the alternating first and second column regions 1, 6. In the exemplary embodiment, the boundary 46, 46' between the outer section 120b and the inner section 120a is rectangular when viewed from above.

[0111] The first and second column regions 1, 6 can extend with the inner first and second column regions 1, 6, which extend over the active area 110, i.e. from the active area 110 into the inner section 120a of the boundary area 120, between the two boundaries 46'.

[0112] Typically, the doping concentration of the first and second column regions 1, 6 in the inner section 120a of the boundary region 120 is lower than that of the active region 110. As shown by the dashed line in Fig. As shown in Figure 10, the doping concentrations of the first and second column regions 1, 6 in an innermost transition region can be reduced from approximately 100% to a lower value of approximately 90%, 80%, 60%, 50%, 40%, or even only approximately 20%. Accordingly, the distances between potential equalization surfaces in blocking mode across the semiconductor body 40 can be more uniform.

[0113] In Fig. Figure 11 additionally shows a typical arrangement of the outermost body region 5'.

[0114] The respective top view and horizontal cross-section in Fig. The semiconductor component 200' shown in section 12 is the one shown above with regard to the Fig. 3, Fig. 10 and Fig. The semiconductor component 200 described in Figure 11 is similar. However, the gate pad 12' is only partially enclosed by the active region 110 when viewed from above. The doping concentrations of the first and second column regions 1, 6 below the gate pad 12' can be lower than those in the active region 110.

[0115] In another embodiment, the gate pad is formed in the outer section 120b of the edge region 120 when viewed from above.

[0116] The respective top view and horizontal cross-section in Fig. The semiconductor component shown in section 13, 200", is similar to the one shown above with regard to the Fig. 3, Fig. 10 and Fig. Figure 11 described the semiconductor device 200 similarly. However, the four corner regions of the edge region 120 are shaped differently. Viewed from above and in a horizontal cross-section, the boundary 46, 46', 46" between the outer section 120b and the inner section 120a of the semiconductor device 200" has an octagonal shape and has four boundaries 46" that form an angle of 45° with each of the four vertical sides 41 of the edge 41.

[0117] In other embodiments, the boundary between the outer section 120b and the inner section 120a of the edge region 120 may have sections in the corner areas that form an angle of 30° or 60° with the outer edge.

[0118] According to one embodiment of a charge-compensating semiconductor device, the charge-compensating semiconductor device 200, 200', 200" comprises a semiconductor body 40 with a first surface (101), a second surface (102) opposite the first surface, and a border 41 that bounds the semiconductor body 40 in a horizontal direction substantially parallel to the first surface. The semiconductor body 40 typically has the shape of a rectangle when viewed from above. An active region 110 of the semiconductor body 40 has the shape of an octagon when viewed from above. A border region 120 is arranged between the active region 110 and the border 41. A low-doped semiconductor region 2 with a first concentration of dopants is arranged in an outer section 120b of the border region 120 and may extend to the border 41.An inner section 120a of the boundary region 120 is provided between the active region 110 and the outer section 120b of the boundary region 120. A boundary 46, 46', 46" between the inner section 120a and the outer section 120b of the boundary region 120 runs, in a corner region of the boundary region 120 next to two adjacent vertical sides of the boundary 41, substantially parallel to one of the two vertical sides or forms an angle of approximately 60°, 45°, or 30° with the boundary 41. For example, the boundary 46, 46', 46" between the outer section 120b and the inner section 120a can have a polygonal shape when viewed from above, e.g., a rectangular or octagonal shape. A source metallization (10) is arranged on the first surface, and a drain metallization (11) is provided opposite the source metallization (10).In a vertical cross-section, essentially orthogonal to the first surface, the charge-compensated semiconductor device further encloses a plurality of first column regions 1 alternating with second column regions 6 in the active region 110. The first column regions 1 and the second column regions 6 extend into the inner section 120a of the boundary region 120. The first column regions 1 exhibit a second concentration of dopants of the first conductivity type, which is higher than the first concentration, and are in ohmic contact with the drain metallization (11). The second column regions 6 exhibit a second conductivity type and are in ohmic contact with the source metallization (10). Viewed from above, the first column regions 1 are essentially parallel to each other and to the second column regions 6.The corresponding doping concentrations of the first column areas 1 and the second column areas 6 are lower in the inner section 120a than in the active area 110.

[0119] According to numerical simulation (not shown), this layout offers several advantages. In blocking mode, high electric field strength can be avoided (especially in the corner regions). The curvature of the depletion region in blocking mode can be fine-tuned. Therefore, a particularly high blocking voltage can be achieved. Furthermore, the design is more tolerant of layout variations (manufacturing tolerances).

[0120] Charge-compensated semiconductor devices are primarily fabricated using a so-called multiple epitaxy process. In this process, an n-doped epitaxial layer, which can be several micrometers thick, is first grown on a highly n-doped substrate and is generally referred to as a "buffer epi." In addition to the doping introduced in the epitaxial step, dopant ions are introduced into the buffer epi through a photoresist mask using implantation with the dopant ions at the first charge sites (for example, boron for phosphorus doping). Counter-doping can also be used via implantation (either through a mask or across the entire surface). It is also possible to separate the individual epitaxial layers with the required doping concentration. The entire process is then repeated until an n- (multiple epitaxial) layer of sufficient thickness and equipped with charge centers is produced.The charge centers are aligned with each other and stacked vertically. These centers are then brought together by thermal diffusion in a wavy vertical column to form adjacent p-charge compensation regions (compensation regions) and n-charge compensation regions (drift sections). From this point, the actual component manufacturing can then take place.

[0121] Another conventional technique for fabricating charge-compensated semiconductor devices involves trench etching and trench filling. The stress-absorbing volume is deposited in a single epitaxial step (n-doped epi) onto a highly n-doped substrate, such that its thickness corresponds to the total thickness of the multilayer epitaxial structure. A deeper trench is then etched, defining the shape of the p-pillar. This trench is subsequently filled with crystal-defect-free p-doped epi. However, integrating the doping during an epi process is only possible with relatively large fluctuations. Especially at very small dimensions, these fluctuations quickly exceed the specified process window, potentially leading to significant yield losses. Furthermore, vertical variation of the doping profile (and thus the vertical development of the field strength) is not feasible.Therefore, meeting various robustness criteria with this technique can be difficult. For these reasons, the n- and p-dopers of the charge compensation structures are primarily introduced by implantation in the following.

[0122] Both techniques can be used to manufacture charge-compensated semiconductor components, as described above with regard to the Fig. The methods described in sections 1 to 13 may be used. Such a method can involve providing a semiconductor body 40, typically a wafer, comprising a first surface 101, a second surface 102 opposite the first surface, a first-conductivity-type drain region 8 extending to the second surface 102, an active region 110, and a perimeter region 120 surrounding the active region 110. In a vertical cross-section that is substantially orthogonal to the first surface 101, the semiconductor body 40 includes a low-doped semiconductor region 2 with a first concentration of dopants and, arranged in the perimeter region, a plurality of first-pillar regions 1 alternating with second-pillar regions 6 in the active region 110 and in the perimeter region 120. The first-pillar regions 1 have a second concentration of dopants of a first-conductivity type that is higher than the first concentration.A corresponding pn junction is formed between adjacent first column regions 1 and second column regions 2. At least one of the outermost first column regions 1 and one of the outermost second column regions 6 forms an interface 46 with the low-doped semiconductor region. A connection region 17 of the second conductivity type is provided in the boundary region 120 and borders at least a majority of the second column regions 6 of the boundary region 120.

[0123] The method can further include forming a potential equalization structure (one or more potential equalization regions) 8, 11a in the edge region at least next to the first surface, forming a source metallization 10 on the first surface 101 in ohmic contact with the second column regions 6 of the active region 110 and with the connection region 17, forming a drain metallization 11 opposite the source metallization 10 in ohmic contact with the potential equalization structure 8, 11a and the first column regions 1, as well as cutting the semiconductor body 40 to form an edge 41 extending between the first surface 101 and the second surface 102 and surrounding the active region 120.The method is typically designed such that a horizontal distance d2, d2' between the interface 46 and the potential equalization structure 8, 11a divided by a vertical distance d4 between the first surface 101 and the drain area 4 lies in a range of approximately 0.5 to approximately 3, typically from approximately 0.8 to approximately 1.5.

[0124] The formation of the potential equalization region structure can include at least one of the following: forming a field plate 11a on the first surface 101, forming a field stop region 8 of the first conductivity type located below the first surface and adjacent to the low-doped semiconductor region 2 with a higher concentration of dopants than the first concentration, and / or forming a doped polysilicon region between the field plate 11a and the field stop region 8.

[0125] The first and second column areas 1, 6 can be used with a mask layout, as shown in the Fig. 14 and Fig. 15 are shown, formed. For the sake of clarity, the mask layouts shown correspond to a small, in Fig. Part 250 shown in section 13.

[0126] After providing the semiconductor body (wafer) 40 with a low-doped (e.g., intrinsic) semiconductor layer 2 extending towards the main surface, an active region 110 of octagonal shape and a boundary region 120 with an outer section 120b and an inner section 120a between the active region 110 and the outer section 120b can be defined.

[0127] After that, donor ions can be deposited on the main surface to form the first columnar regions 1 i first implantation mask (first mask) 1i arranged, and acceptorions can be implanted through a second implantation mask (second mask) 6 arranged on the main surface to form the second column regions 6. iThey are implanted. Typically, several implantations of different ion energies are used prior to a joint treatment to activate the implanted donors and acceptors.

[0128] As in the Fig. 14 and Fig. As shown in 15, the first mask shows 1 i , 1' i first openings 1i, extending from the active area 110 in the first horizontal direction y into the inner section(s) 120a, where they end, and the second mask 6i, 6' i has second openings 6 i on, extending from the active area 110 in the y-direction into the inner section(s) 120a of the boundary area 120, where they end. The first mask 1 i , 1' i and the second mask 6i, 6' i They also typically close corresponding external openings 1' i , 6' ione, which is provided only in the inner section 120a of the boundary area 120, but not in the active area 110. A horizontal extension of the first openings 1 i and the second openings 6 i In a second horizontal direction (x-direction), the area is larger compared to the inner section 120a in the active area 110. Similarly, the extent in the x-direction of the outer openings 1' is i , 6' l lower than the x-direction extent of the openings 1 i , 6 l 110 in the active area. Accordingly, the first and second column regions 1, 6 are characterized by a reduced

[0129] Doping concentration in the inner section 120a of the boundary region 120 compared to the active region 110 and second column regions 1 with a reduced doping concentration in the inner section 120a of the boundary region 120 compared to the active region 110 such that the first column regions 1 and the second column regions 6 are at least partially substantially parallel to each other, and that a boundary 46" between the inner section 120a and the outer section 120b of the boundary region 120, in a corner region where two vertical sides of the boundary 41 are at least close to each other, is substantially parallel to one of the two vertical sides or forms an angle of approximately 45° with the two vertical sides.

[0130] Terms used to denote a relative spatial relationship, such as "below," "under," "lower," "above," "upper," and similar terms, are intended to facilitate the descriptive explanation of the position of one element relative to another. These terms are meant to encompass different orientations of the part in addition to those shown in the figures. Furthermore, terms like "first," "second," and similar terms are also used to describe various elements, areas, parts, etc., and should likewise not be considered restrictive. Throughout the description, similar terms refer to similar elements.

[0131] The terms used here, such as "exhibit," "contain," "including," "comprehensive," and similar terms, are open-ended and indicate the presence of the specified elements or characteristics, but do not exclude additional elements or characteristics. Articles such as "a," "the," etc., are intended to include both the plural and singular unless the context clearly indicates otherwise.

[0132] The present invention is limited only by the following claims.

Claims

[1] Charge compensation semiconductor device comprising: - a nominal breakdown voltage; - a semiconductor body (40) comprising a first surface (101), a border (41) limiting the semiconductor body (40) in a horizontal direction which is substantially parallel to the first surface (101), an active region (110) and a border region (120) arranged between the active region (110) and the border (41); - a source metallization (10) arranged on the first surface (101); and - a drain metallization (11) arranged opposite the source metallization (10), wherein the semiconductor body (40) further comprises in a vertical cross-section that is substantially orthogonal to the first surface (101) of the semiconductor body (40): - an intrinsic semiconductor region (2) located in the boundary region (120); - a potential equalization area (8, 11a) that is in ohmic contact with the drain metallization (11) and is located next to the edge (41) and the first surface (101): and - a plurality of first column regions (1) alternating with second column regions (6) in the active region (110) and in the edge region (120), wherein the first column regions (1) have a higher doping concentration than the intrinsic semiconductor region (2), wherein the first column regions (1) are in ohmic contact with the drain metallization (11), wherein the second column regions (6) of the active region (110) are in ohmic contact with the source metallization (10) via corresponding body regions (5, 5') with a higher doping concentration than the second column regions (6), wherein at least a plurality of the second column regions (6) of the edge region (120) are adjacent to a connection region (17) of the same conductivity type as the second column regions (6) and with a lower doping concentration than an adjacent outer of the body regions (5, 5'),wherein a corresponding pn junction is formed between each adjacent first column region (1) and second column region (6), and wherein an outer of the first column region (1) and / or an outer of the second column region (6) forms an interface (46) to the intrinsic semiconductor region (2) at a horizontal position (x0), where a voltage on the first surface (101) is at least approximately one-fifth of the nominal breakdown voltage when the nominal breakdown voltage is applied between the source metallization (10) and the drain metallization (11), wherein a horizontal distance between the interface (46) and the equipotential bonding region (8) divided by a horizontal distance between the source metallization (10) and the interface (46) is in a range of approximately 0.2 to approximately 5, and wherein the equipotential bonding region (8) is a field plate (11a) arranged on the first surface (101) and / or a field stop region (8),which borders the intrinsic semiconductor region (2) and has a higher average concentration of dopants of the first conductivity type than the intrinsic semiconductor region (2). [2] Charge compensation semiconductor device according to claim 1, wherein the interface (46) is formed at a horizontal position (x0) where the voltage at the first surface (101) is at least approximately one-third of the nominal breakdown voltage when the nominal breakdown voltage is applied between the source metallization (10) and the drain metallization (11); or wherein the interface (46) is formed at a horizontal position (x0) where the voltage at the first surface (101) is lower than approximately four-fifths of the nominal breakdown voltage when the nominal breakdown voltage is applied between the source metallization (10) and the drain metallization (11). [3] Charge compensation semiconductor device according to claim 1 or 2, wherein the edge region (120) comprises an outer section (120b) which has neither first column regions (1) nor second column regions (6) and an inner section (120a) which is arranged between the active region (110) and the outer section (120b), and wherein a boundary between the inner section (120a) and the outer section (120b) of the edge region (120) in a corner region of the edge region (120) which is adjacent to two adjacent vertical sides of the edge (41) is substantially parallel to one of the two vertical sides or forms an angle of approximately 60°, 45° or 30° with the edge (41). [4] Charge compensation semiconductor device according to claim 3, wherein the doping concentration of the first column regions (1) in the inner section (120a) of the edge region (120) is lower compared to the active region (110), and / or wherein the doping concentration of the second column regions (6) in the inner section (120a) of the edge region (120) is lower compared to the active region (110). [5] Charge compensation semiconductor device according to one of claims 1 to 4, wherein a horizontal distance (d1) between the edge (41) and the interface (46) divided by a horizontal distance (d3) between the source metallization (10) and the interface (46) is in a range of approximately 0.1 to approximately 0.

9. [6] Charge compensation semiconductor component according to claims 1 to 5, further comprising: - a drain region (4) adjacent to the drain metallization (11) on a second surface of the semiconductor body (40), in ohmic contact with the first column regions (1) and having a higher doping concentration than the first column regions (1), and a potential equalization region (8) in ohmic contact with the drain metallization (11) and located next to the edge (41) and the first surface (101), wherein a horizontal distance between the interface (46) and the potential equalization region (8) divided by a vertical distance between the first surface (101) and the drain region (4) is in the range of approximately 0.5 to approximately 3. [7] Charge compensation semiconductor component according to one of claims 1 to 6, wherein the connection area (17) extends at least to near the field stop region (8). [8] Charge compensation semiconductor device according to any one of claims 1 to 7, wherein the doping concentration of the first column regions (1) is at least approximately ten times the doping concentration of the intrinsic semiconductor region (2). [9] Charge compensation semiconductor component according to any one of claims 1 to 8, wherein at least one of the second column regions (6) in the edge region (120) extends substantially to the same depth as the second column regions (6) in the active region (110). [10] Charge compensation semiconductor component according to one of claims 1 to 9, wherein a vertical extent of at least one of the second column regions (6) in the edge region (120) is lower than a vertical extent of the second column regions (6) in the active region (110). [11] Charge compensation semiconductor component according to one of claims 1 to 10 wherein a doping concentration of at least one of the second column regions (6) in the boundary region (120) differs from a doping concentration of the second column regions (6) in the active region (110). [12] Charge compensation semiconductor device according to any one of claims 1 to 11, further comprising a depletable semiconductor region (18) arranged between the interconnection region (17) and the first surface (101), forming a pn junction with the interconnection region (17) and having a higher doping concentration than the intrinsic semiconductor region (2). [13] Charge compensation semiconductor device comprising: - a semiconductor body (40) comprising a first surface (101), a second surface (102) opposite the first surface (101), a border (41) limiting the semiconductor body (40) in a horizontal direction substantially parallel to the first surface (101), a drain region (4) of a first conductivity type extending to the second surface (102), an active region (110) and a border region (120) arranged between the active region (110) and the border (41); - a source metallization (10) arranged on the first surface (101); and - a drain metallization (11) arranged on the drain region (4) and in ohmic contact with the drain region (4), wherein the charge compensation semiconductor component further comprises in a vertical cross-section that is substantially orthogonal to the first surface (101): - a potential equalization area (8, 11a) that is in ohmic contact with the drain metallization (11) and is located in the boundary region (120) and adjacent to the first surface (101); - a low-doped semiconductor region (2) located in the edge region (120) and having a first concentration of dopants; and - a plurality of first column regions (1) alternating with second column regions (6) in the active region (110) and in the edge region (120), wherein the first column regions (1) have a second concentration of dopants of the first conductivity type that is higher than the first concentration of dopants, wherein the first column regions (1) are in ohmic contact with the drain region (4), wherein the second column regions (6) have a second conductivity type and are in ohmic contact with the source metallization (10), wherein an outer of the first column regions (1) and / or an outer of the second column regions (6) forms an interface (46) to the low-doped semiconductor region (2), and wherein a horizontal distance (d2) between the interface (46) and the potential equalization region (8) divided by a vertical distance (d4) between the first surface (101) and the drain region (4) is in a range of approximately 0.5 to approximately 3,further comprising a first depletable interconnect (17) of the second conductivity type, which connects at least the majority of the second pillar regions (6) of the boundary region (120), a further depletable semiconductor region (18) of the first conductivity type, which has a higher concentration of dopants than the first concentration of dopants and which is arranged between the depletable interconnect (17) and the first surface (101), and / or a plurality of body regions (5, 5') of the second conductivity type, wherein each of the body regions (5, 5') in the active region (110) has a higher doping concentration than adjacent second pillar regions (6) and an outer body region (5, 5') has a higher doping concentration than the adjacent depletable interconnect (17). [14] Charge compensation semiconductor component according to claim 13, wherein the potential equalization region comprises a field plate (11a) arranged on the first surface (101), a field stop region (8) of the first conductivity type adjacent to the low-doped semiconductor region (2) and having a higher concentration of dopants than the first concentration of dopants, and / or a polysilicon region arranged between the field plate and the field stop region. [15] Charge compensation semiconductor device according to claims 13 and 14, wherein the low-doped semiconductor region (2) has a maximum doping concentration of less than approximately 10 15 cm -3 exhibits. [16] Charge compensation semiconductor device according to one of claims 13 to 15, wherein the interface (46) is formed at a horizontal position (x0) where a voltage on the first surface (101) is at least approximately one fifth of a nominal breakdown voltage of the charge compensation semiconductor device when the nominal breakdown voltage is applied between the source metallization (10) and the drain metallization (11). [17] Charge compensation semiconductor device comprising: - a nominal breakdown voltage; - a semiconductor body (40) comprising a first surface (101), a border (41) limiting the semiconductor body (40) in a horizontal direction which is substantially parallel to the first surface (101), an active region (110) and a border region (120) arranged between the active region (110) and the border (41); - a source metallization (10) arranged on the first surface (101); and - a drain metallization (11) arranged opposite the source metallization (10), wherein the semiconductor body (40) further comprises in a vertical cross-section that is substantially orthogonal to the first surface (101) of the semiconductor body (40): - an intrinsic semiconductor region (2) located in the boundary region (120); and - a plurality of first column regions (1) alternating with second column regions (6) in the active region (110) and in the edge region (120), wherein the first column regions (1) have a higher doping concentration than the intrinsic semiconductor region (2), wherein the first column regions (1) are in ohmic contact with the drain metallization (11), wherein the second column regions (6) of the active region (110) are in ohmic contact with the source metallization (10) via corresponding body regions (5, 5') with a higher doping concentration than the second column regions (6), wherein at least a plurality of the second column regions (6) of the edge region (120) are adjacent to a connection region (17) of the same conductivity type as the second column regions (6) and with a lower doping concentration than an adjacent outer of the body regions (5, 5'),wherein a corresponding pn junction is formed between each adjacent first column region (1) and second column region (6), and wherein an outer of the first column region (1) and / or an outer of the second column region (6) forms an interface (46) with the intrinsic semiconductor region (2) at a horizontal position (x0), where a voltage on the first surface (101) is at least approximately one-fifth of the nominal breakdown voltage when the nominal breakdown voltage is applied between the source metallization (10) and the drain metallization (11), and wherein a depletable semiconductor region (18) located between the junction region (17) and the first surface (101) forms a pn junction with the junction region (17) and has a higher doping concentration than the intrinsic semiconductor region (2).

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