Semiconductor device and method of forming the same

Abstract

Methods of forming a semiconductor device having an epitaxial structure of optimized dimensions are described. The methods include forming a first fin structure and a second fin structure on a substrate; forming a spacer layer on the first fin structure and the second fin structure; forming a first spacer structure adjacent to the first fin structure; and forming a first epitaxial structure adjacent to the first spacer structure. The first fin structure and the second fin structure are separated by an isolation layer. The first spacer structure has a first height above the isolation layer. The methods also include forming a second spacer structure adjacent to the second fin structure and forming a second epitaxial structure adjacent to the second spacer structure. The second spacer structure has a second height above the isolation layer that is greater than the first height. The second epitaxial structure includes a different type of dopant than the first epitaxial structure. Embodiments of the present application also relate to semiconductor devices.

Description

Technical Field

[0001] Some embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] With advancements in semiconductor technology, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs is increasing. To meet these demands, the semiconductor industry is continuously shrinking the size of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), including planar MOSFETs and fin field-effect transistors (FINFETs). This shrinkage increases the complexity of semiconductor manufacturing processes. Summary of the Invention

[0003] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a first fin structure and a second fin structure on a substrate, wherein the first fin structure and the second fin structure are separated by an isolation layer; forming a spacer layer on the first fin structure and the second fin structure; forming a first spacer structure adjacent to the first fin structure, wherein the first spacer structure has a first height above the isolation layer; forming a first epitaxial structure adjacent to the first spacer structure on the first fin structure, wherein the first epitaxial structure includes a first type of dopant; forming a second spacer structure adjacent to the second fin structure, wherein the second spacer structure has a second height above the isolation layer that is greater than the first height; and forming a second epitaxial structure adjacent to the second spacer structure on the second fin structure, wherein the second epitaxial structure includes a second type of dopant different from the first type of dopant.

[0004] Other embodiments of this application provide a method for forming a semiconductor device, comprising: forming a first fin structure and a second fin structure on a substrate, wherein the first fin structure and the second fin structure are separated by an isolation layer; forming a gate structure on the first fin structure and the second fin structure; forming a spacer layer on the first fin structure, the second fin structure, the isolation layer, and the gate structure; forming a first pair of spacer structures on opposite sidewalls of the first fin structure, wherein the first pair of spacer structures has a first height above the isolation layer; forming a first epitaxial structure on the first fin structure and between the first pair of spacer structures, wherein the first epitaxial structure includes a first type of dopant; forming a second pair of spacer structures on opposite sidewalls of the second fin structure, wherein the second pair of spacer structures has a second height above the isolation layer that is greater than the first height; and forming a second epitaxial structure on the second fin structure and between the second pair of spacer structures, wherein the second epitaxial structure includes a second type of dopant different from the first type of dopant.

[0005] Further embodiments of this application provide a semiconductor device including: a first fin structure and a second fin structure located on a substrate; an isolation layer located between the first fin structure and the second fin structure; a first epitaxial structure and a second epitaxial structure, the first epitaxial structure being located on the first fin structure and the second epitaxial structure being located on the second fin structure, wherein the first epitaxial structure includes a first type of dopant and the second epitaxial structure includes a second type of dopant different from the first type of dopant; and a first spacer structure and a second spacer structure, the first spacer structure being adjacent to the first epitaxial structure and having a first height above the isolation layer, and the second spacer structure being adjacent to the second epitaxial structure and having a second height above the isolation layer, wherein the first height is smaller than the second height. Attached Figure Description

[0006] Various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings.

[0007] Figure 1 An isometric view of a semiconductor device with a source / drain (S / D) epitaxial structure having optimized dimensions according to some embodiments is shown.

[0008] Figures 2 to 4 A partial cross-sectional view of a semiconductor device with an optimized S / D epitaxial structure according to some embodiments is shown.

[0009] Figure 5 This is a flowchart of a method for manufacturing a semiconductor device with an optimized S / D epitaxial structure, according to some embodiments.

[0010] Figure 6 , Figures 8 to 15 and Figures 17 to 24 Isometric views and cross-sectional views of a semiconductor device with an optimized source / drain (S / D) epitaxial structure according to some embodiments are shown at various stages of its fabrication.

[0011] Figure 7 and Figure 16 The relationship between process temperature and process time during the fabrication of a semiconductor device with an optimized S / D epitaxial structure according to some embodiments is illustrated.

[0012] Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, the same reference numerals generally indicate the same, functionally identical, and / or structurally identical elements. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. As used herein, forming a first component on a second component means forming a first component in direct contact with the second component. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition, in itself, does not indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0015] It should be noted that references to "an embodiment," "embodiment," "exemplary embodiment," "exemplary," etc., in the specification indicate that the described embodiment may include specific features, structures, or characteristics, but not every embodiment necessarily includes specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0016] It should be understood that the wording or terminology used herein is for descriptive purposes and not for limitation, and that the terminology or terminology used herein shall be interpreted by those skilled in the art in light of the teachings herein.

[0017] In some embodiments, the terms "about" and "substantially" may refer to a given amount of value that varies within 20% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±20% of the value). These values ​​are merely examples and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of the value as interpreted by one of skill in the art in accordance with the teachings herein.

[0018] The scaling down of FET devices introduces a short-channel effect (SCE), which can reduce the off-state current and device performance. The profile of the source / drain (S / D) epitaxial structure on a FET device can affect SCE, device performance, and process yield. Larger S / D epitaxial structures can reduce contact resistance between the S / D epitaxial structure and the contact structure, thus improving device performance. However, larger S / D epitaxial structures may form more epitaxial defects, such as bridging defects between adjacent S / D epitaxial structures. These defects can degrade device performance and process yield. Furthermore, n-type and p-type S / D epitaxial structures can have different shapes, such as the tapered shape of n-type S / D epitaxial structures and the rhomboid shape of p-type S / D epitaxial structures. For n-type and p-type S / D epitaxial structures with the same process conditions, it may not be possible to achieve larger sizes.

[0019] Various embodiments of the present invention provide exemplary methods for forming S / D epitaxial structures with optimized dimensions in field-effect transistor (FET) devices (e.g., finFET, full-to-the-loop FET, MOSFET, etc.) and / or other semiconductor devices in integrated circuits (ICs), as well as exemplary semiconductor devices fabricated using the same methods. The exemplary methods of the present invention may form spacer layers on a first fin structure and a second fin structure. The first fin structure and the second fin structure may be separated by an isolation layer, and the first fin structure and the second fin structure may have a first height above the isolation layer. In some embodiments, the spacer layer may include a first dielectric material layer and a second dielectric material layer different from the first dielectric material. The spacer layer and the first fin structure on the first fin structure may be selectively removed to form a first spacer structure adjacent to the sidewalls of the first fin structure. The first spacer structure may have a second height above the isolation layer. The ratio of the second height to the first height may be in the range of about 5% to about 45%. A first epitaxial structure with an optimized tapered shape may be formed on the first fin structure and between the first spacer structures. The first epitaxial structure may have a first width, and the ratio of the first width to the first height may be in the range of about 55% to about 95%. The spacer layer and the second fin structure can be selectively removed to form a second spacer structure adjacent to the sidewall of the second fin structure. The second spacer structure may have a third height greater than the second height above the isolation layer. The ratio of the second height to the third height may be in the range of about 40% to about 95%. A second epitaxial structure with an optimized rhomboid shape can be formed on the second fin structure and between the second spacer structures. The second epitaxial structure may have a second width, and the ratio of the second width to the first height may be in the range of about 55% to about 95%. The second epitaxial structure may have a dopant of a different type than the first epitaxial structure. By controlling the dimensions and profiles of the first and second spacer structures, as well as the growth processes of the first and second epitaxial structures, the first and second epitaxial structures can have optimized dimensions and profiles to reduce SCE, reduce epitaxial defects, improve device performance, and improve process yield. In some embodiments, a semiconductor device with an S / D epitaxial structure of optimized dimensions can improve process yield by about 2% to about 20% and improve device performance by about 2% to about 10%.

[0020] Although this invention describes the formation of S / D epitaxial structures with optimized dimensions on finFETs, the S / D epitaxial structures with optimized dimensions and the methods for forming S / D epitaxial structures with optimized dimensions described herein can be applied to other FETs and other semiconductor devices, such as gate all-around (GAA) FETs and MOSFETs.

[0021] Figure 1Isometric views of a semiconductor device 100 having S / D epitaxial structures 110A and 110B (collectively, “S / D epitaxial structure 110”) with optimized dimensions according to some embodiments are shown. Figure 2 The following are shown according to some embodiments. Figure 1 A partial cross-sectional view of the semiconductor device 100 with line AA in the figure. Figure 3 The following are shown according to some embodiments. Figure 1 A partial cross-sectional view of the semiconductor device 100 with line BB in the figure. Figure 4 The following are shown according to some embodiments. Figure 1 A partial cross-sectional view of the semiconductor device 100 with line CC in the figure.

[0022] refer to Figures 1 to 4 A semiconductor device 100 having finFETs 105A-105B can be formed on a substrate 102 and may include a fin structure 108, a shallow trench isolation (STI) region 106, a gate spacer 116, a gate structure 118, an S / D epitaxial structure 110, and a spacer layer 120. In some embodiments, finFET 105A may be an n-type finFET (NFET) and have an n-type S / D epitaxial structure 110A. FinFET 105B may be a p-type finFET (PFET) and have a p-type S / D epitaxial structure 110B. In some embodiments, finFETs 105A-105B may all be NFETs. In some embodiments, finFETs 105A-105B may all be PFETs. Although... Figure 1 Two finFETs are shown, but semiconductor device 100 can have any number of finFETs. Furthermore, semiconductor device 100 can be incorporated into an integrated circuit (IC) using other structural components such as S / D contact structures, gate contacts, conductive vias, wires, dielectric layers, passivation layers, interconnects, etc., which are not shown for simplicity. The discussion of the components of finFETs 105A-105B with the same annotations applies to each other unless otherwise stated.

[0023] Substrate 102 may include a semiconductor material, such as silicon. In some embodiments, substrate 102 includes a crystalline silicon substrate (e.g., a wafer). In some embodiments, substrate 102 includes: (i) an elemental semiconductor, such as germanium; (ii) a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; (iii) an alloy semiconductor, including silicon germanium carbide, silicon germanium, gallium arsenide phosphide, gallium indium phosphide, gallium indium arsenide, gallium indium arsenide phosphide, aluminum indium arsenide, and / or aluminum gallium arsenide; or (iv) a combination thereof. Furthermore, substrate 102 may be doped, depending on design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, substrate 102 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic).

[0024] The fin structure 108 can be formed from a patterned portion of the substrate 102. Embodiments of the fin structures disclosed herein can be patterned using any suitable method. For example, the fin structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Dual-patterning or multi-patterning processes can combine photolithography and self-alignment processes to form patterns having, for example, a spacing smaller than that achievable using a single, direct photolithography process. For example, a sacrificial layer is formed over the substrate and patterned using a photolithography process. Spacers can be formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structure.

[0025] like Figures 1 to 4 As shown, the fin structure 108 can be disposed below the S / D epitaxial structure 110 and the gate structure 118, and can extend along the X-axis through the gate structure 118. Figures 2 to 4 As shown, fin structures 108 may have a fin height 108h along the Z-axis above the STI region 106, and adjacent fin structures 108 may have a fin spacing 108s along the Y-axis. In some embodiments, the fin spacing 108s between adjacent n-type fin structures 108 may be in the range of about 30 nm to about 60 nm. In some embodiments, the fin spacing 108s between adjacent p-type fin structures 108 may be in the range of about 25 nm to about 50 nm. In some embodiments, the fin spacing 108s between adjacent n-type and p-type fin structures 108 may be in the range of about 30 nm to about 55 nm. In some embodiments, the ratio between the fin spacing 108s and the fin height 108h may be in the range of about 40% to about 90%.

[0026] The fin structure 108 located below the gate structure 118 can form a channel region of the semiconductor device 100 and represent the current-carrying structure of the semiconductor device 100. In some embodiments, an S / D epitaxial structure 110 can be formed on a partially recessed fin region on the substrate 102. These partially recessed fin regions can be the recessed portions of the fin structure 108 that are not located below the gate structure 118. In some embodiments, the removed fin portions 108* of the fin structure 108 can be... Figure 4 The dashed box indicates this. The top surface of these partially recessed fin regions can form an interface 121 with the S / D epitaxial structure 110. In some embodiments, the interface 121 can be coplanar with the surface 106s of the STI region 106, such as... Figure 1 and Figure 4 As shown in the figure. In some embodiments, interface 121 may be located below surface 106s of STI region 106. In some embodiments, interface 121 may be located above surface 106s of STI region 106. The bottom surface of the recessed portions of these portions of fin structure 108 may form an interface (not shown) with substrate 102, and these interfaces may be located above or below the interface level between STI region 106 and substrate 102.

[0027] STI region 106 can provide electrical isolation between fin structure 108 and adjacent fin structures, and provides electrical isolation between semiconductor device 100 and adjacent structures integrated with or deposited on substrate 102. STI region 106 may have a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric materials, and other suitable insulating materials. In some embodiments, STI region 106 may include a multilayer structure.

[0028] refer to Figures 1 to 3 A gate structure 118 may be disposed on the fin structure 108 above the substrate 102. In some embodiments, the gate structure 118 may be formed by blanket deposition of polysilicon followed by photolithography and etching of the deposited polysilicon. In some embodiments, a protective oxide layer 112 may be disposed between the fin structure 108 and the gate structure 118. Forming the protective oxide layer 112 may include blanket deposition of an oxide material layer on the fin structure 108 followed by a high-temperature annealing process. The protective oxide layer 112 may include a suitable oxide material, such as silicon oxide. In some embodiments, the protective oxide layer 112 may protect the fin structure 108 during subsequent processing steps. Figure 2 and Figure 3 As shown, the gate structure 118 may have a gate spacing 118s along the X-axis between adjacent gate structures 118. In some embodiments, the gate spacing 118s may be in the range of about 50 nm to about 100 nm.

[0029] A hard mask layer 124 may be disposed on the gate structure 118. In some embodiments, such as Figure 2 and Figure 3 As shown, the hard mask layer 124 may include a nitride layer 222 and an oxide layer 224 for contour control of the gate structure 118. The hard mask layer 124 can protect the gate structure 118 from subsequent processing steps (e.g., during the formation of the gate spacer 116 and / or the S / D epitaxial structure 110).

[0030] Gate spacer 116 may be disposed on the sidewall of gate structure 118. Gate spacer 116 may include insulating materials such as silicon oxide, silicon nitride, low-k materials, and combinations thereof. Gate spacer 116 may be a low-k material with a dielectric constant less than about 3.9. In some embodiments, gate spacer 116 may protect gate structure 118 during subsequent processing steps (e.g., during the formation of S / D epitaxial structure 110).

[0031] refer to Figures 1 to 4 The spacer layer 120 may be disposed on the sidewall of the gate structure 118 and in contact with the gate spacer layer 116, disposed on the STI region 106 as a protective layer, and disposed on the sidewall of the fin structure 108. The spacer layer 120 may include an insulating material, such as silicon oxide, silicon nitride, silicon carbonitride, low-k materials, and combinations thereof. The spacer layer 120 may be a low-k material with a dielectric constant less than about 3.9. In some embodiments, the spacer layer 120 may have a thickness in the range of about 2 nm to about 10 nm. In some embodiments, the spacer layer 120 may include a stack of layers.

[0032] In some embodiments, the spacer layer 120 on the sidewall of the fin structure 108 adjacent to the n-type S / D epitaxial structure 110A can be referred to as "spacer structure 120A", such as Figure 4 As shown in the diagram, the spacer structure 120A may include a dielectric layer 120A-1 in contact with the n-type S / D epitaxial structure 110A and a dielectric layer 120A-2 on the dielectric layer 120A-1. The spacer layer 120 on the sidewall of the fin structure 108 adjacent to the p-type S / D epitaxial structure 110B may be referred to as "spacer structure 120B", as shown in the diagram. Figure 4As shown in the diagram. Spacer structure 120B may include dielectric layer 120B-1 and dielectric layer 120B-2 on dielectric layer 120B-1 in contact with p-type S / D epitaxial structure 110B. In some embodiments, dielectric layers 120A-1 and 120B-1 may include a first dielectric material, such as silicon nitride. Dielectric layers 120A-2 and 120B-2 may include a second dielectric material different from the first dielectric material, such as silicon carbonitride. In some embodiments, the size and profile of spacer structures 120A and 120B may be affected by different dielectric materials and etch rates of the dielectric materials in the stack of dielectric layers. In some embodiments, dielectric layer 120A-1 may have the same height as dielectric layer 120A-2 above STI region 106. Similarly, dielectric layer 120B-1 may have the same height as dielectric layer 120B-2 above STI region 106. Because of the same height, the S / D epitaxial structures 110A and 110B can have symmetrical profiles on the fin structure 108, which can reduce epitaxial defects such as bridging defects.

[0033] In some embodiments, spacer structure 120A may have a vertical dimension 120Ah (e.g., height) along the Z-axis above STI region 106 in the range of about 5 nm to about 15 nm. Spacer structure 120B may have a vertical dimension 120Bh (e.g., height) along the Z-axis above STI region 106 in the range of about 5 nm to about 15 nm. The ratio of vertical dimension 120Ah or 120Bh to fin height 108h may be in the range of about 5% to about 45%. If vertical dimensions 120Ah and 120Bh are less than about 5 nm, or the ratio is less than about 5%, then S / D epitaxial structures 110A and 110B may have increased epitaxial defects, such as bridging defects, and may not form the design profiles for n-type epitaxial structures (e.g., tapered shapes) and p-type epitaxial structures (e.g., rhomboid shapes). If the vertical dimensions 120Ah and 120Bh are greater than about 15 nm, or the ratio is greater than about 45%, the S / D epitaxial structures 110A and 110B can have smaller dimensions, such as smaller volume and width, and may not improve device performance. In some embodiments, the vertical dimension 120Bh can be larger than the vertical dimension 120Ah. The ratio of the vertical dimension 120Ah to the vertical dimension 120Bh can range from about 40% to about 95%. If the ratio is less than about 40%, the p-type S / D epitaxial structure 110B may have increased epitaxial defects and may not form a design profile (e.g., a diamond shape). If the ratio is greater than about 95%, the n-type S / D epitaxial structure 110A may not have an optimized volume and may not improve device performance.

[0034] refer to Figures 1 to 4The S / D epitaxial structure 110 may be formed on a partially recessed portion of the fin structure 108 and disposed on the opposite side of the gate structure 118. The S / D epitaxial structure 110 may serve as the source / drain (S / D) region of the semiconductor device 100 and may include epitaxially grown semiconductor material. In some embodiments, the epitaxially grown semiconductor material may include the same material as the substrate 102. In some embodiments, the epitaxially grown semiconductor material may include a material different from the substrate 102 and strain is applied to the channel region located below the gate structure 118. Because the lattice constant of this epitaxially grown semiconductor material is different from that of the substrate 102, the channel region is strained to advantageously increase the carrier mobility in the channel region of the semiconductor device 100. The epitaxially grown semiconductor material may include: (i) semiconductor materials, such as germanium and silicon; (ii) compound semiconductor materials, such as gallium arsenide, aluminum gallium arsenide, etc.; or (iii) semiconductor alloys, such as silicon germanium and gallium arsenide phosphide.

[0035] In some embodiments, the S / D epitaxial structure 110 can be epitaxially grown by: (i) chemical vapor deposition (CVD), such as low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), and any suitable CVD; (ii) molecular beam epitaxy (MBE) process; (iii) any suitable epitaxial process; or (iv) a combination thereof. In some embodiments, the S / D epitaxial structure 110 can be grown by an epitaxial deposition / partial etching process that repeats the epitaxial deposition / partial etching process at least once. Such repeated deposition / partial etching process may be referred to as a cyclic deposition-etch (CDE) process. The CDE process can reduce epitaxial defects formed during growth and can control the profile of the S / D epitaxial structure 110. In some embodiments, the S / D epitaxial structure 110 may include multiple epitaxial layers and may be doped in situ with n-type or p-type dopants during the epitaxial growth process.

[0036] refer to Figure 1 , Figure 2 and Figure 4 The n-type S / D epitaxial structure 110A may include Si and may be in-situ doped with n-type dopants (such as phosphorus (P) and arsenic (As)) during the epitaxial growth process. For n-type in-situ doping, n-type doping precursors such as phosphine (PH3), arsine (AsH3), and other n-type doping precursors may be used. Each of the n-type S / D epitaxial structures 110A may include an epitaxially grown n-type first epitaxial layer 207A, a second epitaxial layer 209A, and a third epitaxial layer 211A, as shown below. Figure 2 and Figure 4As shown in the diagram. A first epitaxial layer 207A can be epitaxially grown on a partially recessed portion of the fin structure 108, a second epitaxial layer 209A can be epitaxially grown on the first epitaxial layer 207A, and a third epitaxial layer 211A can be epitaxially grown on the second epitaxial layer 209A. Although Figures 1 to 4 Three epitaxial layers for an n-type S / D epitaxial structure 110A are shown, but the n-type S / D epitaxial structure 110A may have one or more epitaxial layers and each epitaxial layer may have a different composition.

[0037] In some embodiments, each of the n-type first epitaxial layer 207A, second epitaxial layer 209A, and third epitaxial layer 211A may comprise Si and differ from each other based on, for example, doping concentration and / or epitaxial growth process conditions. For example, the first epitaxial layer 207A may be undoped or may have a doping concentration lower than that of the second epitaxial layer 209A and the third epitaxial layer 211A. The third epitaxial layer 211A may have a doping concentration lower than that of the second epitaxial layer 209A. In some embodiments, the first epitaxial layer 207A may be doped with a doping concentration from about 5 × 10⁻⁶. 20 atoms / cm 3 Approximately 2×10 21 atoms / cm 3 The second epitaxial layer 209A may be doped with arsenic at a concentration ranging from approximately 2 × 10⁻⁶. 21 atoms / cm 3 Approximately 5×10 21 atoms / cm 3 The higher dopant concentration in the second epitaxial layer 209A can reduce the contact resistance between the S / D epitaxial structure 110 and the S / D contact structure (not shown). The third epitaxial layer 211A can be doped with phosphorus of a concentration ranging from approximately 1 × 10⁻⁶. 21 atoms / cm 3 Approximately 2×10 21 atoms / cm 3 Phosphorus concentration.

[0038] In some embodiments, the first epitaxial layer 207A can serve as a shielding layer and prevent dopant diffusion into the channel region of the semiconductor device 100, which can mitigate SCE and improve device performance. In some embodiments, the top surface of the first epitaxial layer 207A can be located about 5 nm to about 15 nm below the top surface of the fin structure 108 along the Z-axis to allow the S / D contact structure to fall on the second epitaxial layer 209A and avoid dopant loss and increased contact resistance. In some embodiments, the top surface of the first epitaxial layer 207A can have a distance 110Ad from the top surface of the fin structure 108. The ratio of the distance 110Ad to the fin height 108h can be in the range of about 5% to about 15% to avoid dopant loss and increased contact resistance. In some embodiments, the third epitaxial layer 211A can serve as a capping layer to protect the second epitaxial layer 209A and prevent dopant in the second epitaxial layer 209A from diffusing outward.

[0039] In some embodiments, such as Figure 4 As shown, the n-type S / D epitaxial structure 110A can have a tapered shape and can have a top surface along the Z-axis from the fin structure 108 (e.g., by...). Figure 4 The dashed box indicates the height 110Ah of the removed fin portion 108*) to the top surface of the n-type S / D epitaxial structure 110A. The height 110Ah can range from about 1 nm to about 10 nm. In some embodiments, the n-type S / D epitaxial structure 110A can have a horizontal dimension 110Aw (e.g., width) along the Y-axis ranging from about 25 nm to about 40 nm. The ratio of the horizontal dimension 110Aw to the fin height 108h can range from about 55% to about 95%. If the height 110Ah is less than about 1 nm, the horizontal dimension 110Aw is less than about 25 nm, or the ratio is less than about 55%, the volume of the n-type S / D epitaxial structure 110A may decrease and the resistance of the n-type S / D epitaxial structure 110A may increase. If the height 110Ah is greater than about 10 nm, the horizontal dimension 110Aw is greater than about 40 nm, or the ratio is greater than about 95%, then the n-type S / D epitaxial structure 110A may have increased bridging defects along the Y-axis and may short-circuit with adjacent structures.

[0040] like Figure 1 , Figure 3 , Figure 4As shown, the p-type S / D epitaxial structure 110B may include Si, SiGe, Ge, or III-V materials (e.g., indium antimonide (InSb), gallium antimonide (GaSb), or indium gallium antimonide (InGaSb)) and may be in-situ doped with p-type dopants (such as boron, indium, and gallium) during the epitaxial growth process. For p-type in-situ doping, p-type doping precursors such as diborane (B2H6), boron trifluoride (BF3), and other p-type doping precursors may be used. Each of the p-type S / D epitaxial structures 110B may include an epitaxially grown p-type first epitaxial layer 207B, a second epitaxial layer 209B, and a third epitaxial layer 211B, as shown. Figure 3 and Figure 4 As shown in the diagram. A first epitaxial layer 207B can be grown on a partially recessed portion of the fin structure 108, a second epitaxial layer 209B can be grown on the first epitaxial layer 207B, and a third epitaxial layer 211B can be grown on the second epitaxial layer 209B. In some embodiments, the first epitaxial layer 207B may further include a first seed layer 207B-1, a second seed layer 207B-2, and an epitaxial layer 207B-3. The first seed layer 207B-1 and the second seed layer 207B-2 can serve as substrate layers for the epitaxial growth of the epitaxial layer 207B-3. In some embodiments, the first seed layer 207B-1 may include Si, and the second seed layer 207B-2 may include SiGe.

[0041] In some embodiments, each of the p-type first epitaxial layer 207B, second epitaxial layer 209B, and third epitaxial layer 211B may comprise SiGe and differ from each other based on, for example, doping concentration, epitaxial growth process conditions, and / or the relative concentration of Ge to Si. For example, the atomic percentage of Ge in the first epitaxial layer 207B may be less than the atomic percentage of Ge in the second epitaxial layer 209B and the third epitaxial layer 211B. In some embodiments, the first epitaxial layer 207B may comprise Ge in the range of about 20 atomic percentages to about 45 atomic percentages, with any remaining atomic percentage being Si. In some embodiments, the second seed layer 207B-2 may comprise Ge in the range of about 20 atomic percentages to about 40 atomic percentages, and the epitaxial layer 207B-3 may comprise Ge in the range of about 30 atomic percentages to about 45 atomic percentages, with any remaining atomic percentage being Si. The second epitaxial layer 209B may include Ge in the range of about 35 atomic percent to about 65 atomic percent, and the third epitaxial layer 211B may include Ge in the range of about 45 atomic percent to about 55 atomic percent, with any remaining atomic percent being Si.

[0042] p-type epitaxial layers can have different dopant concentrations than each other. For example, the first epitaxial layer 207B can have a lower dopant concentration than the second epitaxial layer 209B and the third epitaxial layer 211B. The second epitaxial layer 209B can have a higher dopant concentration than the third epitaxial layer 211B. In some embodiments, the first epitaxial layer 207B can be doped with approximately 1 × 10⁻⁶ dopant. 20 To approximately 1×10 21 atoms / cm 3 The second epitaxial layer 209B can be doped with boron at a concentration of approximately 1 × 10⁻⁶. 21 Approximately 2×10 21 atoms / cm 3 The boron concentration is within a certain range. A higher dopant concentration in the second epitaxial layer 209B can reduce the contact resistance between the S / D epitaxial structure 110 and the S / D contact structure (not shown). The third epitaxial layer 211B can be doped with boron having a concentration of approximately 5 × 10⁻⁶. 20 To approximately 1.5 × 10 21 atoms / cm 3 Boron concentrations within a certain range.

[0043] In some embodiments, similar to the first epitaxial layer 207A, the first epitaxial layer 207B can serve as a shielding layer and prevent dopant diffusion into the channel region of the semiconductor device 100. In some embodiments, the top surface of the first epitaxial layer 207B can be located about 5 nm to about 15 nm below the top surface of the fin structure 108 to allow the S / D contact structure to fall on the second epitaxial layer 209B and avoid dopant loss and increased contact resistance. In some embodiments, the top surface of the first epitaxial layer 207B can have a distance of 110Bd from the top surface of the fin structure 108. The ratio of the distance 110Bd to the fin height 108h can be in the range of about 5% to about 15% to avoid dopant loss and increased contact resistance. In some embodiments, the third epitaxial layer 211B can serve as a capping layer to protect the second epitaxial layer 209B and prevent dopant in the second epitaxial layer 209B from diffusing outward.

[0044] In some embodiments, such as Figure 4 As shown, the p-type S / D epitaxial structure 110B can have a rhomboid shape and can have a top surface along the Z-axis from the fin structure 108 (e.g., by...). Figure 4The dashed box indicates the height 110Bh of the removed fin portion 108*) to the top surface of the p-type S / D epitaxial structure 110B. The height 110Bh can range from about 5 nm to about 15 nm. In some embodiments, the p-type S / D epitaxial structure 110B can have a horizontal dimension 110Bw (e.g., width) along the Y-axis ranging from about 20 nm to about 40 nm. The ratio of the horizontal dimension 110Bw to the fin height 108h can range from about 55% to about 95%. If the height 110Bh is less than about 5 nm, the horizontal dimension 110Bw is less than about 20 nm, or the ratio is less than about 55%, the volume of the p-type S / D epitaxial structure 110B may decrease and the resistance of the p-type S / D epitaxial structure 110B may increase. If the height 110Bh is greater than about 15 nm, the horizontal dimension 110Bw is greater than about 40 nm, or the ratio is greater than about 95%, then the p-type S / D epitaxial structure 110B may have increased bridging defects along the Y-axis and may short-circuit with adjacent structures.

[0045] In some embodiments, the height 110Bh can be greater than the height 110Ah, and the ratio of height 110Ah to height 110Bh can range from about 1% to about 20%. During the formation of the S / D contact structure, the n-type S / D epitaxial structure 110A and the p-type S / D epitaxial structure 110B can be etched in the same etching process. In some embodiments, the p-type S / D epitaxial structure 110B can have a higher etching rate than the n-type S / D epitaxial structure 110A. With a larger height 110Bh, the S / D contact structure can fall on the n-type S / D epitaxial structure 110A and the p-type S / D epitaxial structure 110B at the same level above the top surface of the substrate 102. If the ratio is less than about 1%, the S / D contact structure on the n-type S / D epitaxial structure 110A can fall deeper on the first epitaxial layer 207A and may have dopant loss, which may introduce SCE and degrade device performance. If the ratio is greater than about 20%, the S / D contact structure on the n-type S / D epitaxial structure 110A may fall shallower on the third epitaxial layer 211A and may increase the contact resistance. Furthermore, if the ratio is less than about 0.01 or greater than about 0.2, the S / D contact structure may not fall on the n-type S / D epitaxial structure 110A and the p-type S / D epitaxial structure 110B at the same level above the top surface of the substrate 102.

[0046] Figure 5This is a flowchart of a method 500 for fabricating an S / D epitaxial structure with optimized dimensions on a semiconductor device, according to some embodiments. Method 500 may not be limited to FinFET devices and can be applied to devices that would benefit from an S / D epitaxial structure with optimized dimensions, such as planar FETs, FinFETs, GAA FETs, etc. Additional fabrication operations may be performed between the various operations of method 500, and additional fabrication operations may be omitted simply for clarity and ease of description. Additional processes may be provided before, during, and / or after method 500; one or more of these additional processes are briefly described herein. Furthermore, not all operations need to implement the disclosure provided herein. Additionally, some operations may be performed simultaneously or in conjunction with... Figure 5 The different sequences of operations are shown. In some embodiments, one or more other operations may be performed in addition to or instead of the operations currently described.

[0047] For illustrative purposes, references will be made to manufacturing such as Figures 6 to 24 The exemplary manufacturing process of the semiconductor device 100 shown is described in this way. Figure 5 The operation shown is illustrated. Figure 6 An isometric view of a semiconductor device 100 prior to the formation of a source / drain (S / D) epitaxial structure with optimized dimensions, according to some embodiments, is shown. Figure 7 and Figure 16 The relationship between process temperature and process time during the manufacture of S / D epitaxial structures 110A and 110B with optimized dimensions, according to some embodiments, is shown respectively. Figures 8 to 15 and Figures 17 to 24 Cross-sectional views of a semiconductor device with an optimized source / drain (S / D) epitaxial structure according to some embodiments are shown at various stages of its fabrication. The above describes... Figure 6 , Figures 8 to 15 and Figures 17 to 24 Zhongyu Figures 1 to 4 The components in the text have the same annotations.

[0048] refer to Figure 5 Method 500 begins with operation 510 and the process of forming a first fin structure and a second fin structure on a substrate. The first fin structure and the second fin structure are separated by an isolation layer. For example, as... Figure 6As shown, fin structures 108 on finFETs 105A-105B can be formed on substrate 102. Fin structures 108 can be separated by STI regions 106. Fin structures 108 can be formed from patterned portions of substrate 102. Fin structures 108 can have a fin height 108h along the Z-axis above the STI regions 106, and adjacent fin structures 108 can have a fin spacing 108s along the Y-axis. In some embodiments, the fin height 108h of fin structures 108 can be in the range of about 40 nm to about 60 nm. In some embodiments, the fin spacing 108s between adjacent n-type fin structures 108 can be in the range of about 30 nm to about 60 nm. In some embodiments, the fin spacing 108s between adjacent p-type fin structures 108 can be in the range of about 25 nm to about 50 nm. In some embodiments, the fin spacing 108s between adjacent n-type and p-type fin structures 108 can be in the range of about 30 nm to about 55 nm. In some embodiments, the ratio between the fin spacing 108s and the fin height 108h can be in the range of about 40% to about 90%.

[0049] Forming the fin structure 108 may then involve forming a gate structure 118 on the fin structure 108, forming a hard mask layer 124 on the gate structure 118, and forming gate spacers on the sidewalls of the gate structure 118, such as... Figure 6 As shown in the figure. In some embodiments, a protective oxide layer 112 may be formed on the fin structure 108 to protect the fin structure 108 during the formation of the gate structure 118. During subsequent processes, the protective oxide layer 112 may be removed from a region other than the channel region beneath the gate structure 118. In some embodiments, the gate structure 118 may have a gate spacing 118s along the X-axis between adjacent gate structures 118 in the range of about 50 nm to about 100 nm.

[0050] refer to Figure 5 In operation 520, a spacer layer can be formed on the first fin structure and the second fin structure. For example, as... Figure 6 As shown, spacer layer 120 can be blanket-deposited on fin structure 108, gate structure 118, and STI region 106. Spacer layer 120 may include insulating materials such as silicon oxide, silicon nitride, silicon carbonitride, low-k materials, and combinations thereof. In some embodiments, spacer layer 120 may have a thickness in the range of about 2 nm to about 10 nm. In some embodiments, spacer layer 120 may include a stack of layers. In some embodiments, forming spacer layer 120 may include: depositing a silicon nitride layer on fin structure 108; and depositing a silicon carbonitride layer on the silicon nitride layer.

[0051] refer to Figure 5In operation 530, a first spacer structure adjacent to the first fin structure can be formed. The first spacer structure has a first height above the isolation layer. For example, as... Figure 8 and Figure 9 As shown, portions of the spacer layer 120 and fin structure 108 on the finFET 105A can be selectively etched to form a pair of spacer structures 120A adjacent to the opposite sidewalls of the fin structure 108. The spacer structures 120A may include a dielectric layer 120A-1 adjacent to the fin structure 108 and a dielectric layer 120A-2 on the dielectric layer 120A-1. In some embodiments, dielectric layer 120A-1 may include silicon nitride and dielectric layer 120A-2 may include silicon carbonitride. In some embodiments, dielectric layers 120A-1 and 120A-2 may be removed at the same etch rate. Therefore, after etching, dielectric layers 120A-1 and 120A-2 may have the same vertical dimension 120Ah (e.g., height) along the Z-axis above the STI region 106 to form a symmetrical n-type S / D epitaxial structure 110A above the spacer structures 120A. In some embodiments, the spacer layers 120 on the opposing sidewalls of the fin structure 108 can be removed at the same etching rate. Therefore, after etching, a pair of spacer structures 120A adjacent to the opposing sidewalls of the fin structure 108 can be symmetrical and can have the same vertical dimension 120Ah (e.g., height) above the STI region 106 to form a symmetrical n-type S / D epitaxial structure 110A. The symmetrical n-type S / D epitaxial structure 110A can have increased dimensions without bridging defects.

[0052] In some embodiments, the spacer layer 120 and fin structure 108 on the FinFET 105A can be selectively etched using a dry etching process. In some embodiments, the dry etching process can be plasma-based and may include etching gases such as carbon tetrafluoride (CF4), sulfur dioxide (SO2), hexafluoroethane (C2F6), chlorine (Cl2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), and hydrogen bromide (HBr), as well as mixed gases such as hydrogen (H2), oxygen (O2), nitrogen (N2), and argon (Ar). The dry etching process can be performed at a temperature ranging from about 25°C to about 200°C and a pressure ranging from about 5 mTorr to about 50 mTorr. The flow rate of the etching gas can range from about 5 standard cubic centimeters (sccm) per minute to about 100 sccm per minute. The plasma power can range from about 50 W to about 200 W, and the bias voltage can range from about 30 V to about 200 V.

[0053] In some embodiments, the dry etching process can be an anisotropic etching process and can have a higher etching rate along the Z-axis than along the X-axis or Y-axis. Therefore, the spacer layer 120 on the top surface of the fin structure 108 can be removed, while portions of the spacer layer 120 on the sidewalls of the fin structure 108 can be retained. In some embodiments, the dry etching process can have a higher etching rate for the fin structure 108 compared to the spacer layer 120. The etch selectivity between the fin structure 108 and the spacer layer 120 on the finFET 105A can be in the range of about 5 to about 10. In some embodiments, the size and profile of the spacer structure 120A can be adjusted by modifying the dry etching process conditions, such as the flow rate of the etching gas and the plasma bias. In some embodiments, such as Figure 8 and Figure 9 As shown, dry etching process conditions can be optimized to remove fin structures 108 at a higher etching rate than the spacer layer 120. Therefore, after the dry etching process, the fin structures 108 above the STI region 106 can be completely removed, and a pair of spacer structures 120A with a vertical dimension 120Ah of about 5 nm to about 15 nm can be formed on the opposite sidewalls of the fin structures above the STI region 106. The ratio of the vertical dimension 120Ah to the fin height 108h can be in the range of about 5% to about 45%. If the vertical dimension 120Ah is less than about 5 nm, or the ratio is less than about 5%, the subsequently formed n-type S / D epitaxial structure 110A may have increased epitaxial defects, such as bridging defects, and may not form the design profile for an n-type epitaxial structure (e.g., a tapered shape). If the vertical dimension 120Ah is greater than about 15 nm, or the ratio is greater than about 45%, the n-type S / D epitaxial structure 110A may have smaller dimensions, such as smaller volume and width, and may not improve device performance.

[0054] In some embodiments, after dry etching of the fin structure 108, a groove 810 can be formed in the fin structure 108, and the recess depth 810r along the Z-axis can be in the range of about 40 nm to about 70 nm. The removed fin portion 108* can be made by Figure 9 The dashed box in the figure indicates that the ratio of the recess depth 810r to the fin height 108h can be in the range of approximately 90% to approximately 110%. If the recess depth 810r is less than approximately 40 nm, or the ratio is less than approximately 90%, the volume of the subsequently formed n-type S / D epitaxial structure 110A will decrease and the resistance 110A of the n-type S / D epitaxial structure may increase. If the recess depth 810r is greater than approximately 70 nm, or the ratio is greater than approximately 110%, SCE may be introduced and device performance may be degraded.

[0055] In some embodiments, the dimensions and contours of the partially recessed portions of the spacer structure 120A and the fin structure 108 affect the dimensions and contours of the subsequently formed n-type S / D epitaxial structure 110A. The process conditions of the dry etching process can be adjusted to achieve optimized dimensions and contours of the partially recessed portions of the spacer structure 120A and the fin structure 108, which controls the formation of the n-type S / D epitaxial structure 110A with optimized dimensions and contours. In some embodiments, the region defined by the gate spacing 118s and the recess depth 810r can represent the recessed volume used for filling the n-type S / D epitaxial structure 110A.

[0056] refer to Figure 5 In operation 540, a first epitaxial structure adjacent to the first spacer structure is formed on the first fin structure. The first epitaxial structure includes a first type of dopant. For example, such as... Figure 7 and Figures 10 to 15 As shown, an n-type S / D epitaxial structure 110A adjacent to the spacer structure 120A can be formed on the fin structure 108. The n-type S / D epitaxial structure 110A may include n-type dopants, such as P and As. Forming the n-type S / D epitaxial structure 110A may include: forming a first epitaxial layer 207A on a partially recessed portion of the fin structure 108; forming a second epitaxial layer 209A on the first epitaxial layer 207A; and forming a third epitaxial layer 211A on the second epitaxial layer 209A.

[0057] refer to Figure 7 Before forming the first epitaxial layer 207A, the semiconductor device 100 may be pre-cleaned using plasma of ammonia (NH3), nitrogen trifluoride (NF3), and argon (Ar) for about 80 s to about 400 s from time t0 to time t1 at a temperature ranging from about 25°C to about 250°C to remove surface residues. After the pre-cleaning process, the semiconductor device 100 may be pre-etched using an etching gas (such as hydrogen chloride (HCl) mixed with hydrogen (H2)) for about 50 s to about 150 s from time t1 to time t2 at a temperature ranging from about 600°C to about 700°C and a pressure ranging from about 10 Torr to about 100 Torr. The pre-etching process may also recess the fin structure 108 (e.g., about 5% to about 10% of the fin height 108h) and remove residual oxides and surface contaminants for subsequent epitaxial growth.

[0058] The pre-etching process can then be followed by the formation of the first epitaxial layer 207A. For example... Figure 7 As shown, the deposition process L1AD can be used to epitaxially grow the first epitaxial layer 207A (e.g., from time t2 to time t3, lasting approximately 100s to approximately 400s) from time t2 to time t3. Figure 10 and Figure 11(as shown in the diagram), followed by an etching process L1AE lasting from time t3 to time t4 for approximately 10 s to approximately 80 s. In some embodiments, the deposition process L1AD may include precursors such as dichlorosilane (DCS) or silane (SiH4) as Si precursors, AsH3 and / or PH3, HCl, and hydrogen (H2) as n-type dopant precursors. In some embodiments, the deposition process L1AD may be doped with approximately 1 × 10⁻⁶ ppm. 20 Approximately 8×10 20 atoms / cm 3 The concentration of phosphorus is specified. In some embodiments, the deposition process L1AD can be performed at a temperature of about 600°C to about 700°C and a pressure of about 10 Torr to about 600 Torr. The flow rate ratio of AsH3 to DCS can be less than about 50% to control the dopant concentration. In some embodiments, the etching process L1AE can include HCl and nitrogen (N2). In some embodiments, the etching process L1AE can be performed at a temperature of about 650°C to about 750°C and a pressure of about 10 Torr to about 500 Torr. The flow rate ratio of HCl in the deposition process L1AD to the flow rate of HCl in the etching process L1AE can be in the range of about 10% to about 30% to have a thickness of the first epitaxial layer 207A on the sidewalls of the trench 810 that is smaller than that on the bottom of the trench 810. After the deposition process L1AD and the etching process L1AE, the first epitaxial layer 207A can be conformally formed in the trench 810, such as... Figure 10 and Figure 11 As shown in the diagram, the ratio of the thickness of the first epitaxial layer 207A on the sidewall of the groove 810 to the thickness of the bottom of the groove 810 can be in the range of about 5% to about 30%. Therefore, the subsequently formed second epitaxial layer 209A can be formed within the n-type S / D epitaxial structure 110A (…). Figure 2 This allows for a larger volume and reduces the resistance of the n-type S / D epitaxial structure 110A. In some embodiments, the first epitaxial layer 207A may have a width 207Aw along the Y-axis in the range of about 10 nm to about 40 nm. In some embodiments, the top surface of the first epitaxial layer 207A may be located about 5 nm to about 15 nm below the top surface of the fin structure 108 to allow the S / D contact structure to fall within the fin structure. Figure 2 The second epitaxial layer 209A shown is used to avoid dopant loss and increased contact resistance.

[0059] The formation of the first epitaxial layer 207A can be followed by the formation of the second epitaxial layer 209A. For example... Figure 7 As shown, the deposition process L2AD can be used to epitaxially grow a second epitaxial layer 209A (e.g., from time t4 to time t5, lasting approximately 50 s to approximately 300 s). Figure 12 and Figure 13(as shown in the diagram), followed by an etching process L2AE lasting approximately 10 s to approximately 80 s from time t5 to time t6. In some embodiments, the deposition process L2AD may include precursors such as silane (SiH4) as a Si precursor, and PH3, HCl, and hydrogen (H2) as n-type dopant precursors. In some embodiments, the deposition process L2AD may be carried out at a temperature in the range of approximately 600°C to approximately 700°C and at a pressure of approximately 10 Torr to approximately 600 Torr. Using SiH4 and PH3 precursors instead of DCS and AsH3 can increase the dopant concentration of the second epitaxial layer 209A and reduce the resistance of the n-type S / D epitaxial structure 110A. Figure 2 and Figure 4 (As shown in the diagram). In the deposition process L2AD, the flow rate ratio of SiH4 to PH3 can be in the range of about 1 to about 4 to increase the dopant concentration. In some embodiments, the etching process L2AE can be performed at a temperature in the range of about 600°C to about 700°C and a pressure of about 10 Torr to about 500 Torr. In some embodiments, the etching process L2AE may include HCl and SiH4. The flow rate ratio of SiH4 to HCl can be in the range of about 20% to about 80% to slow down the etching rate of the second epitaxial layer 209A and form a highly doped second epitaxial layer 209A with a larger size. After the deposition process L2AD and the etching process L2AE, the second epitaxial layer 209A can be formed in the trench 810, as shown in the diagram. Figure 12 and Figure 13 As shown in the figure. In some embodiments, the second epitaxial layer 209A may have a width 209Aw along the Y-axis in the range of about 20 nm to about 30 nm.

[0060] The formation of the second epitaxial layer 209A can subsequently be followed by the formation of the third epitaxial layer 211A. For example... Figure 7 As shown, the deposition process L3AD can be used to epitaxially grow a third epitaxial layer 211A (e.g., from time t6 to time t7, lasting approximately 20 s to approximately 100 s). Figure 14 and Figure 15(as shown in the diagram), followed by an etching process L3AE lasting approximately 20 s to approximately 80 s from time t7 to time t8. In some embodiments, the deposition process L3AD may include precursors such as dichlorosilane (DCS) as a Si precursor, PH3, HCl, and hydrogen (H2) as n-type dopant precursors. In some embodiments, the deposition process L3AD may be performed at a temperature in the range of approximately 650°C to approximately 750°C and at a pressure of approximately 10 Torr to approximately 600 Torr. In some embodiments, the etching process L3AE may be performed at a temperature of approximately 700°C to approximately 780°C and at a pressure of approximately 5 Torr to approximately 50 Torr. In some embodiments, the etching process L3AE may include HCl and GeH4. The flow rate ratio of HCl to GeH4 may be in the range of approximately 2 to approximately 5 to increase the etching rate of the third epitaxial layer 211A and to epitaxially grow an n-type S / D epitaxial structure 110A having a desired facet (e.g., a 110 facet). Figure 4 and Figure 15 (As shown in the diagram). Furthermore, the higher temperature etching using GeH4 in etching process L3AE can improve the activity of the dopants in the third epitaxial layer 211A and reduce the contact resistance with the S / D contact structure. After deposition process L3AD and etching process L3AE, the third epitaxial layer 211A can be formed on the second epitaxial layer 209A, as shown in the diagram. Figure 14 and Figure 15 As shown in the figure. In some embodiments, the n-type S / D epitaxial structure 110A ( Figure 4 and Figure 15 The fin shown (as illustrated) can have a tapered shape and can have a horizontal dimension 110Aw (e.g., width) in the range of about 25 nm to about 40 nm along the Y-axis. The ratio of the horizontal dimension 110Aw to the fin height 108h can be in the range of about 55% to about 95%. In some embodiments, such as Figure 14 As shown, the cross-sectional area of ​​the n-type S / D epitaxial structure 110A along the X-axis can cover approximately 30% to approximately 70% of the recessed volume defined by the gate spacing 118s and the recess depth 810r. The n-type S / D epitaxial structure 110A ( Figure 4 These optimized dimensions and profiles (as shown in the figure) can reduce SCE, reduce epitaxial defects, reduce epitaxial structure resistance and contact resistance, and thus improve device performance and process yield.

[0061] In some embodiments, the temperature during deposition process L1AD can be higher than that during deposition process L2AD. The temperature during deposition process L2AD can be lower than that during deposition process L3AD. The temperature during deposition process L1AD can be similar to that during deposition process L3AD. In some embodiments, deposition processes L1AD and L2AD can each have a lower temperature than etching processes L1AE and L2AE. The temperature difference between deposition processes L1AD and L2AD and etching processes L1AE and L2AE can be in the range of about 10°C to about 20°C. Process conditions of the deposition and etching processes, such as temperature, pressure, and precursor flow rate, can be adjusted to optimize the size and profile of the n-type S / D epitaxial structure 110A.

[0062] refer to Figure 5 In operation 550, a second spacer structure adjacent to the second fin structure can be formed. The second spacer structure has a second height above the isolation layer that is greater than the first height. For example, as... Figure 17 and Figure 18 As shown, portions of the spacer layer 120 and fin structure 108 on the finFET 105B can be selectively etched to form a pair of spacer structures 120B adjacent to the opposite sidewalls of the fin structure 108. The spacer structures 120B may have a vertical dimension 120Bh (e.g., height) larger than the vertical dimension 120Ah above the STI region 106. The spacer structures 120B may include a dielectric layer 120B-1 and a dielectric layer 120B-2 on the dielectric layer 120B-1 adjacent to the fin structure 108. The dielectric layers 120B-1 and 120B-2 may each comprise the same dielectric material as the dielectric layers 120A-1 and 120A-2, respectively. The spacer structures 120B may have the same profile as the spacer structure 120A to form a symmetrical p-type S / D epitaxial structure 110B.

[0063] In some embodiments, the same dry etching process can be used to selectively etch the spacer layer 120 and fin structure 108 on the finFET 105B to form the spacer structure 120B. In some embodiments, such as Figure 17 and Figure 18 As shown, dry etching process conditions can be optimized to remove the fin structure 108 at a higher etch rate than the spacer layer 120. The etch selectivity between the fin structure 108 on the finFET 105B and the spacer layer 120 can range from about 2 to about 8. Therefore, after the dry etching process, the fin structure 108 above the STI region 106 can be completely removed, and a pair of spacer structures 120B having a vertical dimension 120Bh of about 5 nm to about 15 nm above the STI region 106 can be formed on the opposite sidewalls of the fin structure. In some embodiments, the ratio of vertical dimension 120Ah to vertical dimension 120Bh can range from about 40% to about 95%.

[0064] In some embodiments, the spacer layer 120 on the finFET 105B may have substantially the same etch rate as the spacer layer 120 on the finFET 105A, while the fin structure 108 on the finFET 105B may have a higher etch rate than the fin structure 108 on the finFET 105A. In some embodiments, the fin structure 108 on the finFET 105B may comprise a different material than the fin structure 108 on the finFET 105A, and therefore may have a higher etch rate than the fin structure 108 on the finFET 105A. For example, the fin structure 108 on the finFET 105A may comprise silicon and the fin structure 108 on the finFET 105B may comprise silicon germanium. In some embodiments, the fin structure 108 on the finFET 105B may comprise the same material as the fin structure 108 on the finFET 105A, such as silicon. The process conditions of the dry etching process can be adjusted for the fin structure 108 on the finFET 105B to have a higher etch rate than the fin structure 108 on the finFET 105A. In some embodiments, the dry etching process for the fin structure 108 on the finFET 105A and finFET 105B can be performed in different process chambers, and the process conditions of the dry etching process can be adjusted for either the finFET 105A or the finFET 105B (e.g., increasing the etching time for the finFET 105B). In some embodiments, the ratio of the etching rate of the fin structure 108 on the finFET 105B to the etching rate of the fin structure 108 on the finFET 105A can be in the range of about 2 to about 5. If the ratio is less than about 2 or greater than about 5, the ratio of the vertical dimension 120Ah to the vertical dimension 120Bh may not be in the range of about 40% to about 95%, and therefore the size and profile of the S / D epitaxial structures 110A and 110B may not be optimized.

[0065] In some embodiments, after dry etching of the fin structure 108, a groove 1710 can be formed in the fin structure 108, and the recess depth 1710r along the Z-axis can be in the range of about 40 nm to about 70 nm. The removed fin portion 108* can be made by Figure 18 The dashed box indicates this. The ratio of the recess depth 1710r to the fin height 108h can range from about 95% to about 120%. If the recess depth 1710r is less than about 40 nm, or the ratio is less than about 95%, the volume of the subsequently formed p-type S / D epitaxial structure 110B will decrease and the resistance 110B of the p-type S / D epitaxial structure may increase. If the recess depth 1710r is greater than about 70 nm, or the ratio is greater than about 120%, SCE may be introduced and device performance may be degraded.

[0066] In some embodiments, similar to the n-type S / D epitaxial structure 110A, the dimensions and contours of the partially recessed portions of the spacer structures 120B and fin structures 108 affect the dimensions and contours of the subsequently formed p-type S / D epitaxial structure 110B. The process conditions of the dry etching process can be adjusted to achieve optimized dimensions and contours of the partially recessed portions of the spacer structures 120A-120B and fin structures 108, which controls the formation of the S / D epitaxial structures 110A-110B with optimized dimensions and contours. In some embodiments, the region defined by the gate spacing 118s and the recess depth 1710r can represent the recessed volume used for filling the p-type S / D epitaxial structure 110B.

[0067] refer to Figure 5 In operation 560, a second epitaxial structure adjacent to the second spacer structure is formed on the second fin structure. The second epitaxial structure includes a second type of dopant different from the first type of dopant. For example, such as... Figure 16 and Figures 19 to 24 As shown, a p-type S / D epitaxial structure 110B adjacent to the spacer structure 120B can be formed on the fin structure 108. The p-type S / D epitaxial structure 110B may include a p-type dopant, such as B, that is different from the n-type dopant in the n-type S / D epitaxial structure 110A. Forming the p-type S / D epitaxial structure 110B may include: forming a first epitaxial layer 207B on a partially recessed portion of the fin structure 108; forming a second epitaxial layer 209B on the first epitaxial layer 207B; and forming a third epitaxial layer 211B on the second epitaxial layer 209B.

[0068] refer to Figure 16 Before forming the first epitaxial layer 207B, the semiconductor device 100 may be pre-cleaned using plasma of ammonia (NH3), nitrogen trifluoride (NF3), and argon (Ar) for approximately 80 s to approximately 400 s from time t0 to time t1 at a temperature ranging from approximately 25°C to approximately 250°C to remove surface residues. After the pre-cleaning process, the first seed layer 207B-1 and the second seed layer 207B-2 may be formed by a deposition process for approximately 30 s to approximately 80 s from time t1 to time t2. In some embodiments, the deposition process may be performed at a temperature ranging from approximately 600°C to approximately 650°C and a pressure ranging from approximately 10 Torr to approximately 50 Torr. In some embodiments, the deposition process may include precursors such as dichlorosilane (DCS) as a Si precursor, GeH4 as a Ge precursor, and HCl. In some embodiments, the first seed layer 207B-1 may include Si and the second seed layer 207B-2 may include SiGe. In some embodiments, the first epitaxial layer 207B may include a stack of seed layers having a Ge concentration gradient.

[0069] The formation of the first seed layer 207B-1 and the second seed layer 207B-2 may subsequently be followed by the formation of the epitaxial layer 207B-3. For example... Figure 16 As shown, the deposition process L1BD can be used to epitaxially grow an epitaxial layer 207B-1 (e.g., from time t2 to time t3) for approximately 30 s to approximately 80 s. Figure 19 and Figure 20 (As shown in the diagram), followed by an etching process L1BE lasting from time t3 to time t4 for approximately 5 s to approximately 20 s. In some embodiments, the deposition process L1BD may include precursors such as dichlorosilane (DCS) and SiH4 as Si precursors, GeH4 as Ge precursors, diborane (B2H6) as p-type dopant precursors, and HCl. In some embodiments, the deposition process L1BD may be carried out at a temperature in the range of approximately 600°C to approximately 650°C and at a pressure of approximately 10 Torr to approximately 50 Torr. The deposition process L1BD may have a constant gas ratio between the precursors. In some embodiments, the etching process L1BE may include HCl. In some embodiments, the etching process L1BE may be carried out at a temperature in the range of approximately 600°C to approximately 650°C and at a pressure of approximately 10 Torr to approximately 50 Torr.

[0070] After forming the first seed layer 207B-1 and the second seed layer 207B-2, the deposition process L1BD, and the etching process L1BE, the first epitaxial layer 207B can be conformally formed in the groove 1710, such as... Figure 19 and Figure 20 As shown in the diagram, the ratio of the thickness of the first epitaxial layer 207B on the sidewall of the groove 1710 to the thickness of the bottom of the groove 1710 can be in the range of about 70% to about 90%. Therefore, the subsequently formed second epitaxial layer 209B can achieve a larger volume in the P-type S / D epitaxial structure 110B. In some embodiments, the top surface of the first epitaxial layer 207B can be located about 5 nm to about 15 nm below the top surface of the fin structure 108 to allow the S / D contact structure to fall on the second epitaxial layer 209B and avoid dopant loss and increased contact resistance.

[0071] The formation of the first epitaxial layer 207B can be followed by the formation of the second epitaxial layer 209B. For example... Figure 16 As shown, the deposition process L2BD can epitaxially grow a second epitaxial layer 209B (e.g., from time t4 to time t5, lasting approximately 50 s to approximately 300 s) from time t4 to time t5. Figure 21 and Figure 22(as shown in the diagram), followed by an etching process L2BE lasting from time t5 to time t6 for approximately 10 s to approximately 80 s. In some embodiments, the deposition process L2BD may include a precursor, such as DCS as a Si precursor, GeH4 as a Ge precursor, B2H6 as a p-type dopant precursor, and HCl. The Si precursor may include DCS without SiH4 to control the dopant concentration. In some embodiments, the deposition process L2BD may be carried out at a temperature in the range of approximately 600°C to approximately 650°C and a pressure of approximately 10 Torr to approximately 50 Torr. The deposition process L2BD may have a linear ramp of the dopant precursor flow rate to form gradient doping in the second epitaxial layer 209B. In some embodiments, the second epitaxial layer 209B ( Figure 21 and Figure 22 The layer shown may include multiple sublayers, such as a first epitaxial sublayer, a second epitaxial sublayer, and a third epitaxial sublayer having a p-type dopant gradient concentration. In some embodiments, the etching process L2BE may be performed at a temperature in the range of about 600°C to about 650°C and a pressure of about 10 Torr to about 50 Torr. In some embodiments, the etching process L2BE may include HCl. After the deposition process L2BD and the etching process L2BE, a second epitaxial layer 209B may be formed in the trench 1710, as shown. Figure 21 and Figure 22 As shown in the image.

[0072] The formation of the second epitaxial layer 209B can subsequently be followed by the formation of the third epitaxial layer 211B. For example... Figure 16 As shown, the deposition process L2BD can be used to epitaxially grow a third epitaxial layer 211B from time t6 to time t7 for approximately 20 s to approximately 100 s. Figure 21 and Figure 22 (as shown in the diagram), followed by an etching process L3BE lasting from time t7 to time t8 for approximately 10 s to approximately 50 s. In some embodiments, the deposition process L3BD may include precursors such as DCS as a Si precursor, GeH4 as a Ge precursor, B2H6 as a p-type dopant precursor, and HCl. The deposition process L3BD may have a constant gas ratio between the precursors. In some embodiments, the deposition process L3BD may be performed at a temperature in the range of approximately 600°C to approximately 650°C and at a pressure of approximately 10 Torr to approximately 50 Torr. In some embodiments, the etching process L3BE may be performed at a temperature in the range of approximately 600°C to approximately 650°C and at a pressure of approximately 5 Torr to approximately 50 Torr. In some embodiments, the etching process L3BE may include HCl and GeH4 to increase the etching rate of the third epitaxial layer 211B and epitaxially grow a p-type S / D epitaxial structure 110B having a desired facet (e.g., 111 facet). Figure 4 and Figure 24(As shown in the diagram). After deposition process L3BD and etching process L3BE, a third epitaxial layer 211B can be formed on the second epitaxial layer 209B, as shown in the diagram. Figure 23 and Figure 24 As shown in the diagram. The third epitaxial layer 211B can be used as a capping layer to prevent dopant from diffusing outward from the highly doped second epitaxial layer 209B. In some embodiments, the p-type S / D epitaxial structure 110B ( Figure 4 and Figure 24 The fin (as shown) can have a rhomboid shape and can have a horizontal dimension 110Bw (e.g., width) in the range of about 20 nm to about 40 nm along the Y-axis. The ratio of the horizontal dimension 110Bw to the fin height 108h can be in the range of about 55% to about 95%. In some embodiments, such as Figure 23 As shown, the cross-sectional area of ​​the p-type S / D epitaxial structure 110B along the X-axis can cover approximately 30% to approximately 70% of the recessed volume defined by the gate spacing 118s and the recess depth 1710r. p-type S / D epitaxial structure 110B ( Figure 4 These optimized dimensions and profiles (as shown in the figure) can reduce SCE, reduce epitaxial defects, reduce epitaxial structure resistance and contact resistance, and thus improve device performance and process yield.

[0073] In some embodiments, the temperature during the deposition of the first seed layer 207B-1 and the second seed layer 207B-2 may be higher than the temperature during the deposition process L1Bd. The temperature during the deposition process L1BD may be higher than the temperature during the deposition process L2Bd. The temperature during the deposition process L2BD may be lower than the temperature during the deposition process L3Bd. The temperature during the deposition of the first seed layer 207B-1 and the second seed layer 207B-2 may be similar to the temperature during the deposition process L3Bd. In some embodiments, the temperature difference between deposition processes may be in the range of about 10°C to about 20°C. In some embodiments, the pressure difference between deposition processes may be in the range of about 10 Torr to about 20 Torr. In some embodiments, the deposition process for the n-type S / D epitaxial structure 110A may have higher pressure and higher temperature than the deposition process for the p-type S / D epitaxial structure 110B. In some embodiments, the process conditions for the deposition and etching of the S / D epitaxial structures 110A-110B can be optimized to form n-type S / D epitaxial structures 110A and p-type S / D epitaxial structures 110B with optimized volume and size, thereby reducing epitaxial defects, lowering epitaxial structure resistance and contact resistance, and thus improving device performance and process yield. In some embodiments, the semiconductor device 100 with n-type and p-type S / D epitaxial structures 110A-110B of optimized size and profile can improve process yield by about 2% to about 20% and device performance by about 2% to about 10%.

[0074] Various embodiments of the present invention provide exemplary methods for forming S / D epitaxial structures 110A-110B with optimized dimensions on a semiconductor device 100. The exemplary methods of the present invention can form a spacer layer 120 on a fin structure 108. For example... Figures 1 to 4 As shown, the fin structure 108 may be separated by an STI region 106 and may have a fin height 108h above the STI region 106. In some embodiments, the spacer layer 120 may include a silicon nitride layer and a silicon carbonitride layer. A portion of the spacer layer 120 and the fin structure 108 on the finFET 105A may be selectively removed to form a spacer structure 120A adjacent to the sidewalls of the fin structure 108. The spacer structure 120A may have a vertical dimension 120Ah above the STI region 106. The ratio of the vertical dimension 120Ah to the fin height 108h may be in the range of about 5% to about 45%. An n-type S / D epitaxial structure 110A with an optimized size and a tapered shape may be formed on the fin structure 108 and between the spacer structure 120A. The n-type S / D epitaxial structure 110A may have a horizontal dimension 110Aw, and the ratio of the horizontal dimension 110Aw to the fin height 108h may be in the range of about 55% to about 95%. A portion of the spacer layer 120 and fin structure 108 on the fin FET 105B can be selectively removed to form a spacer structure 120B adjacent to the sidewall of the fin structure 108. The spacer structure 120B may have a vertical dimension 120Bh larger than the vertical dimension 120Ah above the STI region 106. The ratio of the vertical dimension 120Ah to the vertical dimension 120Bh may be in the range of about 40% to about 95%. A p-type S / D epitaxial structure 110B with an optimized diamond shape can be formed on the fin structure 108 and between the spacer structure 120B. The p-type S / D epitaxial structure 110B may have a horizontal dimension 110Bw, and the ratio of the horizontal dimension 110Bw to the fin height 108h may be in the range of about 55% to about 95%. The p-type S / D epitaxial structure 110B may have dopants of a different type than those of the n-type S / D epitaxial structure 110A. By controlling the dimensions and profiles of the spacer structures 120A-120B and the growth process of the S / D epitaxial structures 110A-110B, both the n-type S / D epitaxial structure 110A and the p-type S / D epitaxial structure 110B can have optimized dimensions and profiles to reduce SCE, reduce epitaxial defects, improve device performance, and increase process yield.

[0075] In some embodiments, the method includes: forming a first fin structure and a second fin structure on a substrate; forming a spacer layer on the first fin structure and the second fin structure; forming a first spacer structure adjacent to the first fin structure; forming a first epitaxial structure adjacent to the first spacer structure on the first fin structure; forming a second spacer structure adjacent to the second fin structure; and forming a second epitaxial structure adjacent to the second spacer structure on the second fin structure. The first fin structure and the second fin structure are separated by an isolation layer. The first spacer structure has a first height above the isolation layer. The first epitaxial structure includes a first type of dopant. The second spacer structure has a second height above the isolation layer that is greater than the first height. The second epitaxial structure includes a second type of dopant different from the first type of dopant.

[0076] In some embodiments, forming the spacer layer includes: depositing a first dielectric material layer on the first fin structure and the second fin structure; and depositing a second dielectric material layer different from the first dielectric material layer on the first dielectric material layer. In some embodiments, forming the spacer layer includes: depositing a silicon nitride layer on the first fin structure and the second fin structure; and depositing a silicon carbonitride layer on the silicon nitride layer. In some embodiments, forming the first spacer structure includes: removing a portion of the spacer layer on the first fin structure at a first etch rate; and removing a portion of the first fin structure at a second etch rate greater than the first etch rate. In some embodiments, forming the second spacer structure includes: removing a portion of the spacer layer on the second fin structure at a first etch rate; and removing a portion of the second fin structure at a second etch rate greater than the first etch rate. In some embodiments, forming the first spacer structure and forming the second spacer structure includes: removing a portion of the first fin structure at a first etch rate; and removing a portion of the second fin structure at a second etch rate, wherein the ratio of the first etch rate to the second etch rate is in the range of about 2 to about 5. In some embodiments, forming the first epitaxial structure includes: forming a first epitaxial layer having a first dopant concentration; forming a second epitaxial layer having a second dopant concentration greater than the first dopant concentration; and forming a third epitaxial layer having a third dopant concentration less than the second dopant concentration. In some embodiments, forming the first epitaxial structure and forming the second epitaxial structure includes: epitaxially growing the first epitaxial structure having a (110) facet; and epitaxially growing the second epitaxial structure having a (111) facet.

[0077] In some embodiments, the method includes: forming a first fin structure and a second fin structure on a substrate; forming a gate structure on the first fin structure and the second fin structure; forming a spacer layer on the first fin structure, the second fin structure, an isolation layer, and the gate structure; forming a first pair of spacer structures on opposite sidewalls of the first fin structure; and forming a first epitaxial structure on the first fin structure and between the first pair of spacer structures. The method further includes: forming a second pair of spacer structures on opposite sidewalls of the second fin structure; and forming a second epitaxial structure on the second fin structure and between the second pair of spacer structures. The first fin structure and the second fin structure are separated by an isolation layer. The first pair of spacer structures has a first height above the isolation layer. The first epitaxial structure includes a first type of dopant. The second pair of spacer structures has a second height above the isolation layer that is greater than the first height. The second epitaxial structure includes a second type of dopant different from the first type of dopant.

[0078] In some embodiments, forming the spacer layer includes: depositing a first dielectric material layer on the first fin structure and the second fin structure, the isolation layer, and the gate structure; and depositing a second dielectric material layer different from the first dielectric material layer on the first dielectric material layer. In some embodiments, forming the first pair of spacer structures includes removing the first dielectric material layer and the second dielectric layer at the same etch rate. In some embodiments, forming the first pair of spacer structures includes: removing portions of the spacer layer located on the opposite sidewalls of the first fin structure at a first etch rate; and removing portions of the first fin structure located above the isolation layer at a second etch rate greater than the first etch rate. In some embodiments, forming the first pair of spacer structures includes: removing portions of the spacer layer located on the first sidewall and the second sidewall of the first fin structure at the same etch rate, wherein the first sidewall is opposite to the second sidewall. In some embodiments, forming the first pair of spacer structures and forming the second pair of spacer structures includes: removing portions of the first fin structure located above the isolation layer at a first etch rate; and removing portions of the second fin structure located above the isolation layer at a second etch rate, wherein the ratio of the first etch rate to the second etch rate is in the range of about 2 to about 5.

[0079] In some embodiments, the semiconductor device includes: a first fin structure and a second fin structure located on a substrate; an isolation layer located between the first fin structure and the second fin structure; a first epitaxial structure and a second epitaxial structure, the first epitaxial structure being located on the first fin structure and the second epitaxial structure being located on the second fin structure; and a first spacer structure and a second spacer structure, the first spacer structure being adjacent to the first epitaxial structure and having a first height above the isolation layer, and the second spacer structure being adjacent to the second epitaxial structure and having a second height above the isolation layer. The first epitaxial structure includes a first type of dopant, and the second epitaxial structure includes a second type of dopant different from the first type of dopant. The first height is smaller than the second height.

[0080] In some embodiments, the ratio of the first height to the second height is in the range of about 40% to about 95%. In some embodiments, the first fin structure and the second fin structure have a third height above the isolation layer; and the ratio of the first height or the second height to the third height is in the range of about 5% to about 45%. In some embodiments, the first fin structure and the second fin structure have a third height; the first extensional structure has a first width and the second extensional structure has a second width; and the ratio of the first width or the second width to the third height is in the range of about 55% to about 95%. In some embodiments, the first extensional structure has a tapered shape, and the second extensional structure has a rhomboid shape. In some embodiments, the first extensional structure has a third height above the top surface of the first fin structure. The second extensional structure has a fourth height above the top surface of the second fin structure; and the fourth height is greater than the third height.

[0081] It should be understood that the detailed description section, rather than the abstract section of the invention, is intended to be used to interpret the claims. The abstract section of the invention may set forth one or more, but not all, possible embodiments of the invention as conceived by the inventors, and is therefore not intended to limit the dependent claims in any way.

[0082] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A method for forming a semiconductor device, comprising: A first fin structure and a second fin structure are formed on a substrate, wherein the first fin structure and the second fin structure are separated by an isolation layer; Spacer layers are formed on the first fin structure and the second fin structure; A first spacer structure is formed adjacent to the first fin structure, wherein the first spacer structure has a first height above the isolation layer; A first epitaxial structure adjacent to the first spacer structure is formed on the first fin structure, wherein the first epitaxial structure includes a first type of dopant, and the first epitaxial structure has a first epitaxial height along a first direction from the top surface of the first fin structure to the top surface of the first epitaxial structure; A second spacer structure is formed adjacent to the second fin structure, wherein the second spacer structure has a second height above the isolation layer that is greater than the first height; and A second epitaxial structure adjacent to the second spacer structure is formed on the second fin structure, wherein the second epitaxial structure includes a second type of dopant different from the first type of dopant, and the second epitaxial structure has a second epitaxial height along the first direction from the top surface of the second fin structure to the top surface of the second epitaxial structure, and the second epitaxial height is greater than the first epitaxial height; In this structure, the fin-removed portion of the second fin structure forms the top surface of the recessed fin region, and the top surface of the recessed fin region forms an interface with the second extensional structure, and the interface is coplanar with the top surface of the isolation layer.

2. The method according to claim 1, wherein, Forming the spacer layer includes: Deposit a first dielectric material layer on the first fin structure and the second fin structure; and A second dielectric material layer, different from the first dielectric material, is deposited on the first dielectric material layer.

3. The method according to claim 1, wherein, Forming the spacer layer includes: Depositing silicon nitride layers on the first fin structure and the second fin structure; and A silicon carbonitride layer is deposited on the silicon nitride layer.

4. The method according to claim 1, wherein, The first spacer structure includes: Remove the portion of the spacer layer located on the first fin structure at a first etch rate; and A portion of the first fin structure is removed at a second etch rate that is greater than the first etch rate.

5. The method according to claim 1, wherein, The second spacer structure includes: The portion of the spacer layer located on the second fin structure is removed at a first etch rate; and A portion of the second fin structure is removed at a second etch rate that is greater than the first etch rate.

6. The method according to claim 1, wherein, Forming the first spacer structure and forming the second spacer structure include: Remove a portion of the first fin structure at a first etch rate; and A portion of the second fin structure is removed at a second etch rate, wherein the ratio of the first etch rate to the second etch rate is in the range of 2 to 5.

7. The method according to claim 1, wherein, The formation of the first epitaxial structure includes: A first epitaxial layer with a first dopant concentration is formed; Forming a second epitaxial layer having a second dopant concentration greater than that of the first dopant; and A third epitaxial layer is formed having a third dopant concentration that is lower than that of the second dopant.

8. The method according to claim 1, wherein, Forming the first epitaxial structure and forming the second epitaxial structure include: Epitaxial growth of the first epitaxial structure having a (110) facet; and The second epitaxial structure having (111) facets is grown epitaxially.

9. A method for forming a semiconductor device, comprising: A first fin structure and a second fin structure are formed on a substrate, wherein the first fin structure and the second fin structure are separated by an isolation layer; A gate structure is formed on the first fin structure and the second fin structure; A spacer layer is formed on the first fin structure, the second fin structure, the isolation layer, and the gate structure; A first pair of spacer structures are formed on opposite sidewalls of the first fin structure, wherein the first pair of spacer structures have a first height above the isolation layer; A first epitaxial structure is formed on the first fin structure and between the first pair of spacer structures, wherein the first epitaxial structure includes a first type of dopant and the first epitaxial structure has a first epitaxial height along a first direction from the top surface of the first fin structure to the top surface of the first epitaxial structure; A second pair of spacer structures are formed on opposite sidewalls of the second fin structure, wherein the second pair of spacer structures have a second height above the isolation layer that is greater than the first height; and A second epitaxial structure is formed on the second fin structure and between the second pair of spacer structures, wherein the second epitaxial structure includes a second type of dopant different from the first type of dopant, and the second epitaxial structure has a second epitaxial height along the first direction from the top surface of the second fin structure to the top surface of the second epitaxial structure, the second epitaxial height being greater than the first epitaxial height; In this structure, the fin-removed portion of the second fin structure forms the top surface of the recessed fin region, and the top surface of the recessed fin region forms an interface with the second extensional structure, and the interface is coplanar with the top surface of the isolation layer.

10. The method of claim 9, wherein, Forming the spacer layer includes: A first dielectric material layer is deposited on the first fin structure, the second fin structure, the isolation layer, and the gate structure; and A second dielectric material layer, different from the first dielectric material, is deposited on the first dielectric material layer.

11. The method according to claim 10, wherein, Forming the first pair of spacer structures involves removing the first dielectric material layer and the second dielectric material layer at the same etching rate.

12. The method according to claim 9, wherein, The structure forming the first pair of spacers includes: The portion of the spacer layer located on the opposite sidewall of the first fin structure is removed at a first etch rate; and The portion of the first fin structure located above the isolation layer is removed at a second etch rate greater than the first etch rate.

13. The method according to claim 9, wherein, The structure forming the first pair of spacers includes: The portion of the spacer layer located on the first and second sidewalls of the first fin structure is removed at the same etching rate, wherein the first sidewall is opposite to the second sidewall.

14. The method of claim 9, wherein, Forming the first pair of spacer structures and forming the second pair of spacer structures includes: Remove the portion of the first fin structure above the isolation layer at a first etch rate; and The portion of the second fin structure above the isolation layer is removed at a second etch rate, wherein the ratio of the first etch rate to the second etch rate is in the range of 2 to 5.

15. A semiconductor device, comprising: The first fin structure and the second fin structure are located on the substrate; An isolation layer is located between the first fin structure and the second fin structure; A first epitaxial structure and a second epitaxial structure, the first epitaxial structure being located on a first fin structure, and the second epitaxial structure being located on a second fin structure, wherein the first epitaxial structure includes a first type of dopant, and the second epitaxial structure includes a second type of dopant different from the first type of dopant; the first epitaxial structure has a first epitaxial height along a first direction from the top surface of the first fin structure to the top surface of the first epitaxial structure; the second epitaxial structure has a second epitaxial height along the first direction from the top surface of the second fin structure to the top surface of the second epitaxial structure; and the second epitaxial height is greater than the first epitaxial height. A first spacer structure and a second spacer structure, wherein the first spacer structure is adjacent to the first epitaxial structure and has a first height above the isolation layer, and the second spacer structure is adjacent to the second epitaxial structure and has a second height above the isolation layer, wherein the first height is less than the second height; In this structure, the fin-removed portion of the second fin structure forms the top surface of the recessed fin region, and the top surface of the recessed fin region forms an interface with the second extensional structure, and the interface is coplanar with the top surface of the isolation layer.

16. The semiconductor device according to claim 15, wherein, The ratio of the first height to the second height is in the range of 40% to 95%.

17. The semiconductor device of claim 15, wherein: The first fin structure and the second fin structure have a third height above the isolation layer; and The ratio of the first height or the second height to the third height is in the range of 5% to 45%.

18. The semiconductor device according to claim 15, wherein: The first fin structure and the second fin structure have a third height; The first epitaxial structure has a first width and the second epitaxial structure has a second width; and The ratio of the first width or the second width to the third height is in the range of 55% to 95%.

19. The semiconductor device according to claim 15, wherein, The first epitaxial structure has a tapered shape, and the second epitaxial structure has a rhomboid shape.

20. The semiconductor device according to claim 15, wherein: The first epitaxial structure has a third height above the top surface of the first fin structure; The second extensional structure has a fourth height above the top surface of the second fin structure; and The fourth height is greater than the third height.

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