Optoelectronic semiconductor device

Abstract

Optoelectronic semiconductor device with - a semiconductor body (1) comprising a sequence of semiconductor layers (2) with a p-type semiconductor region (3), an n-type semiconductor region (5) and an active layer (4) arranged between the p-type semiconductor region (3) and the n-type semiconductor region (5), - a carrier (10) which has a plastic and a first via (11) and a second via (12), - a p-terminal layer (7) and an n-terminal layer (8, 8A) which are arranged at least partially between the support (10) and the semiconductor body (1), wherein the p-terminal layer (7) connects the first via (11) to the p-type semiconductor region (3) and the n-terminal layer (8, 8A) connects the second via (12) to the n-type semiconductor region (5), - an ESD protection element (15) arranged between the carrier (10) and the semiconductor body (1), wherein the ESD protection element (15) is electrically connected to the first via (11) and the second via (12), wherein a forward direction of the ESD protection element (15) is antiparallel to a forward direction of the semiconductor layer sequence (2), and wherein the ESD protection element (15) is directly adjacent to the first via (11) and the second via (12); wherein the optoelectronic semiconductor device is a thin-film LED in which a growth substrate for growing the semiconductor layer sequence (2) has been detached.

Description

[0001] The application relates to an optoelectronic semiconductor device comprising a semiconductor body and a substrate made of a plastic material.

[0002] The optoelectronic semiconductor component can in particular comprise a semiconductor body and a plastic carrier produced by a casting process, which is provided with vias for electrical contacting the semiconductor body.

[0003] The publication DE 10 2014 112 673 A1 describes a light-emitting diode device with a carrier and a light-emitting diode arranged on it.

[0004] In the publication DE 10 2009 032 486 A1, an optoelectronic component with a semiconductor body and a support substrate is specified.

[0005] Document US 2015 / 0179629A1 concerns a semiconductor structure for protection against electrostatic discharge.

[0006] Document US 2011 / 0 147 466 A1 describes an LED package with a substrate and a display element.

[0007] Publication US 2014 / 0 145 633 A1 concerns an LED package in which an LED is attached to a substrate by flip chip bonding.

[0008] Document US 2015 / 0 084 080 A1 describes a light-emitting apparatus with a light-emitting element and a substrate for this element.

[0009] Publication JP 2009 - 252 930 A relates to an antistatic electrical component and a module thereof.

[0010] One task to be solved is to specify an improved optoelectronic semiconductor device that is characterized by low sensitivity to short circuits and / or electrostatic discharges (ESD) and is relatively easy to manufacture.

[0011] This problem is solved by an optoelectronic semiconductor device according to independent claim 1. Advantageous embodiments and further developments of the invention are the subject of dependent claims.

[0012] According to one embodiment, the optoelectronic semiconductor device comprises a semiconductor body with a sequence of semiconductor layers, including a p-type semiconductor region, an n-type semiconductor region, and an active layer located between the p-type and n-type semiconductor regions. The active layer can, in particular, be a radiation-emitting active layer. The p-type semiconductor region, the n-type semiconductor region, and the active layer can each comprise one or more semiconductor layers. The p-type semiconductor region contains one or more p-doped semiconductor layers, and the n-doped semiconductor region contains one or more n-doped semiconductor layers. It is also possible for the p-type and / or the n-type semiconductor region to contain one or more undoped semiconductor layers.

[0013] The active layer can be configured, for example, as a pn junction, a double heterostructure, a single quantum well structure, or a multiple quantum well structure. The term quantum well structure encompasses any structure in which charge carriers undergo quantization of their energy states through confinement. In particular, the term quantum well structure does not specify the dimensionality of the quantization. It therefore includes, among other things, quantum wells, quantum wires, and quantum dots, and any combination of these structures.

[0014] Furthermore, the optoelectronic semiconductor device has a substrate made of plastic. This substrate can be manufactured, in particular, by a casting process. In other words, the substrate is a so-called molded body. The term "casting process" here encompasses all manufacturing processes in which a molding compound is introduced into a predetermined mold and, in particular, subsequently cured. Specifically, the term "casting process" includes casting (potting), injection molding, transfer molding, and compression molding. Preferably, the substrate is formed by compression molding or by a film-assisted transfer molding process.

[0015] The substrate preferably comprises a casting resin, such as an epoxy resin, or a silicone. The substrate may contain one or more additives. For example, the substrate may contain SiO2 particles to adjust the coefficient of thermal expansion. The substrate may have a thickness between 50 µm and 500 µm, preferably between 100 µm and 200 µm, typically around 150 µm.

[0016] According to at least one embodiment, the carrier has a first via and a second via, each of which leads from a first main surface of the carrier facing the semiconductor body to a second main surface of the carrier facing away from the semiconductor body.

[0017] Because the vias extend from the first main surface of the substrate to the opposite second main surface, the optoelectronic component can advantageously be provided with electrical connections on the second main surface of the substrate. In particular, the optoelectronic component can be connected to conductors on a printed circuit board (PCB) at the second main surface of the substrate, for example, by connecting the first via with a solder layer to a first conductor on the PCB and the second via with a second solder layer to a second conductor on the PCB. The optoelectronic component is therefore advantageously surface-mountable.

[0018] Furthermore, the optoelectronic semiconductor device advantageously comprises a p-type contact layer and an n-type contact layer, which are arranged at least partially between the substrate and the semiconductor body, wherein the p-type contact layer connects the first via to the p-type semiconductor region and the n-type contact layer connects the second via to the n-type semiconductor region. The first and second electrical contact layers are isolated from each other by an electrically insulating layer. Advantageously, in the optoelectronic semiconductor chip, both the p-type and the n-type semiconductor regions are contacted from the substrate side. This has the advantage that a radiation emission surface of the semiconductor body opposite the substrate can be free of contact layers. The radiation yield is thus advantageously increased.

[0019] In a preferred embodiment, the n-terminal layer is led into the n-type semiconductor region through a breakdown in the p-type semiconductor region and the active layer. In the region of the breakdown, the n-terminal layer is separated from the active layer and the p-type semiconductor region by an electrically insulating layer.

[0020] Furthermore, it is advantageous if the n-terminal layer and / or the p-terminal layer are reflective to the radiation emitted by the active layer, in order to reflect radiation emitted towards the support towards the radiation exit surface. The n-terminal layer and / or the p-terminal layer can, in particular, comprise a reflective metal layer and preferably contain silver or aluminum. It is possible that the n-terminal layer and / or the p-terminal layer comprises several sublayers, in particular a metal layer and a layer of a transparent conductive oxide such as ITO or doped ZnO, wherein the dopant can be, for example, Al or Ga.

[0021] Furthermore, the optoelectronic semiconductor component advantageously includes an ESD protection element that is arranged between the substrate and the semiconductor body.

[0022] The ESD protection element is electrically connected to the first and second vias, with one forward direction of the ESD protection element being antiparallel to one forward direction of the semiconductor layer sequence. The ESD protection element exhibits direction-dependent electrical conductivity, with the forward direction being the direction with the higher electrical conductivity. In other words, the ESD protection element has higher conductivity in the reverse direction of the semiconductor layer sequence and lower conductivity in the forward direction of the semiconductor layer sequence, or is preferably non-conductive. In this way, the ESD protection element advantageously protects the semiconductor layer sequence from high reverse-bias voltages, which can occur particularly due to electrostatic discharge and could damage the optoelectronic semiconductor device.

[0023] The ESD protection element is preferably a planar layer integrated into the optoelectronic semiconductor device. In other words, the ESD protection element is not a separately manufactured component and does not have a housing. The ESD protection element can be configured, for example, as a diode, a Schottky contact, or a varistor. The ESD protection element can, for example, comprise or consist of at least one of the following materials: ZnO, Si, TiO, ITO, SnO, Ge, Se, Te, AlN, or graphene. The material of the ESD protection element can be at least partially doped with an n-type or p-type dopant to, for example, form a diode.

[0024] In a preferred embodiment, the ESD protection element is arranged at an interface of the carrier facing the semiconductor body. By being positioned between the semiconductor body and the carrier, the ESD protection element is advantageously protected from external influences by the carrier's plastic material and is preferably not visible from the outside.

[0025] The ESD protection element is directly adjacent to the first and second vias of the substrate. For example, the ESD protection element can be applied to a surface of the optoelectronic semiconductor device facing the substrate before the vias and the substrate are manufactured. For instance, the ESD protection element is manufactured first, then the vias are produced, for example, by electroplating, and in a further step, the substrate is manufactured by a casting process.

[0026] In a preferred embodiment, the ESD protection element is a diode having an n-type region and a p-type region. In this case, the n-type region is electrically connected to the first via and the p-type region to the second via. Preferably, the n-type region is directly adjacent to the first via and the p-type region directly adjacent to the second via.

[0027] In a preferred embodiment, the n-type and p-type regions are each arranged in an annular form. For example, the n-type region can be arranged annularly around the first via, with the p-type region arranged annularly around the n-type region. In this embodiment, the n-type termination layer or the second via can surround the p-type region in an annular form.

[0028] Alternatively, the p-type region can be arranged in a ring around the second via, with the n-type region surrounding the p-type region in a ring. In this configuration, either the p-type termination layer or the first via can surround the n-type region in a ring.

[0029] The ring-shaped design of the p-type and n-type regions of the ESD protection element has the advantage that the pn junction has a comparatively large area. This results in high current-carrying capacity and thus particularly good ESD protection against reverse-bias voltage pulses across the semiconductor layer sequence.

[0030] The invention is described below using an exemplary embodiment in connection with the Fig. 1, Fig. 2, Fig. 3 to Fig. 4 explained in more detail.

[0031] They show: Fig. 1 a schematic representation of a cross-section through an optoelectronic semiconductor device according to a first embodiment, Fig. 2 a schematic representation of a top view of the arrangement of the ESD protection element between the first and second vias in the first embodiment, Fig. 3 a schematic representation of a cross-section through an optoelectronic semiconductor device according to an example that shows only partial aspects of the invention; Fig. 4 A schematic representation of a top view of the arrangement of the ESD protection element between the first and second vias in the example.

[0032] The components depicted in the figures, as well as the relative sizes of the components, are not to be considered to scale.

[0033] At the in Fig. Figure 1 illustrates an embodiment of an optoelectronic semiconductor device, which is an LED. The LED comprises a semiconductor body 1, which has a sequence of semiconductor layers 2 with an active layer 4 suitable for radiation emission. The active layer 4 can, for example, have a pn junction or a single or multiple quantum well structure for radiation generation. The active layer 4 is arranged between a p-type semiconductor region 3 and an n-type semiconductor region 5.

[0034] The semiconductor layer sequence 2 is preferably based on a III-V compound semiconductor material, in particular on an arsenide, nitride, or phosphide compound semiconductor material. For example, the semiconductor layer sequence 2 can be in x Al y Ga 1-x-y N, In x Al y Ga 1-x-y P or In x Al y Ga 1-x-yThe formulas contain elements such as 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and x + y ≤ 1. The III-V compound semiconductor material does not necessarily have to have a mathematically exact composition according to one of the formulas above. Rather, it can contain one or more dopants as well as additional components that do not substantially alter the physical properties of the material. For the sake of simplicity, however, the formulas above only include the essential components of the crystal lattice, even though these may be partially replaced by small amounts of other substances.

[0035] The LED according to the exemplary embodiment is a so-called thin-film LED, from which a growth substrate used to grow the semiconductor layer sequence 2 has subsequently been detached. The original growth substrate, for example a sapphire, silicon, or GaAs substrate, has been detached from the side of the semiconductor body 1 where the radiation emission surface 16 is now located. The semiconductor body 1 can be roughened or structured at its radiation emission surface 16 to improve the radiation extraction from the semiconductor body 1. The structuring or roughening of the semiconductor body 1 at the radiation emission surface 16 can be carried out, in particular, by an etching process.

[0036] The semiconductor body 1 is connected to a support 10 on a surface opposite the radiation emission surface 16. The support 10 is made of a plastic. In particular, the support 10 can be manufactured by compression molding, injection molding, or a casting process. The plastic material of the support 10 can, for example, be an epoxy resin or a silicone.

[0037] The carrier 10 has a first main surface 17 facing the semiconductor body 1 and a second main surface 18 facing away from the semiconductor body. The carrier 10 has a first via 11 and a second via 12, each extending from the first main surface 17 to the second main surface 18 of the carrier 10. The vias 11, 12 advantageously comprise a metal or a metal alloy and can, in particular, be electroplated. The vias 11, 12 can, for example, contain Cu, Ni, or a solder.

[0038] The two vias 11, 12 serve for the electrical contacting of the semiconductor body 1. For example, the first via 11 is electrically connected to the p-type semiconductor region 3 of the semiconductor layer sequence 2 and the second via 12 to the n-type semiconductor region 5.

[0039] An electrically conductive connection between the first via 11 and the p-type semiconductor region 3 is established, in particular, by means of a p-termination layer 7, which is arranged between the semiconductor body 1 and the support 10. In this embodiment, the p-termination layer 7 does not directly adjoin the p-type semiconductor region 3. Rather, an electrically conductive reflective layer 6 is arranged between the p-type semiconductor region 3 and the p-termination layer 7, which deflects radiation emitted from the active layer 4 towards the support 10 to the radiation exit surface 16. The reflective layer 6 preferably comprises a silver layer. The reflective layer 6 can also comprise several sublayers, in particular a metal layer and a layer of a transparent conductive oxide such as ITO or ZnO.

[0040] The second via 12 is electrically connected to the n-type semiconductor region 5 by means of an n-terminal layer 8, 8A. This can be achieved, for example, by extending a portion of the n-terminal layer 8 through a breakdown in the semiconductor layer sequence 2 into the n-type semiconductor region 5, thus forming a through-contact 8A. The n-terminal layer 8, 8A is electrically insulated from the p-type semiconductor region 3, the active layer 4, the p-terminal layer 7, and the first via 11 by one or more electrically insulating layers 9. The at least one electrically insulating layer 9 can, for example, comprise silicon oxide or aluminum oxide.

[0041] The contacting of the optoelectronic component by means of the n-type termination layer 8, 8A extending through the active zone 4 has the advantage that both the n-type semiconductor region 5 and the p-type semiconductor region 3 are contacted from the side of the semiconductor body 1 facing the support 10. The radiation emission surface 16 of the optoelectronic component is therefore advantageously free of electrical contact elements such as bond pads, contact metallizations, or connecting wires. In this way, absorption of radiation by contact elements at the radiation emission surface 16 is prevented.

[0042] The vias 11, 12 can advantageously be connected externally to the second main surface 18 of the carrier 10, which is opposite the semiconductor body 1. In particular, the electrically conductive vias 11, 12 on the second main surface 18 of the carrier 10 can, for example, be connected to the conductor tracks of a [missing information]. The optoelectronic semiconductor device is therefore advantageously surface-mountable.

[0043] In the optoelectronic semiconductor device, an ESD protection element 15 is advantageously arranged between the carrier 10 and the semiconductor layer sequence 2. The ESD protection element 15 has a direction-dependent conductivity and is connected antiparallel to a forward direction of the semiconductor layer sequence 2. In particular, the ESD protection element 15 has a lower conductivity in the forward direction of the semiconductor layer sequence 2 than in the reverse direction of the semiconductor layer sequence 2.

[0044] In this embodiment, the ESD protection element 15 is designed as a diode having a p-type region 13 and an n-type region 14. The n-type region 14 borders the first via 11, which is electrically connected to the p-type semiconductor region 3 of the semiconductor layer sequence 2. The p-type region 13 borders the second via 12, which is electrically connected to the n-type semiconductor region 5. The pn junction of the ESD protection element 15 is thus connected antiparallel to the semiconductor layer sequence 2. In the event of an ESD voltage pulse in reverse bias of the semiconductor layer sequence 2, the resulting current can therefore be dissipated via the pn junction of the ESD protection element 15. Damage to the semiconductor layer sequence 2 by electrostatic discharge is thus advantageously prevented.

[0045] The ESD protection element 15 can alternatively be designed as a diode, a Schottky contact or a varistor.

[0046] The ESD protection element 15 is advantageously arranged on one of the first main surfaces 17 of the carrier 10 facing the semiconductor layer sequence 2. In particular, the ESD protection element 15 can directly adjoin the carrier 10, with the p-type region 13 directly adjacent to the second via 12 and the n-type region 14 directly adjacent to the first via 13. The ESD protection element can, at least in some areas, directly adjoin the plastic material of the carrier 10. The ESD protection element 15 is thus arranged inside the optoelectronic semiconductor device and is thereby protected from external influences.

[0047] As in Fig. 2, as can be seen in a schematically represented top view of the ESD protection element 15, the ESD protection element 15 forms in the exemplary embodiment of the Fig. 1. A linear connection is formed between the first via 11 and the second via 12. The schematic circuit diagram shown in the top view illustrates that the ESD protection element is connected antiparallel to the light-emitting semiconductor layer sequence.

[0048] Another example is in the Fig. 3 and Fig. Figure 4 shows a cross-section and a schematic top view of the ESD protection element 15. As in the first embodiment, the ESD protection element 15 is a diode having an n-type conductive region 14 and a p-type conductive region 13. Unlike the first embodiment, the ESD protection element 15 is not located directly at the interface with the carrier 10, but rather in a region between the p-type termination layer 7 and the n-type termination layer 8.

[0049] As in the supervision in Fig.As can be seen in Figure 4, the n-type region 14 and the p-type region 13 are each ring-shaped. The n-type region 14 is electrically connected to the p-type termination layer 7 and can, in particular, directly adjoin the p-type termination layer 7. In this way, the n-type region 14 is indirectly electrically connected to the first via 11 and the p-type semiconductor region 3 of the semiconductor layer sequence 2. The n-type region 14 is, in particular, ring-shaped around the p-type termination layer 7.

[0050] The p-type region 13 is ring-shaped around the n-type region 14, which is electrically connected to the n-type termination layer 8 and can, in particular, directly adjoin the n-type termination layer 8. In this way, the p-type region 13 is indirectly electrically connected to the second via 12 and the n-type semiconductor region 5 of the semiconductor layer sequence 2. The schematic circuit diagram shown in the top view illustrates that the ESD protection element 15 is connected antiparallel to a forward direction of the light-emitting semiconductor layer sequence 2.

[0051] The ring-shaped configuration of the p-type region 13 and the n-type region 14 has the advantage that the pn junction of the ESD protection element 15 has a comparatively large area compared to a linear arrangement of the p-type region 13 and the n-type region 14. This results in a high reverse current carrying capacity of the optoelectronic semiconductor device 1 and thus particularly good ESD protection.

[0052] The invention is not limited by the description based on the exemplary embodiments. Rather, the invention encompasses every new feature as well as every combination of features, which in particular includes every combination of features in the patent claims, even if this feature or combination itself is not explicitly specified in the patent claims or exemplary embodiments. Reference symbol list 1 Semiconductor body 2 Semiconductor layer sequence 3 p-doped semiconductor region 4 active layer 5n-doped semiconductor region 6 Mirror layer 7 p-connection layer 8 n-connection layer 9 electrically insulating layer 10 carriers 11 first through-hole 12 second via 13 p-conducting area 14 n-conducting area 15 ESD protection element 16 Radiation emission surface 17 first main area 18 second main area

Claims

Optoelectronic semiconductor device comprising: - a semiconductor body (1) having a sequence of semiconductor layers (2) with a p-type semiconductor region (3), an n-type semiconductor region (5) and an active layer (4) arranged between the p-type semiconductor region (3) and the n-type semiconductor region (5); - a substrate (10) having a plastic material and a first via (11) and a second via (12); - a p-terminal layer (7) and an n-terminal layer (8, 8A) which are arranged at least partially between the substrate (10) and the semiconductor body (1), wherein the p-terminal layer (7) connects the first via (11) to the p-type semiconductor region (3) and the n-terminal layer (8, 8A) connects the second via (12) to the n-type semiconductor region (5); - an ESD protection element (15) arranged between the substrate (10) and the semiconductor body (1). is,wherein the ESD protection element (15) is electrically connected to the first via (11) and the second via (12), wherein a forward direction of the ESD protection element (15) is antiparallel to a forward direction of the semiconductor layer sequence (2), and wherein the ESD protection element (15) is directly adjacent to the first via (11) and the second via (12); wherein the optoelectronic semiconductor device is a thin-film LED in which a growth substrate for growing the semiconductor layer sequence (2) has been detached. Optoelectronic semiconductor device according to claim 1, wherein the ESD protection element (15) is designed as a planar layer. Optoelectronic semiconductor device according to one of the preceding claims, wherein the ESD protection element (15) is configured as a diode, as a Schottky contact or as a varistor. Optoelectronic semiconductor device according to one of the preceding claims, wherein the ESD protection element (15) comprises at least one of the materials ZnO, Si, TiO, ITO, SnO, Ge, Se, Te, AlN or graphene. Optoelectronic semiconductor device according to one of the preceding claims, wherein the ESD protection element (15) is arranged on an interface of the carrier (10) facing the semiconductor body (1). Optoelectronic semiconductor device according to one of the preceding claims, wherein the ESD protection element (15) is a diode having a p-type region (13) and an n-type region (14), wherein the n-type region (14) is electrically connected to the first via (11) and the p-type region (13) is electrically connected to the second via (12). Optoelectronic semiconductor device according to claim 6, wherein the p-conducting region (13) and the n-conducting region (14) form a linear connection between the first via (11) and the second via (12). Optoelectronic semiconductor device according to claim 6, wherein the p-conducting region (13) and the n-conducting region (14) are each formed in a ring shape. Optoelectronic semiconductor device according to claim 8, wherein the p-conducting region (13) and the n-conducting region (14) are arranged in a ring shape around the p-terminal layer (7) or n-terminal layer (8, 8A). Optoelectronic semiconductor device according to one of the preceding claims, wherein the support (10) comprises an epoxy resin or a silicone. Optoelectronic semiconductor device according to one of the preceding claims, wherein the n-terminal layer (8, 8A) is led through a breakthrough in the p-type semiconductor region (3) and the active layer (4) into the n-type semiconductor region (5).

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