Fail-safe device for an inverter

Abstract

Fail-safe device for an inverter that performs control or driving and electrical power generation by using a synchronous motor (3) in which a permanent magnet is used as a magnetic field magnet, wherein the fail-safe device for the inverter comprises: a three-phase switching circuit having semiconductor switching devices (2) for performing an electrical power conversion in an upper branch and a lower branch; an overvoltage detection circuit (4) that detects an overvoltage by monitoring a DC voltage source voltage of the converter; and a control switching circuit (5) which switches a control method for the semiconductor switching devices (2) between a three-phase PWM control and a three-phase short-circuit control in accordance with an overvoltage determination signal from the overvoltage detection circuit (4) and which comprises: a three-phase PWM control circuit (6), a three-phase short-circuiting control circuit (7), each an AND circuit (8) for each semiconductor switching device (2) of the upper branch, via which the three-phase PWM control circuit (6) is connected to the respective semiconductor switching device (2) of the upper branch of the three-phase circuit and one OR circuit (9) for each semiconductor switching device (2) of the lower branch, via which the three-phase PWM control circuit (6) is connected to the respective semiconductor switching device (2) of the lower branch of the three-phase circuit, wherein the overvoltage detection signal is supplied by the overvoltage detection circuit (4) to the three-phase short-circuiting control circuit (7) as an input signal (EN), and wherein an output signal (7ao) of the three-phase short-circuiting control circuit (7) is supplied to the AND circuits (8) and another output signal (7bo) of the three-phase short-circuiting control circuit (7) is supplied to the OR circuits (9) such that In the case where no overvoltage is detected by the overvoltage detection circuit (4), an output signal (5uo) of the AND circuits (8) and an output signal (5uo*) of the OR circuits (9) perform the three-phase PWM control of the semiconductor switching devices (2) and In the event that an overvoltage is detected by the overvoltage detection circuit (4), the output signal (5uo) of the AND circuits (8) and the output signal (5uo*) of the OR circuits (9) perform the three-phase short-circuiting control of the semiconductor switching devices (2), and wherein, in accordance with an overvoltage detection signal from the overvoltage detection circuit (4), the three-phase short-circuiting control circuit (7) outputs a high-impedance signal or the same signal as an input signal.

Description

BACKGROUND OF THE INVENTION Area of ​​the invention

[0001] The present invention relates to a fail-safe device for a converter. Description of the related technique

[0002] Due to the trend towards fuel efficiency regulations for automobiles, mild hybrid vehicles and similar technologies have been put into practical use in recent years. For example, a synchronous motor equipped with an inverter is used in such a hybrid vehicle. Due to the need for a high-performance motor, a system utilizing a new DC voltage source, such as a 48V battery or a 48V lithium-ion battery, has also attracted attention, compared to a system using a 12V battery DC voltage source. The aforementioned synchronous motor contains a synchronous motor that uses a permanent magnet to produce a magnetic field and operates at high speed.While a synchronous motor equipped with a permanent magnet requires no excitation current, the induced voltage produced by the permanent magnet's magnetic field increases proportionally to the rotational speed. Due to this phenomenon, when the motor's speed exceeds a certain threshold, the produced induced voltage exceeds the inverter's output voltage. Therefore, when the motor is operating at high speed, a method is used to suppress the inverter's output voltage by employing a weak magnetic field control or similar technique using PWM (Pulse Width Modulation).

[0003] The preceding method is also applied in the case where electrical power is generated by using a synchronous motor equipped with a magnetic field permanent magnet; because, when the speed of the motor becomes so high as to exceed a given value, the produced induced voltage exceeds the DC voltage source voltage of the inverter, a method is used in which a weak magnetic field control, which uses a PWM control, is implemented even at a time when electrical power is generated, so that it is suppressed from the generated voltage exceeding the upper limit of the limited voltage.

[0004] In the case of such a motor, as described above, which uses a permanent magnet to produce a magnetic field and operates at high speed, if an abnormality occurs in the inverter while the motor is rotating at high speed, the induced voltage produced by the motor's rotation will become excessively high; thus, the excessively high voltage can damage the inverter; furthermore, in the case of, for example, a 48 V system, the induced voltage exceeds the upper limit of the DC voltage source, and thus the voltage increases to a level high enough to endanger a human body.

[0005] As a suppression method at a time when an abnormality occurs in the inverter, and therefore the motor's induction voltage produces an overvoltage, a design has accordingly been proposed in which, when the inverter is switched off, the inverter is controlled to be in a three-phase short-circuit mode (see JP 2011-172 343 A).

[0006] US 7,652,858 B2 discloses methods and devices for protecting a motor control circuit in a permanent magnet electric motor system. The permanent magnet electric motor system includes a permanent magnet electric motor with a predetermined number of windings corresponding to the phases of the permanent magnet electric motor, and a direct current (DC) bus coupled to a power source to provide operating power to the electric motor system. A motor control circuit is connected to the DC bus to receive operating power from it and is connected to the windings of the permanent magnet electric motor to control the permanent magnet electric motor.A protection circuit is connected to the DC bus to receive the voltage for operating the protection circuit, to detect an overvoltage, and to identify predetermined fault conditions of the motor control circuit from the voltage measured on the DC bus, and in response to this, to create protection for the motor control circuit.

[0007] US 8,605,471 B2 describes a power conversion device comprising an inverter that converts direct current supplied by a direct current source into alternating current by controlling, in switching operation, a plurality of switching elements forming an upper branch and a plurality of switching elements forming a lower branch, a control unit that includes a signal generation unit that generates a switching signal carrying a command to execute the switching operation according to each of the plurality of switching elements forming the upper branch and the plurality of switching elements forming the lower branch, and outputs the switching signal thus generated as a control signal, and a drive unit that individually drives each of the switching elements based on the corresponding control signals.The control unit contains a plurality of protection circuits arranged in series on a control signal line extending between the signal generation unit and the driver unit, each of the protection circuits outputting a control signal input into it when a protection operation is not performed, but outputting a control signal to set the corresponding switching element either to an off state or to an electrically continuous state instead of the control signal input into it when the protection operation is performed.

[0008] The use of the embodiment disclosed in JP 2011-172 343 A allows the inverter to be switched off if, due to an abnormality in the inverter, the inverter is switched off and the voltage produced by the motor's induction voltage becomes equal to or higher than a predetermined voltage. In this case, the inverter is made to operate in three-phase short-circuit mode, thus preventing the voltage from becoming excessively high. However, in the case of the preceding embodiment, the inverter cannot be controlled to operate in three-phase short-circuit mode for overvoltage produced when the motor's connection to a DC voltage source is disconnected while the motor is rotating at high speed and low-speed control is required, or for overvoltage produced by a factor other than switching off the inverter, such as a fault in a sensor. SUMMARY OF THE INVENTION

[0009] A fail-safe device or failsafe device for a converter according to the present invention is intended to solve the aforementioned problems, be constructed from simple means, but still reliably ensure a safe fail-safe function.

[0010] The problems are solved by a fail-safe device for a converter having the features according to claim 1. Advantageous embodiments are set out in the dependent claims.

[0011] The preceding and other problems, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a schematic diagram illustrating a fail-safe device for an inverter according to embodiment 1 of the present invention. Fig. Figure 2 is a schematic diagram illustrating a part (U-phase) of a control switching circuit in the fail-safe device for the inverter according to embodiment 1 of the present invention. Fig. 3 is a logic table at the input and output of a three-phase short-circuit control circuit in the fail-safe device for the inverter according to embodiment 1 of the present invention. Fig. 4 is a logic table at the input and output of the control switching circuit in the fail-safe device for the inverter according to embodiment 1 of the present invention. Fig. Figure 5 is a schematic diagram illustrating a fail-safe device for an inverter according to embodiment 2 of the present invention. Fig. Figure 6 is a timing diagram of a holding circuit in the fail-safe device for the inverter according to embodiment 2 of the present invention. Fig. Figure 7 is a schematic diagram illustrating a fail-safe device for an inverter according to embodiment 3 of the present invention. Fig. Figure 8 is a timing diagram of a holding circuit in the fail-safe device for the inverter according to embodiment 3 of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EXECUTION FORMS Execution format 1

[0012] Fig. Figure 1 illustrates an example of a fail-safe device for a converter according to embodiment 1 of the present invention. This converter has a switching circuit designed with a semiconductor switching device 2, such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), performs PWM control of a DC voltage supplied by a DC voltage source 1 using the semiconductor switching device 2, and converts the DC voltage into a three-phase AC voltage to control or drive a synchronous motor (hereinafter also referred to as a motor) 3.

[0013] For example, motor 3 is directly connected to an internal combustion engine or is connected to an internal combustion engine via a pulley or similar belt. In the case where motor 3 is driven by the internal combustion engine, the inverter can be operated as an electrical power generator; if the induced voltage of motor 3 is greater than the DC source voltage of the inverter, a PWM control, utilizing the rectification action of a flyback diode 2a in the semiconductor switching device 2, or a weak magnetic field control is applied to the three-phase AC voltage to generate electrical power; if the induced voltage of motor 3 is less than the DC source voltage of the inverter, the inverter is made to operate as a boost converter, using the semiconductor switching device 2, so that electrical power is generated.

[0014] Furthermore, the fail-safe device for the inverter has a control switching circuit 5 for switching the control method for the semiconductor switching device 2 between a PWM control and a three-phase short-circuit control in accordance with the output signal of an overvoltage detection circuit 4, which detects the voltage state of the DC voltage source 1.

[0015] The overvoltage detection circuit 4 comprises a circuit that compares a threshold voltage for specifying an overvoltage with a detection voltage detected at the DC voltage source 1 using a comparator or the like, and outputs an "H" signal or an "L" signal. In embodiment 1, an overvoltage determination signal 4a is defined as being "L" when the overvoltage detection circuit 4 detects an overvoltage.

[0016] Next, a single-phase (U-phase) operation of the control switching circuit 5 in the fail-safe device for the inverter according to embodiment 1 is performed based on Fig. 2 will be explained. The explanation also applies to each of the operations of the other phases (V-phase and W-phase).

[0017] As in Fig. As illustrated in Figure 2, the control switching circuit 5 is configured with a three-phase PWM control circuit 6, a three-phase short-circuit control circuit 7, an AND gate 8, and an OR gate 9. The respective outputs of the three-phase PWM control circuit 6 and the three-phase short-circuit control circuit 7 are connected to the upper branch of the semiconductor switching device 2 via the AND gate 8, which is a logic circuit, and to the lower branch of the semiconductor switching device 2 via the OR gate 9, which is a logic circuit. Normally, the output signal of the three-phase PWM control circuit 6, to which a PWM input signal is applied, controls the switching device 2.

[0018] As in Fig. As illustrated in Figure 2, the three-phase short-circuiting control circuit 7 has as its inputs EN, to which the overvoltage detection signal 4a is input, and A1 and A2, to which input signals 7a and 7b, respectively, are input; the three-phase short-circuiting control circuit 7 has as its outputs Y1 and Y2, from which output signals 7ao and 7bo are output. In this situation, the three-phase short-circuiting control circuit 7 is designed such that, in accordance with a Fig. The logic table 3 represents its output Y based on the input EN, to which the overvoltage detection signal 4a is applied, and an input A. Each of the inputs A1 and A2 in Fig. 2 corresponds to input A in Fig. 3; each of Y1 and Y2 in Fig. 2 corresponds to output Y in Fig. 3. When an overvoltage is detected, the input signals 7a and 7b are set to "L" and "H" respectively, so that the output signals 7ao and 7bo, which are the outputs of the three-phase short-circuiting control circuit 7, become "L" and "H" respectively. Conversely, if the overvoltage detection signal 4a is "H", the output Y becomes high-impedance; therefore, to prevent the logic states of the output signals 7ao and 7bo from becoming unstable, the output signal 7ao is pulled high to the voltage source, and the output signal 7bo is pulled low to ground. A buffer IC or the like is used as the three-phase short-circuiting control circuit 7. As described above, the output of the three-phase short-circuiting control circuit 7 becomes high-impedance or the same signal as the input signal.

[0019] When the control switching circuit 5, configured as described above, is used, the signals 5uo and 5uo* to be output to the semiconductor switching device 2 are configured to be output in the manner represented by a logic table 4. This means that, in the case where the voltage of the DC voltage source 1 is normal, the overvoltage detection signal 4a at input EN, the output signal 7ao at output Y1, and the output signal 7bo at output Y2 are "H", "H", and "H", respectively.“L” so that the output signal 5uo of the AND circuit 8 and the output signal 5uo* of the OR circuit 9 perform a three-phase PWM control of the semiconductor switching device 2; in the case where the voltage of the DC voltage source 1 exceeds the upper limit of the specified voltage, and the overvoltage detection circuit 4 detects an overvoltage, the overvoltage determination signal 4a at input EN, the output signal 7ao at output Y1 and the output signal 7bo at output Y2 become “L”, “L” and “H” respectively, and therefore the output signal 5uo of the AND circuit 8 and the output signal 5uo* of the OR circuit 9 become “L” and “H” respectively.“H” and perform a three-phase short-circuiting of the semiconductor switching device 2 to reduce the speed of the motor; since it is made possible to suppress the voltage of the DC voltage source from exceeding the normal voltage, a high-security fail-safe device for a converter can thus be obtained.

[0020] In embodiment 1, when the voltage of the DC voltage source 1 becomes excessive, the overvoltage detection signal 4a is defined by the overvoltage detection circuit 4 as being "L", thus determining the logic states of the three-phase PWM control circuit 6 and the three-phase short-circuit control circuit 7; however, various modes exist for a signal combination that exhibits the same effect as embodiment 1. Thus, the mode is not limited to the preceding combination. Design 2

[0021] Fig. Figure 5 illustrates an example of a fail-safe device for a converter according to embodiment 2 of the present invention. The same component elements as in embodiment 1 are designated with the same reference numerals.

[0022] Embodiment 2 differs from embodiment 1 in that embodiment 2 has a signal retention circuit 10 for holding or temporarily storing the overvoltage determination signal 4a between the overvoltage detection circuit 4 and the control switching circuit 5.

[0023] Upon receiving a falling edge of the overvoltage detection signal 4a, which was output by the overvoltage detection circuit 4, the signal retention circuit 10 holds an overvoltage detection hold signal 10a, which is an output signal of the overvoltage detection circuit 4, at "L". The overvoltage detection hold signal 10a output by the signal retention circuit 10 is input to the control switching circuit 5. In other words, the overvoltage detection hold signal 10a is input to the EN input of the three-phase short-circuiting control circuit 7. The configuration of the control switching circuit 5 is the same as in embodiment 1, except that the overvoltage detection signal 4a is replaced by the overvoltage detection hold signal 10a.

[0024] To explain the preceding operation, the time diagram is shown at a time when an overvoltage is detected in the configuration according to embodiment 2. Fig. 6 represents. As soon as the overvoltage detection circuit 4 detects an overvoltage, the semiconductor switching device 2 is controlled in a three-phase short-circuiting manner, based on the logic tables in Fig. 3 and Fig. 4. After that, even if the voltage of the DC voltage source 1 moves to a normal voltage, the semiconductor switching device 2 can be maintained in the three-phase short-circuit mode.

[0025] This means that when the overvoltage detection signal 4a becomes "L", the signal retention circuit 10 holds the overvoltage detection retention signal 10a at "L" in response to a drop in the overvoltage detection signal 4a, as in Fig. 6 represents. With regard to the control switching circuit 5, the input signals 7a at input A1 and the input signal 7b at input A2 are “L” and “H” respectively; based on the logic table in Fig. 3 are the output signal 7ao from output Y1 and the output signal 7bo from output Y2 “L” and “H” respectively, as in Fig. 6 represents. As a result, as is the case with embodiment 1, the three-phase short-circuiting control is based on the logic table in Fig. 4 realized. In embodiment 2, the three-phase short-circuiting control continues as long as the overvoltage detection hold signal 10a is held at “L”.

[0026] Even if, in embodiment 2, the overvoltage detection signal 4a fluctuates at the time when the voltage of the DC voltage source 1 is just below or above the vicinity of the threshold voltage of the overvoltage detection circuit 4, the three-phase short-circuiting control mode is maintained because the overvoltage detection signal 4a input to the three-phase short-circuiting control circuit 7 is held; therefore, a higher safety fail-safe device for a converter can be obtained. embodiment 3

[0027] Fig. Figure 7 illustrates the design of a fail-safe device for a converter according to embodiment 3 of the present invention. The same component elements as in embodiment 1 are designated with the same reference numerals.

[0028] Embodiment 3 differs from both embodiment 1 and embodiment 2 in that, in addition to embodiment 2, embodiment 3 has a control circuit 11 for releasing a held signal. For example, a microcomputer or the like is used as the control circuit 11.

[0029] Next, the operation of the fail-safe device for the inverter according to embodiment 3 of the present invention will be explained. The voltage of the DC voltage source 1 is detected by the overvoltage detection circuit 4; then, the overvoltage detection signal 4a output by the overvoltage detection circuit 4 is fed to the signal retention circuit 10 and the control circuit 11. As soon as an overvoltage is detected, and therefore the overvoltage detection signal 4a becomes "L", the signal retention circuit 10 holds the overvoltage detection signal 10a at "L"; thus, the semiconductor switching device 2 is driven in a three-phase short-circuit manner. When the voltage transition of the DC voltage source 1 is normalized, the overvoltage detection signal 4a becomes "H".If, in this situation, there is a need for PWM control, and the overvoltage detection signal 4a is "H", the control circuit 11 outputs "H" as a hold-release signal 11a to the signal hold circuit 10. Based on the hold-release signal 11a and the overvoltage detection signal 4a, the signal hold circuit 10 changes the overvoltage detection hold signal 10a from "L" to "H" and then outputs the overvoltage detection hold signal 10a.

[0030] To explain the preceding operation, a time diagram in the configuration according to embodiment 3 is shown. Fig. 8 represents. As soon as the overvoltage detection circuit 4 detects an overvoltage, the semiconductor switching device 2 is controlled in a three-phase short-circuiting manner, based on the logic tables in Fig. 3 and Fig. 4. Subsequently, even if the voltage of the DC voltage source 1 returns to a normal voltage, the semiconductor switching device 2 remains in three-phase short-circuit mode; however, when the control circuit 11 receives a request for PWM drive, and the overvoltage detection signal 4a is normal, the control circuit 11 outputs "H" as the hold-release signal 11a, so that the overvoltage detection hold signal 10a changes from "L" to "H"; thus, the drive mode for the semiconductor switching device 2 can be changed from three-phase short-circuit drive to PWM drive.

[0031] This means that when the overvoltage detection signal 4a becomes "L", the signal retention circuit 10 holds the overvoltage detection retention signal 10a at "L" in response to a drop in the overvoltage detection signal 4a, as in Fig. 8 represents. With regard to the control switching circuit 5, the input signals 7a at input A1 and the input signal 7b at input A2 are “L” and “H” respectively; based on the logic table in Fig. 3 are the output signal 7ao from output Y1 and the output signal 7bo from output Y2 “L” and “H” respectively, as in Fig. 8 represents. As a result, as is the case in embodiment 1, the three-phase short-circuiting is controlled based on the logic table in Fig. 4 realized. Then, when the voltage of the DC voltage source 1 returns to a normal voltage, the overvoltage detection signal 4a is generated by the overvoltage detection circuit 4 “H”, as shown in Fig. 8 represents; when the control circuit 11 receives a request for PWM control, and the overvoltage detection signal 4a is "H", the hold release signal 11a is output as "H". As a result, the hold is released, and therefore the overvoltage detection hold signal 10a is output as "H" by the signal hold circuit 10, as shown in Fig. 8 represents, and the input EN of the three-phase short-circuiting control circuit 7 becomes "H"; simultaneously, the output 7ao at output Y1 and the output 7bo at output Y2 become "H" and "L" respectively, which is the case where the voltage of the DC voltage source 1 is normal; thus, PWM control can be based on the logic table in Fig. 4 will be realized.

[0032] Embodiment 3 makes it possible that, when an overvoltage of the DC voltage source 1 is detected, the semiconductor switching device 2 is controlled in a three-phase short-circuiting manner, and therefore a high-security fail-safe device for a converter is obtained, and that, when a need for PWM control is indicated after the DC voltage source 1 returns to a normal state, the converter is PWM-controlled again.

Claims

[1] Fail-safe device for an inverter that performs control or driving and electrical power generation by using a synchronous motor (3) in which a permanent magnet is used as a magnetic field magnet, wherein the fail-safe device for the inverter comprises: a three-phase switching circuit having semiconductor switching devices (2) for performing an electrical power conversion in an upper branch and a lower branch; an overvoltage detection circuit (4) that detects an overvoltage by monitoring a DC voltage source voltage of the converter; and a control switching circuit (5) which switches a control method for the semiconductor switching devices (2) between a three-phase PWM control and a three-phase short-circuit control in accordance with an overvoltage determination signal from the overvoltage detection circuit (4) and which comprises: a three-phase PWM control circuit (6), a three-phase short-circuiting control circuit (7), each an AND circuit (8) for each semiconductor switching device (2) of the upper branch, via which the three-phase PWM control circuit (6) is connected to the respective semiconductor switching device (2) of the upper branch of the three-phase circuit and one OR circuit (9) for each semiconductor switching device (2) of the lower branch, via which the three-phase PWM control circuit (6) is connected to the respective semiconductor switching device (2) of the lower branch of the three-phase circuit, wherein the overvoltage detection signal is supplied by the overvoltage detection circuit (4) to the three-phase short-circuiting control circuit (7) as an input signal (EN), and wherein an output signal (7ao) of the three-phase short-circuiting control circuit (7) is supplied to the AND circuits (8) and another output signal (7bo) of the three-phase short-circuiting control circuit (7) is supplied to the OR circuits (9) such that In the case where no overvoltage is detected by the overvoltage detection circuit (4), an output signal (5uo) of the AND circuits (8) and an output signal (5uo*) of the OR circuits (9) perform the three-phase PWM control of the semiconductor switching devices (2) and In the event that an overvoltage is detected by the overvoltage detection circuit (4), the output signal (5uo) of the AND circuits (8) and the output signal (5uo*) of the OR circuits (9) perform the three-phase short-circuiting control of the semiconductor switching devices (2), and wherein, in accordance with an overvoltage detection signal from the overvoltage detection circuit (4), the three-phase short-circuiting control circuit (7) outputs a high-impedance signal or the same signal as an input signal. [2] Fail-safe device according to claim 1, characterized by , that the control switching circuit (5) has a signal retention circuit (10) for retaining an overvoltage determination signal from the overvoltage detection circuit (4) and a control method for the switching device (2) switches between a three-phase PWM control and a three-phase short-circuit control in accordance with a signal from the signal retention circuit (10). [3] Fail-safe device according to claim 2, characterized by , that the control switching circuit (5) has a control circuit (11) for releasing a signal from the signal holding circuit (10).

Images