Method for fabricating a subassembly with a suspended III-V nanowire layer and a suspended silicon germanium nanowire layer

Abstract

A method for at least partially manufacturing a semiconductor device (100), the method comprising: Providing a first subassembly (100c) comprising: Providing an intermediate stage comprising: - a substrate layer (102), - a germanium-containing layer (104) formed on at least a first zone (120) and a second zone (122) of an upper surface of the substrate layer (102), - a III-V material nanowire layer (106) disposed on top of the first zone (120) and the second zone (122) of the upper surface of the germanium-containing layer (104), Etching away the III-V material nanowire layer (106) in the second zone (122) of the germanium-containing layer (104) but not in the first zone (120); and Growing a silicon germanium nanowire layer (112) in the second zone (122) on top of the germanium-containing layer (104) while the first zone (120) is covered by a hard mask, such that the silicon germanium nanowire layer (112) is disposed on top of the second zone (122) of the upper surface of the germanium-containing layer (104); and Further processing the first sub-array (100c) into a second sub-array (100d) by removing the germanium-containing layer (104), so that: (i) the III-V material nanowire layer (106) is at least partially suspended above the substrate layer (102), and (ii) the silicon germanium nanowire layer (112) is at least partially suspended above the substrate layer (102).

Description

BACKGROUND OF THE INVENTION

[0001] The present invention relates generally to the field of nanowire-type semiconductor devices, and more particularly to nanowire-type semiconductor devices having a "release layer" (i.e., a layer that underlies and supports a nanowire when the nanowire structure is initially formed, but which is then removed so that the nanowire is suspended without any material that underlies and supports the suspended portions of the nanowire). It is known to fabricate semiconductor devices that include nanowire portions. For example, in some transistors, nanowire is used to form the gate portion of the transistor. The "release" of nanowire devices is a key step in the fabrication process. In particular, "releasing" a nanowire in a nanowire-type semiconductor device refers to a fabrication process wherein a nanowire is initially formed on the top surface of another layer (i.e.,the “release layer”) is formed and (ii) the release layer or at least a part of the release layer below the nanowire is removed (or detached) (without removing the nanowire) and (iii) as a result, the nanowire is suspended above the area where the release layer was.

[0002] It is known to use "III-V compounds" as semiconductor materials in semiconductor devices. Examples of widely used III-V semiconductor materials include, but are not limited to, gallium arsenide (GaAs), indium phosphide (InP), and indium gallium arsenide (InGaAs). Any other binary, ternary, or other combination of III-V semiconductors may be used.

[0003] A pair of semiconductor devices is known from document US 2013 / 0 270 512 A1. The pair of semiconductor devices comprises a first nanowire arranged above a substrate, wherein a longitudinal length of the first nanowire further comprises a first channel region of a group IV semiconductor material, a first source region and a first drain region electrically coupled to the first channel region, and a first gate stack comprising a gate insulator and a gate conductor completely coaxially encircling the first channel region.The pair of semiconductor devices further comprises a second nanowire disposed over the substrate, the second nanowire further comprising a second channel region of a group III-V semiconductor material, a second source region and a second drain region electrically coupled to the second channel region, and a second gate stack comprising a gate insulator and a gate conductor completely coaxially wrapping the second channel region. SUMMARY

[0004] According to the present invention, a method is provided according to independent claim 1. An advantageous embodiment thereof is defined in dependent claim 2. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a longitudinal cross-sectional view (hatching omitted for clarity of illustration) of a first intermediate stage of a subassembly used in the manufacture of a first embodiment of a semiconductor device according to the present invention; Fig. 1B is a longitudinal cross-sectional view (hatching omitted for clarity of illustration) of a second intermediate stage of a subassembly used in the manufacture of the semiconductor device of the first embodiment; Fig. 1C is a longitudinal cross-sectional view (hatching omitted for clarity of illustration) of a third intermediate stage of a subassembly used in the manufacture of the semiconductor device of the first embodiment; Fig. 1D is a longitudinal cross-sectional view (hatching omitted for clarity of illustration) of a fourth intermediate stage of a subassembly used in the manufacture of the semiconductor device of the first embodiment; Fig. 1E is a transverse cross-sectional view (hatching shown for clarity of illustration) of the fourth intermediate stage of a subassembly used in the manufacture of the semiconductor device of the first embodiment; Fig. 2A is a longitudinal cross-sectional view (hatching omitted for simplicity of illustration) of a first intermediate stage of a subassembly used in the manufacture of a second embodiment of a semiconductor device according to the present invention; Fig. 2B is a longitudinal cross-sectional view (hatching omitted for simplicity of illustration) of a second intermediate stage of a subassembly used in the manufacture of the semiconductor device of the second embodiment; Fig. 2C is a longitudinal cross-sectional view (hatching omitted for simplicity of illustration) of a third intermediate stage of a subassembly used in the manufacture of the semiconductor device of the second embodiment; Fig. 2D is a longitudinal cross-sectional view (hatching omitted for simplicity of illustration) of a fourth intermediate stage of a subassembly used in the manufacture of the semiconductor device of the second embodiment; Fig. 2E is a longitudinal cross-sectional view (hatching omitted for simplicity of illustration) of a fifth intermediate stage of a subassembly used in the manufacture of the semiconductor device of the second embodiment; and Fig. 2F is a transverse cross-sectional view (hatching shown for clarity of illustration) of the fifth intermediate stage of a subassembly used in the fabrication of the semiconductor device of the second embodiment. DETAILED DESCRIPTION

[0005] Some embodiments of the present invention relate to the fabrication of a semiconductor device comprising: a substrate layer; a first group of source / drain component(s) defining an nFET (n-type field effect transistor) region; a second group of source / drain component(s) defining a pFET (p-type field effect transistor) region; a first suspended nanowire suspended at least partially above the substrate layer in the nFET region and made of III-V material; and a second suspended nanowire suspended at least partially above the substrate layer in the pFET region and made of germanium-containing material.The first suspended nanowire and the second suspended nanowire are fabricated by adding appropriate nanowire layers on top of a germanium-containing release layer and then removing the germanium-containing release layers so that the nanowires are suspended.

[0006] In some embodiments, a fabrication method for fabricating suspended nanowire-type semiconductor devices comprises: (i) fabricating III-V compound nanowires; and (ii) using a germanium-containing (Ge-containing) layer as the release layer (which is at least partially removed during fabrication) for the suspended III-V compound nanowires. "Lattice matching" is a useful technique that can be applied in conjunction with suspended III-V nanowire / germanium-containing release layer fabrication methods. Semiconductor materials generally have a crystalline structure, with atoms arranged in a regular lattice characterized by a lattice constant. Lattice matching attempts to match (or at least approximately match) the lattice constants for two semiconductor materials that are intermixed and / or placed adjacent to each other.For example: (i) GaAs is a III-V semiconductor material with a lattice constant of 0.565325 nm (5.65325 Å) and (ii) germanium is a material used in semiconductor devices that has a lattice constant of 0.5658 nm (5.658 Å); and (iii) since the lattice constant values of GaAs and germanium are quite similar, these materials are considered lattice-matched for most purposes.

[0007] In some embodiments of the present invention, a germanium (Ge) or silicon germanium (SiGe) layer is used as a release layer. Herein, a germanium release layer and / or a SiGe release layer are collectively referred to as a "germanium-containing release layer." In some embodiments of the present invention, the germanium-containing release layer is selectively etched, meaning that the germanium or SiGe release layer (or germanium or SiGe portions of a release layer) are stripped by etching with an etchant that removes the germanium and / or SiGe without removing other materials in the intermediate stage of the suspended nanowire-type semiconductor subassembly being fabricated.

[0008] The material used to fabricate the carrier wafer can be graded down to pure germanium. For clarity, the term "grading SiGe" as used in this document refers to increasing the germanium content of a SiGe layer up to a maximum grade of pure germanium without silicon. For example, SiGe with a 10% grade would have 10% germanium and 90% silicon in the alloy structure.

[0009] Fig. 1A to 1C show a first process flow for manufacturing a nanowire-type semiconductor device 100. More specifically: (i) Fig. 1A shows a first subassembly intermediate stage 100a; (ii) Fig. Figure 1B shows a second subassembly intermediate stage 100b and (iii) Fig. 1C shows a third subassembly intermediate stage 100c.

[0010] As in Fig. 1A, the first sub-array intermediate stage 100a comprises: a carrier wafer 102; a germanium-containing release layer 104; a III-V compound nanowire layer 106; and a dashed zone 107. In this example: (i) the carrier wafer layer is made of pure silicon, several hundred micrometers thick; (ii) the germanium-containing release layer is made of relatively germanium-rich SiGe (alternatively, it could be made of pure Ge), 4 nm (nanometers) to 8 nm thick; and (iii) the III-V compound nanowire layer is made of a suitable III-V compound, 4 nm to 8 nm thick (in other embodiments, the thickness may range from 2 nm to 20 nm).

[0011] Starting with the subarray intermediate stage 100a, the following operations are performed to form an oxide isolation region: (i) depositing nitride; (ii) etching a trench (see the dashed region 107, which shows where the trench is etched); (iii) depositing an oxide stop 108 (see Fig. 1B); (iv) polishing until deposited; and (v) stripping the deposit. This process for forming an oxide isolation zone will now be described in more detail in the following paragraphs.

[0012] With respect to operation (i), the nitride deposition deposited in this step is not illustrated in the figures, but those skilled in the art will recognize that nitride deposition is a standard process for STI (Shallow Trench Isolation). In this embodiment, the particular nitride used in the nitride deposition operation is silicon nitride. In particular, in this embodiment, the nitride deposition operation is performed by plasma-enhanced chemical vapor deposition (PECVD), which is an STI process used to create active regions. In particular, nitride deposition is helpful in creating an NFET (n-type field-effect transistor) region 120 (see FIG. Fig. 1C) on the left side of the dashed zone 107 and a PFET (p-type field effect transistor) zone 122 (cf. Fig. 1C) on the right side of the dashed zone 107.

[0013] Regarding operation (ii) (etching a trench), the process used to remove material and create the trench is RIE (Reactive Ion Etching). As indicated by the dashed zone 107 in Fig. As shown in Figure 1A, the trench extends downward into the germanium-containing layer 104.

[0014] With respect to operation (iii), the oxide stop 108 is deposited in the trench previously formed in operation (ii) according to current conventional methods for depositing oxide stops.

[0015] Regarding operation (iv), "polishing to deposit," chemical mechanical planarization (CMP) is performed to perform a top-down material removal, from the top surface of the nitride deposit (not shown in the figures) downwards. The top surface of the oxide stop 108 stops the top-down material removal by the CMP of operation (iv), so that the nitride deposit (not shown in the figures) is flat and level and has the correct height. In particular, the oxide stop 108 prevents the CMP of operation (iv) from removing material from the III-V compound nanowire layer 106 (which, in this example, is only 4 to 8 nanometers thick and therefore not feasibly sensitive to conventional CMP processes).

[0016] During the deposit stripping step (v), the nitride deposit (not shown in the figures) is removed by a conventional stripping process to complete the shallow trench isolation and thereby create the NFET and PFET regions. After operations (i) to (v) of the oxide isolation region forming process, the intermediate sub-array stage 100b of the Fig. 1B. The subassembly intermediate 100b comprises: a carrier wafer 102; a germanium-containing release layer 104; a III-V compound nanowire layer 106 and an oxide stop 108. As in Fig. 1B, the oxide stop 108 now separates the III-V compound layer 106 into two zones 120 and 122.

[0017] In order to switch from the sub-assembly intermediate stage 100b of the Fig. 1B to the subassembly intermediate stage 100c of the Fig. 1C, a process for forming a SiGe nanowire layer is performed. The process for forming a SiGe nanowire layer comprises the following operations: (i) patterning with a hard mask (e.g., SiN or SiO2 hard mask material); (ii) etching away the III-V compound nanowire layer in region 122 (but not in region 120); and (iii) growing a SiGe nanowire layer 112 (cf. Fig. 1C). The steps of the process for forming a SiGe nanowire layer are discussed in the following paragraphs.

[0018] In operation (i) of the method for forming a SiGe nanowire layer, the hard mask layer 110 is deposited in the region 120, but not in the region 122, by conventional hard mask deposition techniques.

[0019] In operation (ii) of the process for forming a SiGe nanowire layer, the III-V compound nanowire layer is etched away in region 122, but not in region 120 (where it is protected from etching by the hard mask layer 110). The choice of etching chemicals depends heavily on the III-V compound used, as is known to those skilled in the art. For example, the etching chemical could be: (i) HF in the case of GaAs or InGaAs, or (ii) HCl in the case of InP.

[0020] In operation (iii) of the process for forming a SiGe nanowire layer, a layer of SiGe nanowires is left on top of the germanium-containing release layer 104 in the region 122 (cf. Fig. 1C) grow a SiGe nanowire layer 112. The SiGe nanowire layer 112 is relatively germanium-poor compared to the SiGe release layer 104. To the extent that pure silicon can be used for the nanowire layer 112, pure silicon should be considered a type of "SiGe layer" for nanowire fabrication under the present disclosure. This will become important later when the SiGe release layer 104 is removed (i.e., stripped). In this embodiment, the SiGe nanowire layer 112 is grown by epitaxial growth, but it can also be added by any method currently in use. In this embodiment, the layer 112 is 2 nm to 20 nm thick, with 4 nm to 8 nm being preferred. During the step of growing the germanium-containing nanowire layer, the germanium-containing release layer 104 underlies and supports the SiGe nanowire layer 112.At the end of the SiGe nanowire growth step (iii), the subassembly intermediate 100c of the . Fig. Received 1C.

[0021] After the above-described process of forming the SiGe nanowire layer, the hard mask layer 110 is removed by conventional methods (compare the sub-array intermediate stage 100c of the Fig. 1C with the sub-assembly intermediate stage 100d of the Fig. 1D). Subsequently, touch-up CMP is performed to planarize the upper surfaces of the III-V compound nanowire layer 106 and the SiGe nanowire layer 112. Again, the upper surface of the oxide stop 108 acts as a stop for the touch-up CMP.

[0022] A comparison of the subassembly intermediate stage 100c of the Fig. 1C with the sub-assembly intermediate stage 100d of the Fig. Figure 1D shows the detachment of the germanium-containing release layer 104, resulting in the suspension of the III-V compound nanowire layer 106 and the SiGe nanowire layer 112. As in Fig. 1D, the suspension zone 130 is now free of material, so that the III-V compound nanowire layer and the germanium-containing nanowire layer are suspended above the support wafer 102 and are not supported on their respective undersides.

[0023] Specifically, in this embodiment, the germanium-containing release layer is removed (or "stripped") by a wet etching process. The relatively high germanium content compared to the germanium content of the nanowire layer helps to selectively remove the release layer without damaging the germanium-containing nanowire layer, as high-germanium content portions can be wet-etched without significantly etching or damaging relatively low-germanium (SiGe) portions. For selective etching to work, there is typically a difference in germanium content of at least 20% to 30% between the SiGe release layer and the SiGe nanowire layer.

[0024] As shown in the orthogonal left-side view 100e of the Fig. 1E (see the cross-sectional arrows in Fig. 1D for viewer orientation), the III-V compound nanowire layer 106 has a rectangular cross-section in this embodiment. Alternatively, the suspended nanowires can be profiled (e.g., by annealing) to have other shapes, e.g., a circular cross-section. The nanowires 106 and 112 can be integrated as gate regions in a field-effect transistor (FET) device, where: (i) the III-V compound nanowire 106 serves as a gate for the nFET portion (also referred to as an nFET region) of the semiconductor device, and (ii) the SiGe nanowire 112 serves as a gate for a pFET portion (also referred to as a pFET region) of the semiconductor device. The source / drain components for the pFET and nFET regions (cf. Fig. 1D at blocks 150 and 152) are shown only in schematic form because, in this embodiment, they are structured and arranged similarly to source / drain components of known nFET / pFET semiconductor devices. Now, with reference to Fig. 2A to 2C, a variation of the semiconductor manufacturing process discussed above is discussed. In this process, a wafer bonding approach is used to implement a stressing technique of the PFET region. The process begins with providing a first subassembly 200a, as shown in Fig. 2A, and a second sub-assembly 200b, as shown in Fig. 2B. The first sub-array 200a includes: a first carrier wafer layer 202; a first germanium-containing layer 204 (in this embodiment, SiGe with atomic fractions and / or doping to be optimized for an interface with a III-V material layer); and a III-V material layer 206. The second sub-array 200b includes: a second carrier wafer layer 220; and a second germanium-containing layer 222 (in this embodiment, SiGe with atomic fractions and / or doping to be optimized for use as a seed layer for a PFET).

[0025] The first and second subassemblies 200a and 200b are joined together by “wafer bonding” (ie, joined together like two slices of bread in a sandwich) to produce a third subassembly, as shown in Fig. 2C. Note that the first and second wafer layers are the upper and lower outer layers, respectively, of the third sub-array, as shown in Fig. 2C. The third subassembly is further processed to produce a fourth subassembly, as will now be discussed. The first carrier wafer layer 202 and the first germanium-containing layer 204 are removed from the top surface of the third subassembly (as shown in Fig. 2C), so that a fourth sub-arrangement is obtained (as in Fig. 2D). The fourth sub-arrangement (as shown in Fig. 2D) is structurally similar to the first subassembly intermediate 100a, which is the starting part for the process discussed in connection with Figure Series 1. However, in this variation, illustrated in Figure Series 2, the fact that the III-V material layer 206 was initially grown and / or deposited on a layer optimized for a III-V material interface (specifically, the first germanium-containing layer 204) means that the III-V material layer 206 may be subject to less adverse tensile stresses and / or strains than the III-V material layer 106 of Figure Series 1.

[0026] The fourth sub-arrangement (as in Fig. 2D) is then processed similarly to the above in conjunction with Fig. 1A to 1E, such that the second germanium-containing layer 222 is stripped away and the III-V material layer 206 is suspended as a suspended nanowire over the second carrier wafer layer 220 (see FIG. Fig. 2E and Fig. 2F).

[0027] The following paragraphs provide some definitions for certain words or terms to help understand and / or interpret this document.

[0028] And / or: inclusive or; for example, A, B and / or C means that at least one of A or B or C is true and applicable.

[0029] Above: directly above and / or indirectly above; for example, if a table has a tablecloth and a glass is "above" the tablecloth, then the glass is also considered to be "above" the table, since that is how the word "above" is defined.

Claims

[1] A method for at least partially manufacturing a semiconductor device (100), the method comprising: Providing a first subassembly (100c) comprising: Providing an intermediate stage comprising: - a substrate layer (102), - a germanium-containing layer (104) formed on at least a first zone (120) and a second zone (122) of an upper surface of the substrate layer (102), - a III-V material nanowire layer (106) disposed on top of the first zone (120) and the second zone (122) of the upper surface of the germanium-containing layer (104), Etching away the III-V material nanowire layer (106) in the second zone (122) of the germanium-containing layer (104) but not in the first zone (120); and Growing a silicon germanium nanowire layer (112) in the second zone (122) on top of the germanium-containing layer (104) while the first zone (120) is covered by a hard mask, such that the silicon germanium nanowire layer (112) is disposed on top of the second zone (122) of the upper surface of the germanium-containing layer (104); and Further processing the first sub-array (100c) into a second sub-array (100d) by removing the germanium-containing layer (104), so that: (i) the III-V material nanowire layer (106) is at least partially suspended above the substrate layer (102), and (ii) the silicon germanium nanowire layer (112) is at least partially suspended above the substrate layer (102). [2] The process according to claim 1, wherein the intermediate is obtained by: Providing the germanium-containing layer (204) on the substrate layer (202); Providing the III-V material nanowire layer on another germanium-containing layer (222) deposited on a carrier wafer (220); Bonding the III-V material nanowire layer (206) to the germanium-containing layer (204); and Removing the carrier wafer (220) and the other germanium-containing layer (222).

Images